diff options
Diffstat (limited to 'src/vhdl')
| -rw-r--r-- | src/vhdl/vhdl-annotations.adb | 8 | ||||
| -rw-r--r-- | src/vhdl/vhdl-ieee-numeric.adb | 32 | ||||
| -rw-r--r-- | src/vhdl/vhdl-ieee-std_logic_1164.adb | 20 | ||||
| -rw-r--r-- | src/vhdl/vhdl-nodes.ads | 9 |
4 files changed, 62 insertions, 7 deletions
diff --git a/src/vhdl/vhdl-annotations.adb b/src/vhdl/vhdl-annotations.adb index d81e70adf..0b15f37b0 100644 --- a/src/vhdl/vhdl-annotations.adb +++ b/src/vhdl/vhdl-annotations.adb @@ -487,7 +487,10 @@ package body Vhdl.Annotations is | Iir_Kind_Interface_Variable_Declaration | Iir_Kind_Interface_Constant_Declaration | Iir_Kind_Interface_File_Declaration => - Annotate_Anonymous_Type_Definition (Block_Info, Get_Type (El)); + if Get_Subtype_Indication (El) /= Null_Iir then + Annotate_Anonymous_Type_Definition + (Block_Info, Get_Type (El)); + end if; when others => Error_Kind ("annotate_interface_list_subtype", El); end case; @@ -877,7 +880,8 @@ package body Vhdl.Annotations is when Iir_Kind_Simple_Signal_Assignment_Statement | Iir_Kind_Selected_Waveform_Assignment_Statement | Iir_Kind_Conditional_Signal_Assignment_Statement - | Iir_Kind_Variable_Assignment_Statement => + | Iir_Kind_Variable_Assignment_Statement + | Iir_Kind_Conditional_Variable_Assignment_Statement => null; when Iir_Kind_Procedure_Call_Statement => null; diff --git a/src/vhdl/vhdl-ieee-numeric.adb b/src/vhdl/vhdl-ieee-numeric.adb index 4a9ba8508..a1ac7927e 100644 --- a/src/vhdl/vhdl-ieee-numeric.adb +++ b/src/vhdl/vhdl-ieee-numeric.adb @@ -429,6 +429,36 @@ package body Vhdl.Ieee.Numeric is raise Error; end if; end Handle_Resize; + + procedure Handle_Std_Match + is + Predefined : Iir_Predefined_Functions; + begin + if Arg1_Kind /= Arg2_Kind or else Arg1_Sign /= Arg2_Sign then + raise Error; + end if; + + if Arg1_Kind = Arg_Scal and Arg1_Sign = Type_Log then + Predefined := Iir_Predefined_Ieee_Numeric_Std_Match_Log; + elsif Arg1_Kind = Arg_Vect then + case Arg1_Sign is + when Type_Unsigned => + Predefined := Iir_Predefined_Ieee_Numeric_Std_Match_Uns; + when Type_Signed => + Predefined := Iir_Predefined_Ieee_Numeric_Std_Match_Sgn; + when Type_Suv => + Predefined := Iir_Predefined_Ieee_Numeric_Std_Match_Suv; + when Type_Slv => + Predefined := Iir_Predefined_Ieee_Numeric_Std_Match_Slv; + when Type_Log => + raise Error; + end case; + else + raise Error; + end if; + + Set_Implicit_Definition (Decl, Predefined); + end Handle_Std_Match; begin Decl := Get_Declaration_Chain (Pkg_Decl); @@ -537,6 +567,8 @@ package body Vhdl.Ieee.Numeric is Handle_To_Signed; when Name_Resize => Handle_Resize; + when Name_Std_Match => + Handle_Std_Match; when others => null; end case; diff --git a/src/vhdl/vhdl-ieee-std_logic_1164.adb b/src/vhdl/vhdl-ieee-std_logic_1164.adb index 14468e1c4..7ea7da787 100644 --- a/src/vhdl/vhdl-ieee-std_logic_1164.adb +++ b/src/vhdl/vhdl-ieee-std_logic_1164.adb @@ -250,11 +250,21 @@ package body Vhdl.Ieee.Std_Logic_1164 is end case; Set_Implicit_Definition (Decl, Predefined); end; - elsif Is_Scalar_Function (Decl) - and then Get_Identifier (Decl) = Name_Not - then - Set_Implicit_Definition - (Decl, Iir_Predefined_Ieee_1164_Scalar_Not); + elsif Is_Scalar_Function (Decl) then + declare + Predefined : Iir_Predefined_Functions; + begin + case Get_Identifier (Decl) is + when Name_Not => + Predefined := Iir_Predefined_Ieee_1164_Scalar_Not; + when Name_Op_Condition => + Predefined := + Iir_Predefined_Ieee_1164_Condition_Operator; + when others => + Predefined := Iir_Predefined_None; + end case; + Set_Implicit_Definition (Decl, Predefined); + end; elsif Is_Vector_Vector_Function (Decl) then declare Predefined : Iir_Predefined_Functions; diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads index 41ef5fd9e..3a2bcb20b 100644 --- a/src/vhdl/vhdl-nodes.ads +++ b/src/vhdl/vhdl-nodes.ads @@ -4905,6 +4905,8 @@ package Vhdl.Nodes is Iir_Predefined_Ieee_1164_Vector_And_Reduce, Iir_Predefined_Ieee_1164_Vector_Or_Reduce, + Iir_Predefined_Ieee_1164_Condition_Operator, + -- Numeric_Std. -- Abbreviations: -- Uns: Unsigned, Sgn: Signed, Nat: Natural, Int: Integer. @@ -5003,6 +5005,13 @@ package Vhdl.Nodes is Iir_Predefined_Ieee_Numeric_Std_Neg_Uns, Iir_Predefined_Ieee_Numeric_Std_Neg_Sgn, + -- Std_Match functions. + Iir_Predefined_Ieee_Numeric_Std_Match_Log, + Iir_Predefined_Ieee_Numeric_Std_Match_Uns, + Iir_Predefined_Ieee_Numeric_Std_Match_Sgn, + Iir_Predefined_Ieee_Numeric_Std_Match_Slv, + Iir_Predefined_Ieee_Numeric_Std_Match_Suv, + -- Math_Real Iir_Predefined_Ieee_Math_Real_Ceil, Iir_Predefined_Ieee_Math_Real_Log2, |