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Diffstat (limited to 'src/vhdl/translate/trans-chap12.adb')
| -rw-r--r-- | src/vhdl/translate/trans-chap12.adb | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/src/vhdl/translate/trans-chap12.adb b/src/vhdl/translate/trans-chap12.adb index 920271fa0..9522b5cd2 100644 --- a/src/vhdl/translate/trans-chap12.adb +++ b/src/vhdl/translate/trans-chap12.adb @@ -424,10 +424,7 @@ package body Trans.Chap12 is -- Write to file FILELIST all the files that are needed to link the design. procedure Gen_Stubs is - use Interfaces.C_Streams; - use System; use Configuration; - use Name_Table; -- Add all dependences of UNIT. -- UNIT is not used, but added during link. @@ -595,7 +592,6 @@ package body Trans.Chap12 is Filelist : String; Whole : Boolean) is - use Name_Table; use Configuration; Unit : Iir_Design_Unit; |