diff options
Diffstat (limited to 'src/synth')
| -rw-r--r-- | src/synth/elab-vhdl_context.adb | 43 | ||||
| -rw-r--r-- | src/synth/elab-vhdl_context.ads | 25 | ||||
| -rw-r--r-- | src/synth/elab-vhdl_debug.adb | 2 | ||||
| -rw-r--r-- | src/synth/elab-vhdl_expr.adb | 128 | ||||
| -rw-r--r-- | src/synth/elab-vhdl_expr.ads | 2 | ||||
| -rw-r--r-- | src/synth/elab-vhdl_insts.adb | 10 | ||||
| -rw-r--r-- | src/synth/elab-vhdl_values-debug.adb | 3 | ||||
| -rw-r--r-- | src/synth/elab-vhdl_values.adb | 26 | ||||
| -rw-r--r-- | src/synth/elab-vhdl_values.ads | 13 | ||||
| -rw-r--r-- | src/synth/synth-vhdl_context.adb | 3 | ||||
| -rw-r--r-- | src/synth/synth-vhdl_expr.adb | 39 | ||||
| -rw-r--r-- | src/synth/synth-vhdl_expr.ads | 2 | ||||
| -rw-r--r-- | src/synth/synth-vhdl_insts.adb | 3 | ||||
| -rw-r--r-- | src/synth/synth-vhdl_oper.adb | 14 | ||||
| -rw-r--r-- | src/synth/synth-vhdl_stmts.adb | 37 | ||||
| -rw-r--r-- | src/synth/synth-vhdl_stmts.ads | 19 |
16 files changed, 325 insertions, 44 deletions
diff --git a/src/synth/elab-vhdl_context.adb b/src/synth/elab-vhdl_context.adb index 136cc50f0..56de0563e 100644 --- a/src/synth/elab-vhdl_context.adb +++ b/src/synth/elab-vhdl_context.adb @@ -53,6 +53,7 @@ package body Elab.Vhdl_Context is new Synth_Instance_Type'(Max_Objs => Global_Info.Nbr_Objects, Is_Const => False, Is_Error => False, + Flag1 | Flag2 => False, Id => Inst_Tables.Last + 1, Block_Scope => Global_Info, Up_Block => null, @@ -101,6 +102,7 @@ package body Elab.Vhdl_Context is Res := new Synth_Instance_Type'(Max_Objs => Nbr_Objs, Is_Const => False, Is_Error => False, + Flag1 | Flag2 => False, Id => Inst_Tables.Last + 1, Block_Scope => Scope, Up_Block => Parent, @@ -142,6 +144,7 @@ package body Elab.Vhdl_Context is Res := new Synth_Instance_Type'(Max_Objs => Object_Slot_Type (Len), Is_Const => False, Is_Error => False, + Flag1 | Flag2 => False, Id => Inst_Tables.Last + 1, Block_Scope => Info, Up_Block => Parent, @@ -237,6 +240,28 @@ package body Elab.Vhdl_Context is return Inst.Foreign; end Get_Instance_Foreign; + procedure Set_Indiv_Signal_Assoc_Flag (Inst : Synth_Instance_Acc) is + begin + Inst.Flag1 := True; + end Set_Indiv_Signal_Assoc_Flag; + + function Get_Indiv_Signal_Assoc_Flag (Inst : Synth_Instance_Acc) + return Boolean is + begin + return Inst.Flag1; + end Get_Indiv_Signal_Assoc_Flag; + + procedure Set_Indiv_Signal_Assoc_Parent_Flag (Inst : Synth_Instance_Acc) is + begin + Inst.Flag2 := True; + end Set_Indiv_Signal_Assoc_Parent_Flag; + + function Get_Indiv_Signal_Assoc_Parent_Flag (Inst : Synth_Instance_Acc) + return Boolean is + begin + return Inst.Flag2; + end Get_Indiv_Signal_Assoc_Parent_Flag; + procedure Add_Extra_Instance (Inst : Synth_Instance_Acc; Extra : Synth_Instance_Acc) is begin @@ -590,15 +615,21 @@ package body Elab.Vhdl_Context is end case; end Get_Instance_By_Scope; - function Get_Parent_Scope (Blk : Node) return Sim_Info_Acc + function Get_Info_Scope (Blk : Node) return Sim_Info_Acc is - Parent : Node; + N : Node; begin - Parent := Get_Parent (Blk); - if Get_Kind (Parent) = Iir_Kind_Architecture_Body then - Parent := Vhdl.Utils.Get_Entity (Parent); + if Get_Kind (Blk) = Iir_Kind_Architecture_Body then + N := Vhdl.Utils.Get_Entity (Blk); + else + N := Blk; end if; - return Get_Info (Parent); + return Get_Info (N); + end Get_Info_Scope; + + function Get_Parent_Scope (Blk : Node) return Sim_Info_Acc is + begin + return Get_Info_Scope (Get_Parent (Blk)); end Get_Parent_Scope; function Get_Value (Syn_Inst: Synth_Instance_Acc; Obj : Node) diff --git a/src/synth/elab-vhdl_context.ads b/src/synth/elab-vhdl_context.ads index 8598bbf56..3a85cd089 100644 --- a/src/synth/elab-vhdl_context.ads +++ b/src/synth/elab-vhdl_context.ads @@ -74,6 +74,8 @@ package Elab.Vhdl_Context is procedure Set_Error (Inst : Synth_Instance_Acc); + -- Get/Set the const flag. + -- This is for subprograms, and set when all parameters are static. function Get_Instance_Const (Inst : Synth_Instance_Acc) return Boolean; procedure Set_Instance_Const (Inst : Synth_Instance_Acc; Val : Boolean); @@ -90,6 +92,19 @@ package Elab.Vhdl_Context is procedure Set_Instance_Foreign (Inst : Synth_Instance_Acc; N : Int32); function Get_Instance_Foreign (Inst : Synth_Instance_Acc) return Int32; + -- For simulation: set a flag if a signal parameter has individual + -- association. In that case, the value of the parameter must be + -- updated after a wait statement. + procedure Set_Indiv_Signal_Assoc_Flag (Inst : Synth_Instance_Acc); + function Get_Indiv_Signal_Assoc_Flag (Inst : Synth_Instance_Acc) + return Boolean; + + -- For simulation: set if a parent has the Indiv_Signal_Assoc_Flag set. + -- In that case, update must continue in the parent. + procedure Set_Indiv_Signal_Assoc_Parent_Flag (Inst : Synth_Instance_Acc); + function Get_Indiv_Signal_Assoc_Parent_Flag (Inst : Synth_Instance_Acc) + return Boolean; + -- Add/Get extra instances. -- Those instances are verification units. procedure Add_Extra_Instance (Inst : Synth_Instance_Acc; @@ -175,6 +190,9 @@ package Elab.Vhdl_Context is function Get_Component_Instance (Syn_Inst : Synth_Instance_Acc) return Synth_Instance_Acc; + -- Return the scope of BLK. Deals with architecture bodies. + function Get_Info_Scope (Blk : Node) return Sim_Info_Acc; + -- Return the scope of the parent of BLK. Deals with architecture bodies. function Get_Parent_Scope (Blk : Node) return Sim_Info_Acc; @@ -233,6 +251,13 @@ private -- of this instance. Is_Error : Boolean; + -- For simulation: set if a subprogram has a signal parameter + -- associated by individual elements. + Flag1 : Boolean; + + -- For simulation: set if a parent instance has Flag1 set. + Flag2 : Boolean; + Id : Instance_Id_Type; -- The corresponding info for this instance. diff --git a/src/synth/elab-vhdl_debug.adb b/src/synth/elab-vhdl_debug.adb index d47c310f0..e5e40011e 100644 --- a/src/synth/elab-vhdl_debug.adb +++ b/src/synth/elab-vhdl_debug.adb @@ -280,6 +280,8 @@ package body Elab.Vhdl_Debug is Disp_Memtyp (Get_Memtyp (Vt), Vtype); when Value_Dyn_Alias => Put ("dyn alias"); + when Value_Sig_Val => + Put ("sig val"); when Value_Memory => Disp_Memtyp (Get_Memtyp (Vt), Vtype); end case; diff --git a/src/synth/elab-vhdl_expr.adb b/src/synth/elab-vhdl_expr.adb index ee15c7e52..d9ad9f27d 100644 --- a/src/synth/elab-vhdl_expr.adb +++ b/src/synth/elab-vhdl_expr.adb @@ -23,6 +23,7 @@ with Str_Table; with Netlists; with Vhdl.Errors; use Vhdl.Errors; +with Vhdl.Scanner; with Vhdl.Utils; use Vhdl.Utils; with Vhdl.Evaluation; use Vhdl.Evaluation; @@ -36,7 +37,9 @@ with Synth.Vhdl_Eval; use Synth.Vhdl_Eval; with Synth.Errors; use Synth.Errors; with Grt.Types; +with Grt.Vhdl_Types; with Grt.To_Strings; +with Grt.Vstrings; package body Elab.Vhdl_Expr is function Synth_Bounds_From_Length (Atype : Node; Len : Int32) @@ -124,17 +127,48 @@ package body Elab.Vhdl_Expr is end if; declare - Str : constant String := Value_To_String (V); + Value : constant String := Value_To_String (V); + First, Last : Integer; Res_N : Node; Val : Int64; begin + -- LRM93 14.1 Predefined attributes. + -- Leading and trailing whitespace are ignored. + First := Value'First; + Last := Value'Last; + while First <= Last loop + exit when not Vhdl.Scanner.Is_Whitespace (Value (First)); + First := First + 1; + end loop; + while Last >= First loop + exit when not Vhdl.Scanner.Is_Whitespace (Value (Last)); + Last := Last - 1; + end loop; + case Get_Kind (Btype) is when Iir_Kind_Enumeration_Type_Definition => - Res_N := Eval_Value_Attribute (Str, Etype, Attr); + Res_N := Eval_Value_Attribute + (Value (First .. Last), Etype, Attr); Val := Int64 (Get_Enum_Pos (Res_N)); Free_Iir (Res_N); when Iir_Kind_Integer_Type_Definition => - Val := Int64'Value (Str); + declare + use Grt.To_Strings; + use Grt.Types; + use Grt.Vhdl_Types; + Value1 : String renames Value (First .. Last); + Res : Value_I64_Result; + begin + Res := Value_I64 (To_Std_String_Basep (Value1'Address), + Value1'Length, 0); + if Res.Status = Value_Ok then + Val := Int64 (Res.Val); + else + Error_Msg_Synth + (Syn_Inst, Attr, "incorrect 'value string"); + return No_Valtyp; + end if; + end; when others => Error_Msg_Elab (+Attr, "unhandled type for 'value"); return No_Valtyp; @@ -420,4 +454,92 @@ package body Elab.Vhdl_Expr is return Res; end Exec_String_Literal; + function Exec_Path_Instance_Name_Attribute + (Inst : Synth_Instance_Acc; Attr : Iir) return Memtyp + is + use Grt.Vstrings; + use Name_Table; + + Is_Instance : constant Boolean := + Get_Kind (Attr) = Iir_Kind_Instance_Name_Attribute; + + Atype : constant Node := Get_Type (Attr); + Str_Typ : constant Type_Acc := Get_Subtype_Object (Inst, Atype); + Name : constant Path_Instance_Name_Type := + Get_Path_Instance_Name_Suffix (Attr); + Instance, Parent : Synth_Instance_Acc; + Rstr : Rstring; + Label : Node; + begin + if Name.Path_Instance = Null_Iir then + return String_To_Memtyp (Name.Suffix, Str_Typ); + end if; + + Instance := Get_Instance_By_Scope + (Inst, Get_Info_Scope (Name.Path_Instance)); + + loop + Parent := Get_Instance_Parent (Instance); + if Parent = Root_Instance then + Parent := null; + end if; + Label := Get_Source_Scope (Instance); + + case Get_Kind (Label) is + when Iir_Kind_Entity_Declaration => + if Parent = null then + Prepend (Rstr, Image (Get_Identifier (Label))); + exit; + end if; + when Iir_Kind_Architecture_Body => + if Is_Instance then + Prepend (Rstr, ')'); + Prepend (Rstr, Image (Get_Identifier (Label))); + Prepend (Rstr, '('); + end if; + + if Is_Instance or else Parent = null then + Prepend (Rstr, Image (Get_Identifier (Get_Entity (Label)))); + end if; + if Parent = null then + Prepend (Rstr, ':'); + exit; + end if; + when Iir_Kind_Block_Statement => + Prepend (Rstr, Image (Get_Label (Label))); + Prepend (Rstr, ':'); + when Iir_Kind_Iterator_Declaration => + declare + Val : Valtyp; + begin + Val := Get_Value (Instance, Label); + Prepend (Rstr, ')'); + Prepend (Rstr, + Synth_Image_Attribute_Str (Val, Get_Type (Label))); + Prepend (Rstr, '('); + end; + when Iir_Kind_Generate_Statement_Body => + Prepend (Rstr, Image (Get_Label (Get_Parent (Label)))); + Prepend (Rstr, ':'); + when Iir_Kind_Component_Instantiation_Statement => + if Is_Instance then + Prepend (Rstr, '@'); + end if; + Prepend (Rstr, Image (Get_Label (Label))); + Prepend (Rstr, ':'); + when others => + Error_Kind ("Execute_Path_Instance_Name_Attribute", + Label); + end case; + Instance := Parent; + end loop; + declare + Str1 : String (1 .. Length (Rstr)); + Len1 : Natural; + begin + Copy (Rstr, Str1, Len1); + Free (Rstr); + return String_To_Memtyp (Str1 & ':' & Name.Suffix, Str_Typ); + end; + end Exec_Path_Instance_Name_Attribute; end Elab.Vhdl_Expr; diff --git a/src/synth/elab-vhdl_expr.ads b/src/synth/elab-vhdl_expr.ads index 3ef89d02c..244f89154 100644 --- a/src/synth/elab-vhdl_expr.ads +++ b/src/synth/elab-vhdl_expr.ads @@ -55,6 +55,8 @@ package Elab.Vhdl_Expr is return Valtyp; function Exec_Instance_Name_Attribute (Syn_Inst : Synth_Instance_Acc; Attr : Node) return Valtyp; + function Exec_Path_Instance_Name_Attribute + (Inst : Synth_Instance_Acc; Attr : Iir) return Memtyp; function Exec_Simple_Aggregate (Syn_Inst : Synth_Instance_Acc; Aggr : Node) return Valtyp; diff --git a/src/synth/elab-vhdl_insts.adb b/src/synth/elab-vhdl_insts.adb index be7d5a7d5..389a816a4 100644 --- a/src/synth/elab-vhdl_insts.adb +++ b/src/synth/elab-vhdl_insts.adb @@ -910,11 +910,17 @@ package body Elab.Vhdl_Insts is Em : Mark_Type; Val : Valtyp; Inter_Typ : Type_Acc; + Defval : Node; begin Mark_Expr_Pool (Em); Inter_Typ := Elab_Declaration_Type (Top_Inst, Inter); - Val := Synth_Expression_With_Type - (Top_Inst, Get_Default_Value (Inter), Inter_Typ); + Defval := Get_Default_Value (Inter); + if Defval /= Null_Node then + Val := Synth_Expression_With_Type (Top_Inst, Defval, Inter_Typ); + else + -- Only for simulation, expect override. + Val := Create_Value_Default (Inter_Typ); + end if; pragma Assert (Is_Static (Val.Val)); Val := Unshare (Val, Instance_Pool); Val.Typ := Unshare_Type_Instance (Val.Typ, Inter_Typ); diff --git a/src/synth/elab-vhdl_values-debug.adb b/src/synth/elab-vhdl_values-debug.adb index aec0b1e20..c995c0204 100644 --- a/src/synth/elab-vhdl_values-debug.adb +++ b/src/synth/elab-vhdl_values-debug.adb @@ -324,6 +324,9 @@ package body Elab.Vhdl_Values.Debug is when Value_Dyn_Alias => Put ("dyn alias: "); Debug_Typ1 (V.Typ); + when Value_Sig_Val => + Put ("sig val: "); + Debug_Typ1 (V.Typ); end case; end Debug_Valtyp; diff --git a/src/synth/elab-vhdl_values.adb b/src/synth/elab-vhdl_values.adb index 045fcce2e..deb0d0ccb 100644 --- a/src/synth/elab-vhdl_values.adb +++ b/src/synth/elab-vhdl_values.adb @@ -34,6 +34,7 @@ package body Elab.Vhdl_Values is | Value_Wire | Value_Signal | Value_Dyn_Alias + | Value_Sig_Val | Value_Quantity | Value_Terminal => return False; @@ -268,6 +269,26 @@ package body Elab.Vhdl_Values is end if; end Strip_Const; + function Create_Value_Sig_Val (Sigs : Memory_Ptr; + Vals : Memory_Ptr; + Pool : Areapool_Acc) return Value_Acc + is + subtype Value_Type_Sig_Val is Value_Type (Value_Sig_Val); + function Alloc is new Areapools.Alloc_On_Pool_Addr (Value_Type_Sig_Val); + begin + return To_Value_Acc (Alloc (Pool, (Kind => Value_Sig_Val, + I_Sigs => Sigs, + I_Vals => Vals))); + end Create_Value_Sig_Val; + + function Create_Value_Sig_Val (Sigs : Memory_Ptr; + Vals : Memory_Ptr; + Typ : Type_Acc; + Pool : Areapool_Acc) return Valtyp is + begin + return (Typ, Create_Value_Sig_Val (Sigs, Vals, Pool)); + end Create_Value_Sig_Val; + procedure Write_Value (Dest : Memory_Ptr; Vt : Valtyp) is Mt : Memtyp; @@ -315,6 +336,8 @@ package body Elab.Vhdl_Values is Src.Val.D_Poff, Src.Val.D_Ptyp, Src.Val.D_Voff, Src.Val.D_Eoff, Current_Pool)); + when Value_Sig_Val => + raise Internal_Error; end case; return Res; end Copy; @@ -545,7 +568,8 @@ package body Elab.Vhdl_Values is when Value_Net | Value_Wire | Value_Signal - | Value_Dyn_Alias => + | Value_Dyn_Alias + | Value_Sig_Val => raise Internal_Error; when Value_Memory => return (V.Typ, V.Val.Mem); diff --git a/src/synth/elab-vhdl_values.ads b/src/synth/elab-vhdl_values.ads index 4ed86da22..0e72fd128 100644 --- a/src/synth/elab-vhdl_values.ads +++ b/src/synth/elab-vhdl_values.ads @@ -60,7 +60,10 @@ package Elab.Vhdl_Values is Value_Alias, -- Used only for associations. - Value_Dyn_Alias + Value_Dyn_Alias, + + -- Used only for individual signal associations in simulation + Value_Sig_Val ); type Value_Type (Kind : Value_Kind); @@ -114,6 +117,9 @@ package Elab.Vhdl_Values is D_Ptyp : Type_Acc; -- Type of the prefix (after offset). D_Voff : Uns32; -- Variable offset D_Eoff : Uns32; -- Fixed offset. + when Value_Sig_Val => + I_Sigs : Memory_Ptr; + I_Vals : Memory_Ptr; end case; end record; @@ -187,6 +193,11 @@ package Elab.Vhdl_Values is function Create_Value_Const (Val : Valtyp; Loc : Node; Pool : Areapool_Acc) return Valtyp; + function Create_Value_Sig_Val (Sigs : Memory_Ptr; + Vals : Memory_Ptr; + Typ : Type_Acc; + Pool : Areapool_Acc) return Valtyp; + -- If VAL is a const, replace it by its value. procedure Strip_Const (Vt : in out Valtyp); diff --git a/src/synth/synth-vhdl_context.adb b/src/synth/synth-vhdl_context.adb index 81143bea9..7d05e203a 100644 --- a/src/synth/synth-vhdl_context.adb +++ b/src/synth/synth-vhdl_context.adb @@ -464,7 +464,8 @@ package body Synth.Vhdl_Context is return True; when Value_Net | Value_Signal - | Value_Dyn_Alias => + | Value_Dyn_Alias + | Value_Sig_Val => return False; when Value_Quantity | Value_Terminal => diff --git a/src/synth/synth-vhdl_expr.adb b/src/synth/synth-vhdl_expr.adb index 036e5a27e..6e397aa1a 100644 --- a/src/synth/synth-vhdl_expr.adb +++ b/src/synth/synth-vhdl_expr.adb @@ -2060,6 +2060,7 @@ package body Synth.Vhdl_Expr is Res := Synth_Name (Syn_Inst, Expr); if Res.Val /= null then if (Res.Val.Kind = Value_Signal + or else Res.Val.Kind = Value_Sig_Val or else (Res.Val.Kind = Value_Alias and then Res.Val.A_Obj.Kind = Value_Signal)) then @@ -2316,6 +2317,7 @@ package body Synth.Vhdl_Expr is declare Param : constant Node := Get_Parameter (Expr); V : Valtyp; + Vi : Int64; Dtype : Type_Acc; begin Dtype := Get_Subtype_Object (Syn_Inst, Get_Type (Expr)); @@ -2323,10 +2325,16 @@ package body Synth.Vhdl_Expr is -- FIXME: to be generalized. Not always as simple as a -- subtype conversion. if Is_Static (V.Val) then - V := Create_Value_Discrete (Read_Discrete (V), Dtype); + Vi := Read_Discrete (V); + if not In_Range (Dtype.Drange, Vi) then + Error_Msg_Synth (Syn_Inst, Expr, "value out of range"); + return No_Valtyp; + end if; + return Create_Value_Discrete (Vi, Dtype); + else + return Synth_Subtype_Conversion + (Syn_Inst, V, Dtype, False, Expr); end if; - return Synth_Subtype_Conversion - (Syn_Inst, V, Dtype, False, Expr); end; when Iir_Kind_Low_Type_Attribute => return Synth_Low_High_Type_Attribute (Syn_Inst, Expr, Dir_To); @@ -2366,9 +2374,15 @@ package body Synth.Vhdl_Expr is return Elab.Vhdl_Expr.Exec_Value_Attribute (Syn_Inst, Expr); when Iir_Kind_Image_Attribute => return Elab.Vhdl_Expr.Exec_Image_Attribute (Syn_Inst, Expr); - when Iir_Kind_Instance_Name_Attribute => - return Elab.Vhdl_Expr.Exec_Instance_Name_Attribute - (Syn_Inst, Expr); + when Iir_Kind_Path_Name_Attribute + | Iir_Kind_Instance_Name_Attribute => + declare + Mt : Memtyp; + begin + Mt := Elab.Vhdl_Expr.Exec_Path_Instance_Name_Attribute + (Syn_Inst, Expr); + return Create_Value_Memtyp (Mt); + end; when Iir_Kind_Null_Literal => return Create_Value_Access (Null_Heap_Index, Expr_Type); when Iir_Kind_Allocator_By_Subtype => @@ -2422,6 +2436,19 @@ package body Synth.Vhdl_Expr is end if; Error_Msg_Synth (Syn_Inst, Expr, "active attribute not allowed"); return No_Valtyp; + when Iir_Kind_Driving_Attribute => + if Hook_Driving_Attribute /= null then + return Hook_Driving_Attribute (Syn_Inst, Expr); + end if; + Error_Msg_Synth (Syn_Inst, Expr, "driving attribute not allowed"); + return No_Valtyp; + when Iir_Kind_Driving_Value_Attribute => + if Hook_Driving_Value_Attribute /= null then + return Hook_Driving_Value_Attribute (Syn_Inst, Expr); + end if; + Error_Msg_Synth (Syn_Inst, Expr, + "driving_value attribute not allowed"); + return No_Valtyp; when Iir_Kind_Last_Value_Attribute => if Hook_Last_Value_Attribute /= null then return Hook_Last_Value_Attribute (Syn_Inst, Expr); diff --git a/src/synth/synth-vhdl_expr.ads b/src/synth/synth-vhdl_expr.ads index 74412fe22..c991f388a 100644 --- a/src/synth/synth-vhdl_expr.ads +++ b/src/synth/synth-vhdl_expr.ads @@ -89,6 +89,8 @@ package Synth.Vhdl_Expr is function (Syn_Inst : Synth_Instance_Acc; Expr : Node) return Valtyp; Hook_Event_Attribute : Hook_Attribute_Acc; Hook_Active_Attribute : Hook_Attribute_Acc; + Hook_Driving_Attribute : Hook_Attribute_Acc; + Hook_Driving_Value_Attribute : Hook_Attribute_Acc; Hook_Last_Value_Attribute : Hook_Attribute_Acc; Hook_Last_Event_Attribute : Hook_Attribute_Acc; Hook_Last_Active_Attribute : Hook_Attribute_Acc; diff --git a/src/synth/synth-vhdl_insts.adb b/src/synth/synth-vhdl_insts.adb index fc9788f78..88f023354 100644 --- a/src/synth/synth-vhdl_insts.adb +++ b/src/synth/synth-vhdl_insts.adb @@ -230,7 +230,8 @@ package body Synth.Vhdl_Insts is | Value_File | Value_Quantity | Value_Terminal - | Value_Dyn_Alias => + | Value_Dyn_Alias + | Value_Sig_Val => raise Internal_Error; end case; end Hash_Const; diff --git a/src/synth/synth-vhdl_oper.adb b/src/synth/synth-vhdl_oper.adb index b46a8ec57..5d5d9cb5c 100644 --- a/src/synth/synth-vhdl_oper.adb +++ b/src/synth/synth-vhdl_oper.adb @@ -1449,6 +1449,7 @@ package body Synth.Vhdl_Oper is | Iir_Predefined_Ieee_Numeric_Std_Add_Uns_Log | Iir_Predefined_Ieee_Numeric_Std_Add_Sgn_Log | Iir_Predefined_Ieee_Numeric_Std_Add_Log_Sgn + | Iir_Predefined_Ieee_Numeric_Std_Unsigned_Add_Slv_Slv | Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Log | Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Log_Slv | Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Slv @@ -1466,7 +1467,8 @@ package body Synth.Vhdl_Oper is | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Log_Sgn_Slv => -- "+" (Unsigned, Unsigned) return Synth_Dyadic_Uns_Uns (Ctxt, Id_Add, L, R, Expr); - when Iir_Predefined_Ieee_Numeric_Std_Add_Uns_Nat => + when Iir_Predefined_Ieee_Numeric_Std_Add_Uns_Nat + | Iir_Predefined_Ieee_Numeric_Std_Unsigned_Add_Slv_Nat => -- "+" (Unsigned, Natural) return Synth_Dyadic_Uns_Nat (Ctxt, Id_Add, L, R, Expr); when Iir_Predefined_Ieee_Std_Logic_Arith_Add_Uns_Int_Slv @@ -1475,6 +1477,7 @@ package body Synth.Vhdl_Oper is -- "+" (Unsigned, Integer) return Synth_Dyadic_Sgn_Int (Ctxt, Id_Add, L, R, Expr); when Iir_Predefined_Ieee_Numeric_Std_Add_Nat_Uns + | Iir_Predefined_Ieee_Numeric_Std_Unsigned_Add_Nat_Slv | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Int_Uns_Uns | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Int_Uns_Slv | Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Int_Slv => @@ -1511,6 +1514,7 @@ package body Synth.Vhdl_Oper is | Iir_Predefined_Ieee_Numeric_Std_Sub_Uns_Log | Iir_Predefined_Ieee_Numeric_Std_Sub_Sgn_Log | Iir_Predefined_Ieee_Numeric_Std_Sub_Log_Sgn + | Iir_Predefined_Ieee_Numeric_Std_Unsigned_Sub_Slv_Slv | Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Slv | Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Log_Slv | Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Log @@ -1534,7 +1538,8 @@ package body Synth.Vhdl_Oper is | Iir_Predefined_Ieee_Std_Logic_Signed_Sub_Slv_Slv => -- "-" (Signed, Signed) return Synth_Dyadic_Sgn_Sgn (Ctxt, Id_Sub, L, R, Expr); - when Iir_Predefined_Ieee_Numeric_Std_Sub_Uns_Nat => + when Iir_Predefined_Ieee_Numeric_Std_Sub_Uns_Nat + | Iir_Predefined_Ieee_Numeric_Std_Unsigned_Sub_Slv_Nat => -- "-" (Unsigned, Natural) return Synth_Dyadic_Uns_Nat (Ctxt, Id_Sub, L, R, Expr); when Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Uns_Int_Uns @@ -1543,6 +1548,7 @@ package body Synth.Vhdl_Oper is -- "-" (Unsigned, Integer) return Synth_Dyadic_Sgn_Int (Ctxt, Id_Sub, L, R, Expr); when Iir_Predefined_Ieee_Numeric_Std_Sub_Nat_Uns + | Iir_Predefined_Ieee_Numeric_Std_Unsigned_Sub_Nat_Slv | Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Int_Uns_Uns | Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Int_Uns_Slv | Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Int_Slv => @@ -1985,7 +1991,8 @@ package body Synth.Vhdl_Oper is | Iir_Predefined_Ieee_Numeric_Std_To_01_Uns | Iir_Predefined_Ieee_Numeric_Std_To_01_Sgn | Iir_Predefined_Ieee_1164_To_X01_Slv - | Iir_Predefined_Ieee_1164_To_UX01_Slv => + | Iir_Predefined_Ieee_1164_To_UX01_Slv + | Iir_Predefined_Ieee_1164_To_X01Z_Slv => if Is_Static (L.Val) then raise Internal_Error; end if; @@ -1994,6 +2001,7 @@ package body Synth.Vhdl_Oper is when Iir_Predefined_Ieee_1164_To_Bit | Iir_Predefined_Ieee_1164_To_X01_Log | Iir_Predefined_Ieee_1164_To_UX01_Log + | Iir_Predefined_Ieee_1164_To_X01Z_Log | Iir_Predefined_Ieee_1164_To_Stdulogic => -- A no-op. return Create_Value_Net (Get_Net (Ctxt, L), Res_Typ); diff --git a/src/synth/synth-vhdl_stmts.adb b/src/synth/synth-vhdl_stmts.adb index 58e04afad..bba8c823b 100644 --- a/src/synth/synth-vhdl_stmts.adb +++ b/src/synth/synth-vhdl_stmts.adb @@ -466,7 +466,8 @@ package body Synth.Vhdl_Stmts is -- Need to reverse offsets. Copy_Memory (Res.Val.Mem, - Val.Val.Mem + (Val.Typ.Sz - Size_Type (Off + 1) * El_Typ.Sz), + Val.Val.Mem + + (Val.Typ.Sz - Typ.Sz - Size_Type (Off) * El_Typ.Sz), Typ.Sz); return Res; end; @@ -769,7 +770,8 @@ package body Synth.Vhdl_Stmts is | Value_Const | Value_Alias | Value_Dyn_Alias - | Value_Signal => + | Value_Signal + | Value_Sig_Val => raise Internal_Error; end case; when Target_Aggregate => @@ -2030,17 +2032,6 @@ package body Synth.Vhdl_Stmts is return Count; end Count_Individual_Associations; - type Assoc_Record is record - Formal : Node; - Form_Off : Value_Offsets; - - Act_Base : Valtyp; - Act_Typ : Type_Acc; - Act_Off : Value_Offsets; - Act_Dyn : Dyn_Name; - end record; - - type Assoc_Array is array (Natural range <>) of Assoc_Record; type Assoc_Array_Acc is access Assoc_Array; procedure Free_Assoc_Array is new Ada.Unchecked_Deallocation (Assoc_Array, Assoc_Array_Acc); @@ -2144,18 +2135,24 @@ package body Synth.Vhdl_Stmts is A.Act_Typ.Sz); end; end loop; - declare - D : Destroy_Type; - begin - Destroy_Init (D, Subprg_Inst); - Destroy_Object (D, Inter); - Destroy_Finish (D); - end; + elsif Flags.Flag_Simulation then + Res := Hook_Create_Value_For_Signal_Individual_Assocs + (Subprg_Inst, Assocs.all, Formal_Typ); else Res := No_Valtyp; raise Internal_Error; end if; + -- Destroy the object. It will be recreated by + -- Synth_Subprogram_Association. + declare + D : Destroy_Type; + begin + Destroy_Init (D, Subprg_Inst); + Destroy_Object (D, Inter); + Destroy_Finish (D); + end; + Free_Assoc_Array (Assocs); return Res; diff --git a/src/synth/synth-vhdl_stmts.ads b/src/synth/synth-vhdl_stmts.ads index c07dc7224..ac9cd13d8 100644 --- a/src/synth/synth-vhdl_stmts.ads +++ b/src/synth/synth-vhdl_stmts.ads @@ -211,6 +211,25 @@ package Synth.Vhdl_Stmts is Val : Valtyp; Loc : Node); + type Assoc_Record is record + Formal : Node; + Form_Off : Value_Offsets; + + Act_Base : Valtyp; + Act_Typ : Type_Acc; + Act_Off : Value_Offsets; + Act_Dyn : Dyn_Name; + end record; + + type Assoc_Array is array (Natural range <>) of Assoc_Record; + + -- For simulation: create a value for individual signal associations. + type Create_Value_For_Signal_Individual_Assocs_Acc is + access function (Inst : Synth_Instance_Acc; + Assocs : Assoc_Array; + Typ : Type_Acc) return Valtyp; + Hook_Create_Value_For_Signal_Individual_Assocs : + Create_Value_For_Signal_Individual_Assocs_Acc; private -- There are 2 execution mode: |