1 files changed, 13 insertions, 13 deletions
diff --git a/src/synth/synth-expr.adb b/src/synth/synth-expr.adb
index cbc9f87d2..7a682dbff 100644
--- a/src/synth/synth-expr.adb
+++ b/src/synth/synth-expr.adb
@@ -21,7 +21,7 @@
 with Ada.Unchecked_Conversion;
 with Ada.Unchecked_Deallocation;
 with Std_Names;
-with Ieee.Std_Logic_1164;
+with Vhdl.Ieee.Std_Logic_1164;
 with Vhdl.Std_Package;
 with Errorout; use Errorout;
 with Simul.Execution;
@@ -85,21 +85,21 @@ package body Synth.Expr is
          when Iir_Value_E8 =>
             --  Std_logic.
             case Lit.E8 is
-               when Ieee.Std_Logic_1164.Std_Logic_0_Pos
-                 |  Ieee.Std_Logic_1164.Std_Logic_L_Pos =>
+               when Vhdl.Ieee.Std_Logic_1164.Std_Logic_0_Pos
+                 |  Vhdl.Ieee.Std_Logic_1164.Std_Logic_L_Pos =>
                   Val := 0;
                   Zx := 0;
-               when Ieee.Std_Logic_1164.Std_Logic_1_Pos
-                 |  Ieee.Std_Logic_1164.Std_Logic_H_Pos =>
+               when Vhdl.Ieee.Std_Logic_1164.Std_Logic_1_Pos
+                 |  Vhdl.Ieee.Std_Logic_1164.Std_Logic_H_Pos =>
                   Val := 1;
                   Zx := 0;
-               when Ieee.Std_Logic_1164.Std_Logic_U_Pos
-                 |  Ieee.Std_Logic_1164.Std_Logic_X_Pos
-                 |  Ieee.Std_Logic_1164.Std_Logic_D_Pos =>
+               when Vhdl.Ieee.Std_Logic_1164.Std_Logic_U_Pos
+                 |  Vhdl.Ieee.Std_Logic_1164.Std_Logic_X_Pos
+                 |  Vhdl.Ieee.Std_Logic_1164.Std_Logic_D_Pos =>
                   Val := 1;
                   Zx := 1;
-               when Ieee.Std_Logic_1164.Std_Logic_Z_Pos
-                 |  Ieee.Std_Logic_1164.Std_Logic_W_Pos =>
+               when Vhdl.Ieee.Std_Logic_1164.Std_Logic_Z_Pos
+                 |  Vhdl.Ieee.Std_Logic_1164.Std_Logic_W_Pos =>
                   Val := 0;
                   Zx := 1;
                when others =>
@@ -696,11 +696,11 @@ package body Synth.Expr is
       end if;
       Lit := Get_Named_Entity (Right);
       if Lit = Vhdl.Std_Package.Bit_0
-        or else Lit = Ieee.Std_Logic_1164.Std_Ulogic_0
+        or else Lit = Vhdl.Ieee.Std_Logic_1164.Std_Ulogic_0
       then
          Posedge := False;
       elsif Lit = Vhdl.Std_Package.Bit_1
-        or else Lit = Ieee.Std_Logic_1164.Std_Ulogic_1
+        or else Lit = Vhdl.Ieee.Std_Logic_1164.Std_Ulogic_1
       then
          Posedge := True;
       else
@@ -851,7 +851,7 @@ package body Synth.Expr is
                Imp : constant Iir := Get_Implementation (Expr);
                Clk : Net;
             begin
-               if Imp = Ieee.Std_Logic_1164.Rising_Edge then
+               if Imp = Vhdl.Ieee.Std_Logic_1164.Rising_Edge then
                   Clk := Get_Net
                     (Synth_Assoc_In
                        (Syn_Inst, Get_Parameter_Association_Chain (Expr)));