diff options
Diffstat (limited to 'pyGHDL/dom/DesignUnit.py')
-rw-r--r-- | pyGHDL/dom/DesignUnit.py | 44 |
1 files changed, 27 insertions, 17 deletions
diff --git a/pyGHDL/dom/DesignUnit.py b/pyGHDL/dom/DesignUnit.py index 9827cec24..dee86cab3 100644 --- a/pyGHDL/dom/DesignUnit.py +++ b/pyGHDL/dom/DesignUnit.py @@ -41,19 +41,24 @@ This module contains all DOM classes for VHDL's design units (:class:`context <E """ from pydecor import export -from pyVHDLModel.VHDLModel import Entity as VHDLModel_Entity -from pyVHDLModel.VHDLModel import Architecture as VHDLModel_Architecture -from pyVHDLModel.VHDLModel import Package as VHDLModel_Package -from pyVHDLModel.VHDLModel import PackageBody as VHDLModel_PackageBody -from pyVHDLModel.VHDLModel import Context as VHDLModel_Context +from pyVHDLModel.VHDLModel import Entity as VHDLModel_Entity +from pyVHDLModel.VHDLModel import Architecture as VHDLModel_Architecture +from pyVHDLModel.VHDLModel import Package as VHDLModel_Package +from pyVHDLModel.VHDLModel import PackageBody as VHDLModel_PackageBody +from pyVHDLModel.VHDLModel import Context as VHDLModel_Context from pyVHDLModel.VHDLModel import Configuration as VHDLModel_Configuration from pyGHDL.libghdl import utils from pyGHDL.libghdl.vhdl import nodes from pyGHDL.dom._Utils import NodeToName, GetIirKindOfNode -from pyGHDL.dom._Translate import GetExpressionFromNode, GetSubtypeIndicationFromNode, GetGenericsFromChainedNodes, GetPortsFromChainedNodes, \ - GetDeclaredItemsFromChainedNodes +from pyGHDL.dom._Translate import ( + GetExpressionFromNode, + GetSubtypeIndicationFromNode, + GetGenericsFromChainedNodes, + GetPortsFromChainedNodes, + GetDeclaredItemsFromChainedNodes, +) from pyGHDL.dom.Common import GHDLMixin, DOMException from pyGHDL.dom.Object import Constant, Signal @@ -62,19 +67,22 @@ __all__ = [] @export class Entity(VHDLModel_Entity, GHDLMixin): - @classmethod def parse(cls, libraryUnit): name = NodeToName(libraryUnit) entity = cls(name) - for generic in GetGenericsFromChainedNodes(nodes.Get_Generic_Chain(libraryUnit)): + for generic in GetGenericsFromChainedNodes( + nodes.Get_Generic_Chain(libraryUnit) + ): entity.GenericItems.append(generic) for port in GetPortsFromChainedNodes(nodes.Get_Port_Chain(libraryUnit)): entity.PortItems.append(port) - for item in GetDeclaredItemsFromChainedNodes(nodes.Get_Declaration_Chain(libraryUnit), "entity", name): + for item in GetDeclaredItemsFromChainedNodes( + nodes.Get_Declaration_Chain(libraryUnit), "entity", name + ): entity.DeclaredItems.append(item) return entity @@ -94,7 +102,9 @@ class Architecture(VHDLModel_Architecture, GHDLMixin): architecture = cls(name, entityName) - for item in GetDeclaredItemsFromChainedNodes(nodes.Get_Declaration_Chain(libraryUnit), "architecture", name): + for item in GetDeclaredItemsFromChainedNodes( + nodes.Get_Declaration_Chain(libraryUnit), "architecture", name + ): architecture.DeclaredItems.append(item) return architecture @@ -105,14 +115,15 @@ class Architecture(VHDLModel_Architecture, GHDLMixin): @export class Package(VHDLModel_Package, GHDLMixin): - @classmethod def parse(cls, libraryUnit): name = NodeToName(libraryUnit) package = cls(name) - for item in GetDeclaredItemsFromChainedNodes(nodes.Get_Declaration_Chain(libraryUnit), "package", name): + for item in GetDeclaredItemsFromChainedNodes( + nodes.Get_Declaration_Chain(libraryUnit), "package", name + ): package.DeclaredItems.append(item) return package @@ -120,14 +131,15 @@ class Package(VHDLModel_Package, GHDLMixin): @export class PackageBody(VHDLModel_PackageBody, GHDLMixin): - @classmethod def parse(cls, libraryUnit): name = NodeToName(libraryUnit) packageBody = cls(name) - for item in GetDeclaredItemsFromChainedNodes(nodes.Get_Declaration_Chain(libraryUnit), "package body", name): + for item in GetDeclaredItemsFromChainedNodes( + nodes.Get_Declaration_Chain(libraryUnit), "package body", name + ): packageBody.DeclaredItems.append(item) return packageBody @@ -135,7 +147,6 @@ class PackageBody(VHDLModel_PackageBody, GHDLMixin): @export class Context(VHDLModel_Context, GHDLMixin): - @classmethod def parse(cls, libraryUnit): name = NodeToName(libraryUnit) @@ -144,7 +155,6 @@ class Context(VHDLModel_Context, GHDLMixin): @export class Configuration(VHDLModel_Configuration, GHDLMixin): - @classmethod def parse(cls, libraryUnit): name = NodeToName(libraryUnit) |