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diff --git a/doc/using/Synthesis.rst b/doc/using/Synthesis.rst
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@@ -13,6 +13,17 @@ Hence, the netlists generated by GHDL are not optimised.
.. NOTE::
Due to GHDL's modular architecture (see :ref:`INT:Overview`), the synthesis kernel shares the VHDL parsing front-end with the simulation back-ends. Hence, available options for synthesis are the same as for analysis and/or simulation elaboration (see :ref:`GHDL:options`).
+.. HINT::
+ Multiple pragmas are supported for preventing blocks of code from being synthesized:
+
+ ``-- pragma|synopsys|synthesis (synthesis|translate)( |_)(on|off)``
+
+ For example:
+
+ - ``-- pragma translate off``
+ - ``-- synthesis translate_on``
+ - ``-- synopsys synthesis_off``
+
.. index:: synthesis command
.. _Synth:command: