1 files changed, 27 insertions, 2 deletions
diff --git a/doc/using/QuickStartGuide.rst b/doc/using/QuickStartGuide.rst
index baf6c6a52..4cbbe8027 100644
--- a/doc/using/QuickStartGuide.rst
+++ b/doc/using/QuickStartGuide.rst
@@ -52,7 +52,31 @@ To illustrate the large purpose of `VHDL`, here is a commented `'Hello world'` p
   * As a result, :option:`-r` is just a passthrough to the binary generated in the `elaboration`. Therefore, the executable can be run directly, :samp:`./hello_world`. See :option:`-r` for more informartion.
  
 .. HINT:: :option:`-e` can be bypassed with mcode, since :option:`-r` actually elaborates the design and saves it on memory before running the simulation. But you can still use it to check for some elaboration problems.
-  
+
+The `heartbeat` program
+=======================
+
+.. code-block:: VHDL
+
+  entity hello_world is
+    port ( clk: out std_logic; )
+  end hearbeat;
+
+  architecture behaviour of hello_world is
+  begin
+    -- Clock process definition
+    clk_process: process
+    begin
+      clk <= '0';
+      wait for clk_period/2;
+      clk <= '1';
+      wait for clk_period/2;
+    end process;
+  end behaviour;
+
+.. TODO:: Complete `heartbeat` example program
+ 
+
 A full adder
 ============
 
@@ -204,4 +228,5 @@ Further examples
 .. TODO::
 
   * Add references to examples/tutorials with GHDL.
-  * Shall `René Doß <https://mail.gna.org/public/ghdl-discuss/2017-01/msg00000.html>` want to contribute adapting his article to RST?
-\ No newline at end of file
+  * Shall `René Doß <https://mail.gna.org/public/ghdl-discuss/2017-01/msg00000.html>` want to contribute adapting his article to RST?
+  *  https://github.com/Obijuan/open-fpga-verilog-tutorial/wiki
+\ No newline at end of file