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@@ -41,6 +41,9 @@ GHDL aims at implementing VHDL as defined by `IEEE 1076 <http://ieeexplore.ieee.
Several third party projects are supported: `VUnit <https://vunit.github.io/>`_, `OSVVM <http://osvvm.org/>`_, `cocotb <https://github.com/potentialventures/cocotb>`_ (through the `VPI interface <https://en.wikipedia.org/wiki/Verilog_Procedural_Interface>`_), ...
+.. HINT::
+ Although synthesis is not supported yet, there is some experimental code. On the one hand, subcommand ``--synth`` is a proof-of-concept to generate a netlist (RTL) with GHDL. For now, it is a dump of an internal structure, so it is not very useful, except for debugging. In the future, it might be an EDIF or VHDL file. On the other hand, `ghdlsynth <https://github.com/tgingold/ghdlsynth-beta>`_ is a complementary repository that allows GHDL to be loaded by `yosys <http://www.clifford.at/yosys/>`_ as a module, which can be used to generate bitstreams for some FPGA devices.
+
.. _INTRO:WHO:
Who uses GHDL?