diff options
| -rw-r--r-- | src/files_map.adb | 7 | ||||
| -rw-r--r-- | src/files_map.ads | 7 | ||||
| -rw-r--r-- | src/ghdldrv/ghdllocal.adb | 4 | ||||
| -rw-r--r-- | src/ghdldrv/ghdlprint.adb | 12 | ||||
| -rw-r--r-- | src/psl/psl-nodes_priv.ads | 1 | ||||
| -rw-r--r-- | src/psl/psl-types.ads | 1 | ||||
| -rw-r--r-- | src/vhdl/translate/trans_analyzes.adb | 4 | ||||
| -rw-r--r-- | src/vhdl/vhdl-canon.adb | 4 | ||||
| -rw-r--r-- | src/vhdl/vhdl-flists.ads | 2 | ||||
| -rw-r--r-- | src/vhdl/vhdl-lists.ads | 2 | ||||
| -rw-r--r-- | src/vhdl/vhdl-nodes.ads | 4 | ||||
| -rw-r--r-- | src/vhdl/vhdl-parse_psl.adb | 2 | ||||
| -rw-r--r-- | src/vhdl/vhdl-prints.adb (renamed from src/vhdl/vhdl-disp_vhdl.adb) | 4 | ||||
| -rw-r--r-- | src/vhdl/vhdl-prints.ads (renamed from src/vhdl/vhdl-disp_vhdl.ads) | 4 | ||||
| -rw-r--r-- | src/vhdl/vhdl-sem_lib.adb | 6 | ||||
| -rw-r--r-- | src/vhdl/vhdl-sem_psl.adb | 136 | ||||
| -rw-r--r-- | src/vhdl/vhdl-types.ads | 3 |
17 files changed, 109 insertions, 94 deletions
diff --git a/src/files_map.adb b/src/files_map.adb index e93934ce2..d6ee415b1 100644 --- a/src/files_map.adb +++ b/src/files_map.adb @@ -626,9 +626,10 @@ package body Files_Map is return Create_Source_File_From_String (Name, ""); end Create_Virtual_Source_File; - function Create_Instance_Source_File - (Ref : Source_File_Entry; Loc : Location_Type; Inst : Vhdl.Types.Node) - return Source_File_Entry + function Create_Instance_Source_File (Ref : Source_File_Entry; + Loc : Location_Type; + Inst : Vhdl.Types.Vhdl_Node) + return Source_File_Entry is pragma Unreferenced (Inst); Base : Source_File_Entry; diff --git a/src/files_map.ads b/src/files_map.ads index a5a05e30e..2e0dd0ae2 100644 --- a/src/files_map.ads +++ b/src/files_map.ads @@ -70,9 +70,10 @@ package Files_Map is -- location LOC). The content of this file is the same as REF, but with -- new locations so that it is possible to retrieve the instance from -- the new locations. - function Create_Instance_Source_File - (Ref : Source_File_Entry; Loc : Location_Type; Inst : Vhdl.Types.Node) - return Source_File_Entry; + function Create_Instance_Source_File (Ref : Source_File_Entry; + Loc : Location_Type; + Inst : Vhdl.Types.Vhdl_Node) + return Source_File_Entry; -- Unload last source file. Works only with the last one. Must be -- carefully used as the corresponding locations will be reused. diff --git a/src/ghdldrv/ghdllocal.adb b/src/ghdldrv/ghdllocal.adb index 3aee26250..3b4884acb 100644 --- a/src/ghdldrv/ghdllocal.adb +++ b/src/ghdldrv/ghdllocal.adb @@ -27,7 +27,7 @@ with Vhdl.Std_Package; with Flags; with Name_Table; with Std_Names; -with Vhdl.Disp_Vhdl; +with Vhdl.Prints; with Default_Paths; with Vhdl.Scanner; with Errorout; @@ -1118,7 +1118,7 @@ package body Ghdllocal is end if; Flags.Bootstrap := True; Libraries.Load_Std_Library; - Vhdl.Disp_Vhdl.Disp_Vhdl (Vhdl.Std_Package.Std_Standard_Unit); + Vhdl.Prints.Disp_Vhdl (Vhdl.Std_Package.Std_Standard_Unit); end Perform_Action; -- Command --find-top. diff --git a/src/ghdldrv/ghdlprint.adb b/src/ghdldrv/ghdlprint.adb index 91168c023..7d232c697 100644 --- a/src/ghdldrv/ghdlprint.adb +++ b/src/ghdldrv/ghdlprint.adb @@ -37,7 +37,7 @@ with Vhdl.Xrefs; with Vhdl.Sem_Lib; use Vhdl.Sem_Lib; with Ghdlmain; use Ghdlmain; with Ghdllocal; use Ghdllocal; -with Vhdl.Disp_Vhdl; +with Vhdl.Prints; with Vhdl.Elocations; package body Ghdlprint is @@ -1024,17 +1024,23 @@ package body Ghdlprint is end if; Unit := Get_First_Design_Unit (Design_File); + if Cmd.Flag_Sem then + Design_File := Null_Iir; + end if; while Unit /= Null_Iir loop if Cmd.Flag_Sem then -- Analyze the design unit. Vhdl.Sem_Lib.Finish_Compilation (Unit, True); + if Cmd.Flag_Sem and then Design_File = Null_Iir then + Design_File := Get_Design_File (Unit); + end if; end if; Next_Unit := Get_Chain (Unit); if Errorout.Nbr_Errors = 0 then - Vhdl.Disp_Vhdl.Disp_Vhdl (Unit); - Set_Chain (Unit, Null_Iir); + Vhdl.Prints.Disp_Vhdl (Unit); if Cmd.Flag_Sem then + Set_Chain (Unit, Null_Iir); Libraries.Add_Design_Unit_Into_Library (Unit); end if; end if; diff --git a/src/psl/psl-nodes_priv.ads b/src/psl/psl-nodes_priv.ads index 5c0bf51d0..9927b8bde 100644 --- a/src/psl/psl-nodes_priv.ads +++ b/src/psl/psl-nodes_priv.ads @@ -20,6 +20,7 @@ with Types; use Types; package PSL.Nodes_Priv is -- PSL Node. type PSL_Node is new Int32; + Null_PSL_Node : constant PSL_Node := 0; -- PSL NFA type PSL_NFA is new Int32; diff --git a/src/psl/psl-types.ads b/src/psl/psl-types.ads index e6e3c700a..24a9f9a80 100644 --- a/src/psl/psl-types.ads +++ b/src/psl/psl-types.ads @@ -22,6 +22,7 @@ package PSL.Types is subtype PSL_Node is PSL.Nodes_Priv.PSL_Node; function "=" (L, R : PSL_Node) return Boolean renames PSL.Nodes_Priv."="; + Null_PSL_Node : constant PSL_Node := PSL.Nodes_Priv.Null_PSL_Node; -- PSL NFA subtype PSL_NFA is PSL.Nodes_Priv.PSL_NFA; diff --git a/src/vhdl/translate/trans_analyzes.adb b/src/vhdl/translate/trans_analyzes.adb index 2311b12eb..420d04c37 100644 --- a/src/vhdl/translate/trans_analyzes.adb +++ b/src/vhdl/translate/trans_analyzes.adb @@ -20,7 +20,7 @@ with Errorout; with Simple_IO; with Vhdl.Utils; use Vhdl.Utils; with Vhdl.Nodes_Walk; use Vhdl.Nodes_Walk; -with Vhdl.Disp_Vhdl; +with Vhdl.Prints; with Vhdl.Errors; use Vhdl.Errors; package body Trans_Analyzes is @@ -247,7 +247,7 @@ package body Trans_Analyzes is else Put (" "); end if; - Vhdl.Disp_Vhdl.Disp_Vhdl (El); + Vhdl.Prints.Disp_Vhdl (El); New_Line; Next (It); end loop; diff --git a/src/vhdl/vhdl-canon.adb b/src/vhdl/vhdl-canon.adb index f0037d298..604272813 100644 --- a/src/vhdl/vhdl-canon.adb +++ b/src/vhdl/vhdl-canon.adb @@ -2155,7 +2155,7 @@ package body Vhdl.Canon is Prop := Get_Property (Decl); Prop := PSL.Rewrites.Rewrite_Property (Prop); Set_Property (Decl, Prop); - if Get_Parameter_List (Decl) = Null_Node then + if Get_Parameter_List (Decl) = Null_PSL_Node then -- Generate the NFA. Fa := PSL.Build.Build_FA (Prop); Set_PSL_NFA (El, Fa); @@ -2176,7 +2176,7 @@ package body Vhdl.Canon is Seq : PSL_Node; Fa : PSL_NFA; begin - pragma Assert (Get_Parameter_List (Decl) = Null_Node); + pragma Assert (Get_Parameter_List (Decl) = Null_PSL_Node); Seq := Get_Sequence (Decl); Seq := PSL.Rewrites.Rewrite_SERE (Seq); Set_Sequence (Decl, Seq); diff --git a/src/vhdl/vhdl-flists.ads b/src/vhdl/vhdl-flists.ads index ae92345ad..a7b389369 100644 --- a/src/vhdl/vhdl-flists.ads +++ b/src/vhdl/vhdl-flists.ads @@ -18,4 +18,4 @@ with Vhdl.Types; with Flists; -package Vhdl.Flists is new Standard.Flists (El_Type => Vhdl.Types.Node); +package Vhdl.Flists is new Standard.Flists (El_Type => Vhdl.Types.Vhdl_Node); diff --git a/src/vhdl/vhdl-lists.ads b/src/vhdl/vhdl-lists.ads index 6d16b81bf..7441f9000 100644 --- a/src/vhdl/vhdl-lists.ads +++ b/src/vhdl/vhdl-lists.ads @@ -18,4 +18,4 @@ with Vhdl.Types; with Lists; -package Vhdl.Lists is new Standard.Lists (El_Type => Vhdl.Types.Node); +package Vhdl.Lists is new Standard.Lists (El_Type => Vhdl.Types.Vhdl_Node); diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads index 97e7d706f..228b58d68 100644 --- a/src/vhdl/vhdl-nodes.ads +++ b/src/vhdl/vhdl-nodes.ads @@ -5471,8 +5471,10 @@ package Vhdl.Nodes is -- Nodes and lists. subtype Iir is Vhdl.Nodes_Priv.Node_Type; + subtype Node is Vhdl.Nodes_Priv.Node_Type; - Null_Iir : constant Iir := 0; + Null_Iir : constant Iir := Vhdl.Nodes_Priv.Null_Node; + Null_Node : constant Node := Vhdl.Nodes_Priv.Null_Node; -- Return True iff Node is null / not set. function Is_Null (Node : Iir) return Boolean; diff --git a/src/vhdl/vhdl-parse_psl.adb b/src/vhdl/vhdl-parse_psl.adb index 630339c79..561f9caff 100644 --- a/src/vhdl/vhdl-parse_psl.adb +++ b/src/vhdl/vhdl-parse_psl.adb @@ -117,7 +117,7 @@ package body Vhdl.Parse_Psl is function Vhdl_To_Psl (N : Vhdl_Node) return Node is use Vhdl.Nodes; - Res : Node; + Res : PSL_Node; begin Res := Create_Node_Loc (N_HDL_Expr); if N /= Null_Iir then diff --git a/src/vhdl/vhdl-disp_vhdl.adb b/src/vhdl/vhdl-prints.adb index 107b3f8a8..a97f413ec 100644 --- a/src/vhdl/vhdl-disp_vhdl.adb +++ b/src/vhdl/vhdl-prints.adb @@ -35,7 +35,7 @@ with PSL.Prints; with PSL.NFAs; with PSL.Errors; -package body Vhdl.Disp_Vhdl is +package body Vhdl.Prints is -- If True, display extra parenthesis to make priority of operators -- explicit. @@ -4152,4 +4152,4 @@ package body Vhdl.Disp_Vhdl is Disp_PSL_NFA (Ctxt, N); end Disp_PSL_NFA; -end Vhdl.Disp_Vhdl; +end Vhdl.Prints; diff --git a/src/vhdl/vhdl-disp_vhdl.ads b/src/vhdl/vhdl-prints.ads index a1c0b2b3c..285d1354e 100644 --- a/src/vhdl/vhdl-disp_vhdl.ads +++ b/src/vhdl/vhdl-prints.ads @@ -20,7 +20,7 @@ with Vhdl.Nodes; use Vhdl.Nodes; with Vhdl.Tokens; use Vhdl.Tokens; with PSL.Types; use PSL.Types; -package Vhdl.Disp_Vhdl is +package Vhdl.Prints is type Disp_Ctxt is abstract tagged null record; procedure Start_Hbox (Ctxt : in out Disp_Ctxt) is abstract; procedure Close_Hbox (Ctxt : in out Disp_Ctxt) is abstract; @@ -54,4 +54,4 @@ package Vhdl.Disp_Vhdl is procedure Disp_Expression (Expr: Iir); -- Display an expression. -end Vhdl.Disp_Vhdl; +end Vhdl.Prints; diff --git a/src/vhdl/vhdl-sem_lib.adb b/src/vhdl/vhdl-sem_lib.adb index e3ff86ed8..c09f1a7a2 100644 --- a/src/vhdl/vhdl-sem_lib.adb +++ b/src/vhdl/vhdl-sem_lib.adb @@ -25,7 +25,7 @@ with Libraries; use Libraries; with Vhdl.Scanner; with Vhdl.Parse; with Vhdl.Disp_Tree; -with Vhdl.Disp_Vhdl; +with Vhdl.Prints; with Vhdl.Sem; with Vhdl.Post_Sems; with Vhdl.Canon; @@ -104,7 +104,7 @@ package body Vhdl.Sem_Lib is end if; if (Main or Flags.List_All) and then Flags.List_Sem then - Vhdl.Disp_Vhdl.Disp_Vhdl (Unit); + Vhdl.Prints.Disp_Vhdl (Unit); end if; if Flags.Check_Ast_Level > 0 then @@ -139,7 +139,7 @@ package body Vhdl.Sem_Lib is end if; if (Main or Flags.List_All) and then Flags.List_Canon then - Vhdl.Disp_Vhdl.Disp_Vhdl (Unit); + Vhdl.Prints.Disp_Vhdl (Unit); end if; if Flags.Check_Ast_Level > 0 then diff --git a/src/vhdl/vhdl-sem_psl.adb b/src/vhdl/vhdl-sem_psl.adb index 28541e7cc..a1afddd44 100644 --- a/src/vhdl/vhdl-sem_psl.adb +++ b/src/vhdl/vhdl-sem_psl.adb @@ -37,7 +37,7 @@ with Vhdl.Errors; use Vhdl.Errors; with Vhdl.Xrefs; use Vhdl.Xrefs; package body Vhdl.Sem_Psl is - procedure Sem_Psl_Directive_Clock (Stmt : Iir; Prop : in out Node); + procedure Sem_Psl_Directive_Clock (Stmt : Iir; Prop : in out PSL_Node); -- Return TRUE iff Atype is a PSL boolean type. -- See PSL1.1 5.1.2 Boolean expressions @@ -61,7 +61,7 @@ package body Vhdl.Sem_Psl is end Is_Psl_Bool_Expr; -- Convert VHDL and/or/not nodes to PSL nodes. - function Convert_Bool (Expr : Iir) return Node + function Convert_Bool (Expr : Iir) return PSL_Node is use Std_Names; Impl : Iir; @@ -72,9 +72,9 @@ package body Vhdl.Sem_Psl is Left : Iir; Right : Iir; - function Build_Op (Kind : Nkind) return Node + function Build_Op (Kind : Nkind) return PSL_Node is - N : Node; + N : PSL_Node; begin N := Create_Node (Kind); Set_Location (N, Get_Location (Expr)); @@ -102,9 +102,9 @@ package body Vhdl.Sem_Psl is declare Operand : Iir; - function Build_Op (Kind : Nkind) return Node + function Build_Op (Kind : Nkind) return PSL_Node is - N : Node; + N : PSL_Node; begin N := Create_Node (Kind); Set_Location (N, Get_Location (Expr)); @@ -141,14 +141,14 @@ package body Vhdl.Sem_Psl is -- Analyze an HDL expression. This may mostly a wrapper except in the -- case when the expression is in fact a PSL expression. - function Sem_Hdl_Expr (N : Node) return Node + function Sem_Hdl_Expr (N : PSL_Node) return PSL_Node is use Sem_Names; Expr : Iir; Name : Iir; - Decl : Node; - Res : Node; + Decl : PSL_Node; + Res : PSL_Node; begin Expr := Get_HDL_Node (N); if Get_Kind (Expr) in Iir_Kinds_Name then @@ -184,7 +184,7 @@ package body Vhdl.Sem_Psl is end case; Set_Location (Res, Get_Location (N)); Set_Declaration (Res, Decl); - if Get_Parameter_List (Decl) /= Null_Node then + if Get_Parameter_List (Decl) /= Null_PSL_Node then Error_Msg_Sem (+Res, "no actual for instantiation"); end if; Free_Node (N); @@ -225,7 +225,7 @@ package body Vhdl.Sem_Psl is end Sem_Hdl_Expr; -- Sem a boolean node. - function Sem_Boolean (Bool : Node) return Node is + function Sem_Boolean (Bool : PSL_Node) return PSL_Node is begin case Get_Kind (Bool) is when N_HDL_Expr => @@ -240,9 +240,9 @@ package body Vhdl.Sem_Psl is end case; end Sem_Boolean; - procedure Sem_Boolean (N : Node) + procedure Sem_Boolean (N : PSL_Node) is - Bool : Node; + Bool : PSL_Node; begin Bool := Get_Boolean (N); Bool := Sem_Boolean (Bool); @@ -251,10 +251,10 @@ package body Vhdl.Sem_Psl is -- Used by Sem_Property to rewrite a property logical operator to a -- boolean logical operator. - function Reduce_Logic_Binary_Node (Prop : Node; Bool_Kind : Nkind) - return Node + function Reduce_Logic_Binary_Node (Prop : PSL_Node; Bool_Kind : Nkind) + return PSL_Node is - Res : Node; + Res : PSL_Node; begin Res := Create_Node (Bool_Kind); Set_Location (Res, Get_Location (Prop)); @@ -264,10 +264,10 @@ package body Vhdl.Sem_Psl is return Res; end Reduce_Logic_Binary_Node; - function Reduce_Logic_Unary_Node (Prop : Node; Bool_Kind : Nkind) - return Node + function Reduce_Logic_Unary_Node (Prop : PSL_Node; Bool_Kind : Nkind) + return PSL_Node is - Res : Node; + Res : PSL_Node; begin Res := Create_Node (Bool_Kind); Set_Location (Res, Get_Location (Prop)); @@ -276,10 +276,10 @@ package body Vhdl.Sem_Psl is return Res; end Reduce_Logic_Unary_Node; - function Sem_Sequence (Seq : Node) return Node + function Sem_Sequence (Seq : PSL_Node) return PSL_Node is - Res : Node; - L, R : Node; + Res : PSL_Node; + L, R : PSL_Node; begin case Get_Kind (Seq) is when N_Braced_SERE => @@ -304,7 +304,7 @@ package body Vhdl.Sem_Psl is return Seq; when N_Star_Repeat_Seq => Res := Get_Sequence (Seq); - if Res /= Null_Node then + if Res /= Null_PSL_Node then Res := Sem_Sequence (Get_Sequence (Seq)); Set_Sequence (Seq, Res); end if; @@ -312,7 +312,7 @@ package body Vhdl.Sem_Psl is return Seq; when N_Plus_Repeat_Seq => Res := Get_Sequence (Seq); - if Res /= Null_Node then + if Res /= Null_PSL_Node then Res := Sem_Sequence (Get_Sequence (Seq)); Set_Sequence (Seq, Res); end if; @@ -341,20 +341,21 @@ package body Vhdl.Sem_Psl is end case; end Sem_Sequence; - function Sem_Property (Prop : Node; Top : Boolean := False) return Node; + function Sem_Property (Prop : PSL_Node; Top : Boolean := False) + return PSL_Node; - procedure Sem_Property (N : Node; Top : Boolean := False) + procedure Sem_Property (N : PSL_Node; Top : Boolean := False) is - Prop : Node; + Prop : PSL_Node; begin Prop := Get_Property (N); Prop := Sem_Property (Prop, Top); Set_Property (N, Prop); end Sem_Property; - procedure Sem_Number (N : Node) + procedure Sem_Number (N : PSL_Node) is - Num : Node; + Num : PSL_Node; begin Num := Get_Number (N); -- FIXME: todo @@ -362,9 +363,10 @@ package body Vhdl.Sem_Psl is Set_Number (N, Num); end Sem_Number; - function Sem_Property (Prop : Node; Top : Boolean := False) return Node + function Sem_Property (Prop : PSL_Node; Top : Boolean := False) + return PSL_Node is - Res : Node; + Res : PSL_Node; begin case Get_Kind (Prop) is when N_Braced_SERE => @@ -400,7 +402,7 @@ package body Vhdl.Sem_Psl is | N_And_Prop | N_Or_Prop => declare - L, R : Node; + L, R : PSL_Node; begin L := Sem_Property (Get_Left (Prop)); Set_Left (Prop, L); @@ -431,7 +433,7 @@ package body Vhdl.Sem_Psl is return Prop; when N_Paren_Prop => declare - Op : Node; + Op : PSL_Node; begin Op := Get_Property (Prop); Op := Sem_Property (Op); @@ -459,10 +461,10 @@ package body Vhdl.Sem_Psl is Res := Sem_Hdl_Expr (Prop); if not Top and then Get_Kind (Res) = N_Property_Instance then declare - Decl : constant Node := Get_Declaration (Res); + Decl : constant PSL_Node := Get_Declaration (Res); begin - if Decl /= Null_Node - and then Get_Global_Clock (Decl) /= Null_Node + if Decl /= Null_PSL_Node + and then Get_Global_Clock (Decl) /= Null_PSL_Node then Error_Msg_Sem (+Prop, "property instance already has a clock"); @@ -476,11 +478,11 @@ package body Vhdl.Sem_Psl is end Sem_Property; -- Extract the clock from PROP. - procedure Extract_Clock (Prop : in out Node; Clk : out Node) + procedure Extract_Clock (Prop : in out PSL_Node; Clk : out PSL_Node) is - Child : Node; + Child : PSL_Node; begin - Clk := Null_Node; + Clk := Null_PSL_Node; case Get_Kind (Prop) is when N_Clock_Event => Clk := Get_Boolean (Prop); @@ -507,10 +509,10 @@ package body Vhdl.Sem_Psl is procedure Sem_Psl_Declaration (Stmt : Iir) is use Sem_Scopes; - Decl : constant Node := Get_Psl_Declaration (Stmt); - Prop : Node; - Clk : Node; - Formal : Node; + Decl : constant PSL_Node := Get_Psl_Declaration (Stmt); + Prop : PSL_Node; + Clk : PSL_Node; + Formal : PSL_Node; El : Iir; begin Sem_Scopes.Add_Name (Stmt); @@ -520,7 +522,7 @@ package body Vhdl.Sem_Psl is -- Make formal parameters visible. Formal := Get_Parameter_List (Decl); - while Formal /= Null_Node loop + while Formal /= Null_PSL_Node loop El := Create_Iir (Iir_Kind_Psl_Declaration); Set_Location (El, Get_Location (Formal)); Set_Identifier (El, Get_Identifier (Formal)); @@ -560,13 +562,13 @@ package body Vhdl.Sem_Psl is procedure Sem_Psl_Endpoint_Declaration (Stmt : Iir) is - Decl : constant Node := Get_Psl_Declaration (Stmt); - Prop : Node; + Decl : constant PSL_Node := Get_Psl_Declaration (Stmt); + Prop : PSL_Node; begin Sem_Scopes.Add_Name (Stmt); Xref_Decl (Stmt); - pragma Assert (Get_Parameter_List (Decl) = Null_Node); + pragma Assert (Get_Parameter_List (Decl) = Null_PSL_Node); pragma Assert (Get_Kind (Decl) = N_Endpoint_Declaration); Prop := Get_Sequence (Decl); @@ -584,10 +586,10 @@ package body Vhdl.Sem_Psl is Set_Visible_Flag (Stmt, True); end Sem_Psl_Endpoint_Declaration; - function Rewrite_As_Boolean_Expression (Prop : Node) return Iir + function Rewrite_As_Boolean_Expression (Prop : PSL_Node) return Iir is function Rewrite_Dyadic_Operator - (Expr : Node; Kind : Iir_Kind) return Iir + (Expr : PSL_Node; Kind : Iir_Kind) return Iir is Res : Iir; begin @@ -599,7 +601,7 @@ package body Vhdl.Sem_Psl is end Rewrite_Dyadic_Operator; function Rewrite_Monadic_Operator - (Expr : Node; Kind : Iir_Kind) return Iir + (Expr : PSL_Node; Kind : Iir_Kind) return Iir is Res : Iir; begin @@ -665,7 +667,7 @@ package body Vhdl.Sem_Psl is end Rewrite_As_Concurrent_Assertion; -- Return True iff EXPR is a boolean expression. - function Is_Boolean_Assertion (Expr : Node) return Boolean is + function Is_Boolean_Assertion (Expr : PSL_Node) return Boolean is begin case Get_Kind (Expr) is when N_HDL_Expr => @@ -677,15 +679,15 @@ package body Vhdl.Sem_Psl is end case; end Is_Boolean_Assertion; - procedure Sem_Psl_Directive_Clock (Stmt : Iir; Prop : in out Node) + procedure Sem_Psl_Directive_Clock (Stmt : Iir; Prop : in out PSL_Node) is - Clk : Node; + Clk : PSL_Node; begin Extract_Clock (Prop, Clk); - if Clk = Null_Node then + if Clk = Null_PSL_Node then if Current_Psl_Default_Clock = Null_Iir then Error_Msg_Sem (+Stmt, "no clock for PSL directive"); - Clk := Null_Node; + Clk := Null_PSL_Node; else Clk := Get_Psl_Boolean (Current_Psl_Default_Clock); end if; @@ -695,7 +697,7 @@ package body Vhdl.Sem_Psl is function Sem_Psl_Assert_Statement (Stmt : Iir) return Iir is - Prop : Node; + Prop : PSL_Node; Res : Iir; begin pragma Assert (Get_Kind (Stmt) = Iir_Kind_Psl_Assert_Statement); @@ -732,7 +734,7 @@ package body Vhdl.Sem_Psl is procedure Sem_Psl_Cover_Statement (Stmt : Iir) is - Seq : Node; + Seq : PSL_Node; begin -- Sem report and severity expressions. Sem_Report_Statement (Stmt); @@ -750,7 +752,7 @@ package body Vhdl.Sem_Psl is procedure Sem_Psl_Default_Clock (Stmt : Iir) is - Expr : Node; + Expr : PSL_Node; begin if Current_Psl_Default_Clock /= Null_Iir and then Get_Parent (Current_Psl_Default_Clock) = Get_Parent (Stmt) @@ -772,14 +774,14 @@ package body Vhdl.Sem_Psl is is Prefix : constant Iir := Get_Prefix (Name); Ent : constant Iir := Get_Named_Entity (Prefix); - Decl : constant Node := Get_Psl_Declaration (Ent); - Formal : Node; + Decl : constant PSL_Node := Get_Psl_Declaration (Ent); + Formal : PSL_Node; Assoc : Iir; - Res : Node; - Last_Assoc : Node; - Assoc2 : Node; + Res : PSL_Node; + Last_Assoc : PSL_Node; + Assoc2 : PSL_Node; Actual : Iir; - Psl_Actual : Node; + Psl_Actual : PSL_Node; Res2 : Iir; begin pragma Assert (Get_Kind (Ent) = Iir_Kind_Psl_Declaration @@ -799,9 +801,9 @@ package body Vhdl.Sem_Psl is Set_Location (Res, Get_Location (Name)); Formal := Get_Parameter_List (Decl); Assoc := Get_Association_Chain (Name); - Last_Assoc := Null_Node; + Last_Assoc := Null_PSL_Node; - while Formal /= Null_Node loop + while Formal /= Null_PSL_Node loop if Assoc = Null_Iir then Error_Msg_Sem (+Name, "not enough association"); exit; @@ -825,7 +827,7 @@ package body Vhdl.Sem_Psl is Set_Location (Assoc2, Get_Location (Assoc)); Set_Formal (Assoc2, Formal); Set_Actual (Assoc2, Psl_Actual); - if Last_Assoc = Null_Node then + if Last_Assoc = Null_PSL_Node then Set_Association_Chain (Res, Assoc2); else Set_Chain (Last_Assoc, Assoc2); diff --git a/src/vhdl/vhdl-types.ads b/src/vhdl/vhdl-types.ads index b9fd673b5..ecd2367ca 100644 --- a/src/vhdl/vhdl-types.ads +++ b/src/vhdl/vhdl-types.ads @@ -21,5 +21,6 @@ with Vhdl.Nodes_Priv; package Vhdl.Types is pragma Preelaborate (Vhdl.Types); - subtype Node is Vhdl.Nodes_Priv.Node_Type; + subtype Vhdl_Node is Vhdl.Nodes_Priv.Node_Type; + Null_Vhdl_Node : constant Vhdl_Node := Vhdl.Nodes_Priv.Null_Node; end Vhdl.Types; |