diff options
-rw-r--r-- | testsuite/gna/issue259/testcase_ce.vhdl | 29 | ||||
-rwxr-xr-x | testsuite/gna/issue259/testsuite.sh | 11 |
2 files changed, 40 insertions, 0 deletions
diff --git a/testsuite/gna/issue259/testcase_ce.vhdl b/testsuite/gna/issue259/testcase_ce.vhdl new file mode 100644 index 000000000..67caf02ca --- /dev/null +++ b/testsuite/gna/issue259/testcase_ce.vhdl @@ -0,0 +1,29 @@ +library IEEE; +use IEEE.std_logic_1164.all; + + +entity Testcase_CE is + +port ( + CLK : in std_logic +); +end Testcase_CE; + +architecture RTL of Testcase_CE is + + signal y : std_logic; + signal x : std_logic; + +begin + +process (CLK) + +begin + if CLK'event and CLK='1' then + + x <= y when false else '0'; + + end if; +end process; + +end RTL; diff --git a/testsuite/gna/issue259/testsuite.sh b/testsuite/gna/issue259/testsuite.sh new file mode 100755 index 000000000..660861196 --- /dev/null +++ b/testsuite/gna/issue259/testsuite.sh @@ -0,0 +1,11 @@ +#! /bin/sh + +. ../../testenv.sh + +export GHDL_STD_FLAGS=--std=08 +analyze testcase_ce.vhdl +elab_simulate testcase_ce + +clean + +echo "Test successful" |