6 files changed, 176 insertions, 0 deletions
diff --git a/testsuite/gna/issue1708/ex1.vhdl b/testsuite/gna/issue1708/ex1.vhdl
new file mode 100644
index 000000000..1b7dd854b
--- /dev/null
+++ b/testsuite/gna/issue1708/ex1.vhdl
@@ -0,0 +1,33 @@
+Library ieee;
+use ieee.std_logic_1164.all;
+
+entity ex1 is
+end entity;
+
+
+architecture tb of ex1 is
+
+    signal a,b : std_logic := '0';
+    signal clk_sys : std_logic;
+
+    default clock is rising_edge(clk_sys);
+begin
+
+    gen_clock_proc : process
+    begin
+    	clk_sys <= '1';
+        wait for 5 ns;
+        clk_sys <= '0';
+        wait for 5 ns;
+    end process;
+
+    test_proc : process
+    begin
+          a <= '1';
+          wait for 50 ns;
+          std.env.finish;
+    end process;
+
+    my_seq : assert never a[=3];
+
+end architecture tb;
diff --git a/testsuite/gna/issue1708/ex2.vhdl b/testsuite/gna/issue1708/ex2.vhdl
new file mode 100644
index 000000000..d425f75c1
--- /dev/null
+++ b/testsuite/gna/issue1708/ex2.vhdl
@@ -0,0 +1,33 @@
+Library ieee;
+use ieee.std_logic_1164.all;
+
+entity ex2 is
+end entity;
+
+
+architecture tb of ex2 is
+
+    signal a,b : std_logic := '0';
+    signal clk_sys : std_logic;
+
+    default clock is rising_edge(clk_sys);
+begin
+
+    gen_clock_proc : process
+    begin
+    	clk_sys <= '1';
+        wait for 5 ns;
+        clk_sys <= '0';
+        wait for 5 ns;
+    end process;
+
+    test_proc : process
+    begin
+          a <= '1';
+          wait for 50 ns;
+          std.env.finish;
+    end process;
+
+    my_seq : assert never (a = '1')[->3];
+
+end architecture tb;
diff --git a/testsuite/gna/issue1708/ex3.vhdl b/testsuite/gna/issue1708/ex3.vhdl
new file mode 100644
index 000000000..ea245aeb1
--- /dev/null
+++ b/testsuite/gna/issue1708/ex3.vhdl
@@ -0,0 +1,33 @@
+Library ieee;
+use ieee.std_logic_1164.all;
+
+entity ex3 is
+end entity;
+
+
+architecture tb of ex3 is
+
+    signal a,b : std_logic := '0';
+    signal clk_sys : std_logic;
+
+    default clock is rising_edge(clk_sys);
+begin
+
+    gen_clock_proc : process
+    begin
+    	clk_sys <= '1';
+        wait for 5 ns;
+        clk_sys <= '0';
+        wait for 5 ns;
+    end process;
+
+    test_proc : process
+    begin
+          a <= '1';
+          wait for 50 ns;
+          std.env.finish;
+    end process;
+
+    my_seq : assert never {a = '1'}[->3];
+
+end architecture tb;
diff --git a/testsuite/gna/issue1708/ex4.vhdl b/testsuite/gna/issue1708/ex4.vhdl
new file mode 100644
index 000000000..c2cc81786
--- /dev/null
+++ b/testsuite/gna/issue1708/ex4.vhdl
@@ -0,0 +1,33 @@
+Library ieee;
+use ieee.std_logic_1164.all;
+
+entity ex4 is
+end entity;
+
+
+architecture tb of ex4 is
+
+    signal a,b : std_logic := '0';
+    signal clk_sys : std_logic;
+
+    default clock is rising_edge(clk_sys);
+begin
+
+    gen_clock_proc : process
+    begin
+    	clk_sys <= '1';
+        wait for 5 ns;
+        clk_sys <= '0';
+        wait for 5 ns;
+    end process;
+
+    test_proc : process
+    begin
+          a <= '1';
+          wait for 50 ns;
+          std.env.finish;
+    end process;
+
+    my_seq : assert never {a = '1'; b = '1'}[->3];
+
+end architecture tb;
diff --git a/testsuite/gna/issue1708/ex5.vhdl b/testsuite/gna/issue1708/ex5.vhdl
new file mode 100644
index 000000000..cb6715780
--- /dev/null
+++ b/testsuite/gna/issue1708/ex5.vhdl
@@ -0,0 +1,33 @@
+Library ieee;
+use ieee.std_logic_1164.all;
+
+entity ex5 is
+end entity;
+
+
+architecture tb of ex5 is
+
+    signal a,b : std_logic := '0';
+    signal clk_sys : std_logic;
+
+    default clock is rising_edge(clk_sys);
+begin
+
+    gen_clock_proc : process
+    begin
+    	clk_sys <= '1';
+        wait for 5 ns;
+        clk_sys <= '0';
+        wait for 5 ns;
+    end process;
+
+    test_proc : process
+    begin
+          a <= '1';
+          wait for 50 ns;
+          std.env.finish;
+    end process;
+
+    my_seq : assert never (a = '1')[*3];
+
+end architecture tb;
diff --git a/testsuite/gna/issue1708/testsuite.sh b/testsuite/gna/issue1708/testsuite.sh
index cafddf06e..9d9a99bac 100755
--- a/testsuite/gna/issue1708/testsuite.sh
+++ b/testsuite/gna/issue1708/testsuite.sh
@@ -4,6 +4,17 @@
 
 export GHDL_STD_FLAGS=--std=08
 analyze_failure tb_top.vhdl
+analyze_failure ex3.vhdl
+analyze_failure ex4.vhdl
+
+analyze ex1.vhdl
+elab_simulate ex1
+
+analyze ex2.vhdl
+elab_simulate ex2
+
+analyze ex5.vhdl
+elab_simulate ex5
 
 clean