diff options
| -rwxr-xr-x | testsuite/gna/issue1771/testsuite.sh | 11 | ||||
| -rw-r--r-- | testsuite/gna/issue1771/tf.vhdl | 32 | 
2 files changed, 43 insertions, 0 deletions
diff --git a/testsuite/gna/issue1771/testsuite.sh b/testsuite/gna/issue1771/testsuite.sh new file mode 100755 index 000000000..f965617d2 --- /dev/null +++ b/testsuite/gna/issue1771/testsuite.sh @@ -0,0 +1,11 @@ +#! /bin/sh + +. ../../testenv.sh + +export GHDL_STD_FLAGS=--std=08 +analyze tf.vhdl +elab_simulate tf + +clean + +echo "Test successful" diff --git a/testsuite/gna/issue1771/tf.vhdl b/testsuite/gna/issue1771/tf.vhdl new file mode 100644 index 000000000..77039f15e --- /dev/null +++ b/testsuite/gna/issue1771/tf.vhdl @@ -0,0 +1,32 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.fixed_pkg.all; + +entity tf is +end entity tf; + +architecture testbench of tf is +    signal sx : sfixed (3 downto 0)  := "1001"; +    signal sy : sfixed (3 downto -3) := "0101110"; +    signal sz : sfixed (3 downto -3); +    signal sci : std_ulogic := '1'; +    signal sco : std_ulogic; +begin +  tt : process is +    variable x : sfixed (3 downto 0) := sx; +    variable y : sfixed (3 downto -3) := sy; +    variable z : sfixed (3 downto -3); +    variable ci : std_ulogic := sci; +    variable co : std_ulogic; +    constant eres : sfixed(3 downto -3) := b"1110_111"; +  begin +    add_carry (L => x, R => y, c_in => ci, result => z, c_out => co); +    sz <= z; +    sco <= co; +    wait for 1 ns; +    assert z = eres; +    report to_bstring(z); +    wait; +  end process tt; +end architecture testbench; +  | 
