diff options
| -rw-r--r-- | testsuite/synth/issue2062/repro.vhdl | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/testsuite/synth/issue2062/repro.vhdl b/testsuite/synth/issue2062/repro.vhdl index 2b676415c..9fb8694fa 100644 --- a/testsuite/synth/issue2062/repro.vhdl +++ b/testsuite/synth/issue2062/repro.vhdl @@ -3,7 +3,7 @@ use ieee.std_logic_1164.all; entity repro is port ( a : in std_logic_vector(5 downto 0); - y : out std_ulogic_vector(3 downto -2)); + y : out std_ulogic_vector(7 downto 2)); end entity; architecture beh of repro is |