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-rw-r--r--testsuite/synth/sns01/sns02.vhdl13
-rwxr-xr-xtestsuite/synth/sns01/testsuite.sh8
2 files changed, 20 insertions, 1 deletions
diff --git a/testsuite/synth/sns01/sns02.vhdl b/testsuite/synth/sns01/sns02.vhdl
new file mode 100644
index 000000000..c68ddbd90
--- /dev/null
+++ b/testsuite/synth/sns01/sns02.vhdl
@@ -0,0 +1,13 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_misc.all;
+
+entity sns02 is
+ port (a : std_logic_vector(7 downto 0);
+ b : out std_logic);
+end sns02;
+
+architecture behav of sns02 is
+begin
+ b <= or_reduce(a);
+end behav;
diff --git a/testsuite/synth/sns01/testsuite.sh b/testsuite/synth/sns01/testsuite.sh
index 2f17c5d8f..d9cb4503a 100755
--- a/testsuite/synth/sns01/testsuite.sh
+++ b/testsuite/synth/sns01/testsuite.sh
@@ -2,11 +2,17 @@
. ../../testenv.sh
-GHDL_STD_FLAGS=--ieee=synopsys
+GHDL_STD_FLAGS=-fsynopsys
+
for t in sns01; do
synth $t.vhdl -e $t > syn_$t.vhdl
+ # No analysis because of conflict between numeric_std.unsigned and
+ # std_logic_arith.unsigned
# analyze syn_$t.vhdl
clean
done
+synth_analyze sns02
+clean
+
echo "Test successful"