diff options
| -rw-r--r-- | src/vhdl/translate/trans-chap7.adb | 8 | ||||
| -rw-r--r-- | src/vhdl/vhdl-sem_expr.adb | 25 | ||||
| -rw-r--r-- | src/vhdl/vhdl-sem_lib.adb | 6 | ||||
| -rw-r--r-- | testsuite/gna/issue2066/aggregate_bug.vhdl | 18 | ||||
| -rw-r--r-- | testsuite/gna/issue2066/repro1.vhdl | 14 | ||||
| -rwxr-xr-x | testsuite/gna/issue2066/testsuite.sh | 14 |
6 files changed, 82 insertions, 3 deletions
diff --git a/src/vhdl/translate/trans-chap7.adb b/src/vhdl/translate/trans-chap7.adb index bd80b1050..17eb783ea 100644 --- a/src/vhdl/translate/trans-chap7.adb +++ b/src/vhdl/translate/trans-chap7.adb @@ -4408,15 +4408,19 @@ package body Trans.Chap7 is function Translate_Overflow_Literal (Expr : Iir) return O_Enode is Expr_Type : constant Iir := Get_Type (Expr); - Tinfo : constant Type_Info_Acc := Get_Info (Expr_Type); - Otype : constant O_Tnode := Tinfo.Ortho_Type (Mode_Value); + Tinfo : Type_Info_Acc; + Otype : O_Tnode; L : O_Dnode; begin + Chap3.Translate_Anonymous_Subtype_Definition (Expr_Type, False); + -- Generate the error message Chap6.Gen_Bound_Error (Expr); -- Create a dummy value, for type checking. But never -- executed. + Tinfo := Get_Info (Expr_Type); + Otype := Tinfo.Ortho_Type (Mode_Value); L := Create_Temp (Otype); if Tinfo.Type_Mode in Type_Mode_Fat then -- For fat pointers or arrays. diff --git a/src/vhdl/vhdl-sem_expr.adb b/src/vhdl/vhdl-sem_expr.adb index 596638464..8a7ea0d89 100644 --- a/src/vhdl/vhdl-sem_expr.adb +++ b/src/vhdl/vhdl-sem_expr.adb @@ -3562,6 +3562,31 @@ package body Vhdl.Sem_Expr is "element is out of the bounds"); end if; + if Is_Array + and then Get_Kind (El) = Iir_Kind_Choice_By_Range + then + declare + Ch_Rng : constant Iir := Get_Choice_Range (El); + Expr_Type : constant Iir := Get_Type (Expr); + Idx : Iir; + begin + if Get_Expr_Staticness (Ch_Rng) = Locally + and then Get_Index_Constraint_Flag (Expr_Type) + then + Idx := Get_Index_Type (Expr_Type, 0); + if Get_Type_Staticness (Idx) = Locally + and then (Eval_Discrete_Type_Length (Idx) + /= Eval_Discrete_Range_Length (Ch_Rng)) + then + Warning_Msg_Sem (Warnid_Runtime_Error, +Expr, + "length mismatch"); + Expr := Build_Overflow (Expr, Expr_Type); + Set_Associated_Expr (El, Expr); + end if; + end if; + end; + end if; + Expr_Staticness := Min (Expr_Staticness, El_Staticness); Info.Nbr_Assocs := Info.Nbr_Assocs + 1; diff --git a/src/vhdl/vhdl-sem_lib.adb b/src/vhdl/vhdl-sem_lib.adb index c4e26ee70..56312701b 100644 --- a/src/vhdl/vhdl-sem_lib.adb +++ b/src/vhdl/vhdl-sem_lib.adb @@ -354,9 +354,13 @@ package body Vhdl.Sem_Lib is -- Disable all warnings. Warnings are emitted only when the unit -- is analyzed. Save_Warnings_Setting (Warnings); - Disable_All_Warnings; if Get_Date_State (Design_Unit) = Date_Disk then + -- The unit is not loaded, so load it. + -- But disable warnings as the unit has already been analyzed. + -- The unit can be in memory but not yet analyzed when -c/-r is + -- used. In that case, warnings shouldn't be disabled. + Disable_All_Warnings; Load_Parse_Design_Unit (Design_Unit, Loc); end if; diff --git a/testsuite/gna/issue2066/aggregate_bug.vhdl b/testsuite/gna/issue2066/aggregate_bug.vhdl new file mode 100644 index 000000000..bf7b53510 --- /dev/null +++ b/testsuite/gna/issue2066/aggregate_bug.vhdl @@ -0,0 +1,18 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity aggregate_bug is +end entity aggregate_bug; + +architecture rtl of aggregate_bug is + signal vec : std_logic_vector(7 downto 0); +begin + vec <= (3 downto 0 => "111", others => '0'); -- Associate a 3 bit element to a 4 bit slice + process + begin + wait for 1 ns; + report to_string(vec); + wait for 1 ns; + std.env.finish; + end process; +end architecture rtl; diff --git a/testsuite/gna/issue2066/repro1.vhdl b/testsuite/gna/issue2066/repro1.vhdl new file mode 100644 index 000000000..aa1dfca11 --- /dev/null +++ b/testsuite/gna/issue2066/repro1.vhdl @@ -0,0 +1,14 @@ +entity repro1 is +end; + +architecture rtl of repro1 is + signal vec : bit_vector(7 downto 0); +begin + vec <= (3 downto 0 => "111", others => '0'); -- Associate a 3 bit element to a 4 bit slice + process + begin + wait for 1 ns; + report to_string(vec); + wait; + end process; +end architecture rtl; diff --git a/testsuite/gna/issue2066/testsuite.sh b/testsuite/gna/issue2066/testsuite.sh new file mode 100755 index 000000000..c763a1451 --- /dev/null +++ b/testsuite/gna/issue2066/testsuite.sh @@ -0,0 +1,14 @@ +#! /bin/sh + +. ../../testenv.sh + +export GHDL_STD_FLAGS=--std=08 +analyze repro1.vhdl +elab_simulate_failure repro1 + +analyze aggregate_bug.vhdl +elab_simulate_failure aggregate_bug + +clean + +echo "Test successful" |