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-rw-r--r--testsuite/gna/issue1480/file1.vhdl7
-rw-r--r--testsuite/gna/issue1480/file2.vhdl8
-rwxr-xr-xtestsuite/gna/issue1480/testsuite.sh11
3 files changed, 26 insertions, 0 deletions
diff --git a/testsuite/gna/issue1480/file1.vhdl b/testsuite/gna/issue1480/file1.vhdl
new file mode 100644
index 000000000..89f659114
--- /dev/null
+++ b/testsuite/gna/issue1480/file1.vhdl
@@ -0,0 +1,7 @@
+entity e is
+end entity;
+
+architecture a of e is
+begin
+end architecture;
+
diff --git a/testsuite/gna/issue1480/file2.vhdl b/testsuite/gna/issue1480/file2.vhdl
new file mode 100644
index 000000000..1a53284ac
--- /dev/null
+++ b/testsuite/gna/issue1480/file2.vhdl
@@ -0,0 +1,8 @@
+entity e is
+ port (clk : std_logic);
+end entity;
+
+architecture a of e is
+begin
+ assert rising_edge(clk);
+end architecture;
diff --git a/testsuite/gna/issue1480/testsuite.sh b/testsuite/gna/issue1480/testsuite.sh
new file mode 100755
index 000000000..6900d23aa
--- /dev/null
+++ b/testsuite/gna/issue1480/testsuite.sh
@@ -0,0 +1,11 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+export GHDL_STD_FLAGS=--std=08
+analyze file1.vhdl
+analyze_failure file2.vhdl
+
+clean
+
+echo "Test successful"