testsuite/synth: add a test for #1076

3 files changed, 56 insertions, 0 deletions

diff --git a/testsuite/synth/issue1076/ent.vhdl b/testsuite/synth/issue1076/ent.vhdl
new file mode 100644
index 000000000..88dc7ccab
--- /dev/null
+++ b/testsuite/synth/issue1076/ent.vhdl
@@ -0,0 +1,18 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity ent is
+	port (
+		o : out std_logic
+	);
+end;
+
+architecture a of ent is
+begin
+	gen: if false generate
+		o <= '1';
+	else generate
+		o <= '0';
+	end generate;
+end;
+
diff --git a/testsuite/synth/issue1076/tb_ent.vhdl b/testsuite/synth/issue1076/tb_ent.vhdl
new file mode 100644
index 000000000..bb1c4c64b
--- /dev/null
+++ b/testsuite/synth/issue1076/tb_ent.vhdl
@@ -0,0 +1,20 @@
+entity tb_ent is
+end tb_ent;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_ent is
+  signal a : std_logic;
+begin
+  dut: entity work.ent
+    port map (a);
+
+  process
+  begin
+    
+    wait for 1 ns;
+    assert a = '0' severity failure;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/issue1076/testsuite.sh b/testsuite/synth/issue1076/testsuite.sh
new file mode 100755
index 000000000..f24786843
--- /dev/null
+++ b/testsuite/synth/issue1076/testsuite.sh
@@ -0,0 +1,18 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+GHDL_STD_FLAGS=--std=08
+
+for t in ent; do
+    analyze $t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t
+    clean
+
+    synth $t.vhdl -e $t > syn_$t.vhdl
+    analyze syn_$t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t --ieee-asserts=disable-at-0
+    clean
+done
+
+echo "Test successful"