testsuite/synth: add test for #1211

5 files changed, 200 insertions, 0 deletions

diff --git a/testsuite/synth/issue1211/delay_ul.vhdl b/testsuite/synth/issue1211/delay_ul.vhdl
new file mode 100644
index 000000000..be798ae45
--- /dev/null
+++ b/testsuite/synth/issue1211/delay_ul.vhdl
@@ -0,0 +1,42 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity delay_ul is
+	generic (
+		STAGES : natural := 4;
+		RESET_ACTIVE_LEVEL : std_ulogic := '1'
+	);
+	port (
+		Clock   : in std_ulogic;
+		Reset   : in std_ulogic;
+		Enable  : in std_ulogic;
+		Sig_in  : in std_ulogic;
+		Sig_out : out std_ulogic
+	);
+end entity;
+
+architecture rtl of delay_ul is
+begin
+	gt: if STAGES > 0 generate
+		reg: process(Clock, Reset, Enable)
+			variable pl_regs : std_ulogic_vector(1 to STAGES);
+		begin
+			if Reset = RESET_ACTIVE_LEVEL then
+				pl_regs := (others => '0');
+			elsif rising_edge(Clock) and Enable = '1' then
+				if STAGES = 1 then
+					pl_regs(1) := Sig_in;
+				else
+					pl_regs := Sig_in & pl_regs(1 to pl_regs'high-1);
+				end if;
+			end if;
+
+			Sig_out <= pl_regs(pl_regs'high);
+		end process;
+	end generate;
+
+	gf: if STAGES = 0 generate
+		Sig_out <= Sig_in;
+	end generate;
+
+end architecture;
diff --git a/testsuite/synth/issue1211/repro1.vhdl b/testsuite/synth/issue1211/repro1.vhdl
new file mode 100644
index 000000000..5e2f1bf41
--- /dev/null
+++ b/testsuite/synth/issue1211/repro1.vhdl
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity repro1 is
+	port (
+		Clock   : in std_ulogic;
+		Reset   : in std_ulogic;
+		Sig_in  : in std_ulogic;
+		Sig_out : out std_ulogic
+	);
+end entity;
+
+architecture rtl of repro1 is
+begin
+  reg: process(Clock, Reset)
+    variable pl_regs : std_ulogic;
+  begin
+    if Reset = '1' then
+      pl_regs := '0';
+    elsif rising_edge(Clock) then
+      pl_regs := Sig_in;
+    end if;
+
+    Sig_out <= pl_regs;
+  end process;
+end architecture;
diff --git a/testsuite/synth/issue1211/tb_delay_ul.vhdl b/testsuite/synth/issue1211/tb_delay_ul.vhdl
new file mode 100644
index 000000000..d7df0152d
--- /dev/null
+++ b/testsuite/synth/issue1211/tb_delay_ul.vhdl
@@ -0,0 +1,77 @@
+entity tb_delay_ul is
+end tb_delay_ul;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_delay_ul is
+  signal clk : std_logic;
+  signal rst : std_logic;
+  signal din : std_logic;
+  signal dout : std_logic;
+  signal en : std_logic;
+begin
+  dut: entity work.delay_ul
+    port map (
+      sig_out => dout,
+      sig_in => din,
+      clock => clk,
+      reset => rst,
+      Enable => En);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    rst <= '1';
+    en <= '1';
+    wait for 1 ns;
+    assert dout = '0' severity failure;
+    rst <= '0';
+
+    din <= '1';
+    pulse;
+    assert dout = '0' severity failure;
+
+    din <= '1';
+    pulse;
+    assert dout = '0' severity failure;
+
+    din <= '0';
+    pulse;
+    assert dout = '0' severity failure;
+
+    din <= '1';
+    pulse;
+    assert dout = '1' severity failure;
+
+    din <= '1';
+    pulse;
+    assert dout = '1' severity failure;
+
+    din <= '1';
+    pulse;
+    assert dout = '0' severity failure;
+
+    din <= '1';
+    pulse;
+    assert dout = '1' severity failure;
+
+    din <= '1';
+    rst <= '1';
+    pulse;
+    assert dout = '0' severity failure;
+
+    rst <= '0';
+    din <= '1';
+    pulse;
+    assert dout = '0' severity failure;
+    
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/issue1211/tb_repro1.vhdl b/testsuite/synth/issue1211/tb_repro1.vhdl
new file mode 100644
index 000000000..9d02396fd
--- /dev/null
+++ b/testsuite/synth/issue1211/tb_repro1.vhdl
@@ -0,0 +1,47 @@
+entity tb_repro1 is
+end tb_repro1;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_repro1 is
+  signal clk : std_logic;
+  signal rst : std_logic;
+  signal din : std_logic;
+  signal dout : std_logic;
+begin
+  dut: entity work.repro1
+    port map (
+      sig_out => dout,
+      sig_in => din,
+      clock => clk,
+      reset => rst);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    rst <= '1';
+    wait for 1 ns;
+    assert dout = '0' severity failure;
+    rst <= '0';
+    din <= '1';
+    pulse;
+    assert dout = '1' severity failure;
+    din <= '0';
+    pulse;
+    assert dout = '0' severity failure;
+    din <= '1';
+    pulse;
+    assert dout = '1' severity failure;
+    rst <= '1';
+    wait for 1 ns;
+    assert dout = '0' severity failure;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/issue1211/testsuite.sh b/testsuite/synth/issue1211/testsuite.sh
new file mode 100755
index 000000000..8f5cdf1e5
--- /dev/null
+++ b/testsuite/synth/issue1211/testsuite.sh
@@ -0,0 +1,8 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+synth_tb repro1
+synth_tb delay_ul
+
+echo "Test successful"