From 62dd5df344c6ff76554920b09dce40641e0faf8c Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Sat, 16 May 2020 08:21:35 +0200
Subject: ghdl.cc: handle Id_Iinout

---
 src/ghdl.cc | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'src')

diff --git a/src/ghdl.cc b/src/ghdl.cc
index ef2ddaf..6f7ff3a 100644
--- a/src/ghdl.cc
+++ b/src/ghdl.cc
@@ -680,6 +680,7 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m)
 			}
 			break;
 		case Id_Inout:
+		case Id_Iinout:
 			//  The wire was created when the port was.
 			break;
 		case Id_Assert:
@@ -983,6 +984,7 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m)
 			module->connect(OUT (0), IN (0));
 			break;
 		case Id_Inout:
+		case Id_Iinout:
 			// Virtual gate.
 			// Connect input to output.
 			module->connect(OUT(0), IN(0));
-- 
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