From 910073d647e55d133494429d8c3a4bacffc32428 Mon Sep 17 00:00:00 2001 From: eine <6628437+eine@users.noreply.github.com> Date: Sun, 19 Jan 2020 03:25:43 +0000 Subject: migrate from Travis to GHA and rework examples (#78) * migrate from Travis to GHA * rework examples --- .github/workflows/push.yml | 18 +++++ .travis.yml | 5 -- ci.sh | 90 +++++++++++++++++++++++ examples/ice40hx8k/leds.vhdl | 8 +++ examples/ice40hx8k/pinmap.pcf | 13 ++++ examples/ice40hx8k/spin1.vhdl | 54 ++++++++++++++ examples/ice40hx8k/spin2.vhdl | 29 ++++++++ examples/icestick/blink.vhdl | 23 ++++++ examples/icestick/fixed1.vhdl | 4 ++ examples/icestick/leds.pcf | 6 ++ examples/icestick/leds.vhdl | 16 +++++ examples/icestick/multi1.vhdl | 83 ++++++++++++++++++++++ examples/icestick/multi2.vhdl | 41 +++++++++++ examples/icestick/rotate1.vhdl | 51 ++++++++++++++ examples/icestick/rotate2.vhdl | 35 +++++++++ examples/icestick/rotate3.vhdl | 38 ++++++++++ examples/icestick/rotate4.vhdl | 41 +++++++++++ examples/icestick/spin1.vhdl | 51 ++++++++++++++ examples/icestick/spin2.vhdl | 51 ++++++++++++++ examples/icestick/uart/README.md | 11 +++ examples/icestick/uart/hdl/uart_rx.vhd | 66 +++++++++++++++++ examples/icestick/uart/hdl/uart_top.vhd | 49 +++++++++++++ examples/icestick/uart/hdl/uart_tx.vhd | 62 ++++++++++++++++ examples/icestick/uart/syn/constraints/uart.pcf | 6 ++ examples/icestick/uart/syn/synth.sh | 15 ++++ examples/icezum/Makefile | 23 ++++++ examples/icezum/blink.vhdl | 35 +++++++++ examples/icezum/counter.vhdl | 35 +++++++++ examples/icezum/icezum.pcf | 13 ++++ examples/icezum/led_on.vhdl | 15 ++++ examples/icezum/pushbutton.vhdl | 18 +++++ examples/icezum/test.sh | 13 ++++ ice40hx8k/leds.vhdl | 8 --- ice40hx8k/pinmap.pcf | 13 ---- ice40hx8k/spin1.vhdl | 54 -------------- ice40hx8k/spin2.vhdl | 29 -------- icestick/blink.vhdl | 23 ------ icestick/fixed1.vhdl | 4 -- icestick/leds.pcf | 6 -- icestick/leds.vhdl | 16 ----- icestick/multi1.vhdl | 83 ---------------------- icestick/multi2.vhdl | 41 ----------- icestick/rotate1.vhdl | 51 -------------- icestick/rotate2.vhdl | 35 --------- icestick/rotate3.vhdl | 38 ---------- icestick/rotate4.vhdl | 41 ----------- icestick/spin1.vhdl | 51 -------------- icestick/spin2.vhdl | 51 -------------- icestick/uart/README.md | 11 --- icestick/uart/hdl/uart_rx.vhd | 66 ----------------- icestick/uart/hdl/uart_top.vhd | 49 ------------- icestick/uart/hdl/uart_tx.vhd | 62 ---------------- icestick/uart/syn/constraints/uart.pcf | 6 -- icestick/uart/syn/synth.sh | 15 ---- icezum/blink/Makefile | 32 --------- icezum/blink/README.md | 16 ----- icezum/blink/blink.pcf | 11 --- icezum/blink/blink.vhdl | 35 --------- icezum/counter-8bits/Makefile | 32 --------- icezum/counter-8bits/README.md | 16 ----- icezum/counter-8bits/counter8.pcf | 9 --- icezum/counter-8bits/counter8.vhdl | 38 ---------- icezum/led_on/Makefile | 31 -------- icezum/led_on/README.md | 16 ----- icezum/led_on/led_on.pcf | 9 --- icezum/led_on/led_on.vhdl | 20 ------ icezum/pushbutton/Makefile | 32 --------- icezum/pushbutton/README.md | 17 ----- icezum/pushbutton/pushbutton.pcf | 7 -- icezum/pushbutton/pushbutton.vhdl | 14 ---- icezum/pushbutton_and/Makefile | 32 --------- icezum/pushbutton_and/README.md | 17 ----- icezum/pushbutton_and/pushbutton_and.pcf | 4 -- icezum/pushbutton_and/pushbutton_and.vhdl | 18 ----- testsuite/examples/test-ice40hx8k/testsuite.sh | 2 +- testsuite/examples/test-icestick/testsuite.sh | 2 +- testsuite/examples/test-icezum/testsuite.sh | 10 +-- testsuite/testenv.sh | 12 ++-- travis.sh | 94 ------------------------- utils.sh | 56 +++++---------- 80 files changed, 1044 insertions(+), 1309 deletions(-) create mode 100644 .github/workflows/push.yml delete mode 100644 .travis.yml create mode 100755 ci.sh create mode 100644 examples/ice40hx8k/leds.vhdl create mode 100644 examples/ice40hx8k/pinmap.pcf create mode 100644 examples/ice40hx8k/spin1.vhdl create mode 100644 examples/ice40hx8k/spin2.vhdl create mode 100644 examples/icestick/blink.vhdl create mode 100644 examples/icestick/fixed1.vhdl create mode 100644 examples/icestick/leds.pcf create mode 100644 examples/icestick/leds.vhdl create mode 100644 examples/icestick/multi1.vhdl create mode 100644 examples/icestick/multi2.vhdl create mode 100644 examples/icestick/rotate1.vhdl create mode 100644 examples/icestick/rotate2.vhdl create mode 100644 examples/icestick/rotate3.vhdl create mode 100644 examples/icestick/rotate4.vhdl create mode 100644 examples/icestick/spin1.vhdl create mode 100644 examples/icestick/spin2.vhdl create mode 100755 examples/icestick/uart/README.md create mode 100755 examples/icestick/uart/hdl/uart_rx.vhd create mode 100755 examples/icestick/uart/hdl/uart_top.vhd create mode 100755 examples/icestick/uart/hdl/uart_tx.vhd create mode 100755 examples/icestick/uart/syn/constraints/uart.pcf create mode 100755 examples/icestick/uart/syn/synth.sh create mode 100644 examples/icezum/Makefile create mode 100644 examples/icezum/blink.vhdl create mode 100644 examples/icezum/counter.vhdl create mode 100644 examples/icezum/icezum.pcf create mode 100644 examples/icezum/led_on.vhdl create mode 100644 examples/icezum/pushbutton.vhdl create mode 100755 examples/icezum/test.sh delete mode 100644 ice40hx8k/leds.vhdl delete mode 100644 ice40hx8k/pinmap.pcf delete mode 100644 ice40hx8k/spin1.vhdl delete mode 100644 ice40hx8k/spin2.vhdl delete mode 100644 icestick/blink.vhdl delete mode 100644 icestick/fixed1.vhdl delete mode 100644 icestick/leds.pcf delete mode 100644 icestick/leds.vhdl delete mode 100644 icestick/multi1.vhdl delete mode 100644 icestick/multi2.vhdl delete mode 100644 icestick/rotate1.vhdl delete mode 100644 icestick/rotate2.vhdl delete mode 100644 icestick/rotate3.vhdl delete mode 100644 icestick/rotate4.vhdl delete mode 100644 icestick/spin1.vhdl delete mode 100644 icestick/spin2.vhdl delete mode 100755 icestick/uart/README.md delete mode 100755 icestick/uart/hdl/uart_rx.vhd delete mode 100755 icestick/uart/hdl/uart_top.vhd delete mode 100755 icestick/uart/hdl/uart_tx.vhd delete mode 100755 icestick/uart/syn/constraints/uart.pcf delete mode 100755 icestick/uart/syn/synth.sh delete mode 100644 icezum/blink/Makefile delete mode 100644 icezum/blink/README.md delete mode 100644 icezum/blink/blink.pcf delete mode 100644 icezum/blink/blink.vhdl delete mode 100644 icezum/counter-8bits/Makefile delete mode 100644 icezum/counter-8bits/README.md delete mode 100644 icezum/counter-8bits/counter8.pcf delete mode 100644 icezum/counter-8bits/counter8.vhdl delete mode 100644 icezum/led_on/Makefile delete mode 100644 icezum/led_on/README.md delete mode 100644 icezum/led_on/led_on.pcf delete mode 100644 icezum/led_on/led_on.vhdl delete mode 100644 icezum/pushbutton/Makefile delete mode 100644 icezum/pushbutton/README.md delete mode 100644 icezum/pushbutton/pushbutton.pcf delete mode 100644 icezum/pushbutton/pushbutton.vhdl delete mode 100644 icezum/pushbutton_and/Makefile delete mode 100644 icezum/pushbutton_and/README.md delete mode 100644 icezum/pushbutton_and/pushbutton_and.pcf delete mode 100644 icezum/pushbutton_and/pushbutton_and.vhdl delete mode 100755 travis.sh diff --git a/.github/workflows/push.yml b/.github/workflows/push.yml new file mode 100644 index 0000000..fc405ef --- /dev/null +++ b/.github/workflows/push.yml @@ -0,0 +1,18 @@ +name: 'push' + +on: + push: + schedule: + - cron: '0 0 * * 5' + +env: + CI: true + DOCKER_BUILDKIT: 1 + +jobs: + + test: + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v1 + - run: ./ci.sh diff --git a/.travis.yml b/.travis.yml deleted file mode 100644 index 9940b13..0000000 --- a/.travis.yml +++ /dev/null @@ -1,5 +0,0 @@ -os: linux -services: docker -language: minimal -install: skip -script: ./travis.sh diff --git a/ci.sh b/ci.sh new file mode 100755 index 0000000..06d595f --- /dev/null +++ b/ci.sh @@ -0,0 +1,90 @@ +#!/bin/sh + +set -e + +cd "$(dirname $0)" +. ./utils.sh + +#-- +gstart "[Build] ghdl/synth:latest" "$ANSI_MAGENTA" + +case "$TRAVIS_COMMIT_MESSAGE" in + "*[stable]*") + echo "IS_STABLE" + GHDL_URL="https://github.com/ghdl/ghdl/archive/9d61a62f96dc4897dadbf88f5f4ee199d20e0f8f.tar.gz" + ;; + *) + echo "IS_MASTER" + GHDL_URL="https://codeload.github.com/ghdl/ghdl/tar.gz/master" + ;; +esac +echo "GHDL_URL: $GHDL_URL" + +docker build -t tmp - <<-EOF +FROM ghdl/build:buster-mcode + +RUN apt-get update -qq \ + && DEBIAN_FRONTEND=noninteractive apt-get -y install --no-install-recommends \ + ca-certificates \ + curl \ + && apt-get autoclean && apt-get clean && apt-get -y autoremove \ + && update-ca-certificates \ + && rm -rf /var/lib/apt/lists + +RUN mkdir -p ghdl && cd ghdl \ + && curl -fsSL "$GHDL_URL" | tar xzf - --strip-components=1 \ + && ./configure --enable-libghdl --enable-synth \ + && make all \ + && make DESTDIR=/opt/ghdl install +EOF + +docker build -t ghdl/synth:latest - <<-EOF +FROM ghdl/run:buster-mcode +COPY --from=tmp /opt/ghdl / +EOF + +gend +#-- +gstart "[Build] ghdl/synth:beta" "$ANSI_MAGENTA" + +docker build -t ghdl/synth:beta . -f- <<-EOF +FROM ghdl/cache:yosys-gnat AS build +COPY --from=tmp /opt/ghdl /opt/ghdl +COPY . /ghdlsynth + +RUN cp -vr /opt/ghdl/* / \ + && cd /ghdlsynth \ + && make \ + && cp ghdl.so /opt/ghdl/usr/local/lib/ghdl_yosys.so + +FROM ghdl/cache:yosys-gnat +COPY --from=build /opt/ghdl / +RUN yosys-config --exec mkdir -p --datdir/plugins \ + && yosys-config --exec ln -s /usr/local/lib/ghdl_yosys.so --datdir/plugins/ghdl.so +EOF + +gend +#--- +gstart "[Build] ghdl/synth:formal" "$ANSI_MAGENTA" + +docker build -t ghdl/synth:formal . -f- <<-EOF +FROM ghdl/synth:beta + +COPY --from=ghdl/cache:formal ./z3 / +COPY --from=ghdl/cache:formal ./symbiyosys / + +RUN apt-get update -qq \ + && DEBIAN_FRONTEND=noninteractive apt-get -y install --no-install-recommends \ + python3 \ + && apt-get autoclean && apt-get clean && apt-get -y autoremove \ + && rm -rf /var/lib/apt/lists/* +EOF + +gend "formal" +#--- +printf "${ANSI_MAGENTA}[Test] testsuite ${ANSI_NOCOLOR}\n" + +docker run --rm -t -e CI -v /$(pwd)://src -w //src -e YOSYS='yosys -m ghdl' ghdl/synth:formal bash -c "$(cat < + case count is + when "00" => + leds <= "10001"; + when "01" => + leds <= "01000"; + when "10" => + leds <= "00101"; + when "11" => + leds <= "00010"; + when others => + null; + end case; + when "1" => + case count is + when "00" => + leds <= "10000"; + when "01" => + leds <= "01011"; + when "10" => + leds <= "00100"; + when "11" => + leds <= "01011"; + when others => + null; + end case; + when others => + null; + end case; + count := count + 1; + end if; + if clk_5sec = '1' then + pat_count := pat_count + 1; + count := "00"; + end if; + end if; + end process; +end multi1; diff --git a/examples/icestick/multi2.vhdl b/examples/icestick/multi2.vhdl new file mode 100644 index 0000000..78bf298 --- /dev/null +++ b/examples/icestick/multi2.vhdl @@ -0,0 +1,41 @@ +architecture multi2 of leds is + signal clk_4hz: std_logic; + signal clk_5sec : std_logic; +begin + process (clk) + -- 3_000_000 is 0x2dc6c0 + variable counter : unsigned (23 downto 0); + begin + if rising_edge(clk) then + if counter = 2_999_999 then + counter := x"000000"; + clk_4hz <= '1'; + else + counter := counter + 1; + clk_4hz <= '0'; + end if; + end if; + end process; + + process (clk) + variable counter5 : unsigned (4 downto 0); + begin + if rising_edge (clk) then + clk_5sec <= '0'; + if clk_4hz = '1' then + if counter5 = 19 then + clk_5sec <= '1'; + counter5 := "00000"; + else + counter5 := counter5 + 1; + end if; + end if; + end if; + end process; + + led1 <= clk_5sec; + led2 <= '0'; + led3 <= '0'; + led4 <= '0'; + led5 <= '0'; +end multi2; diff --git a/examples/icestick/rotate1.vhdl b/examples/icestick/rotate1.vhdl new file mode 100644 index 0000000..34c7afd --- /dev/null +++ b/examples/icestick/rotate1.vhdl @@ -0,0 +1,51 @@ +architecture rotate1 of leds is + signal clk_4hz: std_logic; +begin + process (clk) + -- 3_000_000 is 0x2dc6c0 + variable counter : unsigned (23 downto 0); + begin + if rising_edge(clk) then + if counter = 2_999_999 then + counter := x"000000"; + clk_4hz <= '1'; + else + counter := counter + 1; + clk_4hz <= '0'; + end if; + end if; + end process; + + process (clk) + variable count : unsigned (1 downto 0); + begin + if rising_edge(clk) and clk_4hz = '1' then + count := count + 1; + if count = 0 then + led1 <= '1'; + led2 <= '0'; + led3 <= '0'; + led4 <= '0'; + led5 <= '1'; + elsif count = 1 then + led1 <= '0'; + led2 <= '1'; + led3 <= '0'; + led4 <= '0'; + led5 <= '0'; + elsif count = 2 then + led1 <= '0'; + led2 <= '0'; + led3 <= '1'; + led4 <= '0'; + led5 <= '1'; + else + led1 <= '0'; + led2 <= '0'; + led3 <= '0'; + led4 <= '1'; + led5 <= '0'; + end if; + end if; + end process; +end rotate1; diff --git a/examples/icestick/rotate2.vhdl b/examples/icestick/rotate2.vhdl new file mode 100644 index 0000000..e51ec6c --- /dev/null +++ b/examples/icestick/rotate2.vhdl @@ -0,0 +1,35 @@ +architecture rotate2 of leds is + signal clk_4hz: std_logic; +begin + process (clk) + -- 3_000_000 is 0x2dc6c0 + variable counter : unsigned (23 downto 0); + begin + if rising_edge(clk) then + if counter = 2_999_999 then + counter := x"000000"; + clk_4hz <= '1'; + else + counter := counter + 1; + clk_4hz <= '0'; + end if; + end if; + end process; + + process (clk) + variable count : unsigned (1 downto 0); + begin + if rising_edge(clk) and clk_4hz = '1' then + count := count + 1; + if count = 0 then + (led1, led2, led3, led4, led5) <= unsigned'("10001"); + elsif count = 1 then + (led1, led2, led3, led4, led5) <= unsigned'("01000"); + elsif count = 2 then + (led1, led2, led3, led4, led5) <= unsigned'("00101"); + else + (led1, led2, led3, led4, led5) <= unsigned'("00010"); + end if; + end if; + end process; +end rotate2; diff --git a/examples/icestick/rotate3.vhdl b/examples/icestick/rotate3.vhdl new file mode 100644 index 0000000..213512f --- /dev/null +++ b/examples/icestick/rotate3.vhdl @@ -0,0 +1,38 @@ +architecture rotate3 of leds is + signal clk_4hz: std_logic; +begin + process (clk) + -- 3_000_000 is 0x2dc6c0 + variable counter : unsigned (23 downto 0); + begin + if rising_edge(clk) then + if counter = 2_999_999 then + counter := x"000000"; + clk_4hz <= '1'; + else + counter := counter + 1; + clk_4hz <= '0'; + end if; + end if; + end process; + + process (clk) + variable count : unsigned (1 downto 0); + begin + if rising_edge(clk) and clk_4hz = '1' then + case count is + when "00" => + (led1, led2, led3, led4, led5) <= unsigned'("10001"); + when "01" => + (led1, led2, led3, led4, led5) <= unsigned'("01000"); + when "10" => + (led1, led2, led3, led4, led5) <= unsigned'("00101"); + when "11" => + (led1, led2, led3, led4, led5) <= unsigned'("00010"); + when others => + null; + end case; + count := count + 1; + end if; + end process; +end rotate3; diff --git a/examples/icestick/rotate4.vhdl b/examples/icestick/rotate4.vhdl new file mode 100644 index 0000000..e89aaa5 --- /dev/null +++ b/examples/icestick/rotate4.vhdl @@ -0,0 +1,41 @@ +architecture rotate4 of leds is + signal clk_4hz: std_logic; + signal leds : std_ulogic_vector (1 to 5); +begin + (led1, led2, led3, led4, led5) <= leds; + + process (clk) + -- 3_000_000 is 0x2dc6c0 + variable counter : unsigned (23 downto 0); + begin + if rising_edge(clk) then + if counter = 2_999_999 then + counter := x"000000"; + clk_4hz <= '1'; + else + counter := counter + 1; + clk_4hz <= '0'; + end if; + end if; + end process; + + process (clk) + variable count : unsigned (1 downto 0); + begin + if rising_edge(clk) and clk_4hz = '1' then + case count is + when "00" => + leds <= "10001"; + when "01" => + leds <= "01000"; + when "10" => + leds <= "00101"; + when "11" => + leds <= "00010"; + when others => + null; + end case; + count := count + 1; + end if; + end process; +end rotate4; diff --git a/examples/icestick/spin1.vhdl b/examples/icestick/spin1.vhdl new file mode 100644 index 0000000..79e305c --- /dev/null +++ b/examples/icestick/spin1.vhdl @@ -0,0 +1,51 @@ +architecture spin1 of leds is + signal nrst : std_logic := '0'; + signal clk_4hz: std_logic; + signal leds : std_ulogic_vector (1 to 5); +begin + (led1, led2, led3, led4, led5) <= leds; + + process (clk) + variable cnt : unsigned (1 downto 0) := "00"; + begin + if rising_edge (clk) then + if cnt = 3 then + nrst <= '1'; + else + cnt := cnt + 1; + end if; + end if; + end process; + + process (clk) + -- 3_000_000 is 0x2dc6c0 + variable counter : unsigned (23 downto 0); + begin + if rising_edge(clk) then + if nrst = '0' then + counter := x"000000"; + else + if counter = 2_999_999 then + counter := x"000000"; + clk_4hz <= '1'; + else + counter := counter + 1; + clk_4hz <= '0'; + end if; + end if; + end if; + end process; + + process (clk) + begin + if rising_edge(clk) then + if nrst = '0' then + -- Initialize + leds <= "11000"; + elsif clk_4hz = '1' then + -- Rotate + leds <= (leds (4), leds (1), leds (2), leds (3), '0'); + end if; + end if; + end process; +end spin1; diff --git a/examples/icestick/spin2.vhdl b/examples/icestick/spin2.vhdl new file mode 100644 index 0000000..0f23964 --- /dev/null +++ b/examples/icestick/spin2.vhdl @@ -0,0 +1,51 @@ +architecture spin1 of leds is + signal nrst : std_logic := '0'; + signal clk_4hz: std_logic; + signal leds : std_ulogic_vector (1 to 5); +begin + (led1, led2, led3, led4, led5) <= leds; + + process (clk) + variable cnt : unsigned (1 downto 0) := "00"; + begin + if rising_edge (clk) then + if cnt = 3 then + nrst <= '1'; + else + cnt := cnt + 1; + end if; + end if; + end process; + + process (clk) + -- 3_000_000 is 0x2dc6c0 + variable counter : unsigned (23 downto 0); + begin + if rising_edge(clk) then + if nrst = '0' then + counter := x"000000"; + else + if counter = 2_999_999 then + counter := x"000000"; + clk_4hz <= '1'; + else + counter := counter + 1; + clk_4hz <= '0'; + end if; + end if; + end if; + end process; + + process (clk) + begin + if rising_edge(clk) then + if nrst = '0' then + -- Initialize + leds <= "11000"; + elsif clk_4hz = '1' then + -- Rotate + leds <= leds (4) & leds (1) & leds (2) & leds (3) & '0'; + end if; + end if; + end process; +end spin1; diff --git a/examples/icestick/uart/README.md b/examples/icestick/uart/README.md new file mode 100755 index 0000000..b53def6 --- /dev/null +++ b/examples/icestick/uart/README.md @@ -0,0 +1,11 @@ +# icestick-uart +Simple UART sender and receiver for the lattice icestick. It echoes every received word back. +Configuration: 115200 8N1 + +## Repository structure +- hdl: Contains the hardware design. +- syn: Contains the scripts and constraints for synthesis. + +## Usage +- `cd syn && ./synth.sh` +- configure and open putty or another serial terminal and type something \ No newline at end of file diff --git a/examples/icestick/uart/hdl/uart_rx.vhd b/examples/icestick/uart/hdl/uart_rx.vhd new file mode 100755 index 0000000..5f488cc --- /dev/null +++ b/examples/icestick/uart/hdl/uart_rx.vhd @@ -0,0 +1,66 @@ +library ieee; + use ieee.std_logic_1164.all; + +entity uart_rx is + generic ( + C_BITS : integer := 8; + C_CYCLES_PER_BIT : integer := 104 + ); + port ( + isl_clk : in std_logic; + isl_data_n : in std_logic; + oslv_data : out std_logic_vector(C_BITS-1 downto 0); + osl_valid : out std_logic + ); +end entity uart_rx; + +architecture rtl of uart_rx is + signal int_cycle_cnt : integer range 0 to C_CYCLES_PER_BIT-1 := 0; + signal int_bit_cnt : integer range 0 to C_BITS+1 := 0; + + signal slv_data : std_logic_vector(C_BITS-1 downto 0) := (others => '0'); + signal sl_valid : std_logic := '0'; + + type t_state is (IDLE, INIT, RECEIVE); + signal state : t_state; + +begin + process(isl_clk) + begin + if rising_edge(isl_clk) then + case state is + when IDLE => + sl_valid <= '0'; + if isl_data_n = '0' then + -- wait for the start bit + state <= INIT; + end if; + + when INIT => + int_cycle_cnt <= C_CYCLES_PER_BIT / 2; + int_bit_cnt <= 0; + state <= RECEIVE; + + when RECEIVE => + if int_bit_cnt < C_BITS+1 then + if int_cycle_cnt < C_CYCLES_PER_BIT-1 then + int_cycle_cnt <= int_cycle_cnt+1; + else + -- receive data bits + int_cycle_cnt <= 0; + int_bit_cnt <= int_bit_cnt+1; + slv_data <= not isl_data_n & slv_data(slv_data'LEFT downto 1); -- low active + end if; + elsif isl_data_n = '1' then + -- wait for the stop bit + sl_valid <= '1'; + state <= IDLE; + end if; + + end case; + end if; + end process; + + oslv_data <= slv_data; + osl_valid <= sl_valid; +end architecture rtl; diff --git a/examples/icestick/uart/hdl/uart_top.vhd b/examples/icestick/uart/hdl/uart_top.vhd new file mode 100755 index 0000000..889a3a0 --- /dev/null +++ b/examples/icestick/uart/hdl/uart_top.vhd @@ -0,0 +1,49 @@ +library ieee; + use ieee.std_logic_1164.all; + +entity uart_top is + generic ( + C_BITS : integer := 8 + ); + port ( + isl_clk : in std_logic; + isl_data_n : in std_logic; + osl_data_n : out std_logic; + osl_ready : out std_logic + ); +end uart_top; + +architecture behavioral of uart_top is + constant C_QUARTZ_FREQ : integer := 12000000; -- Hz + constant C_BAUDRATE : integer := 115200; -- words / s + constant C_CYCLES_PER_BIT : integer := C_QUARTZ_FREQ / C_BAUDRATE; + + signal sl_valid_out_tx : std_logic := '0'; + signal slv_data_out_tx : std_logic_vector(C_BITS-1 downto 0) := (others => '0'); + +begin + i_uart_rx: entity work.uart_rx + generic map ( + C_BITS => C_BITS, + C_CYCLES_PER_BIT => C_CYCLES_PER_BIT + ) + port map ( + isl_clk => isl_clk, + isl_data_n => isl_data_n, + oslv_data => slv_data_out_tx, + osl_valid => sl_valid_out_tx + ); + + i_uart_tx: entity work.uart_tx + generic map ( + C_BITS => C_BITS, + C_CYCLES_PER_BIT => C_CYCLES_PER_BIT + ) + port map ( + isl_clk => isl_clk, + isl_valid => sl_valid_out_tx, + islv_data => slv_data_out_tx, + osl_data_n => osl_data_n, + osl_ready => osl_ready + ); +end behavioral; \ No newline at end of file diff --git a/examples/icestick/uart/hdl/uart_tx.vhd b/examples/icestick/uart/hdl/uart_tx.vhd new file mode 100755 index 0000000..b6c5800 --- /dev/null +++ b/examples/icestick/uart/hdl/uart_tx.vhd @@ -0,0 +1,62 @@ +library ieee; + use ieee.std_logic_1164.all; + +entity uart_tx is + generic ( + -- TODO: range in submodules is not yet supported by synthesis + -- it would be useful to limit between 5 to 8 + C_BITS : integer := 8; + C_CYCLES_PER_BIT : integer := 104 + ); + port ( + isl_clk : in std_logic; + isl_valid : in std_logic; + islv_data : in std_logic_vector(C_BITS-1 downto 0); + osl_ready : out std_logic; + osl_data_n : out std_logic + ); +end entity uart_tx; + +architecture rtl of uart_tx is + signal int_cycle_cnt : integer range 0 to C_CYCLES_PER_BIT-1 := 0; + signal int_bit_cnt : integer range 0 to C_BITS+2 := 0; + + signal slv_data : std_logic_vector(C_BITS downto 0) := (others => '0'); + + type t_state is (IDLE, INIT, SEND); + signal state : t_state; + +begin + process(isl_clk) + begin + if rising_edge(isl_clk) then + case state is + when IDLE => + if isl_valid = '1' then + state <= INIT; + end if; + + when INIT => + int_cycle_cnt <= 0; + int_bit_cnt <= 0; + slv_data <= islv_data & '1'; + state <= SEND; + + when SEND => + if int_cycle_cnt < C_CYCLES_PER_BIT-1 then + int_cycle_cnt <= int_cycle_cnt+1; + elsif int_bit_cnt < C_BITS+1 then + int_cycle_cnt <= 0; + int_bit_cnt <= int_bit_cnt+1; + slv_data <= '0' & slv_data(slv_data'LEFT downto 1); + else + state <= IDLE; + end if; + + end case; + end if; + end process; + + osl_ready <= '1' when state = IDLE else '0'; + osl_data_n <= not slv_data(0); -- low active +end architecture rtl; \ No newline at end of file diff --git a/examples/icestick/uart/syn/constraints/uart.pcf b/examples/icestick/uart/syn/constraints/uart.pcf new file mode 100755 index 0000000..e3e5016 --- /dev/null +++ b/examples/icestick/uart/syn/constraints/uart.pcf @@ -0,0 +1,6 @@ +# FTDI Port B UART +set_io osl_data_n 8 # UART TX +set_io isl_data_n 9 # UART RX + +# 12 MHz clock +set_io isl_clk 21 diff --git a/examples/icestick/uart/syn/synth.sh b/examples/icestick/uart/syn/synth.sh new file mode 100755 index 0000000..884f1b6 --- /dev/null +++ b/examples/icestick/uart/syn/synth.sh @@ -0,0 +1,15 @@ +set -e + +ROOT="$(pwd)/.." + +rm -rf build +mkdir -p build +cd build + +ghdl -a "$ROOT"/hdl/uart_rx.vhd +ghdl -a "$ROOT"/hdl/uart_tx.vhd +ghdl -a "$ROOT"/hdl/uart_top.vhd +yosys -m ghdl -p 'ghdl uart_top; synth_ice40 -json uart_top.json' +nextpnr-ice40 --hx1k --json uart_top.json --pcf ../constraints/uart.pcf --asc uart_top.asc --pcf-allow-unconstrained +icepack uart_top.asc uart_top.bin +iceprog uart_top.bin diff --git a/examples/icezum/Makefile b/examples/icezum/Makefile new file mode 100644 index 0000000..ab6f5d7 --- /dev/null +++ b/examples/icezum/Makefile @@ -0,0 +1,23 @@ +PROJ ?= blink +PIN_DEF = icezum.pcf +DEVICE = hx1k + +all: report bin + +json: $(PROJ).vhdl + yosys -m ghdl -p 'ghdl $(PROJ).vhdl -e $(PROJ); synth_ice40 -json $@' + +asc: $(PIN_DEF) json + nextpnr-ice40 --$(DEVICE) --json json --pcf $(PIN_DEF) --asc $@ + +bin: asc + icepack $< $@ + +report: asc + icetime -d $(DEVICE) -mtr $@ $< + +clean: + rm -f json asc bin report work-obj93.cf + +.SECONDARY: +.PHONY: all prog clean diff --git a/examples/icezum/blink.vhdl b/examples/icezum/blink.vhdl new file mode 100644 index 0000000..81c32ed --- /dev/null +++ b/examples/icezum/blink.vhdl @@ -0,0 +1,35 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity blink is + port ( + clk : in std_logic; + led0, led1, led2, led3, led4, led5, led6, led7 : out std_logic + ); +end blink; + +architecture synth of blink is + signal blink: std_logic; +begin + process (clk) + variable cnt : unsigned (23 downto 0); -- 3_000_000 requires 24 bits + begin + if rising_edge(clk) then + if cnt = 2_999_999 then + cnt := x"000000"; + blink <= not blink; + else + cnt := cnt + 1; + end if; + end if; + end process; + led0 <= blink; + led1 <= blink; + led2 <= blink; + led3 <= blink; + led4 <= blink; + led5 <= blink; + led6 <= blink; + led7 <= blink; +end synth; diff --git a/examples/icezum/counter.vhdl b/examples/icezum/counter.vhdl new file mode 100644 index 0000000..9cc4d7e --- /dev/null +++ b/examples/icezum/counter.vhdl @@ -0,0 +1,35 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity counter is + port ( + clk : in std_logic; + led0, led1, led2, led3, led4, led5, led6, led7 : out std_logic + ); +end counter; + +architecture synth of counter is + signal clk_6hz : std_logic; +begin + -- Presscaler + prescaler: process(clk) + variable timer : unsigned (20 downto 0) := (others=>'0'); + begin + if rising_edge(clk) then + timer := timer + 1; + clk_6hz <= timer(20); + end if; + end process; + + -- 8 bits counter + process (clk_6hz) + variable temp : unsigned (7 downto 0); + begin + if rising_edge(clk_6hz) then + temp:= temp + 1; + -- Show the counter on the icezum Alhambra leds + (led7, led6, led5, led4, led3, led2, led1, led0) <= temp; + end if; + end process; +end synth; diff --git a/examples/icezum/icezum.pcf b/examples/icezum/icezum.pcf new file mode 100644 index 0000000..9ea27ad --- /dev/null +++ b/examples/icezum/icezum.pcf @@ -0,0 +1,13 @@ +set_io sw1 10 +set_io sw2 11 + +set_io clk 21 + +set_io led0 95 +set_io led1 96 +set_io led2 97 +set_io led3 98 +set_io led4 99 +set_io led5 101 +set_io led6 102 +set_io led7 104 diff --git a/examples/icezum/led_on.vhdl b/examples/icezum/led_on.vhdl new file mode 100644 index 0000000..a67ead4 --- /dev/null +++ b/examples/icezum/led_on.vhdl @@ -0,0 +1,15 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity led_on is + port (led0, led1, led2, led3, led4, led5, led6, led7 : out std_logic); +end led_on; + +architecture test of led_on is +begin + -- Turn on the Led0 + led0 <= '1'; + -- Turn off the other leds + (led1, led2, led3, led4, led5, led6, led7) <= std_logic_vector'("0000000"); +end test; diff --git a/examples/icezum/pushbutton.vhdl b/examples/icezum/pushbutton.vhdl new file mode 100644 index 0000000..55ede2f --- /dev/null +++ b/examples/icezum/pushbutton.vhdl @@ -0,0 +1,18 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity pushbutton is + port ( + sw1, sw2 : in std_logic; + led0, led7 : out std_logic + ); +end pushbutton; + +architecture synth of pushbutton is + signal a : std_logic; +begin + a <= sw1 and sw2; + led0 <= a; + led7 <= not a; +end synth; diff --git a/examples/icezum/test.sh b/examples/icezum/test.sh new file mode 100755 index 0000000..72da526 --- /dev/null +++ b/examples/icezum/test.sh @@ -0,0 +1,13 @@ +#!/usr/bin/env sh + +cd $(dirname $0) + +DOCKER_CMD="docker run --rm -v /$(pwd)://wrk -w //wrk" + +mkdir -p build + +for prj in blink counter led_on pushbutton; do + $DOCKER_CMD ghdl/synth:beta yosys -m ghdl -p "ghdl $prj.vhdl -e $prj; synth_ice40 -json build/json" + $DOCKER_CMD ghdl/synth:nextpnr nextpnr-ice40 --hx1k --json build/json --pcf icezum.pcf --asc build/asc + $DOCKER_CMD ghdl/synth:icestorm icepack build/asc build/$prj.bin +done diff --git a/ice40hx8k/leds.vhdl b/ice40hx8k/leds.vhdl deleted file mode 100644 index 557585b..0000000 --- a/ice40hx8k/leds.vhdl +++ /dev/null @@ -1,8 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity leds is - port (clk : in std_logic; - led1, led2, led3, led4, led5, led6, led7, led8 : out std_logic); -end leds; diff --git a/ice40hx8k/pinmap.pcf b/ice40hx8k/pinmap.pcf deleted file mode 100644 index 6862c43..0000000 --- a/ice40hx8k/pinmap.pcf +++ /dev/null @@ -1,13 +0,0 @@ -# example.pcf -set_io --warn-no-port led1 B5 -set_io --warn-no-port led2 B4 -set_io --warn-no-port led3 A2 -set_io --warn-no-port led4 A1 -set_io --warn-no-port led5 C5 -set_io --warn-no-port led6 C4 -set_io --warn-no-port led7 B3 -set_io --warn-no-port led8 C3 -set_io --warn-no-port clk J3 -# FTDI -set_io --warn-no-port ftdi_tx B12 -set_io --warn-no-port ftdi_rx B10 diff --git a/ice40hx8k/spin1.vhdl b/ice40hx8k/spin1.vhdl deleted file mode 100644 index 7c50586..0000000 --- a/ice40hx8k/spin1.vhdl +++ /dev/null @@ -1,54 +0,0 @@ -architecture spin1 of leds is - signal nrst : std_logic := '0'; - signal clk_4hz: std_logic; - signal leds : std_ulogic_vector (1 to 5); -begin - (led1, led2, led3, led4, led5) <= leds; - led6 <= '0'; - led7 <= '0'; - led8 <= '0'; - - process (clk) - variable cnt : unsigned (1 downto 0) := "00"; - begin - if rising_edge (clk) then - if cnt = 3 then - nrst <= '1'; - else - cnt := cnt + 1; - end if; - end if; - end process; - - process (clk) - -- 3_000_000 is 0x2dc6c0 - variable counter : unsigned (23 downto 0); - begin - if rising_edge(clk) then - if nrst = '0' then - counter := x"000000"; - else - if counter = 2_999_999 then - counter := x"000000"; - clk_4hz <= '1'; - else - counter := counter + 1; - clk_4hz <= '0'; - end if; - end if; - end if; - end process; - - process (clk) - begin - if rising_edge(clk) then - if nrst = '0' then - -- Initialize - leds <= "11000"; - elsif clk_4hz = '1' then - -- Rotate - leds <= (leds (4), leds (1), leds (2), leds (3), '0'); - end if; - end if; - end process; -end spin1; diff --git a/ice40hx8k/spin2.vhdl b/ice40hx8k/spin2.vhdl deleted file mode 100644 index ccdab8b..0000000 --- a/ice40hx8k/spin2.vhdl +++ /dev/null @@ -1,29 +0,0 @@ -architecture spin2 of leds is - signal clk_4hz: std_logic; - signal leds : std_ulogic_vector (1 to 8) := "11000000"; -begin - (led1, led2, led3, led4, led5, led6, led7, led8) <= leds; - - process (clk) - -- 3_000_000 is 0x2dc6c0 - variable counter : unsigned (23 downto 0); - begin - if rising_edge(clk) then - if counter = 2_999_999 then - counter := x"000000"; - clk_4hz <= '1'; - else - counter := counter + 1; - clk_4hz <= '0'; - end if; - end if; - end process; - - process (clk) - begin - if rising_edge(clk) and clk_4hz = '1' then - -- Rotate - leds <= (leds (8), leds (1), leds (2), leds (3), leds (4), leds (5), leds (6), leds (7)); - end if; - end process; -end spin2; diff --git a/icestick/blink.vhdl b/icestick/blink.vhdl deleted file mode 100644 index d7e6dd4..0000000 --- a/icestick/blink.vhdl +++ /dev/null @@ -1,23 +0,0 @@ -architecture blink of leds is - signal clk_4hz: std_logic; -begin - process (clk) - -- 3_000_000 is 0x2dc6c0 - variable counter : unsigned (23 downto 0); - begin - if rising_edge(clk) then - if counter = 2_999_999 then - counter := x"000000"; - clk_4hz <= not clk_4hz; - else - counter := counter + 1; - end if; - end if; - end process; - - led1 <= clk_4hz; - led2 <= clk_4hz; - led3 <= clk_4hz; - led4 <= clk_4hz; - led5 <= clk_4hz; -end blink; diff --git a/icestick/fixed1.vhdl b/icestick/fixed1.vhdl deleted file mode 100644 index b1bbf4b..0000000 --- a/icestick/fixed1.vhdl +++ /dev/null @@ -1,4 +0,0 @@ -architecture fixed1 of leds is -begin - (led1, led2, led3, led4, led5) <= std_logic_vector'("00101"); -end fixed1; diff --git a/icestick/leds.pcf b/icestick/leds.pcf deleted file mode 100644 index 397bdc4..0000000 --- a/icestick/leds.pcf +++ /dev/null @@ -1,6 +0,0 @@ -set_io led1 99 -set_io led2 98 -set_io led3 97 -set_io led4 96 -set_io led5 95 -set_io clk 21 diff --git a/icestick/leds.vhdl b/icestick/leds.vhdl deleted file mode 100644 index 95aa5cf..0000000 --- a/icestick/leds.vhdl +++ /dev/null @@ -1,16 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - --- Led positions --- --- I D3 --- r --- D D2 D5 D4 --- A --- D1 --- -entity leds is - port (clk : in std_logic; - led1, led2, led3, led4, led5 : out std_logic); -end leds; diff --git a/icestick/multi1.vhdl b/icestick/multi1.vhdl deleted file mode 100644 index a304765..0000000 --- a/icestick/multi1.vhdl +++ /dev/null @@ -1,83 +0,0 @@ -architecture multi1 of leds is - signal clk_4hz: std_logic; - signal clk_5sec : std_logic; - signal leds : std_ulogic_vector (1 to 5); -begin - (led1, led2, led3, led4, led5) <= leds; - - process (clk) - -- 3_000_000 is 0x2dc6c0 - variable counter : unsigned (23 downto 0); - begin - if rising_edge(clk) then - if counter = 2_999_999 then - counter := x"000000"; - clk_4hz <= '1'; - else - counter := counter + 1; - clk_4hz <= '0'; - end if; - end if; - end process; - - process (clk) - variable counter5 : unsigned (4 downto 0); - begin - if rising_edge (clk) then - clk_5sec <= '0'; - if clk_4hz = '1' then - if counter5 = 19 then - clk_5sec <= '1'; - counter5 := "00000"; - else - counter5 := counter5 + 1; - end if; - end if; - end if; - end process; - - process (clk) - variable count : unsigned (1 downto 0); - variable pat_count : unsigned (0 downto 0); - begin - if rising_edge(clk) then - if clk_4hz = '1' then - case pat_count is - when "0" => - case count is - when "00" => - leds <= "10001"; - when "01" => - leds <= "01000"; - when "10" => - leds <= "00101"; - when "11" => - leds <= "00010"; - when others => - null; - end case; - when "1" => - case count is - when "00" => - leds <= "10000"; - when "01" => - leds <= "01011"; - when "10" => - leds <= "00100"; - when "11" => - leds <= "01011"; - when others => - null; - end case; - when others => - null; - end case; - count := count + 1; - end if; - if clk_5sec = '1' then - pat_count := pat_count + 1; - count := "00"; - end if; - end if; - end process; -end multi1; diff --git a/icestick/multi2.vhdl b/icestick/multi2.vhdl deleted file mode 100644 index 78bf298..0000000 --- a/icestick/multi2.vhdl +++ /dev/null @@ -1,41 +0,0 @@ -architecture multi2 of leds is - signal clk_4hz: std_logic; - signal clk_5sec : std_logic; -begin - process (clk) - -- 3_000_000 is 0x2dc6c0 - variable counter : unsigned (23 downto 0); - begin - if rising_edge(clk) then - if counter = 2_999_999 then - counter := x"000000"; - clk_4hz <= '1'; - else - counter := counter + 1; - clk_4hz <= '0'; - end if; - end if; - end process; - - process (clk) - variable counter5 : unsigned (4 downto 0); - begin - if rising_edge (clk) then - clk_5sec <= '0'; - if clk_4hz = '1' then - if counter5 = 19 then - clk_5sec <= '1'; - counter5 := "00000"; - else - counter5 := counter5 + 1; - end if; - end if; - end if; - end process; - - led1 <= clk_5sec; - led2 <= '0'; - led3 <= '0'; - led4 <= '0'; - led5 <= '0'; -end multi2; diff --git a/icestick/rotate1.vhdl b/icestick/rotate1.vhdl deleted file mode 100644 index 34c7afd..0000000 --- a/icestick/rotate1.vhdl +++ /dev/null @@ -1,51 +0,0 @@ -architecture rotate1 of leds is - signal clk_4hz: std_logic; -begin - process (clk) - -- 3_000_000 is 0x2dc6c0 - variable counter : unsigned (23 downto 0); - begin - if rising_edge(clk) then - if counter = 2_999_999 then - counter := x"000000"; - clk_4hz <= '1'; - else - counter := counter + 1; - clk_4hz <= '0'; - end if; - end if; - end process; - - process (clk) - variable count : unsigned (1 downto 0); - begin - if rising_edge(clk) and clk_4hz = '1' then - count := count + 1; - if count = 0 then - led1 <= '1'; - led2 <= '0'; - led3 <= '0'; - led4 <= '0'; - led5 <= '1'; - elsif count = 1 then - led1 <= '0'; - led2 <= '1'; - led3 <= '0'; - led4 <= '0'; - led5 <= '0'; - elsif count = 2 then - led1 <= '0'; - led2 <= '0'; - led3 <= '1'; - led4 <= '0'; - led5 <= '1'; - else - led1 <= '0'; - led2 <= '0'; - led3 <= '0'; - led4 <= '1'; - led5 <= '0'; - end if; - end if; - end process; -end rotate1; diff --git a/icestick/rotate2.vhdl b/icestick/rotate2.vhdl deleted file mode 100644 index e51ec6c..0000000 --- a/icestick/rotate2.vhdl +++ /dev/null @@ -1,35 +0,0 @@ -architecture rotate2 of leds is - signal clk_4hz: std_logic; -begin - process (clk) - -- 3_000_000 is 0x2dc6c0 - variable counter : unsigned (23 downto 0); - begin - if rising_edge(clk) then - if counter = 2_999_999 then - counter := x"000000"; - clk_4hz <= '1'; - else - counter := counter + 1; - clk_4hz <= '0'; - end if; - end if; - end process; - - process (clk) - variable count : unsigned (1 downto 0); - begin - if rising_edge(clk) and clk_4hz = '1' then - count := count + 1; - if count = 0 then - (led1, led2, led3, led4, led5) <= unsigned'("10001"); - elsif count = 1 then - (led1, led2, led3, led4, led5) <= unsigned'("01000"); - elsif count = 2 then - (led1, led2, led3, led4, led5) <= unsigned'("00101"); - else - (led1, led2, led3, led4, led5) <= unsigned'("00010"); - end if; - end if; - end process; -end rotate2; diff --git a/icestick/rotate3.vhdl b/icestick/rotate3.vhdl deleted file mode 100644 index 213512f..0000000 --- a/icestick/rotate3.vhdl +++ /dev/null @@ -1,38 +0,0 @@ -architecture rotate3 of leds is - signal clk_4hz: std_logic; -begin - process (clk) - -- 3_000_000 is 0x2dc6c0 - variable counter : unsigned (23 downto 0); - begin - if rising_edge(clk) then - if counter = 2_999_999 then - counter := x"000000"; - clk_4hz <= '1'; - else - counter := counter + 1; - clk_4hz <= '0'; - end if; - end if; - end process; - - process (clk) - variable count : unsigned (1 downto 0); - begin - if rising_edge(clk) and clk_4hz = '1' then - case count is - when "00" => - (led1, led2, led3, led4, led5) <= unsigned'("10001"); - when "01" => - (led1, led2, led3, led4, led5) <= unsigned'("01000"); - when "10" => - (led1, led2, led3, led4, led5) <= unsigned'("00101"); - when "11" => - (led1, led2, led3, led4, led5) <= unsigned'("00010"); - when others => - null; - end case; - count := count + 1; - end if; - end process; -end rotate3; diff --git a/icestick/rotate4.vhdl b/icestick/rotate4.vhdl deleted file mode 100644 index e89aaa5..0000000 --- a/icestick/rotate4.vhdl +++ /dev/null @@ -1,41 +0,0 @@ -architecture rotate4 of leds is - signal clk_4hz: std_logic; - signal leds : std_ulogic_vector (1 to 5); -begin - (led1, led2, led3, led4, led5) <= leds; - - process (clk) - -- 3_000_000 is 0x2dc6c0 - variable counter : unsigned (23 downto 0); - begin - if rising_edge(clk) then - if counter = 2_999_999 then - counter := x"000000"; - clk_4hz <= '1'; - else - counter := counter + 1; - clk_4hz <= '0'; - end if; - end if; - end process; - - process (clk) - variable count : unsigned (1 downto 0); - begin - if rising_edge(clk) and clk_4hz = '1' then - case count is - when "00" => - leds <= "10001"; - when "01" => - leds <= "01000"; - when "10" => - leds <= "00101"; - when "11" => - leds <= "00010"; - when others => - null; - end case; - count := count + 1; - end if; - end process; -end rotate4; diff --git a/icestick/spin1.vhdl b/icestick/spin1.vhdl deleted file mode 100644 index 79e305c..0000000 --- a/icestick/spin1.vhdl +++ /dev/null @@ -1,51 +0,0 @@ -architecture spin1 of leds is - signal nrst : std_logic := '0'; - signal clk_4hz: std_logic; - signal leds : std_ulogic_vector (1 to 5); -begin - (led1, led2, led3, led4, led5) <= leds; - - process (clk) - variable cnt : unsigned (1 downto 0) := "00"; - begin - if rising_edge (clk) then - if cnt = 3 then - nrst <= '1'; - else - cnt := cnt + 1; - end if; - end if; - end process; - - process (clk) - -- 3_000_000 is 0x2dc6c0 - variable counter : unsigned (23 downto 0); - begin - if rising_edge(clk) then - if nrst = '0' then - counter := x"000000"; - else - if counter = 2_999_999 then - counter := x"000000"; - clk_4hz <= '1'; - else - counter := counter + 1; - clk_4hz <= '0'; - end if; - end if; - end if; - end process; - - process (clk) - begin - if rising_edge(clk) then - if nrst = '0' then - -- Initialize - leds <= "11000"; - elsif clk_4hz = '1' then - -- Rotate - leds <= (leds (4), leds (1), leds (2), leds (3), '0'); - end if; - end if; - end process; -end spin1; diff --git a/icestick/spin2.vhdl b/icestick/spin2.vhdl deleted file mode 100644 index 0f23964..0000000 --- a/icestick/spin2.vhdl +++ /dev/null @@ -1,51 +0,0 @@ -architecture spin1 of leds is - signal nrst : std_logic := '0'; - signal clk_4hz: std_logic; - signal leds : std_ulogic_vector (1 to 5); -begin - (led1, led2, led3, led4, led5) <= leds; - - process (clk) - variable cnt : unsigned (1 downto 0) := "00"; - begin - if rising_edge (clk) then - if cnt = 3 then - nrst <= '1'; - else - cnt := cnt + 1; - end if; - end if; - end process; - - process (clk) - -- 3_000_000 is 0x2dc6c0 - variable counter : unsigned (23 downto 0); - begin - if rising_edge(clk) then - if nrst = '0' then - counter := x"000000"; - else - if counter = 2_999_999 then - counter := x"000000"; - clk_4hz <= '1'; - else - counter := counter + 1; - clk_4hz <= '0'; - end if; - end if; - end if; - end process; - - process (clk) - begin - if rising_edge(clk) then - if nrst = '0' then - -- Initialize - leds <= "11000"; - elsif clk_4hz = '1' then - -- Rotate - leds <= leds (4) & leds (1) & leds (2) & leds (3) & '0'; - end if; - end if; - end process; -end spin1; diff --git a/icestick/uart/README.md b/icestick/uart/README.md deleted file mode 100755 index b53def6..0000000 --- a/icestick/uart/README.md +++ /dev/null @@ -1,11 +0,0 @@ -# icestick-uart -Simple UART sender and receiver for the lattice icestick. It echoes every received word back. -Configuration: 115200 8N1 - -## Repository structure -- hdl: Contains the hardware design. -- syn: Contains the scripts and constraints for synthesis. - -## Usage -- `cd syn && ./synth.sh` -- configure and open putty or another serial terminal and type something \ No newline at end of file diff --git a/icestick/uart/hdl/uart_rx.vhd b/icestick/uart/hdl/uart_rx.vhd deleted file mode 100755 index 5f488cc..0000000 --- a/icestick/uart/hdl/uart_rx.vhd +++ /dev/null @@ -1,66 +0,0 @@ -library ieee; - use ieee.std_logic_1164.all; - -entity uart_rx is - generic ( - C_BITS : integer := 8; - C_CYCLES_PER_BIT : integer := 104 - ); - port ( - isl_clk : in std_logic; - isl_data_n : in std_logic; - oslv_data : out std_logic_vector(C_BITS-1 downto 0); - osl_valid : out std_logic - ); -end entity uart_rx; - -architecture rtl of uart_rx is - signal int_cycle_cnt : integer range 0 to C_CYCLES_PER_BIT-1 := 0; - signal int_bit_cnt : integer range 0 to C_BITS+1 := 0; - - signal slv_data : std_logic_vector(C_BITS-1 downto 0) := (others => '0'); - signal sl_valid : std_logic := '0'; - - type t_state is (IDLE, INIT, RECEIVE); - signal state : t_state; - -begin - process(isl_clk) - begin - if rising_edge(isl_clk) then - case state is - when IDLE => - sl_valid <= '0'; - if isl_data_n = '0' then - -- wait for the start bit - state <= INIT; - end if; - - when INIT => - int_cycle_cnt <= C_CYCLES_PER_BIT / 2; - int_bit_cnt <= 0; - state <= RECEIVE; - - when RECEIVE => - if int_bit_cnt < C_BITS+1 then - if int_cycle_cnt < C_CYCLES_PER_BIT-1 then - int_cycle_cnt <= int_cycle_cnt+1; - else - -- receive data bits - int_cycle_cnt <= 0; - int_bit_cnt <= int_bit_cnt+1; - slv_data <= not isl_data_n & slv_data(slv_data'LEFT downto 1); -- low active - end if; - elsif isl_data_n = '1' then - -- wait for the stop bit - sl_valid <= '1'; - state <= IDLE; - end if; - - end case; - end if; - end process; - - oslv_data <= slv_data; - osl_valid <= sl_valid; -end architecture rtl; diff --git a/icestick/uart/hdl/uart_top.vhd b/icestick/uart/hdl/uart_top.vhd deleted file mode 100755 index 889a3a0..0000000 --- a/icestick/uart/hdl/uart_top.vhd +++ /dev/null @@ -1,49 +0,0 @@ -library ieee; - use ieee.std_logic_1164.all; - -entity uart_top is - generic ( - C_BITS : integer := 8 - ); - port ( - isl_clk : in std_logic; - isl_data_n : in std_logic; - osl_data_n : out std_logic; - osl_ready : out std_logic - ); -end uart_top; - -architecture behavioral of uart_top is - constant C_QUARTZ_FREQ : integer := 12000000; -- Hz - constant C_BAUDRATE : integer := 115200; -- words / s - constant C_CYCLES_PER_BIT : integer := C_QUARTZ_FREQ / C_BAUDRATE; - - signal sl_valid_out_tx : std_logic := '0'; - signal slv_data_out_tx : std_logic_vector(C_BITS-1 downto 0) := (others => '0'); - -begin - i_uart_rx: entity work.uart_rx - generic map ( - C_BITS => C_BITS, - C_CYCLES_PER_BIT => C_CYCLES_PER_BIT - ) - port map ( - isl_clk => isl_clk, - isl_data_n => isl_data_n, - oslv_data => slv_data_out_tx, - osl_valid => sl_valid_out_tx - ); - - i_uart_tx: entity work.uart_tx - generic map ( - C_BITS => C_BITS, - C_CYCLES_PER_BIT => C_CYCLES_PER_BIT - ) - port map ( - isl_clk => isl_clk, - isl_valid => sl_valid_out_tx, - islv_data => slv_data_out_tx, - osl_data_n => osl_data_n, - osl_ready => osl_ready - ); -end behavioral; \ No newline at end of file diff --git a/icestick/uart/hdl/uart_tx.vhd b/icestick/uart/hdl/uart_tx.vhd deleted file mode 100755 index b6c5800..0000000 --- a/icestick/uart/hdl/uart_tx.vhd +++ /dev/null @@ -1,62 +0,0 @@ -library ieee; - use ieee.std_logic_1164.all; - -entity uart_tx is - generic ( - -- TODO: range in submodules is not yet supported by synthesis - -- it would be useful to limit between 5 to 8 - C_BITS : integer := 8; - C_CYCLES_PER_BIT : integer := 104 - ); - port ( - isl_clk : in std_logic; - isl_valid : in std_logic; - islv_data : in std_logic_vector(C_BITS-1 downto 0); - osl_ready : out std_logic; - osl_data_n : out std_logic - ); -end entity uart_tx; - -architecture rtl of uart_tx is - signal int_cycle_cnt : integer range 0 to C_CYCLES_PER_BIT-1 := 0; - signal int_bit_cnt : integer range 0 to C_BITS+2 := 0; - - signal slv_data : std_logic_vector(C_BITS downto 0) := (others => '0'); - - type t_state is (IDLE, INIT, SEND); - signal state : t_state; - -begin - process(isl_clk) - begin - if rising_edge(isl_clk) then - case state is - when IDLE => - if isl_valid = '1' then - state <= INIT; - end if; - - when INIT => - int_cycle_cnt <= 0; - int_bit_cnt <= 0; - slv_data <= islv_data & '1'; - state <= SEND; - - when SEND => - if int_cycle_cnt < C_CYCLES_PER_BIT-1 then - int_cycle_cnt <= int_cycle_cnt+1; - elsif int_bit_cnt < C_BITS+1 then - int_cycle_cnt <= 0; - int_bit_cnt <= int_bit_cnt+1; - slv_data <= '0' & slv_data(slv_data'LEFT downto 1); - else - state <= IDLE; - end if; - - end case; - end if; - end process; - - osl_ready <= '1' when state = IDLE else '0'; - osl_data_n <= not slv_data(0); -- low active -end architecture rtl; \ No newline at end of file diff --git a/icestick/uart/syn/constraints/uart.pcf b/icestick/uart/syn/constraints/uart.pcf deleted file mode 100755 index e3e5016..0000000 --- a/icestick/uart/syn/constraints/uart.pcf +++ /dev/null @@ -1,6 +0,0 @@ -# FTDI Port B UART -set_io osl_data_n 8 # UART TX -set_io isl_data_n 9 # UART RX - -# 12 MHz clock -set_io isl_clk 21 diff --git a/icestick/uart/syn/synth.sh b/icestick/uart/syn/synth.sh deleted file mode 100755 index 884f1b6..0000000 --- a/icestick/uart/syn/synth.sh +++ /dev/null @@ -1,15 +0,0 @@ -set -e - -ROOT="$(pwd)/.." - -rm -rf build -mkdir -p build -cd build - -ghdl -a "$ROOT"/hdl/uart_rx.vhd -ghdl -a "$ROOT"/hdl/uart_tx.vhd -ghdl -a "$ROOT"/hdl/uart_top.vhd -yosys -m ghdl -p 'ghdl uart_top; synth_ice40 -json uart_top.json' -nextpnr-ice40 --hx1k --json uart_top.json --pcf ../constraints/uart.pcf --asc uart_top.asc --pcf-allow-unconstrained -icepack uart_top.asc uart_top.bin -iceprog uart_top.bin diff --git a/icezum/blink/Makefile b/icezum/blink/Makefile deleted file mode 100644 index e7c2964..0000000 --- a/icezum/blink/Makefile +++ /dev/null @@ -1,32 +0,0 @@ -PROJ = blink -PIN_DEF = blink.pcf -DEVICE = hx1k - -all: $(PROJ).rpt $(PROJ).bin - -%.blif: %.vhdl - ghdl -a $(PROJ).vhdl - yosys -m ../../ghdl.so -p 'ghdl $(PROJ); synth_ice40 -blif $@' - - -%.asc: $(PIN_DEF) %.blif - arachne-pnr -d $(subst hx,,$(subst lp,,$(DEVICE))) -o $@ -p $^ - -%.bin: %.asc - icepack $< $@ - -%.rpt: %.asc - icetime -d $(DEVICE) -mtr $@ $< - -prog: $(PROJ).bin - iceprog $< - -sudo-prog: $(PROJ).bin - @echo 'Executing prog as root!!!' - sudo iceprog $< - -clean: - rm -f $(PROJ).blif $(PROJ).asc $(PROJ).rpt $(PROJ).bin work-obj93.cf - -.SECONDARY: -.PHONY: all prog clean diff --git a/icezum/blink/README.md b/icezum/blink/README.md deleted file mode 100644 index e61330b..0000000 --- a/icezum/blink/README.md +++ /dev/null @@ -1,16 +0,0 @@ -A hello world example for the **Icezum Alhambra board** -It just blinks all the leds - -Execute - -```sh -$ make -``` - -for synthesizing the example and - -```sh -$ make prog -``` - -for programing the board diff --git a/icezum/blink/blink.pcf b/icezum/blink/blink.pcf deleted file mode 100644 index 2f686f6..0000000 --- a/icezum/blink/blink.pcf +++ /dev/null @@ -1,11 +0,0 @@ -set_io led0 95 -set_io led1 96 -set_io led2 97 -set_io led3 98 -set_io led4 99 -set_io led5 101 -set_io led6 102 -set_io led7 104 -set_io clk 21 - - diff --git a/icezum/blink/blink.vhdl b/icezum/blink/blink.vhdl deleted file mode 100644 index 9279622..0000000 --- a/icezum/blink/blink.vhdl +++ /dev/null @@ -1,35 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity blink is - port (clk : in std_logic; - led0, led1, led2, led3, led4, led5, led6, led7 : out std_logic); -end blink; - -architecture synth of blink is - signal clk_4hz: std_logic; -begin - process (clk) - -- 3_000_000 is 0x2dc6c0 - variable counter : unsigned (23 downto 0); - begin - if rising_edge(clk) then - if counter = 2_999_999 then - counter := x"000000"; - clk_4hz <= not clk_4hz; - else - counter := counter + 1; - end if; - end if; - end process; - - led0 <= clk_4hz; - led1 <= clk_4hz; - led2 <= clk_4hz; - led3 <= clk_4hz; - led4 <= clk_4hz; - led5 <= clk_4hz; - led6 <= clk_4hz; - led7 <= clk_4hz; -end synth; diff --git a/icezum/counter-8bits/Makefile b/icezum/counter-8bits/Makefile deleted file mode 100644 index c618b42..0000000 --- a/icezum/counter-8bits/Makefile +++ /dev/null @@ -1,32 +0,0 @@ -PROJ = counter8 -PIN_DEF = counter8.pcf -DEVICE = hx1k - -all: $(PROJ).rpt $(PROJ).bin - -%.blif: %.vhdl - ghdl -a $(PROJ).vhdl - yosys -m ../../ghdl.so -p 'ghdl $(PROJ); synth_ice40 -blif $@' - - -%.asc: $(PIN_DEF) %.blif - arachne-pnr -d $(subst hx,,$(subst lp,,$(DEVICE))) -o $@ -p $^ - -%.bin: %.asc - icepack $< $@ - -%.rpt: %.asc - icetime -d $(DEVICE) -mtr $@ $< - -prog: $(PROJ).bin - iceprog $< - -sudo-prog: $(PROJ).bin - @echo 'Executing prog as root!!!' - sudo iceprog $< - -clean: - rm -f $(PROJ).blif $(PROJ).asc $(PROJ).rpt $(PROJ).bin work-obj93.cf - -.SECONDARY: -.PHONY: all prog clean diff --git a/icezum/counter-8bits/README.md b/icezum/counter-8bits/README.md deleted file mode 100644 index 4549251..0000000 --- a/icezum/counter-8bits/README.md +++ /dev/null @@ -1,16 +0,0 @@ -An example for the **Icezum Alhambra board** -A binary counter shown in the 8 test leds - -Execute - -```sh -$ make -``` - -for synthesizing the example and - -```sh -$ make prog -``` - -for programing the board diff --git a/icezum/counter-8bits/counter8.pcf b/icezum/counter-8bits/counter8.pcf deleted file mode 100644 index 9d25064..0000000 --- a/icezum/counter-8bits/counter8.pcf +++ /dev/null @@ -1,9 +0,0 @@ -set_io --warn-no-port led0 95 # output -set_io --warn-no-port led1 96 # output -set_io --warn-no-port led2 97 # output -set_io --warn-no-port led3 98 # output -set_io --warn-no-port led4 99 # output -set_io --warn-no-port led5 101 # output -set_io --warn-no-port led6 102 # output -set_io --warn-no-port led7 104 # output -set_io --warn-no-port clk 21 diff --git a/icezum/counter-8bits/counter8.vhdl b/icezum/counter-8bits/counter8.vhdl deleted file mode 100644 index 4c5017e..0000000 --- a/icezum/counter-8bits/counter8.vhdl +++ /dev/null @@ -1,38 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity counter8 is - port (clk : in std_logic; - led0, led1, led2, led3, led4, led5, led6, led7 : out std_logic); -end counter8; - -architecture synth of counter8 is - - signal clk_6hz : std_logic; - -begin - - -- Presscaler - prescaler: process(clk) - variable timer : unsigned (20 downto 0):=(others=>'0'); - begin - if rising_edge(clk) then - timer := timer + 1; - clk_6hz <= timer(20); - end if; - end process; - - -- 8 bits counter - process (clk_6hz) - variable temp : unsigned (7 downto 0); - begin - if rising_edge(clk_6hz) then - temp:= temp + 1; - - -- Show the counter on the icezum Alhambra leds - (led7, led6, led5, led4, led3, led2, led1, led0) <= temp; - end if; - end process; - -end synth; diff --git a/icezum/led_on/Makefile b/icezum/led_on/Makefile deleted file mode 100644 index b85feb3..0000000 --- a/icezum/led_on/Makefile +++ /dev/null @@ -1,31 +0,0 @@ -PROJ = led_on -PIN_DEF = led_on.pcf -DEVICE = hx1k - -all: $(PROJ).rpt $(PROJ).bin - -%.blif: %.vhdl - ghdl -a $(PROJ).vhdl - yosys -m ../../ghdl.so -p 'ghdl $(PROJ); synth_ice40 -blif $@' - -%.asc: $(PIN_DEF) %.blif - arachne-pnr -d $(subst hx,,$(subst lp,,$(DEVICE))) -o $@ -p $^ - -%.bin: %.asc - icepack $< $@ - -%.rpt: %.asc - icetime -d $(DEVICE) -mtr $@ $< - -prog: $(PROJ).bin - iceprog $< - -sudo-prog: $(PROJ).bin - @echo 'Executing prog as root!!!' - sudo iceprog $< - -clean: - rm -f $(PROJ).blif $(PROJ).asc $(PROJ).rpt $(PROJ).bin work-obj93.cf - -.SECONDARY: -.PHONY: all prog clean diff --git a/icezum/led_on/README.md b/icezum/led_on/README.md deleted file mode 100644 index 9073c11..0000000 --- a/icezum/led_on/README.md +++ /dev/null @@ -1,16 +0,0 @@ -A hello world example for the **Icezum Alhambra board** -It just turn on the led0 and turn off the others - -Execute - -```sh -$ make -``` - -for synthesizing the example and - -```sh -$ make prog -``` - -for programing the board diff --git a/icezum/led_on/led_on.pcf b/icezum/led_on/led_on.pcf deleted file mode 100644 index 522e201..0000000 --- a/icezum/led_on/led_on.pcf +++ /dev/null @@ -1,9 +0,0 @@ -set_io led0 95 -set_io led1 96 -set_io led2 97 -set_io led3 98 -set_io led4 99 -set_io led5 101 -set_io led6 102 -set_io led7 104 - diff --git a/icezum/led_on/led_on.vhdl b/icezum/led_on/led_on.vhdl deleted file mode 100644 index 49a88ad..0000000 --- a/icezum/led_on/led_on.vhdl +++ /dev/null @@ -1,20 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity led_on is - port (led0, led1, led2, led3, led4, led5, led6, led7 : out std_logic); -end led_on; - -architecture test of led_on is -begin - - -- Turn on the Led0 - led0 <= '1'; - - -- Turn off the other leds - (led1, led2, led3, led4, led5, led6, led7) <= std_logic_vector'("0000000"); - -end test; - - diff --git a/icezum/pushbutton/Makefile b/icezum/pushbutton/Makefile deleted file mode 100644 index d483e9a..0000000 --- a/icezum/pushbutton/Makefile +++ /dev/null @@ -1,32 +0,0 @@ -PROJ = pushbutton -PIN_DEF = $(PROJ).pcf -DEVICE = hx1k - -all: $(PROJ).rpt $(PROJ).bin - -%.blif: %.vhdl - ghdl -a $(PROJ).vhdl - yosys -m ../../ghdl.so -p 'ghdl $(PROJ); synth_ice40 -blif $@' - - -%.asc: $(PIN_DEF) %.blif - arachne-pnr -d $(subst hx,,$(subst lp,,$(DEVICE))) -o $@ -p $^ - -%.bin: %.asc - icepack $< $@ - -%.rpt: %.asc - icetime -d $(DEVICE) -mtr $@ $< - -prog: $(PROJ).bin - iceprog $< - -sudo-prog: $(PROJ).bin - @echo 'Executing prog as root!!!' - sudo iceprog $< - -clean: - rm -f $(PROJ).blif $(PROJ).asc $(PROJ).rpt $(PROJ).bin work-obj93.cf - -.SECONDARY: -.PHONY: all prog clean diff --git a/icezum/pushbutton/README.md b/icezum/pushbutton/README.md deleted file mode 100644 index 6aba730..0000000 --- a/icezum/pushbutton/README.md +++ /dev/null @@ -1,17 +0,0 @@ -A hello world example for the **Icezum Alhambra board** -Testing the sw1 pushbutton. The state of the button and its negated are wired -to led0 and led7 respectively - -Execute - -```sh -$ make -``` - -for synthesizing the example and - -```sh -$ make prog -``` - -for programing the board diff --git a/icezum/pushbutton/pushbutton.pcf b/icezum/pushbutton/pushbutton.pcf deleted file mode 100644 index 807307f..0000000 --- a/icezum/pushbutton/pushbutton.pcf +++ /dev/null @@ -1,7 +0,0 @@ -set_io sw1 10 -set_io led0 95 -set_io led7 104 - - - - diff --git a/icezum/pushbutton/pushbutton.vhdl b/icezum/pushbutton/pushbutton.vhdl deleted file mode 100644 index 8ad516e..0000000 --- a/icezum/pushbutton/pushbutton.vhdl +++ /dev/null @@ -1,14 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity pushbutton is - port (sw1 : in std_logic; - led0, led7 : out std_logic); -end pushbutton; - -architecture synth of pushbutton is -begin - led0 <= sw1; - led7 <= not sw1; -end synth; diff --git a/icezum/pushbutton_and/Makefile b/icezum/pushbutton_and/Makefile deleted file mode 100644 index 2042685..0000000 --- a/icezum/pushbutton_and/Makefile +++ /dev/null @@ -1,32 +0,0 @@ -PROJ = pushbutton_and -PIN_DEF = $(PROJ).pcf -DEVICE = hx1k - -all: $(PROJ).rpt $(PROJ).bin - -%.blif: %.vhdl - ghdl -a $(PROJ).vhdl - yosys -m ../../ghdl.so -p 'ghdl $(PROJ); synth_ice40 -blif $@' - - -%.asc: $(PIN_DEF) %.blif - arachne-pnr -d $(subst hx,,$(subst lp,,$(DEVICE))) -o $@ -p $^ - -%.bin: %.asc - icepack $< $@ - -%.rpt: %.asc - icetime -d $(DEVICE) -mtr $@ $< - -prog: $(PROJ).bin - iceprog $< - -sudo-prog: $(PROJ).bin - @echo 'Executing prog as root!!!' - sudo iceprog $< - -clean: - rm -f $(PROJ).blif $(PROJ).asc $(PROJ).rpt $(PROJ).bin work-obj93.cf - -.SECONDARY: -.PHONY: all prog clean diff --git a/icezum/pushbutton_and/README.md b/icezum/pushbutton_and/README.md deleted file mode 100644 index b4734c5..0000000 --- a/icezum/pushbutton_and/README.md +++ /dev/null @@ -1,17 +0,0 @@ -A hello world example for the **Icezum Alhambra board** -Testing the sw1 and sw1 pushbutton with an AND gate. The state of the AND -and its negated are wired to the led0 and led7 respectively - -Execute - -```sh -$ make -``` - -for synthesizing the example and - -```sh -$ make prog -``` - -for programing the board diff --git a/icezum/pushbutton_and/pushbutton_and.pcf b/icezum/pushbutton_and/pushbutton_and.pcf deleted file mode 100644 index 31883fc..0000000 --- a/icezum/pushbutton_and/pushbutton_and.pcf +++ /dev/null @@ -1,4 +0,0 @@ -set_io sw1 10 -set_io sw2 11 -set_io led0 95 -set_io led7 104 diff --git a/icezum/pushbutton_and/pushbutton_and.vhdl b/icezum/pushbutton_and/pushbutton_and.vhdl deleted file mode 100644 index 0a9831d..0000000 --- a/icezum/pushbutton_and/pushbutton_and.vhdl +++ /dev/null @@ -1,18 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity pushbutton_and is - port (sw1, sw2 : in std_logic; - led0, led7 : out std_logic); -end pushbutton_and; - -architecture synth of pushbutton_and is - -signal a : std_logic; - -begin - a <= sw1 and sw2; - led0 <= a; - led7 <= not a; -end synth; diff --git a/testsuite/examples/test-ice40hx8k/testsuite.sh b/testsuite/examples/test-ice40hx8k/testsuite.sh index 3bf7f9c..52e061a 100755 --- a/testsuite/examples/test-ice40hx8k/testsuite.sh +++ b/testsuite/examples/test-ice40hx8k/testsuite.sh @@ -3,7 +3,7 @@ topdir=../.. . $topdir/testenv.sh -src=../../../ice40hx8k +src=../../../examples/ice40hx8k synth_ice40 $src/leds.vhdl $src/spin1.vhdl -e leds synth_ice40 $src/leds.vhdl $src/spin2.vhdl -e leds diff --git a/testsuite/examples/test-icestick/testsuite.sh b/testsuite/examples/test-icestick/testsuite.sh index 025e8c2..7184fcc 100755 --- a/testsuite/examples/test-icestick/testsuite.sh +++ b/testsuite/examples/test-icestick/testsuite.sh @@ -3,7 +3,7 @@ topdir=../.. . $topdir/testenv.sh -src=../../../icestick +src=../../../examples/icestick # spin2 diff --git a/testsuite/examples/test-icezum/testsuite.sh b/testsuite/examples/test-icezum/testsuite.sh index 4906689..5386f10 100755 --- a/testsuite/examples/test-icezum/testsuite.sh +++ b/testsuite/examples/test-icezum/testsuite.sh @@ -3,11 +3,11 @@ topdir=../.. . $topdir/testenv.sh -src=../../../icezum +src=../../../examples/icezum -synth_ice40 $src/led_on/led_on.vhdl -e led_on -synth_ice40 $src/blink/blink.vhdl -e blink -synth_ice40 $src/pushbutton/pushbutton.vhdl -e pushbutton -synth_ice40 $src/pushbutton_and/pushbutton_and.vhdl -e pushbutton_and +synth_ice40 $src/led_on.vhdl -e led_on +synth_ice40 $src/blink.vhdl -e blink +synth_ice40 $src/pushbutton.vhdl -e pushbutton +synth_ice40 $src/counter.vhdl -e counter clean diff --git a/testsuite/testenv.sh b/testsuite/testenv.sh index 5dd7811..0046d49 100644 --- a/testsuite/testenv.sh +++ b/testsuite/testenv.sh @@ -47,18 +47,18 @@ analyze () synth_import () { - travis_start "synth" "Synthesize $*" + gstart "Synthesize $*" run_yosys -q -p "ghdl $*" status=$? - travis_finish "synth" + gend return $status } synth_ice40 () { - travis_start "synth" "Synthesize $*" + gstart "synth" "Synthesize $*" run_yosys -q -p "ghdl $*; synth_ice40 -blif out.blif" - travis_finish "synth" + gend } synth () @@ -68,9 +68,9 @@ synth () formal () { - travis_start "formal" "Verify $@" + gstart "Verify $@" run_symbiyosys -f -d work $@.sby - travis_finish "formal" + gend } clean () diff --git a/travis.sh b/travis.sh deleted file mode 100755 index 2ce0d20..0000000 --- a/travis.sh +++ /dev/null @@ -1,94 +0,0 @@ -#!/bin/sh - -set -e - -cd "$(dirname $0)" -. ./utils.sh - -prefix='/opt/ghdl' - -#-- -travis_start "ghdl" "[Build] ghdl/synth:latest" "$ANSI_MAGENTA" - -case "$TRAVIS_COMMIT_MESSAGE" in - "*[stable]*") - echo "IS_STABLE" - GHDL_URL="https://github.com/ghdl/ghdl/archive/9d61a62f96dc4897dadbf88f5f4ee199d20e0f8f.tar.gz" - ;; - *) - echo "IS_MASTER" - GHDL_URL="https://codeload.github.com/ghdl/ghdl/tar.gz/master" - ;; -esac -echo "GHDL_URL: $GHDL_URL" - -docker build -t ghdl/synth:latest - <<-EOF -FROM ghdl/build:buster-mcode AS build - -RUN apt-get update -qq \ - && DEBIAN_FRONTEND=noninteractive apt-get -y install --no-install-recommends \ - ca-certificates \ - curl \ - && apt-get autoclean && apt-get clean && apt-get -y autoremove \ - && update-ca-certificates \ - && rm -rf /var/lib/apt/lists - -RUN mkdir -p ghdl && cd ghdl \ - && curl -fsSL "$GHDL_URL" | tar xzf - --strip-components=1 \ - && ./configure --prefix="$prefix" --enable-libghdl --enable-synth \ - && make all \ - && make install - -FROM ghdl/run:buster-mcode -COPY --from=build $prefix $prefix -ENV PATH $prefix/bin:\$PATH -EOF - -travis_finish "ghdl" -#-- -travis_start "ghdlsynth" "[Build] ghdl/synth:beta" "$ANSI_MAGENTA" - -docker build -t ghdl/synth:beta . -f- <<-EOF -FROM ghdl/synth:yosys-gnat AS build -COPY --from=ghdl/synth:latest $prefix $prefix -COPY . /ghdlsynth - -RUN cd /ghdlsynth \ - && export PATH=\$PATH:$prefix/bin \ - && make \ - && cp ghdl.so $prefix/lib/ghdl_yosys.so - -FROM ghdl/synth:yosys-gnat -COPY --from=build $prefix $prefix -ENV PATH $prefix/bin:\$PATH -RUN yosys-config --exec mkdir -p --datdir/plugins \ - && yosys-config --exec ln -s $prefix/lib/ghdl_yosys.so --datdir/plugins/ghdl.so -EOF - -travis_finish "ghdlsynth" -#--- -travis_start "formal" "[Build] ghdl/synth:formal" "$ANSI_MAGENTA" - -docker build -t ghdl/synth:formal . -f- <<-EOF -FROM ghdl/synth:beta - -COPY --from=ghdl/cache:formal ./z3 /opt/z3 -COPY --from=ghdl/cache:formal ./symbiyosys /usr/local - -RUN apt-get update -qq \ - && DEBIAN_FRONTEND=noninteractive apt-get -y install --no-install-recommends \ - python3 \ - && apt-get autoclean && apt-get clean && apt-get -y autoremove \ - && rm -rf /var/lib/apt/lists/* - -ENV PATH=/opt/z3/bin:\$PATH -EOF - -travis_finish "formal" -#--- -printf "${ANSI_MAGENTA}[Test] testsuite ${ANSI_NOCOLOR}\n" - -docker run --rm -t -e TRAVIS=$TRAVIS -v /$(pwd)://src -w //src -e YOSYS='yosys -m ghdl' ghdl/synth:formal bash -c "$(cat < $2$ANSI_NOCOLOR\n" + printf "${COL}${1}$ANSI_NOCOLOR\n" } -travis_start () { +gstart () { print_start "$@" } -travis_finish () { +gend () { : } -[ -n "$TRAVIS" ] && { - # This is a trimmed down copy of - # https://github.com/travis-ci/travis-build/blob/master/lib/travis/build/templates/header.sh - travis_time_start() { - # `date +%N` returns the date in nanoseconds. It is used as a replacement for $RANDOM, which is only available in bash. - travis_timer_id=`date +%N` - travis_start_time=$(travis_nanoseconds) - echo "travis_time:start:$travis_timer_id" - } - travis_time_finish() { - travis_end_time=$(travis_nanoseconds) - local duration=$(($travis_end_time-$travis_start_time)) - echo "travis_time:end:$travis_timer_id:start=$travis_start_time,finish=$travis_end_time,duration=$duration" - } +if [ -n "$GITHUB_EVENT_PATH" ]; then + export CI=true +fi - if [ "$TRAVIS_OS_NAME" = "osx" ]; then - travis_nanoseconds() { - date -u '+%s000000000' - } - else - travis_nanoseconds() { - date -u '+%s%N' - } - fi - - travis_start () { - echo "travis_fold:start:$1" - travis_time_start +[ -n "$CI" ] && { + gstart () { + printf '::group::' print_start "$@" } - travis_finish () { - travis_time_finish - echo "travis_fold:end:$1" + gend () { + echo '::endgroup::' } - -} || echo "INFO: not in Travis CI" +} || echo "INFO: not in CI" -- cgit v1.2.3