From 7aed75ba30157e52de737b2e082d2e1b6f82435d Mon Sep 17 00:00:00 2001
From: "Alastair M. Robinson" <robinsonb5@gmail.com>
Date: Wed, 31 Aug 2022 20:42:24 +0100
Subject: Fix to block RAM handling as per
 https://github.com/YosysHQ/yosys/issues/3364#issuecomment-1148066807 (#171)

---
 src/ghdl.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/ghdl.cc b/src/ghdl.cc
index fb6cb8e..edc60cf 100644
--- a/src/ghdl.cc
+++ b/src/ghdl.cc
@@ -563,7 +563,7 @@ static void import_memory(RTLIL::Module *module, std::vector<RTLIL::Wire *> &net
                         vec.resize(nbr_wr);
 			// Emitted write ports (ie j <= widx) don't have priority.
                         for (int j = 0; j < nbr_wr; j++)
-                                vec[j] = j <= widx ? RTLIL::State::S0 : RTLIL::State::S1;
+                                vec[j] = j < widx ? RTLIL::State::S1 : RTLIL::State::S0;
                         p->parameters[ID::PRIORITY_MASK] = Const(vec);
                         break;
 		default:
-- 
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