aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
-rw-r--r--testsuite/examples/blackbox/blackbox3.vhdl4
-rwxr-xr-xtestsuite/examples/blackbox/testsuite.sh1
2 files changed, 3 insertions, 2 deletions
diff --git a/testsuite/examples/blackbox/blackbox3.vhdl b/testsuite/examples/blackbox/blackbox3.vhdl
index a506df0..864247d 100644
--- a/testsuite/examples/blackbox/blackbox3.vhdl
+++ b/testsuite/examples/blackbox/blackbox3.vhdl
@@ -9,10 +9,10 @@ end;
architecture behav of blackbox3 is
component \lib__cell__box2.3\ is
port (a, b : std_logic;
- \OUT\ : out std_logic);
+ \O\ : out std_logic);
end component;
begin
inst: \lib__cell__box2.3\
- port map (a => a, b => b, \OUT\ => o);
+ port map (a => a, b => b, \O\ => o);
end behav;
diff --git a/testsuite/examples/blackbox/testsuite.sh b/testsuite/examples/blackbox/testsuite.sh
index 35322f2..a0db873 100755
--- a/testsuite/examples/blackbox/testsuite.sh
+++ b/testsuite/examples/blackbox/testsuite.sh
@@ -11,6 +11,7 @@ fgrep -q ".OUT(" blackbox2.v
run_yosys -q -p "ghdl blackbox3.vhdl -e; write_verilog blackbox3.v"
fgrep -q "\lib__cell__box2.3 " blackbox3.v
+fgrep -q ".O(" blackbox3.v
clean
echo OK