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| author | Keith Rothman <537074+litghost@users.noreply.github.com> | 2021-03-18 13:08:20 -0700 |
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| committer | Keith Rothman <537074+litghost@users.noreply.github.com> | 2021-03-18 13:08:20 -0700 |
| commit | d0a0a0bf38434a257dd8493791fcc266fb58d53d (patch) | |
| tree | 52d51039b63e4203028ec16a059480c2ce799e82 | |
| parent | 1884e4b9786ae660d02a8c3c1151be682058bf36 (diff) | |
| download | fpga-interchange-schema-d0a0a0bf38434a257dd8493791fcc266fb58d53d.tar.gz fpga-interchange-schema-d0a0a0bf38434a257dd8493791fcc266fb58d53d.tar.bz2 fpga-interchange-schema-d0a0a0bf38434a257dd8493791fcc266fb58d53d.zip | |
Clarify some lines based on review comments.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| -rw-r--r-- | docs/pseudo_cells.md | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/docs/pseudo_cells.md b/docs/pseudo_cells.md index 064c656..a55fc44 100644 --- a/docs/pseudo_cells.md +++ b/docs/pseudo_cells.md @@ -1,7 +1,7 @@ ## Pseudo Cells Pseudo PIPs and site pseudo PIPs are edges in the device graph that route -through other sites and/or BELs. Pseudo cells are the expression of the what +through other sites and/or BELs. Pseudo cells are the expression of what routing resources are "blocked" by the use of a pseudo PIP. The device database currently expresses pseudo PIPs as using BEL pins within @@ -11,11 +11,12 @@ the site wire. ### Example -In the case of a `CLBLL`'s `CLBLL_LL_A1` to `CLBLL_LL_A` pseudo PIP, this PIP -connects a signal from an input site port to an output site port. Each site -wire that is consumed has **both** a output BEL pin (from the site wire -source) and a input BEL pin (connected to either a logic BEL, e.g. `A6LUT` or -routing BEL, e.g. `AUSED` or output site port BEL, e.g. `A`). +In the case of a Xilinx 7-series `CLBLL`'s `CLBLL_LL_A1` to `CLBLL_LL_A` +pseudo PIP, this PIP connects a signal from an input site port to an output +site port. Each site wire that is consumed has **both** a output BEL pin +(from the site wire source) and a input BEL pin (connected to either a logic +BEL, e.g. `A6LUT` or routing BEL, e.g. `AUSED` or output site port BEL, e.g. +`A`). In the case of a `CLBLL`'s `CLBLL_LL_A` to `CLBLL_LL_AMUX` pseudo PIP, this PIP connects a signal from an output site port to an output site port. In |