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| author | gatecat <gatecat@ds0.me> | 2021-04-23 14:39:15 +0100 |
|---|---|---|
| committer | gatecat <gatecat@ds0.me> | 2021-04-23 14:39:15 +0100 |
| commit | 314842347f393a3c9985eeea8c6d3c05c36c8cd4 (patch) | |
| tree | 5609b65141c955b4797fb01ba5b172b5390eb4e0 | |
| parent | 5208d794d318e9151b93120d7e5ba75d8aef45e7 (diff) | |
| download | fpga-interchange-schema-314842347f393a3c9985eeea8c6d3c05c36c8cd4.tar.gz fpga-interchange-schema-314842347f393a3c9985eeea8c6d3c05c36c8cd4.tar.bz2 fpga-interchange-schema-314842347f393a3c9985eeea8c6d3c05c36c8cd4.zip | |
Add a documented requirement for primLibs library names
Signed-off-by: gatecat <gatecat@ds0.me>
| -rw-r--r-- | interchange/DeviceResources.capnp | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/interchange/DeviceResources.capnp b/interchange/DeviceResources.capnp index 5a52bec..7d3a95c 100644 --- a/interchange/DeviceResources.capnp +++ b/interchange/DeviceResources.capnp @@ -80,7 +80,10 @@ struct Device { tileList @4 : List(Tile); wires @5 : List(Wire); nodes @6 : List(Node); - primLibs @7 : Dir.Netlist; # Netlist libraries of Unisim primitives and macros + # Netlist libraries of Unisim primitives and macros + # The library containing primitives should be called "primitives", and + # the library containing macros called "macros". + primLibs @7 : Dir.Netlist; exceptionMap @8 : List(PrimToMacroExpansion); # Prims to macros expand w/same name, except these cellBelMap @9 : List(CellBelMapping); cellInversions @10 : List(CellInversion); |