From f43c654ad0dcb11b2738bbfac9246d09bb1949e5 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sat, 14 Oct 2017 17:47:28 +0200 Subject: spi25: Integrate 4BA support Allow 4-byte addresses for instructions usually used with 3-byte addresses. Decide in which way the 4th byte will be communicated based on the state of the chip (i.e. have we enabled 4BA mode) and a new feature bit for an extended address register. If we are not in 4BA mode and no extended address register is available or the write to it fails, bail out. We cache the state of 4BA mode and the extended address register in the flashctx. Change-Id: I644600beaab9a571b97b67f7516abe571d3460c1 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/22384 Reviewed-by: Stefan Reinauer Tested-by: build bot (Jenkins) --- spi4ba.h | 1 + 1 file changed, 1 insertion(+) (limited to 'spi4ba.h') diff --git a/spi4ba.h b/spi4ba.h index 8a017924..a0316bc7 100644 --- a/spi4ba.h +++ b/spi4ba.h @@ -114,5 +114,6 @@ int spi_block_erase_21_4ba_direct(struct flashctx *flash, unsigned int addr, uns int spi_block_erase_5c_4ba_direct(struct flashctx *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_dc_4ba_direct(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_write_extended_address_register(struct flashctx *flash, uint8_t regdata); #endif /* __SPI_4BA_H__ */ -- cgit v1.2.3