From ed098d62d66d91cf7330a37f9b83e303eb7f56d8 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Fri, 21 Apr 2017 23:47:08 +0200 Subject: spi: Move ICH BBAR quirk out of the way Get rid of the layering violations around ICH's BBAR. Move all the weird address handling into (surprise, surprise) `ichspi.c`. Might fix writes for the `BBAR != 0` case by accident. Background: Some ICHs have a BBAR (BIOS Base Address Configuration Register) that, if set, limits the valid address range to [BBAR, 2^24). Current code lifted addresses for REMS, RES and READ operations by BBAR, now we do it for all addresses in ichspi. Special care has to be taken if the BBAR is not aligned by the flash chip's size. In this case, the lower part of the chip (from BBAR aligned down, up to BBAR) is inacces- sible (this seems to be the original intend behind BBAR) and has to be left out in the address offset calculation. Change-Id: Icbac513c5339e8aff624870252133284ef85ab73 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/22396 Reviewed-by: David Hendricks Tested-by: build bot (Jenkins) --- programmer.h | 1 - 1 file changed, 1 deletion(-) (limited to 'programmer.h') diff --git a/programmer.h b/programmer.h index a98b7135..b390a533 100644 --- a/programmer.h +++ b/programmer.h @@ -661,7 +661,6 @@ enum ich_chipset { /* ichspi.c */ #if CONFIG_INTERNAL == 1 -extern uint32_t ichspi_bbar; int ich_init_spi(void *spibar, enum ich_chipset ich_generation); int via_init_spi(uint32_t mmio_base); -- cgit v1.2.3