From 125a328b4d8445f41c9fdde9e51c1b2bb40ad72e Mon Sep 17 00:00:00 2001 From: Sergii Dmytruk Date: Sun, 24 Jul 2022 17:11:05 +0300 Subject: spi25_statusreg: support reading/writing configuration register One more variation of registers. This one is read via a separate RDCR command, but written as if it's SR2 using WRSR_EXT2. Change-Id: I45f9afcc31f1928ef6263a749596380082963de4 Signed-off-by: Sergii Dmytruk Reviewed-on: https://review.coreboot.org/c/flashrom/+/66211 Reviewed-by: Edward O'Callaghan Reviewed-by: Nikolai Artemiev Tested-by: build bot (Jenkins) --- include/flash.h | 4 ++++ include/spi.h | 5 +++++ 2 files changed, 9 insertions(+) (limited to 'include') diff --git a/include/flash.h b/include/flash.h index 197c11ea..23222c72 100644 --- a/include/flash.h +++ b/include/flash.h @@ -161,6 +161,9 @@ enum write_granularity { */ #define FEATURE_SCUR (1 << 24) +/* Whether chip has configuration register (RDCR/WRSR_EXT2 commands) */ +#define FEATURE_CFGR (1 << 25) + #define ERASED_VALUE(flash) (((flash)->chip->feature_bits & FEATURE_ERASED_ZERO) ? 0x00 : 0xff) #define UNERASED_VALUE(flash) (((flash)->chip->feature_bits & FEATURE_ERASED_ZERO) ? 0xff : 0x00) @@ -196,6 +199,7 @@ enum flash_reg { STATUS2, STATUS3, SECURITY, + CONFIG, MAX_REGISTERS }; diff --git a/include/spi.h b/include/spi.h index c77866c4..505aecd0 100644 --- a/include/spi.h +++ b/include/spi.h @@ -177,6 +177,11 @@ #define JEDEC_WRSCUR_OUTSIZE 0x01 #define JEDEC_WRSCUR_INSIZE 0x00 +/* Read Configuration Register */ +#define JEDEC_RDCR 0x15 +#define JEDEC_RDCR_OUTSIZE 0x01 +#define JEDEC_RDCR_INSIZE 0x01 + /* Enter 4-byte Address Mode */ #define JEDEC_ENTER_4_BYTE_ADDR_MODE 0xB7 -- cgit v1.2.3