From 90286fe643bbc2493275a5280a26766784435dda Mon Sep 17 00:00:00 2001
From: Thomas Heijligen <thomas.heijligen@secunet.com>
Date: Tue, 14 Feb 2023 16:50:38 +0100
Subject: printf: Use inttype.h macros for format strings
DJGPP for compiling DOS has other sizes for the normal int types and
therefore throwing errors when using %i %d or %x with uint32_t.
Fix these warnings by using the macros created for it and provided in
inttypes.h.
Change-Id: Ia75b6df981ce60c891161fe553c7ceab8570178d
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/73040
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
atavia.c | 2 +-
board_enable.c | 2 +-
cbtable.c | 8 +-
chipset_enable.c | 20 ++---
cli_classic.c | 16 ++--
dummyflasher.c | 2 +-
erasure_layout.c | 16 ++--
flashrom.c | 24 +++---
gfxnvidia.c | 2 +-
ich_descriptors.c | 56 +++++++-------
ichspi.c | 223 +++++++++++++++++++++++++++---------------------------
jedec.c | 4 +-
layout.c | 2 +-
mcp6x_spi.c | 2 +-
nicintel_eeprom.c | 2 +-
s25f.c | 4 +-
satamv.c | 38 +++++-----
satasii.c | 2 +-
sb600spi.c | 28 +++----
sfdp.c | 12 +--
spi25.c | 10 +--
spi95.c | 2 +-
22 files changed, 239 insertions(+), 238 deletions(-)
diff --git a/atavia.c b/atavia.c
index f35771a4..da2ab2fc 100644
--- a/atavia.c
+++ b/atavia.c
@@ -166,7 +166,7 @@ static int atavia_init(const struct programmer_cfg *cfg)
pci_write_long(dev, PCI_ROM_ADDRESS, (uint32_t)PCI_ROM_ADDRESS_MASK);
default_delay(90);
uint32_t base = pci_read_long(dev, PCI_ROM_ADDRESS);
- msg_pdbg2("BROM base=0x%08x\n", base);
+ msg_pdbg2("BROM base=0x%08"PRIx32"\n", base);
if ((base & PCI_ROM_ADDRESS_MASK) == 0) {
msg_pwarn("Controller thinks there is no ROM attached.\n");
}
diff --git a/board_enable.c b/board_enable.c
index d9af44e9..6e48a626 100644
--- a/board_enable.c
+++ b/board_enable.c
@@ -672,7 +672,7 @@ int it8705f_write_enable(uint8_t port)
*/
ret = 1;
}
- msg_pdbg("Maximum IT8705F parallel flash decode size is %u.\n",
+ msg_pdbg("Maximum IT8705F parallel flash decode size is %"PRIu32".\n",
max_rom_decode.parallel);
if (ret) {
msg_pinfo("Not enabling IT8705F flash write.\n");
diff --git a/cbtable.c b/cbtable.c
index 38f9cbe2..dd6a0b95 100644
--- a/cbtable.c
+++ b/cbtable.c
@@ -159,7 +159,7 @@ static int lb_header_valid(struct lb_header *head, unsigned long addr)
msg_pdbg("Found candidate at: %08lx-%08lx\n",
addr, addr + sizeof(*head) + head->table_bytes);
if (head->header_bytes != sizeof(*head)) {
- msg_perr("Header bytes of %d are incorrect.\n",
+ msg_perr("Header bytes of %"PRId32" are incorrect.\n",
head->header_bytes);
return 0;
}
@@ -175,12 +175,12 @@ static int lb_table_valid(struct lb_header *head, struct lb_record *recs)
{
if (compute_checksum(recs, head->table_bytes)
!= head->table_checksum) {
- msg_perr("Bad table checksum: %04x.\n",
+ msg_perr("Bad table checksum: %04"PRIx32".\n",
head->table_checksum);
return 0;
}
if (count_lb_records(head) != head->table_entries) {
- msg_perr("Bad record count: %d.\n",
+ msg_perr("Bad record count: %"PRId32".\n",
head->table_entries);
return 0;
}
@@ -352,7 +352,7 @@ int cb_parse_table(const char **vendor, const char **model)
(unsigned long)lb_table - (unsigned long)table_area + start);
rec = (struct lb_record *)(((char *)lb_table) + lb_table->header_bytes);
last = (struct lb_record *)(((char *)rec) + lb_table->table_bytes);
- msg_pdbg("coreboot header(%d) checksum: %04x table(%d) checksum: %04x entries: %d\n",
+ msg_pdbg("coreboot header(%"PRId32") checksum: %04"PRIx32" table(%"PRId32") checksum: %04"PRIx32" entries: %"PRId32"\n",
lb_table->header_bytes, lb_table->header_checksum,
lb_table->table_bytes, lb_table->table_checksum,
lb_table->table_entries);
diff --git a/chipset_enable.c b/chipset_enable.c
index 596899a5..9d3df5f8 100644
--- a/chipset_enable.c
+++ b/chipset_enable.c
@@ -550,7 +550,7 @@ idsel_garbage_out:
}
}
max_rom_decode.fwh = min(max_decode_fwh_idsel, max_decode_fwh_decode);
- msg_pdbg("Maximum FWH chip size: 0x%x bytes\n", max_rom_decode.fwh);
+ msg_pdbg("Maximum FWH chip size: 0x%"PRIx32" bytes\n", max_rom_decode.fwh);
return 0;
}
@@ -625,7 +625,7 @@ static enum chipbustype enable_flash_ich_report_gcs(
break;
}
- msg_pdbg("%s = 0x%x: ", reg_name, gcs);
+ msg_pdbg("%s = 0x%"PRIx32": ", reg_name, gcs);
msg_pdbg("BIOS Interface Lock-Down: %sabled, ", bild ? "en" : "dis");
struct boot_straps {
@@ -774,7 +774,7 @@ static int enable_flash_ich_spi(const struct programmer_cfg *cfg, struct pci_dev
{
/* Get physical address of Root Complex Register Block */
uint32_t rcra = pci_read_long(dev, 0xf0) & 0xffffc000;
- msg_pdbg("Root Complex Register Block address = 0x%x\n", rcra);
+ msg_pdbg("Root Complex Register Block address = 0x%"PRIx32"\n", rcra);
/* Map RCBA to virtual memory */
void *rcrb = rphysmap("ICH RCRB", rcra, 0x4000);
@@ -958,7 +958,7 @@ static int enable_flash_pch100_or_c620(const struct programmer_cfg *cfg,
void *const spibar = rphysmap("SPIBAR", phys_spibar, 0x1000);
if (spibar == ERROR_PTR)
goto _freepci_ret;
- msg_pdbg("SPIBAR = 0x%0*" PRIxPTR " (phys = 0x%08x)\n", PRIxPTR_WIDTH, (uintptr_t)spibar, phys_spibar);
+ msg_pdbg("SPIBAR = 0x%0*" PRIxPTR " (phys = 0x%08"PRIx32")\n", PRIxPTR_WIDTH, (uintptr_t)spibar, phys_spibar);
/* This adds BUS_SPI */
const int ret_spi = ich_init_spi(cfg, spibar, pch_generation);
@@ -1050,7 +1050,7 @@ static int enable_flash_silvermont(const struct programmer_cfg *cfg, struct pci_
/* Get physical address of Root Complex Register Block */
uint32_t rcba = pci_read_long(dev, 0xf0) & 0xfffffc00;
- msg_pdbg("Root Complex Register Block address = 0x%x\n", rcba);
+ msg_pdbg("Root Complex Register Block address = 0x%"PRIx32"\n", rcba);
/* Handle GCS (in RCRB) */
void *rcrb = physmap("BYT RCRB", rcba, 4);
@@ -1068,7 +1068,7 @@ static int enable_flash_silvermont(const struct programmer_cfg *cfg, struct pci_
/* Get physical address of SPI Base Address and map it */
uint32_t sbase = pci_read_long(dev, 0x54) & 0xfffffe00;
- msg_pdbg("SPI_BASE_ADDRESS = 0x%x\n", sbase);
+ msg_pdbg("SPI_BASE_ADDRESS = 0x%"PRIx32"\n", sbase);
void *spibar = rphysmap("BYT SBASE", sbase, 512); /* Last defined address on Bay Trail is 0x100 */
if (spibar == ERROR_PTR)
return ERROR_FLASHROM_FATAL;
@@ -1387,7 +1387,7 @@ static int enable_flash_sb600(const struct programmer_cfg *cfg, struct pci_dev *
/* No protection flags for this region?*/
if ((prot & 0x3) == 0)
continue;
- msg_pdbg("Chipset %s%sprotected flash from 0x%08x to 0x%08x, unlocking...",
+ msg_pdbg("Chipset %s%sprotected flash from 0x%08"PRIx32" to 0x%08"PRIx32", unlocking...",
(prot & 0x2) ? "read " : "",
(prot & 0x1) ? "write " : "",
(prot & 0xfffff800),
@@ -1396,7 +1396,7 @@ static int enable_flash_sb600(const struct programmer_cfg *cfg, struct pci_dev *
rpci_write_byte(dev, reg, prot);
prot = pci_read_long(dev, reg);
if ((prot & 0x3) != 0) {
- msg_perr("Disabling %s%sprotection of flash addresses from 0x%08x to 0x%08x failed.\n",
+ msg_perr("Disabling %s%sprotection of flash addresses from 0x%08"PRIx32" to 0x%08"PRIx32" failed.\n",
(prot & 0x2) ? "read " : "",
(prot & 0x1) ? "write " : "",
(prot & 0xfffff800),
@@ -1494,7 +1494,7 @@ static int enable_flash_ck804(const struct programmer_cfg *cfg, struct pci_dev *
segctrl = pci_read_byte(dev, reg);
if ((segctrl & 0x3) != 0x0) {
- msg_pinfo("Could not unlock protection in register 0x%02x (new value: 0x%x).\n",
+ msg_pinfo("Could not unlock protection in register 0x%02x (new value: 0x%"PRIx32").\n",
reg, segctrl);
err++;
} else
@@ -1518,7 +1518,7 @@ static int enable_flash_ck804(const struct programmer_cfg *cfg, struct pci_dev *
segctrl = pci_read_long(dev, reg);
if ((segctrl & 0x33333333) != 0x00000000) {
- msg_pinfo("Could not unlock protection in register 0x%02x (new value: 0x%08x).\n",
+ msg_pinfo("Could not unlock protection in register 0x%02x (new value: 0x%08"PRIx32").\n",
reg, segctrl);
err++;
} else
diff --git a/cli_classic.c b/cli_classic.c
index d804caec..60f3fd50 100644
--- a/cli_classic.c
+++ b/cli_classic.c
@@ -579,32 +579,32 @@ static unsigned int count_max_decode_exceedings(const struct flashctx *flash,
if ((buses & BUS_PARALLEL) && (max_rom_decode_->parallel < size)) {
limitexceeded++;
- msg_pdbg("Chip size %u kB is bigger than supported "
- "size %u kB of chipset/board/programmer "
+ msg_pdbg("Chip size %"PRIu32" kB is bigger than supported "
+ "size %"PRIu32" kB of chipset/board/programmer "
"for %s interface, "
"probe/read/erase/write may fail. ", size / 1024,
max_rom_decode_->parallel / 1024, "Parallel");
}
if ((buses & BUS_LPC) && (max_rom_decode_->lpc < size)) {
limitexceeded++;
- msg_pdbg("Chip size %u kB is bigger than supported "
- "size %u kB of chipset/board/programmer "
+ msg_pdbg("Chip size %"PRIu32" kB is bigger than supported "
+ "size %"PRIu32" kB of chipset/board/programmer "
"for %s interface, "
"probe/read/erase/write may fail. ", size / 1024,
max_rom_decode_->lpc / 1024, "LPC");
}
if ((buses & BUS_FWH) && (max_rom_decode_->fwh < size)) {
limitexceeded++;
- msg_pdbg("Chip size %u kB is bigger than supported "
- "size %u kB of chipset/board/programmer "
+ msg_pdbg("Chip size %"PRIu32" kB is bigger than supported "
+ "size %"PRIu32" kB of chipset/board/programmer "
"for %s interface, "
"probe/read/erase/write may fail. ", size / 1024,
max_rom_decode_->fwh / 1024, "FWH");
}
if ((buses & BUS_SPI) && (max_rom_decode_->spi < size)) {
limitexceeded++;
- msg_pdbg("Chip size %u kB is bigger than supported "
- "size %u kB of chipset/board/programmer "
+ msg_pdbg("Chip size %"PRIu32" kB is bigger than supported "
+ "size %"PRIu32" kB of chipset/board/programmer "
"for %s interface, "
"probe/read/erase/write may fail. ", size / 1024,
max_rom_decode_->spi / 1024, "SPI");
diff --git a/dummyflasher.c b/dummyflasher.c
index fa43bcd0..cf4ca03b 100644
--- a/dummyflasher.c
+++ b/dummyflasher.c
@@ -215,7 +215,7 @@ static void dummy_chip_writew(const struct flashctx *flash, uint16_t val, chipad
static void dummy_chip_writel(const struct flashctx *flash, uint32_t val, chipaddr addr)
{
- msg_pspew("%s: addr=0x%" PRIxPTR ", val=0x%08x\n", __func__, addr, val);
+ msg_pspew("%s: addr=0x%" PRIxPTR ", val=0x%08"PRIx32"\n", __func__, addr, val);
}
static void dummy_chip_writen(const struct flashctx *flash, const uint8_t *buf, chipaddr addr, size_t len)
diff --git a/erasure_layout.c b/erasure_layout.c
index 2097b33b..a802ae48 100644
--- a/erasure_layout.c
+++ b/erasure_layout.c
@@ -313,7 +313,7 @@ int erase_write(struct flashctx *const flashctx, chipoff_t region_start, chipoff
if (region.write_prot) {
msg_gdbg("%s: cannot erase inside %s "
- "region (%#08x..%#08x), skipping range (%#08x..%#08x).\n",
+ "region (%#08"PRIx32"..%#08"PRIx32"), skipping range (%#08x..%#08x).\n",
__func__, region.name,
region.start, region.end - 1,
addr, addr + len - 1);
@@ -321,7 +321,7 @@ int erase_write(struct flashctx *const flashctx, chipoff_t region_start, chipoff
continue;
}
- msg_gdbg("%s: %s region (%#08x..%#08x) is "
+ msg_gdbg("%s: %s region (%#08"PRIx32"..%#08"PRIx32") is "
"writable, erasing range (%#08x..%#08x).\n",
__func__, region.name,
region.start, region.end - 1,
@@ -339,7 +339,7 @@ int erase_write(struct flashctx *const flashctx, chipoff_t region_start, chipoff
ret = erasefn(flashctx, start_addr, block_len);
if (ret) {
msg_cerr("Failed to execute erase command "
- "for offset %#x to %#x.\n",
+ "for offset %#"PRIx32" to %#"PRIx32".\n",
start_addr, start_addr + block_len);
ret = -1;
goto _end;
@@ -349,11 +349,11 @@ int erase_write(struct flashctx *const flashctx, chipoff_t region_start, chipoff
memset(curcontents+start_addr, erased_value, block_len);
// after erase make it unselected again
erase_layout[i].layout_list[j].selected = false;
- msg_cdbg("E(%x:%x)", start_addr, start_addr + block_len - 1);
+ msg_cdbg("E(%"PRIx32":%"PRIx32")", start_addr, start_addr + block_len - 1);
// verify erase
ret = check_erased_range(flashctx, start_addr, block_len);
if (ret) {
- msg_cerr("Verifying flash. Erase failed for range %#x : %#x, Abort.\n",
+ msg_cerr("Verifying flash. Erase failed for range %#"PRIx32" : %#"PRIx32", Abort.\n",
start_addr, start_addr + block_len - 1);
goto _end;
}
@@ -381,14 +381,14 @@ int erase_write(struct flashctx *const flashctx, chipoff_t region_start, chipoff
// adjust curcontents
memcpy(curcontents + region_start + start_here,
newcontents + region_start + start_here, len_here);
- msg_cdbg("W(%x:%x)", region_start + start_here, region_start + start_here + len_here - 1);
+ msg_cdbg("W(%"PRIx32":%"PRIx32")", region_start + start_here, region_start + start_here + len_here - 1);
*all_skipped = false;
}
// verify write
ret = verify_range(flashctx, newcontents + region_start, region_start, region_end - region_start);
if (ret) {
- msg_cerr("Verifying flash. Write failed for range %#x : %#x, Abort.\n",
+ msg_cerr("Verifying flash. Write failed for range %#"PRIx32" : %#"PRIx32", Abort.\n",
region_start, region_end);
goto _end;
}
@@ -400,6 +400,6 @@ _end:
free(old_start_buf);
free(old_end_buf);
- msg_cinfo("Erase/write done from %x to %x\n", region_start, region_end);
+ msg_cinfo("Erase/write done from %"PRIx32" to %"PRIx32"\n", region_start, region_end);
return ret;
}
diff --git a/flashrom.c b/flashrom.c
index e14516f6..07ed0dfc 100644
--- a/flashrom.c
+++ b/flashrom.c
@@ -391,7 +391,7 @@ int check_for_unwritable_regions(const struct flashctx *flash, unsigned int star
get_flash_region(flash, addr, ®ion);
if (region.write_prot) {
- msg_gerr("%s: cannot write/erase inside %s region (%#08x..%#08x).\n",
+ msg_gerr("%s: cannot write/erase inside %s region (%#08"PRIx32"..%#08"PRIx32").\n",
__func__, region.name, region.start, region.end - 1);
free(region.name);
return -1;
@@ -587,7 +587,7 @@ int read_flash(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigne
if (region.read_prot) {
if (flash->flags.skip_unreadable_regions) {
- msg_gdbg("%s: cannot read inside %s region (%#08x..%#08x), "
+ msg_gdbg("%s: cannot read inside %s region (%#08"PRIx32"..%#08"PRIx32"), "
"filling (%#08x..%#08x) with erased value instead.\n",
__func__, region.name, region.start, region.end - 1,
addr, addr + read_len - 1);
@@ -597,12 +597,12 @@ int read_flash(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigne
continue;
}
- msg_gerr("%s: cannot read inside %s region (%#08x..%#08x).\n",
+ msg_gerr("%s: cannot read inside %s region (%#08"PRIx32"..%#08"PRIx32").\n",
__func__, region.name, region.start, region.end - 1);
free(region.name);
return -1;
}
- msg_gdbg("%s: %s region (%#08x..%#08x) is readable, reading range (%#08x..%#08x).\n",
+ msg_gdbg("%s: %s region (%#08"PRIx32"..%#08"PRIx32") is readable, reading range (%#08x..%#08x).\n",
__func__, region.name, region.start, region.end - 1, addr, addr + read_len - 1);
free(region.name);
@@ -655,20 +655,20 @@ int verify_range(struct flashctx *flash, const uint8_t *cmpbuf, unsigned int sta
if ((region.write_prot && flash->flags.skip_unwritable_regions) ||
(region.read_prot && flash->flags.skip_unreadable_regions)) {
- msg_gdbg("%s: Skipping verification of %s region (%#08x..%#08x)\n",
+ msg_gdbg("%s: Skipping verification of %s region (%#08"PRIx32"..%#08"PRIx32")\n",
__func__, region.name, region.start, region.end - 1);
free(region.name);
continue;
}
if (region.read_prot) {
- msg_gerr("%s: Verification imposible because %s region (%#08x..%#08x) is unreadable.\n",
+ msg_gerr("%s: Verification imposible because %s region (%#08"PRIx32"..%#08"PRIx32") is unreadable.\n",
__func__, region.name, region.start, region.end - 1);
free(region.name);
goto out_free;
}
- msg_gdbg("%s: Verifying %s region (%#08x..%#08x)\n",
+ msg_gdbg("%s: Verifying %s region (%#08"PRIx32"..%#08"PRIx32")\n",
__func__, region.name, region.start, region.end - 1);
free(region.name);
@@ -1032,13 +1032,13 @@ int write_flash(struct flashctx *flash, const uint8_t *buf,
const uint8_t *rbuf = buf + addr - start;
if (region.write_prot) {
- msg_gdbg("%s: cannot write inside %s region (%#08x..%#08x), skipping (%#08x..%#08x).\n",
+ msg_gdbg("%s: cannot write inside %s region (%#08"PRIx32"..%#08"PRIx32"), skipping (%#08x..%#08x).\n",
__func__, region.name, region.start, region.end - 1, addr, addr + write_len - 1);
free(region.name);
continue;
}
- msg_gdbg("%s: %s region (%#08x..%#08x) is writable, writing range (%#08x..%#08x).\n",
+ msg_gdbg("%s: %s region (%#08"PRIx32"..%#08"PRIx32") is writable, writing range (%#08x..%#08x).\n",
__func__, region.name, region.start, region.end - 1, addr, addr + write_len - 1);
write_func_t *write_func = lookup_write_func_ptr(flash->chip);
@@ -1364,7 +1364,7 @@ static int walk_eraseblocks(struct flashctx *const flashctx,
first = false;
else
msg_cdbg(", ");
- msg_cdbg("0x%06x-0x%06x:", info->erase_start, info->erase_end);
+ msg_cdbg("0x%06"PRIx32"-0x%06"PRIx32":", info->erase_start, info->erase_end);
erasefunc_t *erase_func = lookup_erase_func_ptr(eraser);
ret = per_blockfn(flashctx, info, erase_func, all_skipped);
@@ -1496,13 +1496,13 @@ static int erase_block(struct flashctx *const flashctx,
len = min(info->erase_start + erase_len, region.end) - addr;
if (region.write_prot) {
- msg_gdbg("%s: cannot erase inside %s region (%#08x..%#08x), skipping range (%#08x..%#08x).\n",
+ msg_gdbg("%s: cannot erase inside %s region (%#08"PRIx32"..%#08"PRIx32"), skipping range (%#08x..%#08x).\n",
__func__, region.name, region.start, region.end - 1, addr, addr + len - 1);
free(region.name);
continue;
}
- msg_gdbg("%s: %s region (%#08x..%#08x) is writable, erasing range (%#08x..%#08x).\n",
+ msg_gdbg("%s: %s region (%#08"PRIx32"..%#08"PRIx32") is writable, erasing range (%#08x..%#08x).\n",
__func__, region.name, region.start, region.end - 1, addr, addr + len - 1);
free(region.name);
diff --git a/gfxnvidia.c b/gfxnvidia.c
index b4209751..080c8854 100644
--- a/gfxnvidia.c
+++ b/gfxnvidia.c
@@ -115,7 +115,7 @@ static int gfxnvidia_init(const struct programmer_cfg *cfg)
return 1;
io_base_addr += 0x300000;
- msg_pinfo("Detected NVIDIA I/O base address: 0x%x.\n", io_base_addr);
+ msg_pinfo("Detected NVIDIA I/O base address: 0x%"PRIx32".\n", io_base_addr);
bar = rphysmap("NVIDIA", io_base_addr, GFXNVIDIA_MEMMAP_SIZE);
if (bar == ERROR_PTR)
diff --git a/ich_descriptors.c b/ich_descriptors.c
index b37ce6d5..a2a99bd0 100644
--- a/ich_descriptors.c
+++ b/ich_descriptors.c
@@ -94,13 +94,13 @@ ssize_t ich_number_of_masters(const enum ich_chipset cs, const struct ich_desc_c
void prettyprint_ich_reg_vscc(uint32_t reg_val, int verbosity, bool print_vcl)
{
- print(verbosity, "BES=0x%x, ", (reg_val & VSCC_BES) >> VSCC_BES_OFF);
- print(verbosity, "WG=%d, ", (reg_val & VSCC_WG) >> VSCC_WG_OFF);
- print(verbosity, "WSR=%d, ", (reg_val & VSCC_WSR) >> VSCC_WSR_OFF);
- print(verbosity, "WEWS=%d, ", (reg_val & VSCC_WEWS) >> VSCC_WEWS_OFF);
- print(verbosity, "EO=0x%x", (reg_val & VSCC_EO) >> VSCC_EO_OFF);
+ print(verbosity, "BES=0x%"PRIx32", ", (reg_val & VSCC_BES) >> VSCC_BES_OFF);
+ print(verbosity, "WG=%"PRId32", ", (reg_val & VSCC_WG) >> VSCC_WG_OFF);
+ print(verbosity, "WSR=%"PRId32", ", (reg_val & VSCC_WSR) >> VSCC_WSR_OFF);
+ print(verbosity, "WEWS=%"PRId32", ", (reg_val & VSCC_WEWS) >> VSCC_WEWS_OFF);
+ print(verbosity, "EO=0x%"PRIx32"", (reg_val & VSCC_EO) >> VSCC_EO_OFF);
if (print_vcl)
- print(verbosity, ", VCL=%d", (reg_val & VSCC_VCL) >> VSCC_VCL_OFF);
+ print(verbosity, ", VCL=%"PRId32"", (reg_val & VSCC_VCL) >> VSCC_VCL_OFF);
print(verbosity, "\n");
}
@@ -145,23 +145,23 @@ void prettyprint_ich_descriptors(enum ich_chipset cs, const struct ich_descripto
void prettyprint_ich_descriptor_content(enum ich_chipset cs, const struct ich_desc_content *cont)
{
msg_pdbg2("=== Content Section ===\n");
- msg_pdbg2("FLVALSIG 0x%08x\n", cont->FLVALSIG);
- msg_pdbg2("FLMAP0 0x%08x\n", cont->FLMAP0);
- msg_pdbg2("FLMAP1 0x%08x\n", cont->FLMAP1);
- msg_pdbg2("FLMAP2 0x%08x\n", cont->FLMAP2);
+ msg_pdbg2("FLVALSIG 0x%08"PRIx32"\n", cont->FLVALSIG);
+ msg_pdbg2("FLMAP0 0x%08"PRIx32"\n", cont->FLMAP0);
+ msg_pdbg2("FLMAP1 0x%08"PRIx32"\n", cont->FLMAP1);
+ msg_pdbg2("FLMAP2 0x%08"PRIx32"\n", cont->FLMAP2);
msg_pdbg2("\n");
msg_pdbg2("--- Details ---\n");
msg_pdbg2("NR (Number of Regions): %5zd\n", ich_number_of_regions(cs, cont));
- msg_pdbg2("FRBA (Flash Region Base Address): 0x%03x\n", getFRBA(cont));
+ msg_pdbg2("FRBA (Flash Region Base Address): 0x%03"PRIx32"\n", getFRBA(cont));
msg_pdbg2("NC (Number of Components): %5d\n", cont->NC + 1);
- msg_pdbg2("FCBA (Flash Component Base Address): 0x%03x\n", getFCBA(cont));
+ msg_pdbg2("FCBA (Flash Component Base Address): 0x%03"PRIx32"\n", getFCBA(cont));
msg_pdbg2("ISL (ICH/PCH/SoC Strap Length): %5d\n", cont->ISL);
- msg_pdbg2("FISBA/FPSBA (Flash ICH/PCH/SoC Strap Base Addr): 0x%03x\n", getFISBA(cont));
+ msg_pdbg2("FISBA/FPSBA (Flash ICH/PCH/SoC Strap Base Addr): 0x%03"PRIx32"\n", getFISBA(cont));
msg_pdbg2("NM (Number of Masters): %5zd\n", ich_number_of_masters(cs, cont));
- msg_pdbg2("FMBA (Flash Master Base Address): 0x%03x\n", getFMBA(cont));
+ msg_pdbg2("FMBA (Flash Master Base Address): 0x%03"PRIx32"\n", getFMBA(cont));
msg_pdbg2("MSL/PSL (MCH/PROC Strap Length): %5d\n", cont->MSL);
- msg_pdbg2("FMSBA (Flash MCH/PROC Strap Base Address): 0x%03x\n", getFMSBA(cont));
+ msg_pdbg2("FMSBA (Flash MCH/PROC Strap Base Address): 0x%03"PRIx32"\n", getFMSBA(cont));
msg_pdbg2("\n");
}
@@ -374,10 +374,10 @@ void prettyprint_ich_descriptor_component(enum ich_chipset cs, const struct ich_
}
msg_pdbg2("=== Component Section ===\n");
- msg_pdbg2("FLCOMP 0x%08x\n", desc->component.FLCOMP);
- msg_pdbg2("FLILL 0x%08x\n", desc->component.FLILL );
+ msg_pdbg2("FLCOMP 0x%08"PRIx32"\n", desc->component.FLCOMP);
+ msg_pdbg2("FLILL 0x%08"PRIx32"\n", desc->component.FLILL );
if (has_flill1)
- msg_pdbg2("FLILL1 0x%08x\n", desc->component.FLILL1);
+ msg_pdbg2("FLILL1 0x%08"PRIx32"\n", desc->component.FLILL1);
msg_pdbg2("\n");
msg_pdbg2("--- Details ---\n");
@@ -442,11 +442,11 @@ static void pprint_freg(const struct ich_desc_region *reg, uint32_t i)
}
uint32_t base = ICH_FREG_BASE(reg->FLREGs[i]);
uint32_t limit = ICH_FREG_LIMIT(reg->FLREGs[i]);
- msg_pdbg2("Region %d (%-7s) ", i, region_names[i]);
+ msg_pdbg2("Region %"PRId32" (%-7s) ", i, region_names[i]);
if (base > limit)
msg_pdbg2("is unused.\n");
else
- msg_pdbg2("0x%08x - 0x%08x\n", base, limit);
+ msg_pdbg2("0x%08"PRIx32" - 0x%08"PRIx32"\n", base, limit);
}
void prettyprint_ich_descriptor_region(const enum ich_chipset cs, const struct ich_descriptors *const desc)
@@ -460,7 +460,7 @@ void prettyprint_ich_descriptor_region(const enum ich_chipset cs, const struct i
return;
}
for (i = 0; i < nr; i++)
- msg_pdbg2("FLREG%zd 0x%08x\n", i, desc->region.FLREGs[i]);
+ msg_pdbg2("FLREG%zd 0x%08"PRIx32"\n", i, desc->region.FLREGs[i]);
msg_pdbg2("\n");
msg_pdbg2("--- Details ---\n");
@@ -480,7 +480,7 @@ void prettyprint_ich_descriptor_master(const enum ich_chipset cs, const struct i
return;
}
for (i = 0; i < nm; i++)
- msg_pdbg2("FLMSTR%zd 0x%08x\n", i + 1, desc->master.FLMSTRs[i]);
+ msg_pdbg2("FLMSTR%zd 0x%08"PRIx32"\n", i + 1, desc->master.FLMSTRs[i]);
msg_pdbg2("\n");
msg_pdbg2("--- Details ---\n");
@@ -912,7 +912,7 @@ void prettyprint_ich_descriptor_straps(enum ich_chipset cs, const struct ich_des
msg_pdbg2("--- North/MCH/PROC (%d entries) ---\n", max_count);
for (i = 0; i < max_count; i++)
- msg_pdbg2("STRP%-2d = 0x%08x\n", i, desc->north.STRPs[i]);
+ msg_pdbg2("STRP%-2d = 0x%08"PRIx32"\n", i, desc->north.STRPs[i]);
msg_pdbg2("\n");
max_count = MIN(ARRAY_SIZE(desc->south.STRPs), desc->content.ISL);
@@ -924,7 +924,7 @@ void prettyprint_ich_descriptor_straps(enum ich_chipset cs, const struct ich_des
msg_pdbg2("--- South/ICH/PCH (%d entries) ---\n", max_count);
for (i = 0; i < max_count; i++)
- msg_pdbg2("STRP%-2d = 0x%08x\n", i, desc->south.STRPs[i]);
+ msg_pdbg2("STRP%-2d = 0x%08"PRIx32"\n", i, desc->south.STRPs[i]);
msg_pdbg2("\n");
switch (cs) {
@@ -970,20 +970,20 @@ void prettyprint_ich_descriptor_upper_map(const struct ich_desc_upper_map *umap)
{
int i;
msg_pdbg2("=== Upper Map Section ===\n");
- msg_pdbg2("FLUMAP1 0x%08x\n", umap->FLUMAP1);
+ msg_pdbg2("FLUMAP1 0x%08"PRIx32"\n", umap->FLUMAP1);
msg_pdbg2("\n");
msg_pdbg2("--- Details ---\n");
msg_pdbg2("VTL (length in DWORDS) = %d\n", umap->VTL);
- msg_pdbg2("VTBA (base address) = 0x%6.6x\n", getVTBA(umap));
+ msg_pdbg2("VTBA (base address) = 0x%6.6"PRIx32"\n", getVTBA(umap));
msg_pdbg2("\n");
msg_pdbg2("VSCC Table: %d entries\n", umap->VTL/2);
for (i = 0; i < umap->VTL/2; i++) {
uint32_t jid = umap->vscc_table[i].JID;
uint32_t vscc = umap->vscc_table[i].VSCC;
- msg_pdbg2(" JID%d = 0x%08x\n", i, jid);
- msg_pdbg2(" VSCC%d = 0x%08x\n", i, vscc);
+ msg_pdbg2(" JID%d = 0x%08"PRIx32"\n", i, jid);
+ msg_pdbg2(" VSCC%d = 0x%08"PRIx32"\n", i, vscc);
msg_pdbg2(" "); /* indentation */
prettyprint_rdid(jid);
msg_pdbg2(" "); /* indentation */
diff --git a/ichspi.c b/ichspi.c
index 1522d2b4..e9668ef2 100644
--- a/ichspi.c
+++ b/ichspi.c
@@ -445,14 +445,15 @@ static void prettyprint_opcodes(OPCODES *ops)
ops->preop[1]);
}
-#define pprint_reg(reg, bit, val, sep) msg_pdbg("%s=%d" sep, #bit, (val & reg##_##bit) >> reg##_##bit##_OFF)
+#define pprint_reg16(reg, bit, val, sep) msg_pdbg("%s=%"PRId16"" sep, #bit, (val & reg##_##bit) >> reg##_##bit##_OFF)
+#define pprint_reg32(reg, bit, val, sep) msg_pdbg("%s=%"PRId32"" sep, #bit, (val & reg##_##bit) >> reg##_##bit##_OFF)
static void prettyprint_ich9_reg_hsfs(uint16_t reg_val, enum ich_chipset ich_gen)
{
msg_pdbg("HSFS: ");
- pprint_reg(HSFS, FDONE, reg_val, ", ");
- pprint_reg(HSFS, FCERR, reg_val, ", ");
- pprint_reg(HSFS, AEL, reg_val, ", ");
+ pprint_reg16(HSFS, FDONE, reg_val, ", ");
+ pprint_reg16(HSFS, FCERR, reg_val, ", ");
+ pprint_reg16(HSFS, AEL, reg_val, ", ");
switch (ich_gen) {
case CHIPSET_100_SERIES_SUNRISE_POINT:
case CHIPSET_C620_SERIES_LEWISBURG:
@@ -462,10 +463,10 @@ static void prettyprint_ich9_reg_hsfs(uint16_t reg_val, enum ich_chipset ich_gen
case CHIPSET_ELKHART_LAKE:
break;
default:
- pprint_reg(HSFS, BERASE, reg_val, ", ");
+ pprint_reg16(HSFS, BERASE, reg_val, ", ");
break;
}
- pprint_reg(HSFS, SCIP, reg_val, ", ");
+ pprint_reg16(HSFS, SCIP, reg_val, ", ");
switch (ich_gen) {
case CHIPSET_100_SERIES_SUNRISE_POINT:
case CHIPSET_C620_SERIES_LEWISBURG:
@@ -473,21 +474,21 @@ static void prettyprint_ich9_reg_hsfs(uint16_t reg_val, enum ich_chipset ich_gen
case CHIPSET_400_SERIES_COMET_POINT:
case CHIPSET_500_SERIES_TIGER_POINT:
case CHIPSET_ELKHART_LAKE:
- pprint_reg(HSFS, PRR34_LOCKDN, reg_val, ", ");
- pprint_reg(HSFS, WRSDIS, reg_val, ", ");
+ pprint_reg16(HSFS, PRR34_LOCKDN, reg_val, ", ");
+ pprint_reg16(HSFS, WRSDIS, reg_val, ", ");
break;
default:
break;
}
- pprint_reg(HSFS, FDOPSS, reg_val, ", ");
- pprint_reg(HSFS, FDV, reg_val, ", ");
- pprint_reg(HSFS, FLOCKDN, reg_val, "\n");
+ pprint_reg16(HSFS, FDOPSS, reg_val, ", ");
+ pprint_reg16(HSFS, FDV, reg_val, ", ");
+ pprint_reg16(HSFS, FLOCKDN, reg_val, "\n");
}
static void prettyprint_ich9_reg_hsfc(uint16_t reg_val, enum ich_chipset ich_gen)
{
msg_pdbg("HSFC: ");
- pprint_reg(HSFC, FGO, reg_val, ", ");
+ pprint_reg16(HSFC, FGO, reg_val, ", ");
switch (ich_gen) {
case CHIPSET_100_SERIES_SUNRISE_POINT:
case CHIPSET_C620_SERIES_LEWISBURG:
@@ -495,51 +496,51 @@ static void prettyprint_ich9_reg_hsfc(uint16_t reg_val, enum ich_chipset ich_gen
case CHIPSET_400_SERIES_COMET_POINT:
case CHIPSET_500_SERIES_TIGER_POINT:
case CHIPSET_ELKHART_LAKE:
- pprint_reg(PCH100_HSFC, FCYCLE, reg_val, ", ");
- pprint_reg(PCH100_HSFC, WET, reg_val, ", ");
+ pprint_reg16(PCH100_HSFC, FCYCLE, reg_val, ", ");
+ pprint_reg16(PCH100_HSFC, WET, reg_val, ", ");
break;
default:
- pprint_reg(ICH9_HSFC, FCYCLE, reg_val, ", ");
+ pprint_reg16(ICH9_HSFC, FCYCLE, reg_val, ", ");
break;
}
- pprint_reg(HSFC, FDBC, reg_val, ", ");
- pprint_reg(HSFC, SME, reg_val, "\n");
+ pprint_reg16(HSFC, FDBC, reg_val, ", ");
+ pprint_reg16(HSFC, SME, reg_val, "\n");
}
static void prettyprint_ich9_reg_ssfs(uint32_t reg_val)
{
msg_pdbg("SSFS: ");
- pprint_reg(SSFS, SCIP, reg_val, ", ");
- pprint_reg(SSFS, FDONE, reg_val, ", ");
- pprint_reg(SSFS, FCERR, reg_val, ", ");
- pprint_reg(SSFS, AEL, reg_val, "\n");
+ pprint_reg32(SSFS, SCIP, reg_val, ", ");
+ pprint_reg32(SSFS, FDONE, reg_val, ", ");
+ pprint_reg32(SSFS, FCERR, reg_val, ", ");
+ pprint_reg32(SSFS, AEL, reg_val, "\n");
}
static void prettyprint_ich9_reg_ssfc(uint32_t reg_val)
{
msg_pdbg("SSFC: ");
- pprint_reg(SSFC, SCGO, reg_val, ", ");
- pprint_reg(SSFC, ACS, reg_val, ", ");
- pprint_reg(SSFC, SPOP, reg_val, ", ");
- pprint_reg(SSFC, COP, reg_val, ", ");
- pprint_reg(SSFC, DBC, reg_val, ", ");
- pprint_reg(SSFC, SME, reg_val, ", ");
- pprint_reg(SSFC, SCF, reg_val, "\n");
+ pprint_reg32(SSFC, SCGO, reg_val, ", ");
+ pprint_reg32(SSFC, ACS, reg_val, ", ");
+ pprint_reg32(SSFC, SPOP, reg_val, ", ");
+ pprint_reg32(SSFC, COP, reg_val, ", ");
+ pprint_reg32(SSFC, DBC, reg_val, ", ");
+ pprint_reg32(SSFC, SME, reg_val, ", ");
+ pprint_reg32(SSFC, SCF, reg_val, "\n");
}
static void prettyprint_pch100_reg_dlock(const uint32_t reg_val)
{
msg_pdbg("DLOCK: ");
- pprint_reg(DLOCK, BMWAG_LOCKDN, reg_val, ", ");
- pprint_reg(DLOCK, BMRAG_LOCKDN, reg_val, ", ");
- pprint_reg(DLOCK, SBMWAG_LOCKDN, reg_val, ", ");
- pprint_reg(DLOCK, SBMRAG_LOCKDN, reg_val, ",\n ");
- pprint_reg(DLOCK, PR0_LOCKDN, reg_val, ", ");
- pprint_reg(DLOCK, PR1_LOCKDN, reg_val, ", ");
- pprint_reg(DLOCK, PR2_LOCKDN, reg_val, ", ");
- pprint_reg(DLOCK, PR3_LOCKDN, reg_val, ", ");
- pprint_reg(DLOCK, PR4_LOCKDN, reg_val, ",\n ");
- pprint_reg(DLOCK, SSEQ_LOCKDN, reg_val, "\n");
+ pprint_reg32(DLOCK, BMWAG_LOCKDN, reg_val, ", ");
+ pprint_reg32(DLOCK, BMRAG_LOCKDN, reg_val, ", ");
+ pprint_reg32(DLOCK, SBMWAG_LOCKDN, reg_val, ", ");
+ pprint_reg32(DLOCK, SBMRAG_LOCKDN, reg_val, ",\n ");
+ pprint_reg32(DLOCK, PR0_LOCKDN, reg_val, ", ");
+ pprint_reg32(DLOCK, PR1_LOCKDN, reg_val, ", ");
+ pprint_reg32(DLOCK, PR2_LOCKDN, reg_val, ", ");
+ pprint_reg32(DLOCK, PR3_LOCKDN, reg_val, ", ");
+ pprint_reg32(DLOCK, PR4_LOCKDN, reg_val, ",\n ");
+ pprint_reg32(DLOCK, SSEQ_LOCKDN, reg_val, "\n");
}
static struct swseq_data {
@@ -591,7 +592,7 @@ static int program_opcodes(OPCODES *op, int enable_undo, enum ich_chipset ich_ge
opmenu[1] |= ((uint32_t) op->opcode[a].opcode) << ((a - 4) * 8);
}
- msg_pdbg2("\n%s: preop=%04x optype=%04x opmenu=%08x%08x\n", __func__, preop, optype, opmenu[0], opmenu[1]);
+ msg_pdbg2("\n%s: preop=%04x optype=%04x opmenu=%08"PRIx32"%08"PRIx32"\n", __func__, preop, optype, opmenu[0], opmenu[1]);
switch (ich_gen) {
case CHIPSET_ICH7:
case CHIPSET_TUNNEL_CREEK:
@@ -713,7 +714,7 @@ static void ich_set_bbar(uint32_t min_addr, enum ich_chipset ich_gen)
ichspi_bbar = mmio_readl(ich_spibar + bbar_off) & ~BBAR_MASK;
if (ichspi_bbar) {
- msg_pdbg("Reserved bits in BBAR not zero: 0x%08x\n",
+ msg_pdbg("Reserved bits in BBAR not zero: 0x%08"PRIx32"\n",
ichspi_bbar);
}
min_addr &= BBAR_MASK;
@@ -725,7 +726,7 @@ static void ich_set_bbar(uint32_t min_addr, enum ich_chipset ich_gen)
* failed, the restore will fail as well, so no problem there.
*/
if (ichspi_bbar != min_addr)
- msg_perr("Setting BBAR to 0x%08x failed! New value: 0x%08x.\n",
+ msg_perr("Setting BBAR to 0x%08"PRIx32" failed! New value: 0x%08"PRIx32".\n",
min_addr, ichspi_bbar);
}
@@ -1081,7 +1082,7 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset,
default_delay(10);
}
if (!timeout) {
- msg_perr("timeout, REG_SSFS=0x%08x\n", REGREAD32(swseq_data.reg_ssfsc));
+ msg_perr("timeout, REG_SSFS=0x%08"PRIx32"\n", REGREAD32(swseq_data.reg_ssfsc));
return 1;
}
@@ -1230,7 +1231,7 @@ static int ich_spi_send_command(const struct flashctx *flash, unsigned int write
if (addr < valid_base ||
addr_end < addr || /* integer overflow check */
addr_end > valid_end) {
- msg_perr("%s: Addressed region 0x%06x-0x%06x not in allowed range 0x%06x-0x%06x\n",
+ msg_perr("%s: Addressed region 0x%06"PRIx32"-0x%06"PRIx32" not in allowed range 0x%06"PRIx32"-0x%06"PRIx32"\n",
__func__, addr, addr_end - 1, valid_base, valid_end - 1);
return SPI_INVALID_ADDRESS;
}
@@ -1242,7 +1243,7 @@ static int ich_spi_send_command(const struct flashctx *flash, unsigned int write
msg_pdbg("Running OPCODE 0x%02x failed ", opcode->opcode);
if ((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) ||
(opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS)) {
- msg_pdbg("at address 0x%06x ", addr);
+ msg_pdbg("at address 0x%06"PRIx32" ", addr);
}
msg_pdbg("(payload length was %d).\n", count);
@@ -1254,7 +1255,7 @@ static int ich_spi_send_command(const struct flashctx *flash, unsigned int write
int i;
msg_pspew("The data was:\n");
for (i = 0; i < count; i++){
- msg_pspew("%3d: 0x%02x\n", i, data[i]);
+ msg_pspew("%3d: 0x%02"PRIx8"\n", i, data[i]);
}
}
}
@@ -1341,8 +1342,8 @@ static int ich_hwseq_wait_for_cycle_complete(unsigned int len, enum ich_chipset
REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS));
if (!timeout_us) {
addr = REGREAD32(ICH9_REG_FADDR) & addr_mask;
- msg_perr("Timeout error between offset 0x%08x and "
- "0x%08x (= 0x%08x + %d)!\n",
+ msg_perr("Timeout error between offset 0x%08"PRIx32" and "
+ "0x%08"PRIx32" (= 0x%08"PRIx32" + %d)!\n",
addr, addr + len - 1, addr, len - 1);
prettyprint_ich9_reg_hsfs(hsfs, ich_gen);
prettyprint_ich9_reg_hsfc(REGREAD16(ICH9_REG_HSFC), ich_gen);
@@ -1351,8 +1352,8 @@ static int ich_hwseq_wait_for_cycle_complete(unsigned int len, enum ich_chipset
if (hsfs & HSFS_FCERR) {
addr = REGREAD32(ICH9_REG_FADDR) & addr_mask;
- msg_perr("Transaction error between offset 0x%08x and "
- "0x%08x (= 0x%08x + %d)!\n",
+ msg_perr("Transaction error between offset 0x%08"PRIx32" and "
+ "0x%08"PRIx32" (= 0x%08"PRIx32" + %d)!\n",
addr, addr + len - 1, addr, len - 1);
prettyprint_ich9_reg_hsfs(hsfs, ich_gen);
prettyprint_ich9_reg_hsfc(REGREAD16(ICH9_REG_HSFC), ich_gen);
@@ -1563,8 +1564,8 @@ static void ich_hwseq_get_flash_id(struct flashctx *flash, enum ich_chipset ich_
const struct flashchip *entry = flash_id_to_entry(mfg_id, model_id);
if (!entry) {
- msg_pwarn("Unable to identify chip, mfg_id: 0x%02x, "
- "model_id: 0x%02x\n", mfg_id, model_id);
+ msg_pwarn("Unable to identify chip, mfg_id: 0x%02"PRIx32", "
+ "model_id: 0x%02"PRIx32"\n", mfg_id, model_id);
}
msg_pdbg("Chip identified: %s\n", entry->name);
@@ -1597,7 +1598,7 @@ static int ich_hwseq_probe(struct flashctx *flash)
msg_cdbg("s with a combined");
else
msg_cdbg(" with a");
- msg_cdbg(" density of %d kB.\n", total_size / 1024);
+ msg_cdbg(" density of %"PRId32" kB.\n", total_size / 1024);
flash->chip->total_size = total_size / 1024;
eraser = &(flash->chip->block_erasers[0]);
@@ -1610,29 +1611,29 @@ static int ich_hwseq_probe(struct flashctx *flash)
if (boundary == 0) {
msg_cdbg2("There is only one partition containing the whole "
- "address space (0x%06x - 0x%06x).\n", 0, size_high-1);
+ "address space (0x%06x - 0x%06"PRIx32").\n", 0, size_high-1);
eraser->eraseblocks[0].size = erase_size_high;
eraser->eraseblocks[0].count = size_high / erase_size_high;
- msg_cdbg2("There are %d erase blocks with %d B each.\n",
+ msg_cdbg2("There are %"PRId32" erase blocks with %"PRId32" B each.\n",
size_high / erase_size_high, erase_size_high);
} else {
- msg_cdbg2("The flash address space (0x%06x - 0x%06x) is divided "
- "at address 0x%06x in two partitions.\n",
+ msg_cdbg2("The flash address space (0x%06x - 0x%06"PRIx32") is divided "
+ "at address 0x%06"PRIx32" in two partitions.\n",
0, total_size-1, boundary);
size_low = total_size - size_high;
erase_size_low = ich_hwseq_get_erase_block_size(0, hwseq_data->addr_mask, hwseq_data->only_4k);
eraser->eraseblocks[0].size = erase_size_low;
eraser->eraseblocks[0].count = size_low / erase_size_low;
- msg_cdbg("The first partition ranges from 0x%06x to 0x%06x.\n", 0, size_low-1);
- msg_cdbg("In that range are %d erase blocks with %d B each.\n",
+ msg_cdbg("The first partition ranges from 0x%06x to 0x%06"PRIx32".\n", 0, size_low-1);
+ msg_cdbg("In that range are %"PRId32" erase blocks with %"PRId32" B each.\n",
size_low / erase_size_low, erase_size_low);
eraser->eraseblocks[1].size = erase_size_high;
eraser->eraseblocks[1].count = size_high / erase_size_high;
- msg_cdbg("The second partition ranges from 0x%06x to 0x%06x.\n",
+ msg_cdbg("The second partition ranges from 0x%06"PRIx32" to 0x%06"PRIx32".\n",
boundary, total_size-1);
- msg_cdbg("In that range are %d erase blocks with %d B each.\n",
+ msg_cdbg("In that range are %"PRId32" erase blocks with %"PRId32" B each.\n",
size_high / erase_size_high, erase_size_high);
}
@@ -1652,7 +1653,7 @@ static int ich_hwseq_block_erase(struct flashctx *flash, unsigned int addr,
erase_block = ich_hwseq_get_erase_block_size(addr, hwseq_data->addr_mask, hwseq_data->only_4k);
if (len != erase_block) {
- msg_cerr("Erase block size for address 0x%06x is %d B, "
+ msg_cerr("Erase block size for address 0x%06x is %"PRId32" B, "
"but requested erase block size is %d B. "
"Not erasing anything.\n", addr, erase_block, len);
return -1;
@@ -1662,7 +1663,7 @@ static int ich_hwseq_block_erase(struct flashctx *flash, unsigned int addr,
* containing the address) we play safe here. */
if (addr % erase_block != 0) {
msg_cerr("Erase address 0x%06x is not aligned to the erase "
- "block boundary (any multiple of %d). "
+ "block boundary (any multiple of %"PRId32"). "
"Not erasing anything.\n", addr, erase_block);
return -1;
}
@@ -1851,11 +1852,11 @@ static enum ich_access_protection ich9_handle_frap(struct fd_region *fd_regions,
limit = ICH_FREG_LIMIT(freg);
if (base > limit || (freg == 0 && i > 0)) {
/* this FREG is disabled */
- msg_pdbg2("0x%02X: 0x%08x FREG%u: %s region is unused.\n",
+ msg_pdbg2("0x%02X: 0x%08"PRIx32" FREG%u: %s region is unused.\n",
offset, freg, i, region_name);
return NO_PROT;
}
- msg_pdbg("0x%02X: 0x%08x ", offset, freg);
+ msg_pdbg("0x%02X: 0x%08"PRIx32" ", offset, freg);
if (i < 8) {
rwperms_idx = (((ICH_BRWA(frap) >> i) & 1) << 1) |
@@ -1866,11 +1867,11 @@ static enum ich_access_protection ich9_handle_frap(struct fd_region *fd_regions,
can't rely on the actual descriptor settings either as there
are several overrides for them (those by other masters are
not even readable by us, *shrug*). */
- msg_pdbg("FREG%u: %s region (0x%08x-0x%08x) has unknown permissions.\n",
+ msg_pdbg("FREG%u: %s region (0x%08"PRIx32"-0x%08"PRIx32") has unknown permissions.\n",
i, region_name, base, limit);
return NO_PROT;
}
- msg_pinfo("FREG%u: %s region (0x%08x-0x%08x) is %s.\n", i,
+ msg_pinfo("FREG%u: %s region (0x%08"PRIx32"-0x%08"PRIx32") is %s.\n", i,
region_name, base, limit, access_names[rwperms]);
/* Save region attributes for use by ich_get_region(). */
@@ -1904,12 +1905,12 @@ static enum ich_access_protection ich9_handle_pr(const size_t reg_pr0, unsigned
i -= 5;
if (rwperms == NO_PROT) {
- msg_pdbg2("0x%02X: 0x%08x (%sPR%u is unused)\n", off, pr, prefix, i);
+ msg_pdbg2("0x%02"PRIX8": 0x%08"PRIx32" (%sPR%u is unused)\n", off, pr, prefix, i);
return NO_PROT;
}
- msg_pdbg("0x%02X: 0x%08x ", off, pr);
- msg_pwarn("%sPR%u: Warning: 0x%08x-0x%08x is %s.\n", prefix, i, ICH_FREG_BASE(pr),
+ msg_pdbg("0x%02"PRIX8": 0x%08"PRIx32" ", off, pr);
+ msg_pwarn("%sPR%u: Warning: 0x%08"PRIx32"-0x%08"PRIx32" is %s.\n", prefix, i, ICH_FREG_BASE(pr),
ICH_FREG_LIMIT(pr), access_names[rwperms]);
return rwperms;
@@ -1923,7 +1924,7 @@ static void ich9_set_pr(const size_t reg_pr0, int i, int read_prot, int write_pr
uint32_t old = mmio_readl(addr);
uint32_t new;
- msg_gspew("PR%u is 0x%08x", i, old);
+ msg_gspew("PR%u is 0x%08"PRIx32"", i, old);
new = old & ~((1 << PR_RP_OFF) | (1 << PR_WP_OFF));
if (read_prot)
new |= (1 << PR_RP_OFF);
@@ -1933,9 +1934,9 @@ static void ich9_set_pr(const size_t reg_pr0, int i, int read_prot, int write_pr
msg_gspew(" already.\n");
return;
}
- msg_gspew(", trying to set it to 0x%08x ", new);
+ msg_gspew(", trying to set it to 0x%08"PRIx32" ", new);
rmmio_writel(new, addr);
- msg_gspew("resulted in 0x%08x.\n", mmio_readl(addr));
+ msg_gspew("resulted in 0x%08"PRIx32".\n", mmio_readl(addr));
}
static const struct spi_master spi_master_ich7 = {
@@ -1978,22 +1979,22 @@ static int init_ich7_spi(void *spibar, enum ich_chipset ich_gen)
{
unsigned int i;
- msg_pdbg("0x00: 0x%04x (SPIS)\n", mmio_readw(spibar + 0));
- msg_pdbg("0x02: 0x%04x (SPIC)\n", mmio_readw(spibar + 2));
- msg_pdbg("0x04: 0x%08x (SPIA)\n", mmio_readl(spibar + 4));
+ msg_pdbg("0x00: 0x%04"PRIx16" (SPIS)\n", mmio_readw(spibar + 0));
+ msg_pdbg("0x02: 0x%04"PRIx16" (SPIC)\n", mmio_readw(spibar + 2));
+ msg_pdbg("0x04: 0x%08"PRIx32" (SPIA)\n", mmio_readl(spibar + 4));
ichspi_bbar = mmio_readl(spibar + 0x50);
- msg_pdbg("0x50: 0x%08x (BBAR)\n", ichspi_bbar);
- msg_pdbg("0x54: 0x%04x (PREOP)\n", mmio_readw(spibar + 0x54));
- msg_pdbg("0x56: 0x%04x (OPTYPE)\n", mmio_readw(spibar + 0x56));
- msg_pdbg("0x58: 0x%08x (OPMENU)\n", mmio_readl(spibar + 0x58));
- msg_pdbg("0x5c: 0x%08x (OPMENU+4)\n", mmio_readl(spibar + 0x5c));
+ msg_pdbg("0x50: 0x%08"PRIx32" (BBAR)\n", ichspi_bbar);
+ msg_pdbg("0x54: 0x%04"PRIx16" (PREOP)\n", mmio_readw(spibar + 0x54));
+ msg_pdbg("0x56: 0x%04"PRIx16" (OPTYPE)\n", mmio_readw(spibar + 0x56));
+ msg_pdbg("0x58: 0x%08"PRIx32" (OPMENU)\n", mmio_readl(spibar + 0x58));
+ msg_pdbg("0x5c: 0x%08"PRIx32" (OPMENU+4)\n", mmio_readl(spibar + 0x5c));
for (i = 0; i < 3; i++) {
int offs;
offs = 0x60 + (i * 4);
- msg_pdbg("0x%02x: 0x%08x (PBR%u)\n", offs, mmio_readl(spibar + offs), i);
+ msg_pdbg("0x%02x: 0x%08"PRIx32" (PBR%u)\n", offs, mmio_readl(spibar + offs), i);
}
if (mmio_readw(spibar) & (1 << 15)) {
msg_pwarn("WARNING: SPI Configuration Lockdown activated.\n");
@@ -2138,12 +2139,12 @@ static int init_ich_default(const struct programmer_cfg *cfg, void *spibar, enum
if (desc_valid) {
tmp2 = mmio_readw(spibar + ICH9_REG_HSFC);
- msg_pdbg("0x06: 0x%04x (HSFC)\n", tmp2);
+ msg_pdbg("0x06: 0x%04"PRIx16" (HSFC)\n", tmp2);
prettyprint_ich9_reg_hsfc(tmp2, ich_gen);
}
tmp = mmio_readl(spibar + ICH9_REG_FADDR);
- msg_pdbg2("0x08: 0x%08x (FADDR)\n", tmp);
+ msg_pdbg2("0x08: 0x%08"PRIx32" (FADDR)\n", tmp);
switch (ich_gen) {
case CHIPSET_100_SERIES_SUNRISE_POINT:
@@ -2158,7 +2159,7 @@ static int init_ich_default(const struct programmer_cfg *cfg, void *spibar, enum
case CHIPSET_JASPER_LAKE:
case CHIPSET_ELKHART_LAKE:
tmp = mmio_readl(spibar + PCH100_REG_DLOCK);
- msg_pdbg("0x0c: 0x%08x (DLOCK)\n", tmp);
+ msg_pdbg("0x0c: 0x%08"PRIx32" (DLOCK)\n", tmp);
prettyprint_pch100_reg_dlock(tmp);
break;
default:
@@ -2167,11 +2168,11 @@ static int init_ich_default(const struct programmer_cfg *cfg, void *spibar, enum
if (desc_valid) {
tmp = mmio_readl(spibar + ICH9_REG_FRAP);
- msg_pdbg("0x50: 0x%08x (FRAP)\n", tmp);
- msg_pdbg("BMWAG 0x%02x, ", ICH_BMWAG(tmp));
- msg_pdbg("BMRAG 0x%02x, ", ICH_BMRAG(tmp));
- msg_pdbg("BRWA 0x%02x, ", ICH_BRWA(tmp));
- msg_pdbg("BRRA 0x%02x\n", ICH_BRRA(tmp));
+ msg_pdbg("0x50: 0x%08"PRIx32" (FRAP)\n", tmp);
+ msg_pdbg("BMWAG 0x%02"PRIx32", ", ICH_BMWAG(tmp));
+ msg_pdbg("BMRAG 0x%02"PRIx32", ", ICH_BMRAG(tmp));
+ msg_pdbg("BRWA 0x%02"PRIx32", ", ICH_BRWA(tmp));
+ msg_pdbg("BRRA 0x%02"PRIx32"\n", ICH_BRRA(tmp));
/* Handle FREGx and FRAP registers */
for (i = 0; i < num_freg; i++)
@@ -2205,22 +2206,22 @@ static int init_ich_default(const struct programmer_cfg *cfg, void *spibar, enum
}
tmp = mmio_readl(spibar + swseq_data.reg_ssfsc);
- msg_pdbg("0x%zx: 0x%02x (SSFS)\n", swseq_data.reg_ssfsc, tmp & 0xff);
+ msg_pdbg("0x%zx: 0x%02"PRIx32" (SSFS)\n", swseq_data.reg_ssfsc, tmp & 0xff);
prettyprint_ich9_reg_ssfs(tmp);
if (tmp & SSFS_FCERR) {
msg_pdbg("Clearing SSFS.FCERR\n");
mmio_writeb(SSFS_FCERR, spibar + swseq_data.reg_ssfsc);
}
- msg_pdbg("0x%zx: 0x%06x (SSFC)\n", swseq_data.reg_ssfsc + 1, tmp >> 8);
+ msg_pdbg("0x%zx: 0x%06"PRIx32" (SSFC)\n", swseq_data.reg_ssfsc + 1, tmp >> 8);
prettyprint_ich9_reg_ssfc(tmp);
- msg_pdbg("0x%zx: 0x%04x (PREOP)\n",
+ msg_pdbg("0x%zx: 0x%04"PRIx16" (PREOP)\n",
swseq_data.reg_preop, mmio_readw(spibar + swseq_data.reg_preop));
- msg_pdbg("0x%zx: 0x%04x (OPTYPE)\n",
+ msg_pdbg("0x%zx: 0x%04"PRIx16" (OPTYPE)\n",
swseq_data.reg_optype, mmio_readw(spibar + swseq_data.reg_optype));
- msg_pdbg("0x%zx: 0x%08x (OPMENU)\n",
+ msg_pdbg("0x%zx: 0x%08"PRIx32" (OPMENU)\n",
swseq_data.reg_opmenu, mmio_readl(spibar + swseq_data.reg_opmenu));
- msg_pdbg("0x%zx: 0x%08x (OPMENU+4)\n",
+ msg_pdbg("0x%zx: 0x%08"PRIx32" (OPMENU+4)\n",
swseq_data.reg_opmenu + 4, mmio_readl(spibar + swseq_data.reg_opmenu + 4));
if (desc_valid) {
@@ -2241,24 +2242,24 @@ static int init_ich_default(const struct programmer_cfg *cfg, void *spibar, enum
break;
default:
ichspi_bbar = mmio_readl(spibar + ICH9_REG_BBAR);
- msg_pdbg("0x%x: 0x%08x (BBAR)\n", ICH9_REG_BBAR, ichspi_bbar);
+ msg_pdbg("0x%x: 0x%08"PRIx32" (BBAR)\n", ICH9_REG_BBAR, ichspi_bbar);
ich_set_bbar(0, ich_gen);
break;
}
if (ich_gen == CHIPSET_ICH8) {
tmp = mmio_readl(spibar + ICH8_REG_VSCC);
- msg_pdbg("0x%x: 0x%08x (VSCC)\n", ICH8_REG_VSCC, tmp);
+ msg_pdbg("0x%x: 0x%08"PRIx32" (VSCC)\n", ICH8_REG_VSCC, tmp);
msg_pdbg("VSCC: ");
prettyprint_ich_reg_vscc(tmp, FLASHROM_MSG_DEBUG, true);
} else {
tmp = mmio_readl(spibar + ICH9_REG_LVSCC);
- msg_pdbg("0x%x: 0x%08x (LVSCC)\n", ICH9_REG_LVSCC, tmp);
+ msg_pdbg("0x%x: 0x%08"PRIx32" (LVSCC)\n", ICH9_REG_LVSCC, tmp);
msg_pdbg("LVSCC: ");
prettyprint_ich_reg_vscc(tmp, FLASHROM_MSG_DEBUG, true);
tmp = mmio_readl(spibar + ICH9_REG_UVSCC);
- msg_pdbg("0x%x: 0x%08x (UVSCC)\n", ICH9_REG_UVSCC, tmp);
+ msg_pdbg("0x%x: 0x%08"PRIx32" (UVSCC)\n", ICH9_REG_UVSCC, tmp);
msg_pdbg("UVSCC: ");
prettyprint_ich_reg_vscc(tmp, FLASHROM_MSG_DEBUG, false);
}
@@ -2279,7 +2280,7 @@ static int init_ich_default(const struct programmer_cfg *cfg, void *spibar, enum
break;
default:
tmp = mmio_readl(spibar + ICH9_REG_FPB);
- msg_pdbg("0x%x: 0x%08x (FPB)\n", ICH9_REG_FPB, tmp);
+ msg_pdbg("0x%x: 0x%08"PRIx32" (FPB)\n", ICH9_REG_FPB, tmp);
break;
}
@@ -2398,27 +2399,27 @@ int via_init_spi(uint32_t mmio_base)
ich_generation = CHIPSET_ICH7;
register_spi_master(&spi_master_via, NULL);
- msg_pdbg("0x00: 0x%04x (SPIS)\n", mmio_readw(ich_spibar + 0));
- msg_pdbg("0x02: 0x%04x (SPIC)\n", mmio_readw(ich_spibar + 2));
- msg_pdbg("0x04: 0x%08x (SPIA)\n", mmio_readl(ich_spibar + 4));
+ msg_pdbg("0x00: 0x%04"PRIx16" (SPIS)\n", mmio_readw(ich_spibar + 0));
+ msg_pdbg("0x02: 0x%04"PRIx16" (SPIC)\n", mmio_readw(ich_spibar + 2));
+ msg_pdbg("0x04: 0x%08"PRIx32" (SPIA)\n", mmio_readl(ich_spibar + 4));
for (i = 0; i < 2; i++) {
int offs;
offs = 8 + (i * 8);
- msg_pdbg("0x%02x: 0x%08x (SPID%d)\n", offs, mmio_readl(ich_spibar + offs), i);
- msg_pdbg("0x%02x: 0x%08x (SPID%d+4)\n", offs + 4,
+ msg_pdbg("0x%02x: 0x%08"PRIx32" (SPID%d)\n", offs, mmio_readl(ich_spibar + offs), i);
+ msg_pdbg("0x%02x: 0x%08"PRIx32" (SPID%d+4)\n", offs + 4,
mmio_readl(ich_spibar + offs + 4), i);
}
ichspi_bbar = mmio_readl(ich_spibar + 0x50);
- msg_pdbg("0x50: 0x%08x (BBAR)\n", ichspi_bbar);
- msg_pdbg("0x54: 0x%04x (PREOP)\n", mmio_readw(ich_spibar + 0x54));
- msg_pdbg("0x56: 0x%04x (OPTYPE)\n", mmio_readw(ich_spibar + 0x56));
- msg_pdbg("0x58: 0x%08x (OPMENU)\n", mmio_readl(ich_spibar + 0x58));
- msg_pdbg("0x5c: 0x%08x (OPMENU+4)\n", mmio_readl(ich_spibar + 0x5c));
+ msg_pdbg("0x50: 0x%08"PRIx32" (BBAR)\n", ichspi_bbar);
+ msg_pdbg("0x54: 0x%04"PRIx16" (PREOP)\n", mmio_readw(ich_spibar + 0x54));
+ msg_pdbg("0x56: 0x%04"PRIx16" (OPTYPE)\n", mmio_readw(ich_spibar + 0x56));
+ msg_pdbg("0x58: 0x%08"PRIx32" (OPMENU)\n", mmio_readl(ich_spibar + 0x58));
+ msg_pdbg("0x5c: 0x%08"PRIx32" (OPMENU+4)\n", mmio_readl(ich_spibar + 0x5c));
for (i = 0; i < 3; i++) {
int offs;
offs = 0x60 + (i * 4);
- msg_pdbg("0x%02x: 0x%08x (PBR%d)\n", offs, mmio_readl(ich_spibar + offs), i);
+ msg_pdbg("0x%02x: 0x%08"PRIx32" (PBR%d)\n", offs, mmio_readl(ich_spibar + offs), i);
}
msg_pdbg("0x6c: 0x%04x (CLOCK/DEBUG)\n", mmio_readw(ich_spibar + 0x6c));
if (mmio_readw(ich_spibar) & (1 << 15)) {
diff --git a/jedec.c b/jedec.c
index db2e3e86..2d18de7f 100644
--- a/jedec.c
+++ b/jedec.c
@@ -141,7 +141,7 @@ int probe_jedec_29gl(struct flashctx *flash)
/* Issue JEDEC Product ID Exit command */
chip_writeb(flash, 0xF0, bios + (0x5555 & mask));
- msg_cdbg("%s: man_id 0x%02x, dev_id 0x%06x", __func__, man_id, dev_id);
+ msg_cdbg("%s: man_id 0x%02"PRIx32", dev_id 0x%06"PRIx32"", __func__, man_id, dev_id);
if (!oddparity(man_id))
msg_cdbg(", man_id parity violation");
@@ -252,7 +252,7 @@ int probe_jedec(struct flashctx *flash)
chip_writeb(flash, 0xF0, bios + ((shifted ? 0x2AAA : 0x5555) & mask));
programmer_delay(flash, probe_timing_exit);
- msg_cdbg("%s: id1 0x%02x, id2 0x%02x", __func__, largeid1, largeid2);
+ msg_cdbg("%s: id1 0x%02"PRIx32", id2 0x%02"PRIx32"", __func__, largeid1, largeid2);
if (!oddparity(id1))
msg_cdbg(", id1 parity violation");
diff --git a/layout.c b/layout.c
index 2d7747e7..cddd9087 100644
--- a/layout.c
+++ b/layout.c
@@ -301,7 +301,7 @@ int included_regions_overlap(const struct flashrom_layout *const l)
if (lhsr->end < rhsr->start)
continue;
- msg_gwarn("Regions %s [0x%08x-0x%08x] and %s [0x%08x-0x%08x] overlap\n",
+ msg_gwarn("Regions %s [0x%08"PRIx32"-0x%08"PRIx32"] and %s [0x%08"PRIx32"-0x%08"PRIx32"] overlap\n",
lhsr->name, lhsr->start, lhsr->end, rhsr->name, rhsr->start, rhsr->end);
overlap_detected = 1;
}
diff --git a/mcp6x_spi.c b/mcp6x_spi.c
index 78699251..165bca50 100644
--- a/mcp6x_spi.c
+++ b/mcp6x_spi.c
@@ -146,7 +146,7 @@ int mcp6x_spi_init(int want_spi)
* 32-bit non-prefetchable memory BAR.
*/
mcp6x_spibaraddr &= ~0xffff;
- msg_pdbg("MCP SPI BAR is at 0x%08x\n", mcp6x_spibaraddr);
+ msg_pdbg("MCP SPI BAR is at 0x%08"PRIx32"\n", mcp6x_spibaraddr);
/* Accessing a NULL pointer BAR is evil. Don't do it. */
if (!mcp6x_spibaraddr && want_spi) {
diff --git a/nicintel_eeprom.c b/nicintel_eeprom.c
index 2c351da3..6a734b05 100644
--- a/nicintel_eeprom.c
+++ b/nicintel_eeprom.c
@@ -140,7 +140,7 @@ static int nicintel_ee_probe_82580(struct flashctx *flash)
flash->chip->total_size = 32;
break;
default:
- msg_cerr("Unsupported chip size 0x%x\n", tmp);
+ msg_cerr("Unsupported chip size 0x%"PRIx32"\n", tmp);
return 0;
}
}
diff --git a/s25f.c b/s25f.c
index 549883b9..dd15efcd 100644
--- a/s25f.c
+++ b/s25f.c
@@ -184,7 +184,7 @@ static int s25fs_read_cr(const struct flashctx *flash, uint32_t addr)
int result = spi_send_command(flash, sizeof(read_cr_cmd), 1, read_cr_cmd, &cfg);
if (result) {
- msg_cerr("%s failed during command execution at address 0x%x\n",
+ msg_cerr("%s failed during command execution at address 0x%"PRIx32"\n",
__func__, addr);
return -1;
}
@@ -222,7 +222,7 @@ static int s25fs_write_cr(const struct flashctx *flash,
int result = spi_send_multicommand(flash, cmds);
if (result) {
- msg_cerr("%s failed during command execution at address 0x%x\n",
+ msg_cerr("%s failed during command execution at address 0x%"PRIx32"\n",
__func__, addr);
return -1;
}
diff --git a/satamv.c b/satamv.c
index fea4c2ba..1b8640a8 100644
--- a/satamv.c
+++ b/satamv.c
@@ -134,38 +134,38 @@ static int satamv_init(const struct programmer_cfg *cfg)
tmp = pci_mmio_readl(bar + FLASH_PARAM);
msg_pspew("Flash Parameters:\n");
- msg_pspew("TurnOff=0x%01x\n", (tmp >> 0) & 0x7);
- msg_pspew("Acc2First=0x%01x\n", (tmp >> 3) & 0xf);
- msg_pspew("Acc2Next=0x%01x\n", (tmp >> 7) & 0xf);
- msg_pspew("ALE2Wr=0x%01x\n", (tmp >> 11) & 0x7);
- msg_pspew("WrLow=0x%01x\n", (tmp >> 14) & 0x7);
- msg_pspew("WrHigh=0x%01x\n", (tmp >> 17) & 0x7);
- msg_pspew("Reserved[21:20]=0x%01x\n", (tmp >> 20) & 0x3);
- msg_pspew("TurnOffExt=0x%01x\n", (tmp >> 22) & 0x1);
- msg_pspew("Acc2FirstExt=0x%01x\n", (tmp >> 23) & 0x1);
- msg_pspew("Acc2NextExt=0x%01x\n", (tmp >> 24) & 0x1);
- msg_pspew("ALE2WrExt=0x%01x\n", (tmp >> 25) & 0x1);
- msg_pspew("WrLowExt=0x%01x\n", (tmp >> 26) & 0x1);
- msg_pspew("WrHighExt=0x%01x\n", (tmp >> 27) & 0x1);
- msg_pspew("Reserved[31:28]=0x%01x\n", (tmp >> 28) & 0xf);
+ msg_pspew("TurnOff=0x%01"PRIx32"\n", (tmp >> 0) & 0x7);
+ msg_pspew("Acc2First=0x%01"PRIx32"\n", (tmp >> 3) & 0xf);
+ msg_pspew("Acc2Next=0x%01"PRIx32"\n", (tmp >> 7) & 0xf);
+ msg_pspew("ALE2Wr=0x%01"PRIx32"\n", (tmp >> 11) & 0x7);
+ msg_pspew("WrLow=0x%01"PRIx32"\n", (tmp >> 14) & 0x7);
+ msg_pspew("WrHigh=0x%01"PRIx32"\n", (tmp >> 17) & 0x7);
+ msg_pspew("Reserved[21:20]=0x%01"PRIx32"\n", (tmp >> 20) & 0x3);
+ msg_pspew("TurnOffExt=0x%01"PRIx32"\n", (tmp >> 22) & 0x1);
+ msg_pspew("Acc2FirstExt=0x%01"PRIx32"\n", (tmp >> 23) & 0x1);
+ msg_pspew("Acc2NextExt=0x%01"PRIx32"\n", (tmp >> 24) & 0x1);
+ msg_pspew("ALE2WrExt=0x%01"PRIx32"\n", (tmp >> 25) & 0x1);
+ msg_pspew("WrLowExt=0x%01"PRIx32"\n", (tmp >> 26) & 0x1);
+ msg_pspew("WrHighExt=0x%01"PRIx32"\n", (tmp >> 27) & 0x1);
+ msg_pspew("Reserved[31:28]=0x%01"PRIx32"\n", (tmp >> 28) & 0xf);
tmp = pci_mmio_readl(bar + EXPANSION_ROM_BAR_CONTROL);
msg_pspew("Expansion ROM BAR Control:\n");
- msg_pspew("ExpROMSz=0x%01x\n", (tmp >> 19) & 0x7);
+ msg_pspew("ExpROMSz=0x%01"PRIx32"\n", (tmp >> 19) & 0x7);
/* Enable BAR2 mapping to flash */
tmp = pci_mmio_readl(bar + PCI_BAR2_CONTROL);
msg_pspew("PCI BAR2 (Flash/NVRAM) Control:\n");
- msg_pspew("Bar2En=0x%01x\n", (tmp >> 0) & 0x1);
- msg_pspew("BAR2TransAttr=0x%01x\n", (tmp >> 1) & 0x1f);
- msg_pspew("BAR2Sz=0x%01x\n", (tmp >> 19) & 0x7);
+ msg_pspew("Bar2En=0x%01"PRIx32"\n", (tmp >> 0) & 0x1);
+ msg_pspew("BAR2TransAttr=0x%01"PRIx32"\n", (tmp >> 1) & 0x1f);
+ msg_pspew("BAR2Sz=0x%01"PRIx32"\n", (tmp >> 19) & 0x7);
tmp &= 0xffffffc0;
tmp |= 0x0000001f;
pci_rmmio_writel(tmp, bar + PCI_BAR2_CONTROL);
/* Enable flash: GPIO Port Control Register 0x104f0 */
tmp = pci_mmio_readl(bar + GPIO_PORT_CONTROL);
- msg_pspew("GPIOPortMode=0x%01x\n", (tmp >> 0) & 0x3);
+ msg_pspew("GPIOPortMode=0x%01"PRIx32"\n", (tmp >> 0) & 0x3);
if (((tmp >> 0) & 0x3) != 0x2)
msg_pinfo("Warning! Either the straps are incorrect or you "
"have no flash or someone overwrote the strap "
diff --git a/satasii.c b/satasii.c
index e881f966..ad872bfc 100644
--- a/satasii.c
+++ b/satasii.c
@@ -46,7 +46,7 @@ static uint32_t satasii_wait_done(const uint8_t *bar)
int i = 0;
while ((ctrl_reg = pci_mmio_readl(bar)) & (1 << 25)) {
if (++i > 10000) {
- msg_perr("%s: control register stuck at %08x, ignoring.\n",
+ msg_perr("%s: control register stuck at %08"PRIx32", ignoring.\n",
__func__, pci_mmio_readl(bar));
break;
}
diff --git a/sb600spi.c b/sb600spi.c
index df7caedb..cec7e0a5 100644
--- a/sb600spi.c
+++ b/sb600spi.c
@@ -638,7 +638,7 @@ int sb600_probe_spi(const struct programmer_cfg *cfg, struct pci_dev *dev)
/* Read SPI_BaseAddr */
tmp = pci_read_long(dev, 0xa0);
tmp &= 0xffffffe0; /* remove bits 4-0 (reserved) */
- msg_pdbg("SPI base address is at 0x%x\n", tmp);
+ msg_pdbg("SPI base address is at 0x%"PRIx32"\n", tmp);
/* If the BAR has address 0, it is unlikely SPI is used. */
if (!tmp)
@@ -676,14 +676,14 @@ int sb600_probe_spi(const struct programmer_cfg *cfg, struct pci_dev *dev)
*/
if (amd_gen >= CHIPSET_SB7XX) {
tmp = pci_read_long(dev, 0xa0);
- msg_pdbg("SpiRomEnable=%i", (tmp >> 1) & 0x1);
+ msg_pdbg("SpiRomEnable=%"PRIi32"", (tmp >> 1) & 0x1);
if (amd_gen == CHIPSET_SB7XX)
- msg_pdbg(", AltSpiCSEnable=%i, AbortEnable=%i", tmp & 0x1, (tmp >> 2) & 0x1);
+ msg_pdbg(", AltSpiCSEnable=%"PRIi32", AbortEnable=%"PRIi32"", tmp & 0x1, (tmp >> 2) & 0x1);
else if (amd_gen >= CHIPSET_YANGTZE)
- msg_pdbg(", RouteTpm2Sp=%i", (tmp >> 3) & 0x1);
+ msg_pdbg(", RouteTpm2Sp=%"PRIi32"", (tmp >> 3) & 0x1);
tmp = pci_read_byte(dev, 0xba);
- msg_pdbg(", PrefetchEnSPIFromIMC=%i", (tmp & 0x4) >> 2);
+ msg_pdbg(", PrefetchEnSPIFromIMC=%"PRIi32"", (tmp & 0x4) >> 2);
tmp = pci_read_byte(dev, 0xbb);
/* FIXME: Set bit 3,6,7 if not already set.
@@ -691,8 +691,8 @@ int sb600_probe_spi(const struct programmer_cfg *cfg, struct pci_dev *dev)
* See doc 42413 AMD SB700/710/750 RPR.
*/
if (amd_gen == CHIPSET_SB7XX)
- msg_pdbg(", SpiOpEnInLpcMode=%i", (tmp >> 5) & 0x1);
- msg_pdbg(", PrefetchEnSPIFromHost=%i\n", tmp & 0x1);
+ msg_pdbg(", SpiOpEnInLpcMode=%"PRIi32"", (tmp >> 5) & 0x1);
+ msg_pdbg(", PrefetchEnSPIFromHost=%"PRIi32"\n", tmp & 0x1);
}
/* Chipset support matrix for SPI_Cntrl0 (spibar + 0x0)
@@ -714,25 +714,25 @@ int sb600_probe_spi(const struct programmer_cfg *cfg, struct pci_dev *dev)
* <1> see handle_speed
*/
tmp = mmio_readl(sb600_spibar + 0x00);
- msg_pdbg("(0x%08" PRIx32 ") SpiArbEnable=%i", tmp, (tmp >> 19) & 0x1);
+ msg_pdbg("(0x%08" PRIx32 ") SpiArbEnable=%"PRIi32"", tmp, (tmp >> 19) & 0x1);
if (amd_gen >= CHIPSET_YANGTZE)
- msg_pdbg(", IllegalAccess=%i", (tmp >> 21) & 0x1);
+ msg_pdbg(", IllegalAccess=%"PRIi32"", (tmp >> 21) & 0x1);
- msg_pdbg(", SpiAccessMacRomEn=%i, SpiHostAccessRomEn=%i, ArbWaitCount=%i",
+ msg_pdbg(", SpiAccessMacRomEn=%"PRIi32", SpiHostAccessRomEn=%"PRIi32", ArbWaitCount=%"PRIi32"",
(tmp >> 22) & 0x1, (tmp >> 23) & 0x1, (tmp >> 24) & 0x7);
if (amd_gen < CHIPSET_YANGTZE)
- msg_pdbg(", SpiBridgeDisable=%i", (tmp >> 27) & 0x1);
+ msg_pdbg(", SpiBridgeDisable=%"PRIi32"", (tmp >> 27) & 0x1);
switch (amd_gen) {
case CHIPSET_SB7XX:
- msg_pdbg(", DropOneClkOnRd/SpiClkGate=%i", (tmp >> 28) & 0x1);
+ msg_pdbg(", DropOneClkOnRd/SpiClkGate=%"PRIi32"", (tmp >> 28) & 0x1);
/* Fall through. */
case CHIPSET_SB89XX:
case CHIPSET_HUDSON234:
case CHIPSET_YANGTZE:
case CHIPSET_PROMONTORY:
- msg_pdbg(", SpiBusy=%i", (tmp >> 31) & 0x1);
+ msg_pdbg(", SpiBusy=%"PRIi32"", (tmp >> 31) & 0x1);
default: break;
}
msg_pdbg("\n");
@@ -744,7 +744,7 @@ int sb600_probe_spi(const struct programmer_cfg *cfg, struct pci_dev *dev)
if (amd_gen >= CHIPSET_SB89XX) {
tmp = mmio_readb(sb600_spibar + 0x1D);
- msg_pdbg("Using SPI_CS%d\n", tmp & 0x3);
+ msg_pdbg("Using SPI_CS%"PRId32"\n", tmp & 0x3);
/* FIXME: Handle SpiProtect* configuration on Yangtze. */
}
diff --git a/sfdp.c b/sfdp.c
index 5eddb211..86837793 100644
--- a/sfdp.c
+++ b/sfdp.c
@@ -35,7 +35,7 @@ static int spi_sfdp_read_sfdp_chunk(struct flashctx *flash, uint32_t address, ui
*/
0
};
- msg_cspew("%s: addr=0x%x, len=%d, data:\n", __func__, address, len);
+ msg_cspew("%s: addr=0x%"PRIx32", len=%d, data:\n", __func__, address, len);
newbuf = malloc(len + 1);
if (!newbuf)
return SPI_PROGRAMMER_ERROR;
@@ -96,7 +96,7 @@ static int sfdp_add_uniform_eraser(struct flashchip *chip, uint8_t opcode, uint3
if (eraser->eraseblocks[0].size == block_size &&
eraser->block_erase == erasefn) {
msg_cdbg2(" Tried to add a duplicate block eraser: "
- "%d x %d B with opcode 0x%02x.\n",
+ "%"PRId32" x %"PRId32" B with opcode 0x%02x.\n",
total_size/block_size, block_size, opcode);
return 1;
}
@@ -110,7 +110,7 @@ static int sfdp_add_uniform_eraser(struct flashchip *chip, uint8_t opcode, uint3
eraser->block_erase = erasefn;
eraser->eraseblocks[0].size = block_size;
eraser->eraseblocks[0].count = total_size/block_size;
- msg_cdbg2(" Block eraser %d: %d x %d B with opcode "
+ msg_cdbg2(" Block eraser %d: %"PRId32" x %"PRId32" B with opcode "
"0x%02x\n", i, total_size/block_size, block_size,
opcode);
return 0;
@@ -274,7 +274,7 @@ int probe_spi_sfdp(struct flashctx *flash)
tmp32 |= ((unsigned int)buf[3]) << 24;
if (tmp32 != 0x50444653) {
- msg_cdbg2("Signature = 0x%08x (should be 0x50444653)\n", tmp32);
+ msg_cdbg2("Signature = 0x%08"PRIx32" (should be 0x50444653)\n", tmp32);
msg_cdbg("No SFDP signature found.\n");
return 0;
}
@@ -320,7 +320,7 @@ int probe_spi_sfdp(struct flashctx *flash)
hdrs[i].v_major, hdrs[i].v_minor);
len = hdrs[i].len * 4;
tmp32 = hdrs[i].ptp;
- msg_cdbg2(" Length %d B, Parameter Table Pointer 0x%06x\n",
+ msg_cdbg2(" Length %d B, Parameter Table Pointer 0x%06"PRIx32"\n",
len, tmp32);
if (tmp32 + len >= (1 << 24)) {
@@ -345,7 +345,7 @@ int probe_spi_sfdp(struct flashctx *flash)
msg_cspew(" Parameter table contents:\n");
for (tmp32 = 0; tmp32 < len; tmp32++) {
if ((tmp32 % 8) == 0) {
- msg_cspew(" 0x%04x: ", tmp32);
+ msg_cspew(" 0x%04"PRIx32": ", tmp32);
}
msg_cspew(" %02x", tbuf[tmp32]);
if ((tmp32 % 8) == 7) {
diff --git a/spi25.c b/spi25.c
index f54e4c8d..6a6ee75d 100644
--- a/spi25.c
+++ b/spi25.c
@@ -141,7 +141,7 @@ static int compare_id(const struct flashctx *flash, uint32_t id1, uint32_t id2)
{
const struct flashchip *chip = flash->chip;
- msg_cdbg("%s: id1 0x%02x, id2 0x%02x\n", __func__, id1, id2);
+ msg_cdbg("%s: id1 0x%02"PRIx32", id2 0x%02"PRIx32"\n", __func__, id1, id2);
if (id1 == chip->manufacture_id && id2 == chip->model_id)
return 1;
@@ -232,7 +232,7 @@ int probe_spi_res1(struct flashctx *flash)
id2 = readarr[0];
- msg_cdbg("%s: id 0x%x\n", __func__, id2);
+ msg_cdbg("%s: id 0x%"PRIx32"\n", __func__, id2);
if (id2 != flash->chip->model_id)
return 0;
@@ -252,7 +252,7 @@ int probe_spi_res2(struct flashctx *flash)
id1 = id_cache[RES2].bytes[0];
id2 = id_cache[RES2].bytes[1];
- msg_cdbg("%s: id1 0x%x, id2 0x%x\n", __func__, id1, id2);
+ msg_cdbg("%s: id1 0x%"PRIx32", id2 0x%"PRIx32"\n", __func__, id1, id2);
if (id1 != flash->chip->manufacture_id || id2 != flash->chip->model_id)
return 0;
@@ -272,7 +272,7 @@ int probe_spi_res3(struct flashctx *flash)
id1 = (id_cache[RES3].bytes[0] << 8) | id_cache[RES3].bytes[1];
id2 = id_cache[RES3].bytes[3];
- msg_cdbg("%s: id1 0x%x, id2 0x%x\n", __func__, id1, id2);
+ msg_cdbg("%s: id1 0x%"PRIx32", id2 0x%"PRIx32"\n", __func__, id1, id2);
if (id1 != flash->chip->manufacture_id || id2 != flash->chip->model_id)
return 0;
@@ -294,7 +294,7 @@ int probe_spi_at25f(struct flashctx *flash)
id1 = readarr[0];
id2 = readarr[1];
- msg_cdbg("%s: id1 0x%02x, id2 0x%02x\n", __func__, id1, id2);
+ msg_cdbg("%s: id1 0x%02"PRIx32", id2 0x%02"PRIx32"\n", __func__, id1, id2);
if (id1 == flash->chip->manufacture_id && id2 == flash->chip->model_id)
return 1;
diff --git a/spi95.c b/spi95.c
index 976f99a1..d1f0ba13 100644
--- a/spi95.c
+++ b/spi95.c
@@ -46,7 +46,7 @@ int probe_spi_st95(struct flashctx *flash)
id1 = readarr[0]; // manufacture id
id2 = (readarr[1] << 8) | readarr[2]; // SPI family code + model id
- msg_cdbg("%s: id1 0x%02x, id2 0x%02x\n", __func__, id1, id2);
+ msg_cdbg("%s: id1 0x%02"PRIx32", id2 0x%02"PRIx32"\n", __func__, id1, id2);
if (id1 == flash->chip->manufacture_id && id2 == flash->chip->model_id)
return 1;
--
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