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* flashrom_tester: Move all subprocess stderr logging to dispatchEvan Benn2022-08-031-62/+34
| | | | | | | | | | | | | | | Instead of printing stderr in each function separately, print all stderr in the dispatch function. BUG=None BRANCH=None TEST=/usr/bin/flashrom_tester --debug host Lock_top_quad Change-Id: Id76f83c8c089537aa44aa13533c75900eb6ed175 Signed-off-by: Evan Benn <evanbenn@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/65279 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashrom_tester: Parse fmap header as little endianEvan Benn2022-08-021-1/+1
| | | | | | | | | | | | | The fmap header was incorrectly parsed as big endian. BUG=b:240097529 BRANCH=None TEST=/usr/bin/flashrom_tester --debug :lib: host Coreboot_ELOG_sanity Change-Id: Ia683ce7a6ce3bc009218c300abb9c3a16ea06a6d Reviewed-on: https://review.coreboot.org/c/flashrom/+/66119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* flashrom_tester: update to built-0.5George Burgess IV2022-08-021-2/+2
| | | | | | | | | | | | | | | | | built-0.3 depends on git2-0.9, which is our only user of url-1, which is our only user of idna-0.1, which depends on rustc-serialize, which suffers from RUSTSEC-2022-0004. That's a mouthful :) BUG=b:239449434 TEST=CQ BRANCH=none Change-Id: I0d39b417fd2291838e85f91a2af1c8a4fe28a6c2 Signed-off-by: George Burgess IV <gbiv@google.com> Signed-off-by: Evan Benn <evanbenn@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66140 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* flashrom_tester: Add write_file_with_layout positive testEvan Benn2022-07-212-2/+26
| | | | | | | | | | | | | | | | | | write_file_with_layout test was checking that writing to a region was failing, and assuming that was because write protect is working as expected. Other failures are possible, so check that a write to a non write protected region can succeed. BUG=b:235916336 BRANCH=None TEST=/usr/bin/flashrom_tester --debug host Lock_top_quad Change-Id: I2b220f323e259f5c7bfae06f6cf996b22e264555 Signed-off-by: Evan Benn <evanbenn@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/65278 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Peter Marheine <pmarheine@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashrom_tester: Refactor Error typeEvan Benn2022-07-213-21/+46
| | | | | | | | | | | | | | | | | Use a type implementing Error instead of a string for errors. Error implements Display so can be easily converted to a String. This will allow libflashrom to be more easily integrated. BUG=b:230545739 BRANCH=None TEST=cargo test Change-Id: Id166053c7edfd07576e7823692cfa0ea4d438948 Signed-off-by: Evan Benn <evanbenn@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/65277 Reviewed-by: Peter Marheine <pmarheine@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* flashrom_tester: Remove subprocess from elog_sanity_testEvan Benn2022-07-214-33/+43
| | | | | | | | | | | | | | | | | Make elog_sanity_test read the elog region itself, instead of calling out to elogtool. This avoids the need to subprocess and resolves a deadlock when elogtool attempts to obtain a flash reading lock. TEST=/usr/bin/flashrom_tester host Coreboot_ELOG_sanity TEST=flashrom --image RW_ELOG -p host -r /tmp/file.tmp2 # comparison TEST=hexdump the file and check magic signature == 0x474f4c45 Change-Id: I8ac63e15e063f9c0928e3e185154bb083b367ba9 Signed-off-by: Evan Benn <evanbenn@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/65119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Peter Marheine <pmarheine@chromium.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* flashrom_tester: Use Flashrom trait instead of struct FlashromCmdEvan Benn2022-07-215-319/+356
| | | | | | | | | | | | | | To allow FlashromCmd to be reimplemented with libflashrom move all concrete cmd functions into the FlashromCmd type that implements the Flashrom trait. This allows users to be generalised upon the Flashrom trait as the contract rather than the concrete FlashromCmd type. Change-Id: Ie2b4e7e91d69043fd50d1c57f6585fc9946fab10 Signed-off-by: Evan Benn <evanbenn@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/64849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Peter Marheine <pmarheine@chromium.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* ft2232_spi.c: Add support for kt-link jtag interfaceJacek Naglak2022-07-181-0/+4
| | | | | | | | | | | | | | | | | | | | Change tested writing, reading and erasing spi flashes pinout: jtag - spi 1 vcc - vcc, wp#, hold# 4 gnd - gnd 5 tdi - si 7 tms - cs# 9 tck - sck 13 tdo - so Connect pins 9 and 12 in EXT connector for 3.3V power. Signed-off-by: Jacek Naglak <jnaglak@tlen.pl> Change-Id: Id58c675bc410ec3ef6d58603d13efc9ca53bb87c Reviewed-on: https://review.coreboot.org/c/flashrom/+/64440 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/shell.nix: Add libjaylinkFelix Singer2022-05-191-1/+1
| | | | | | | | | | | | libjaylink is packaged since NixOS 21.11 and it is out for many months now. Thus, include the package libjaylink and remove comments. Signed-off-by: Felix Singer <felixsinger@posteo.net> Change-Id: I56e750831143a4e34be95ec111a37bb476abfe85 Reviewed-on: https://review.coreboot.org/c/flashrom/+/64352 Reviewed-by: Thomas Heijligen <src@posteo.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/ich_descriptors_tool: Remove unneeded meson dependenciesThomas Heijligen2022-05-121-3/+0
| | | | | | | | | Change-Id: Ice1437cb294729b6af0e24f0a02692459b7a1412 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/63757 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* util/flashrom_tester: Update sys-info crate to version 0.9Angel Pons2022-05-121-1/+1
| | | | | | | | | | | | | | | | | | | | | An issue was discovered in the sys-info crate before 0.8.0 for Rust. sys_info::disk_info calls can trigger a double free. To prevent any potential problems, update this crate to version 0.9 (as of writing, sys-info version 0.9.1 is the latest). Refer to CVE-2020-36434 for more details about the sys-info crate bug. TEST=Run `cargo build` in `util/flashrom_tester`, it still works fine. Change-Id: I3b6b21e830ff3107860f7bcbfe2d58b29efe0c12 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/63975 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Peter Marheine <pmarheine@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Global cleanup: Fix a few spelling errorsMartin Roth2022-05-032-3/+3
| | | | | | | | | | | | | | | | Just a trivial patch to fix a few errors found by codespell. Here's the command I used: codespell -S subprojects,out \ -L fwe,dout,tast,crate,parms,claus,nt,nd,te,truns,trun Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I4e3b277f220fa70dcab21912c30f1d26d9bd8749 Reviewed-on: https://review.coreboot.org/c/flashrom/+/62840 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ich_descriptors_tool: Fix -Wsign-compare warningsAnastasia Klimchuk2022-04-291-4/+4
| | | | | | | | | | | | | | | | | | | | | | | This patch is fixing -Wsign-compare warnings, specifically: warning: comparison of integer expressions of different signedness: ‘int’ and ‘uint32_t’ {aka ‘unsigned int’} [-Wsign-compare] Both instances in this patch produce the same warning. The patch is needed to sync compiler warning options between meson and makefile. TEST=running the following gives no warnings: meson setup --wipe (to clean build directory) ninja test Change-Id: I1f9325e9cf89f57f18d63cc3906a0958b47286d7 Signed-off-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/63488 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* Introduce an `include` directory for header filesThomas Heijligen2022-04-292-1/+2
| | | | | | | | | | | | Move all header files to the new `include` directory. Adapt include directives and build systems to the new directory. Change-Id: Iaddd6bbfa0624b166d422f665877f096983bf4cf Signed-off-by: Felix Singer <felix.singer@secunet.com> Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/58622 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* ichspi: Add Jasper Lake supportEdward O'Callaghan2022-04-141-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Additionally, utilize CSSO (CPU Soft Strap Offset) to uniquely detect the chipset when the CSSL (CPU Soft Strap Length) field default value (0x03) on Jasper Lake is the same as Elkhart Lake. BUG=b:221175960 TEST=dedede with `flashrom -p internal --flash-size`. ``` $ flashrom -VVV -p internal --ifd -i fd -i bios -r /tmp/filename.rom <snip> Enabling hardware sequencing by default for 100+ series PCH. OK. No board enable found matching coreboot IDs vendor="Google", model="Magolor". The following protocols are supported: Programmer-specific. Probing for Programmer Opaque flash chip, 0 kB: Chip identified: GD25Q127C/GD25Q128C Hardware sequencing reports 1 attached SPI flash chip with a density of 16384 kB. There is only one partition containing the whole address space (0x000000 - 0xffffff). There are 4096 erase blocks with 4096 B each. Added layout entry 00000000 - 00ffffff named complete flash Found GigaDevice flash chip "GD25Q127C/GD25Q128C" (16384 kB, Programmer-specific) mapped at physical address 0x0000000000000000. Found GigaDevice flash chip "GD25Q127C/GD25Q128C" (16384 kB, Programmer-specific). This chip may contain one-time programmable memory. flashrom cannot read and may never be able to write it, hence it may not be able to completely clone the contents of this chip (see man page for details). Reading Status register Block protection is disabled. Reading ich descriptor... Reading 4096 bytes starting at 0x000000. done. Assuming chipset 'Jasper Lake'. Added layout entry 00000000 - 00000fff named fd Added layout entry 00381000 - 00ffffff named bios Added layout entry 00001000 - 00380fff named me restore_power_management: Re-enabling power management. Using regions: "bios", "fd". Reading Status register Block protection is disabled. Reading flash... 0x381000-0xffffff:R Reading 13103104 bytes starting at 0x381000. 000000-0x0fff:R Reading 4096 bytes starting at 0x000000. done. restore_power_management: Re-enabling power management. SUCCESS Restoring PCI config space for 00:1f:5 reg 0xdc restore_power_management: Re-enabling power management. ``` Change-Id: Ib942d0b8942fe0a991b2af0b187414818485153d Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/62282 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sam McNally <sammc@google.com>
* ichspi: Add support for Meteor LakeSubrata Banik2022-03-301-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds Meteor Lake support into flashrom. Additionally, utilize CSSO (CPU Soft Strap Offset) to uniquely detect the chipset when the CSSL (CPU Soft Strap Length) field default value (0x03) on Meteor Lake is the same as Elkhart Lake. BUG=b:224325352 TEST=Flashrom is able to detect MTL SPI DID and show chipset name as below: > flashrom --flash-name .... Found chipset "Intel Meteor Lake-P/M". .... > flashrom - internal --ifd -i fd -i bios -r /tmp/bios.rom .... Reading ich_descriptor... done. Assuming chipset 'Meteor Lake'. Using regions: "bios", "fd". Reading flash... done. SUCCESS Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I0a2ffe2ba8d96c90d89b77e0d8583d179ff02a75 Reviewed-on: https://review.coreboot.org/c/flashrom/+/62783 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Sam McNally <sammc@google.com>
* ichspi: Add Alder Lake supportEdward O'Callaghan2022-03-071-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Does exactly what it says on the tin. BUG=b:220799648 TEST=```localhost ~ # flashrom --flash-name <snip> Found Programmer flash chip "Opaque flash chip" (32768 kB, Programmer-specific) mapped at physical address 0x0000000000000000. vendor="Programmer" name="Opaque flash chip" flashrom -p internal --ifd -i fd -i bios -r /tmp/filename.rom flashrom unknown on Linux 5.15.22 (x86_64) flashrom is free software, get the source code at https://flashrom.org Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns). coreboot table found at 0x768a7000. Found chipset "Intel Alder Lake-N". Enabling flash write... Warning: Setting BIOS Control at 0xdc from 0x8b to 0x89 failed. New value is 0x8b. SPI Configuration is locked down. OK. Found Winbond flash chip "W25Q256JV_M" (32768 kB, Programmer-specific) mapped at physical address 0x0000000000000000. Error accessing W25Q256JV_M, 0x2000000 bytes at 0x00000000fe000000 /dev/mem mmap failed: Resource temporarily unavailable Could not map flash chip W25Q256JV_M at 0x00000000fe000000. Reading ich descriptor... done. Using regions: "bios", "fd". Error accessing W25Q256JV_M, 0x2000000 bytes at 0x00000000fe000000 /dev/mem mmap failed: Resource temporarily unavailable Could not map flash chip W25Q256JV_M at 0x00000000fe000000. Reading flash... done. SUCCESS Also, Reading ich descriptor... Reading 4096 bytes starting at 0x000000. done. Assuming chipset '600 series Alder Point'. Added layout entry 00000000 - 00000fff named fd Added layout entry 00500000 - 01ffffff named bios Added layout entry 00001000 - 004fffff named me ``` Tested on Nivviks/ADL-N and Brya/ADL-P. Change-Id: Ie66cf519df13f3391c41f5016b16a81ef3dfd4bf Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/62251 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sam McNally <sammc@google.com>
* Add Elkhart Lake supportWerner Zeh2022-02-041-0/+2
| | | | | | | | | | | | | | | | Elkhart Lake has a chipset called Mule Creek Canyon which is quite compatible with 300 series chipsets. There are a few differences though, e.g. different encoding for the SPI clock values for read and write in the FLCOMP register. In addition Elkhart Lake has a new PCI device ID for the SPI controller which is added, too. TEST=Read and flash complete flash on Siemens MC EHL1 Change-Id: I711e39a3ec9cd7098389231eaa1cb864d615a475 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/60711 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* Add Tiger Lake U Premium supportMichał Żygowski2021-11-171-0/+4
| | | | | | | | | | | | | | | | | | | | | | Tiger Lake has very low ICCRIBA (TGL=0x11, CNL=0x34 and CML=0x34) and detects as unknown chipset compatible with 300 series chipset. Add a new enum CHIPSET_500_SERIES_TIGER_POINT and treat it identically to CHIPSET_400_SERIES_COMET_POINT. There are some exceptions though, ICCRIBA is no longer present n descriptor content so a new union has been defined for new fields and used in descriptor guessing. freq_read field is not present on Tiger Lake, moreover in CannonPoint and Comet Point this field is used as eSPI/EC frequency, so a new function to print read frequency has ben added. Finally Tiger lake boot straps include eSPI, so a new bus has been added for the new straps. TEST=Flash BIOS region on Intel i5-1135G7 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I28f3b6fe9f8ce9e976a6808683f46b6f4ec72bdd Reviewed-on: https://review.coreboot.org/c/flashrom/+/55578 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashrom_tester: Use elogtool to list firmware eventlogJack Rosenthal2021-10-272-7/+7
| | | | | | | | | | | | | | Mosys is dropping the eventlog command, in favor of the elogtool command provided in coreboot. The output is compatible with what mosys used to output. Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I8c4be82fed28b6a19746e6b93fafce23bd8ede5d Reviewed-on: https://review.coreboot.org/c/flashrom/+/58527 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ricardo Quesada <ricardoq@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* Makefile, ich_descriptors_tool/Makefile: unify behaviorThomas Heijligen2021-10-261-8/+7
| | | | | | | | | | | | | | ich_descriptors_tool/Makefile: have the same behavior as the main flashrom Makefile - only set gcc explicit on MinGW HOST_OS - don't fallback to gcc if CC was not set - set CFLAGS and EXEC_SUFFIX for TARGET_OS, not for HOST_OS Change-Id: I353c3de250167994a4aea1edfef57d839e900d78 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/58468 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* Makefile: move determination test for OS to Makefile.dThomas Heijligen2021-10-151-2/+3
| | | | | | | | | | | Move the test code for OS detection in a extra directory to split it from the main flashrom code. Change-Id: Id911f17f4100f242e1fde10d23a8459ddf38b369 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/58015 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* util: Add Nix shell fileFelix Singer2021-10-101-0/+16
| | | | | | | | | | Add a Nix shell file which is able to compile flashrom. Change-Id: I9757b952f4b034e98c2b4b70fbede52d8efb9d50 Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/58012 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* util/ich_descriptors_tool: Use GNU-style printf in MinGWDavid Hendricks2021-10-011-0/+4
| | | | | | | | | | | | | | This allows MinGW targets to use certain printf formatting identifiers such as "%v" by adding -D__USE_MINGW_ANSI_STDIO=1 to the CFLAGS. This is also done in flashrom's top-level Makefile. Reported on https://github.com/flashrom/flashrom/issues/149 Change-Id: I644be8b5b607cc77b4be2121c443f0d41d8da687 Signed-off-by: David Hendricks <david.hendricks@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/43052 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* ich_descriptors_tool: Add missing Comet Point in usageMichał Żygowski2021-09-121-0/+1
| | | | | | | | Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ia1e3e231944513521d5db064340a0247f1884290 Reviewed-on: https://review.coreboot.org/c/flashrom/+/55993 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* util: Name udev-rules file accordinglyFelix Singer2021-06-281-0/+0
| | | | | | | | | | | Rename `z60_flashrom.rules` to `flashrom_udev.rules`. Change-Id: I1e7918d3121d89d3c388745e433a3a413eac0e21 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/flashrom/+/55866 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Add Gemini Lake supportAngel Pons2021-05-161-0/+3
| | | | | | | | | | | The SPI hardware is pretty much unchanged from Apollo Lake. However, the IFD differs significantly enough to require special handling. Signed-off-by: Angel Pons <th3fanbus@gmail.com> Change-Id: Ib5dcdf204166f44a8531c19b5f363b851d2ccd77 Reviewed-on: https://review.coreboot.org/c/flashrom/+/54276 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* CHROMIUM: flashrom_tester: Remove --ignore-fmap optionDaniel Campello2021-05-062-10/+3
| | | | | | | | | | | | | | | | | This change removes --ignore-fmap as this is implicitly computed based on other supplied options by the user. Original-Signed-off-by: Daniel Campello <campello@chromium.org> Original-Cq-Depend: chromium:2854174, chrome-internal:3789445, chromium:2854014 Original-Change-Id: I841a56d8726644cedd7d616ddfd5656b92dd7e59 Original-Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/flashrom/+/2851658 Original-Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> (cherry picked from commit 2e2a5e449229e9c9604235a98b56e5dd29bf25cf) Change-Id: Ib329f3adb59ce1848d1540844d64b968f49eb22a Reviewed-on: https://review.coreboot.org/c/flashrom/+/52890 Reviewed-by: Peter Marheine <pmarheine@chromium.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* CHROMIUM: flashrom_tester: Drop nix dependencyChirantan Ekbote2021-05-062-7/+13
| | | | | | | | | | | | | | | | | | | | | | We can just use the libc functions directly. This is exactly what nix does anyway. BUG=none TEST=unit tests BRANCH=none Original-Change-Id: I45c02f0c71d164bd8f504fe2b8d3acd54e0d5704 Original-Signed-off-by: Chirantan Ekbote <chirantan@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/flashrom/+/2560393 Original-Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Original-Reviewed-by: Allen Webb <allenwebb@google.com> Original-Commit-Queue: Allen Webb <allenwebb@google.com> (cherry picked from commit 1ba7dbe83e01d270b6d8d597a079ea3bfeb2117e) Change-Id: Iea61c65efb04da9cd0bc0bd85a34fc10912ea87b Reviewed-on: https://review.coreboot.org/c/flashrom/+/52889 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Peter Marheine <pmarheine@chromium.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* flashrom_tester: update syntax for --wp-rangeDaniel Campello2021-05-061-5/+4
| | | | | | | | | | | TEST=cargo test Signed-off-by: Daniel Campello <campello@chromium.org> Change-Id: If17a40fba1f7d41e09e0163b353d1602c215c8db Reviewed-on: https://review.coreboot.org/c/flashrom/+/52876 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Peter Marheine <pmarheine@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* manibuilder: Add more NetBSD targetsNico Huber2021-04-222-1/+31
| | | | | | | | | | | Looks like these build fine. Add all the 9.1 targets to the default run. Change-Id: Ic323ced43132921d9f6f2c0d5fcf9c581afec0c7 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/52485 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* manibuilder/anita: Always provide reasonable --memory-sizeNico Huber2021-04-223-11/+19
| | | | | | | | | | | | | | | | | | | | | | It turned out that the `--memory-size` given at install time is not persistent. All later anita runs use an arch-dependent default (32M for i386, so this might explain why it was never stable). Assuming most machines have >1GiB RAM per processor core available, we can also increase the runtime size further (better to waste some RAM than to wait very long because it starts swapping things out). We choose 512MiB for 64-bit targets and 256MiB for 32-bit ones. However, we don't need that much for the initial installation step and it also decides the size of the swap partition. So we use a smaller size initially that's just enough to get us through the installation quickly enough (192MiB & 128MiB). Change-Id: I255c41aeb92cda29ed23a236017472982e839530 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/52484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* manibuilder/anita: Fix ccache image for non-x86Nico Huber2021-04-221-5/+9
| | | | | | | | | | | | There is no disk label `a` on non-x86 (at least not on Sparc64). Instead, we use the whole disk which is `d` on x86 and `c` else- where. `newfs` and `fsck` needs a little help in this scenario. Change-Id: Ib298d9cbf5d49ff38a898f4ce3ad54bb6af98d86 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/52482 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* manibuilder/anita: Factor things out into Makefile.anitaNico Huber2021-04-222-24/+25
| | | | | | | | | | | The anita-based NetBSD targets need noisy, per-target handling. Factor it out into another Makefile. Change-Id: I0a3ca751b42f1ca8c05d93eb9740bb0ee5cc6d09 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/52483 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* util/manibuilder/README.md: Fix typoAngel Pons2021-03-231-1/+1
| | | | | | | | Change-Id: I68d3055d0d6b80b79673f66769663387fe15dcde Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/51518 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* manibuilder: Add NetBSD 8.2 target (anita:8.2-amd64)Nico Huber2021-03-162-5/+11
| | | | | | | | | | | It needs more disk space and RAM. Also, make it the default as NetBSD 7.1 packages are gone. Change-Id: Ic823cd30228f15859462844eb50d213487f74873 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/51481 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* manibuilder: Add a version number to anita tagsNico Huber2021-03-162-10/+10
| | | | | | | | | | | | | | | | NetBSD 7.1 mirrors have dropped its packages, so we need something new and more flexibility. As we have always used NetBSD 7.1 so far, prepend the tags with `7.1-`. To avoid re-building old images, one can re-tag them, e.g.: $ docker image tag mani/anita:amd64 mani/anita:7.1-amd64 Change-Id: I44351805abab93c666d1d12c2bb17380caa75cec Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/51480 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* manibuilder/anita: Make disk and memory sizes configurableNico Huber2021-03-162-2/+10
| | | | | | | | Change-Id: I95e428a19b4c2042430d3147845397adb1c37e9b Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/51479 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* manibuilder: Add list of tags used for the 1.1.x branchNico Huber2021-03-161-2/+55
| | | | | | | | | Change-Id: I243aa11f4a017a4209efcc227cec56eb12020e28 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/33340 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* manibuilder: Add newer targets for Alpine, CentOS, FedoraNico Huber2021-03-161-2/+8
| | | | | | | | | Change-Id: I6c9939601abd3bd67424b8fa9a5ec800e50e3a51 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/33342 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* manibuilder: Allow warnings in NetBSD and CentOS buildsNico Huber2021-03-161-1/+2
| | | | | | | | | | | Their old compilers stumble because of `-Wmissing-braces`. Change-Id: Ia9ee17fd1f0c8b191091f89ffbf44329c6521d7d Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/33339 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* manibuilder: Add libjaylink where possible, disable where notNico Huber2021-03-164-4/+10
| | | | | | | | | Change-Id: I2f7aebe602ebdb0a4748640e281b9a92146f0ca8 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/33338 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* manibuilder: Enable CONFIG_EVERYTHING=yesNico Huber2021-03-161-2/+3
| | | | | | | | | Change-Id: I4651b55744d730956aa8fda8fdfccbbd68cdda19 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/33337 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* manibuilder: Add list of tags used for the 1.0.x branchNico Huber2021-03-161-2/+55
| | | | | | | | | | | Also add two new make targets `1.0.x` and `show-1.0.x`. Change-Id: I2bc2e79729016a8f9908f316b051deeb73dc096f Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/30418 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Add ManibuilderNico Huber2021-03-1613-0/+470
| | | | | | | | | | | | | | | | | | | Add a set of Dockerfiles for build testing. If you have an x86 machine and ~20GiB free disk space, run `make register` and `make -jxx` in util/manibuilder and go eat some pizza. The former runs a privileged docker container to set binfmt_misc up for qemu (read the code, don't trust it). Regarding the build targets, this is the original state of Manibuilder as it was used to build-test `flashrom-1.0`. Some fixes to the frame- work were applied, but fixups for the targets will be done in separate patches to maintain their original state for reference. Change-Id: I60863a5c7d70dde71486fccb66cb59b30ba4d982 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/23005 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* CHROMIUM: avl_tool: more gracefully handle termination by SIGINTPeter Marheine2021-02-114-1/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | Since interrupting the test process may be dangerous (leaving the flash in an inconsistent state), we'll catch SIGINT and print a warning the first time, also using it as a signal that we should stop at a convenient time. Any following SIGINT will be handled as normal (killing the process). BUG=b:143251344 TEST=Run tool and verify it exits after a test with a single ^C, exits immediately given two. BRANCH=None Original-Cq-Depend: chromium:2059548 Original-Change-Id: Ib8a7799cba6dbca57dc7f1d3c87521f132c21818 Original-Signed-off-by: Peter Marheine <pmarheine@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/flashrom/+/2050050 Original-Tested-by: Edward O'Callaghan <quasisec@chromium.org> Original-Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Change-Id: If43aea0580fcc7e698daad2ffe085a3c9da5bc41 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/49915 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* util/getrevision.sh: Fallback when git tags is missingEdward O'Callaghan2021-01-181-1/+1
| | | | | | | | | | | | | | | If the tags are missing the version may not be evaluated correctly. BUG=b:177691209 BRANCH=none TEST=none Change-Id: Ib9f85b2be8b6f5e1332ba98a8a71fcad12331818 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/49618 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
* Add support for Comet Lake-U/400-series PCHMatt DeVillier2020-09-241-0/+3
| | | | | | | | | | | | | | | | Add enum CHIPSET_400_SERIES_COMET_POINT and treat it identically to CHIPSET_300_SERIES_CANNON_POINT. Add PCI IDs for Comet Lake, CML-U Premium and classify as CHIPSET_400_SERIES_COMET_POINT. Test: read/write unlocked CML-U board Change-Id: I43b4ad1eecfed16fec59863e46d4e997fbe45f1b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/44420 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* util/flashrom_tester: Upstream E2E testing frameworkEdward O'Callaghan2020-02-2416-0/+2680
| | | | | | | | | | | | | | | | | | | The following is a E2E tester for a specific chip/chipset combo. The tester itself is completely self-contained and allows the user to specify which tests they wish to preform. Supported tests include: - chip-name - read - write - erase - wp-locking Change-Id: Ic2905a76cad90b1546b9328d668bf8abbf8aed44 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/38951 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* ubertest: Add blackbox test uber-scriptDavid Hendricks2020-02-238-0/+2086
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This modifies CB:23025 further to work with upstream as it is now, without the syntax changes in the patch chain. I also gave it a new name since this script is, well, uber. Since flashrom currently only supports reading/writing ROM-sized files we can't easily determine a targeted region offset and size except when a layout file is used. Therefore, some extra arithmetic is needed in the partial write test and the only modes allowed are clobber mode and layout mode. A few other changes: - Update paths and script name - Remove write-protect testing support - Use ROM-sized files only, no region-sized files - Return error if flashmap or ifd mode are used Documentation is ported from https://goo.gl/3jNoL7 into a markdown file and accompanying SVGs. Minor changes were made for clarity and formatting, and references to write protect testing have been removed for the time being. Tested using a Raspberry Pi with a W25Q16 Change-Id: I1af55d5088c54ee33853009797adbd535a506b49 Signed-off-by: David Hendricks <david.hendricks@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/38788 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-13 12:19:28 +0000