| Commit message (Collapse) | Author | Age | Files | Lines |
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Move the message to a lower level where we can do a more generic check
and don't need internal knowledge of the SPI-master driver.
Change-Id: Idd21d20465cb214f3ff5bf3267b9014f8beee3f3
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/33650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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None of these functions are used outside of the files they are defined
in, so make them all static.
Change-Id: Ie9cbe12d289bcedacf2f1bf483ae64ef8039ccc1
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/33667
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Change-Id: I8aa3e2992f64906edc669060936f9522d32637fb
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/33649
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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We enforced a 16MiB limit in spi_read_chunked() for multi-die flash
chips that can't be fully read at once. The same limit can be useful
for dediprog programmers. So move it into a more generic place.
Change-Id: Iab1fd5b2ea550b4b3ef3e8402e0b6ca218485a51
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/33613
Reviewed-by: Ryan O'Leary
Reviewed-by: ron minnich <rminnich@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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With an SF100 and protocol version 1, using the extended address
register of the flash chip seems safe. Make use of that and remove
the broken 4BA modes flag.
Tested with SF100 V:5.1.9 and W25Q256FV.
Change-Id: If926cf3cbbebf88231116c4d65bafc19d23646f6
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/32016
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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Change-Id: Ib4487d4c1a38fa8471fa1f9034604412e9d14cf7
Signed-off-by: Richard Hughes <richard@hughsie.com>
Reviewed-on: https://review.coreboot.org/c/30405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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4BA mode is entered by setting bit 7 for the extended address register.
Change-Id: I807bf55d65763a9f48a6a3377f14f4e5288a7a4c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Tested-by: Michael Fuckner <michael@fuckner.net>
Reviewed-on: https://review.coreboot.org/25133
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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The Spansion 25SFL256S supports 4BA through an extended address register,
a 4BA mode set by bit 7 of that register, or native 4BA instructions.
Enable the former only for now.
Unfortunately the S25SF256S uses another instruction to write the exten-
ded address register. So we add an override for the instruction byte.
Change-Id: I0a95a81dfe86434f049215ebd8477392391b9efc
Signed-off-by: Nico Huber <nico.h@gmx.de>
Tested-by: Michael Fuckner <michael@fuckner.net>
Reviewed-on: https://review.coreboot.org/25132
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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Change-Id: I7bfc339673cbf5ee2d2ff7564c4db04ca088d0a4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/25381
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Instead of arbitrarily deciding whether to enter 4BA mode in the flash
chip's declaration, advertise that entering 4BA mode is supported and
only enter it if the SPI master supports 4-byte addresses. If not, exit
4BA mode (the chip might be in 4BA mode after reset). If we can't assure
the state of 4BA mode, we bail out to simplify the code (we'd have to
ensure that we don't run any instructions that can usually be switched
to 4BA mode otherwise).
Two new feature flags are introduced:
* FEATURE_4BA_ENTER:
Can enter/exit 4BA mode with instructions 0xb7/0xe9 w/o WREN.
* FEATURE_4BA_ENTER_WREN
Can enter/exit 4BA mode with instructions 0xb7/0xe9 after WREN.
FEATURE_4BA_SUPPORT is dropped, it's completely implicit now.
Also, draw the with/without WREN distinction into the enter/exit
functions to reduce code redundancy.
Change-Id: I877fe817f801fc54bd0ee2ce4e3ead324cbb3673
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/22422
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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Add a feature flag SPI_MASTER_4BA to `struct spi_master` that advertises
programmer-side support for 4-byte addresses in generic commands (and
read/write commands if the master uses the default implementations). Set
it for all masters that handle commands address-agnostic.
Don't prefer native 4BA instructions if the master doesn't support them.
Change-Id: Ife66e3fc49b9716f9c99cad957095b528135ec2c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/22421
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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Get rid of the layering violations around ICH's BBAR. Move all the weird
address handling into (surprise, surprise) `ichspi.c`. Might fix writes
for the `BBAR != 0` case by accident.
Background: Some ICHs have a BBAR (BIOS Base Address Configuration
Register) that, if set, limits the valid address range to [BBAR, 2^24).
Current code lifted addresses for REMS, RES and READ operations by BBAR,
now we do it for all addresses in ichspi. Special care has to be taken
if the BBAR is not aligned by the flash chip's size. In this case, the
lower part of the chip (from BBAR aligned down, up to BBAR) is inacces-
sible (this seems to be the original intend behind BBAR) and has to be
left out in the address offset calculation.
Change-Id: Icbac513c5339e8aff624870252133284ef85ab73
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/22396
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: If581e24347e45cbb27002ea99ffd70e334c110cf
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/22388
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Idb7c576cb159630da2268813388b497cb5f46b43
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/22386
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Prefer the native 4BA instruction when they are supported. In this
case, override our logic to decide to use a 4BA address.
Change-Id: I2f6817ca198bf923671a7aa67e956e5477d71848
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/22385
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Allow 4-byte addresses for instructions usually used with 3-byte
addresses. Decide in which way the 4th byte will be communicated
based on the state of the chip (i.e. have we enabled 4BA mode)
and a new feature bit for an extended address register. If we
are not in 4BA mode and no extended address register is available
or the write to it fails, bail out.
We cache the state of 4BA mode and the extended address register
in the flashctx.
Change-Id: I644600beaab9a571b97b67f7516abe571d3460c1
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/22384
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Introduce spi_prepare_address() and spi_write_cmd() and use them in
nbyte_program, nbyte_read and block-erase procedures. The former
abstracts over the address part of a SPI command to make it exten-
sible for 4-byte adressing. spi_write_cmd() implements a WREN + write
operation with address and optionally up to 256 bytes of data. It
provides a common path to reduce overall redundancy.
Also, reduce the polling delay in spi_block_erase_c4() from 500s to
500ms as the comment suggests.
Change-Id: Ibc1ae48acbfbd427a30bcd64bdc080dc3dc20503
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/22383
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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spi_simple_write_cmd() executes WREN plus a single byte write and polls
WIP afterwards. It's used to replace current spi_erase_chip_*() imple-
mentations.
Change-Id: Ib244356fa471e15863b52e6037899d19113cb4a9
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/22382
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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This patch integrates code of the previous patch into Flashrom's code.
All the integrations is around 3 functions spi_nbyte_read, spi_nbyte_program
and spi_byte_program. After this patch then are not static and can be called
by their pointers saved in flashchips array. Also I added to flashrom.c some
code to switch a chip to 4-bytes addressing mode. And one error message is
corrected in spi.c because it's not suitable for 32-bit addresses.
Patched files
-------------
flash.h
+ added set of 4-bytes address functions to flashchip structure definition
flashrom.c
+ added switch to 4-bytes addressing more for chips which support it
serprog.c
+ added 4-bytes addressing spi_nbyte_read call to serprog_spi_read
spi.c
+ fixed flash chip size check in spi_chip_read
spi25.c
+ added 4-bytes addressing spi_nbyte_read call to spi_read_chunked
+ added 4-bytes addressing spi_nbyte_program call to spi_write_chunked
+ added 4-bytes addressing spi_byte_program call to spi_chip_write_1
Conflicts:
serprog.c
Change-Id: Ib051cfc93bd4aa7580519e0e6206d025f3ca8049
Signed-off-by: Boris Baykov <dev@borisbaykov.com>, Russia, Jan 2014
[clg: ported from
https://www.flashrom.org/pipermail/flashrom/2015-January/013205.html ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-on: https://review.coreboot.org/20505
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Previous unnecessary page-by-page reading is repurposed to
read by big naturally aligned areas (now chip size limited
to 16MB for future-proofing of 4 byte addressed multi-die chips)
and serprog hack for continuous reads is removed.
Change-Id: Iadf909c9216578b1c5dacd4c4991bb436e32edc9
Signed-off-by: Urja Rannikko <urjaman@gmail.com>
Reviewed-on: https://review.coreboot.org/20223
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Saying that manufacturer id 0x00 is an "unknown SPI chip"
just confuses people with external programmers without a
proper connection to a chip and makes them think flashrom
doesn't support the chip they're trying to use.
Also causes unnecessary -c requirement with a multiple-slot
(FWH/LPC and SPI) serprog device i was testing.
Corresponding to flashrom svn r1893.
Signed-off-by: Urja Rannikko <urjaman@gmail.com>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
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Register_programmer suggests that we register a programmer. However,
that function registers a master for a given bus type, and a programmer
may support multiple masters (e.g. SPI, FWH). Rename a few other
functions to be more consistent.
Corresponding to flashrom svn r1831.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
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Corresponding to flashrom svn r1789.
Inspired by and mostly based on a patch
Signed-off-by: Mark Marshall <mark.marshall@omicron.at>
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
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Corresponding to flashrom svn r1780.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
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Also, try to always disable WRDI because else the user is stuck
with a chip in AAI mode that won't return by itself w/o a reset.
Corresponding to flashrom svn r1779.
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
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Add...
- N25Q128..3E
- N25Q128..1E
- N25Q256..1E (defunct due to addressing)
- N25Q256..3E (defunct due to addressing)
- N25Q512..1E (defunct due to addressing)
- N25Q512..3E (defunct due to addressing)
- N25Q00A..3G (defunct due to addressing)
Also, refine existing family members.
Corresponding to flashrom svn r1693.
Signed-off-by: Nikolay Nikolaev <evrinoma@gmail.com>
Reviewed-by: Steven Zakulec <spzakulec@gmail.com>
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
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Used for page erase on some chips (e.g. Numonyx M45PE and
Sanyo LF25FW series).
Corresponding to flashrom svn r1682.
Signed-off-by: Nikolay Nikolaev <evrinoma@gmail.com>
Reviewed-by: Steven Zakulec <spzakulec@gmail.com>
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
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We forgot to add a few SPI erase functions to the helper function that is
used for SFDP. Also, sort the declarations in the header.
Corresponding to flashrom svn r1672.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
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- Add missing bits and resort chips
- Refine Pm25LV512(A) and Pm25LV010
Due to manufacturer ID continuation this one needs a new probing
function: probe_spi_res3() which should be refactored in the future.
The datasheet describes a very weird order of ID bytes:
Vendor byte, model byte, vendor continuation byte. Let's pretend we did
not read that or the datasheet is bogus (although the datasheet of the
successor series describes the same but luckily additionally to RDID).
- Add Pm25LV010A
This was tested by Chi Zhang:
http://paste.flashrom.org/view.php?id=1573
Corresponding to flashrom svn r1670.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
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This adds support for the following chips:
- AT25F512, AT25F512A, AT25F512B
- AT25F1024, AT25F1024A
- AT25F2048
- AT25F4096
Besides the definitions of the the chips in flashchips.c this includes
- a dedicated probing method (probe_spi_at25f)
- pretty printing methods (spi_prettyprint_status_register_at25f*), and
- unlocking methods (spi_disable_blockprotect_at25f*)
Corresponding to flashrom svn r1637.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
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- Move all functions related to SPI status registers to a new file
spi25_statusreg.c. This includes the generic as well as the
SST-specific functions from spi25.c and the chip-specific functions
from a25.c and at25.c.
- introduce helper functions
* spi_prettyprint_status_register_hex()
* spi_prettyprint_status_register_bpl()
* spi_prettyprint_status_register_plain()
Use the latter on every compatible flash chip that has no better printlock
function set and get rid of the implicit pretty printing in the SPI probing
functions.
- remove
* spi_prettyprint_status_register_common()
* spi_prettyprint_status_register_amic_a25lq032() because it can be fully
substituted with spi_prettyprint_status_register_amic_a25l032().
* spi_prettyprint_status_register() (old switch, no longer needed)
- promote and export
* spi_prettyprint_status_register_amic_a25l05p() as spi_prettyprint_status_register_default_bp1().
* spi_prettyprint_status_register_amic_a25l40p() as spi_prettyprint_status_register_default_bp2().
* spi_prettyprint_status_register_st_m25p() as spi_prettyprint_status_register_default_bp3().
- add #define TEST_BAD_REW and use it for a number of Atmel chips which
had only TEST_BAD_READ set even though they dont have erasers or a write
function set.
Corresponding to flashrom svn r1634.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
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Wicked chip: No WRSR, no write enable command (but swallows our
default one without a problem), supports an auto-erasing page write
(but even without that page writes are recommended to write the
whole page i.e. operate on a completely erased page), mad
requirements on block refreshments if only partly written.
Found on my Intel D946GZIS and tested with my serprog in situ.
Using the page write by setting JEDEC_BYTE_PROGRAM to 0x11 and using
the spi_chip_write_256 command greatly improves performance and works
flawlessly.
Corresponding to flashrom svn r1616.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
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Corresponding to flashrom svn r1602.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
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This is used by the AT25F series (only?), but is generic enough to
reside in spi25.c. The only currently supported chip is the AT25F512B.
Other members of that series need some additional infrastructure code,
hence this patch adds the erase function to the AT25F512B only.
Corresponding to flashrom svn r1600.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
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All the driver conversion work and cleanup has been done by Stefan.
flashrom.c and cli_classic.c are a joint work of Stefan and Carl-Daniel.
Corresponding to flashrom svn r1579.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
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Make them real progress indicators with a final "done" message on success.
Corresponding to flashrom svn r1561.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
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- introduce spi_prettyprint_status_register_atmel_at25_wpen()
- use spi_prettyprint_status_register_bit() where possible
- generify spi_prettyprint_status_register_bp3210 and use it in at25.c too
Corresponding to flashrom svn r1560.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
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Currently spi_aai_write() is implemented without an abstraction
mechanism for the programmer driver. This adds another function
pointer 'write_aai' to struct spi_programmer, which is set to
default_spi_write_aai (renamed spi_aai_write) for all programmers
for now.
A patch which utilises this abstraction in the dediprog driver will
follow.
Corresponding to flashrom svn r1543.
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
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Corresponding to flashrom svn r1532.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
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In r1115 "Write protection handling for Atmel AT25*" the old
spi_write_status_register function was duplicated to send WREN and
EWSR commands respectively controlled by a new common wrapper function
spi_write_status_register without a reason. Both functions' resulting
code is equal apart from the opcode used. The code itself does also
differ in the macros used, but their value (apart from the opcode) is
equal. This patch adds a new parameter for the opcode to the helper
function which allows removal of the other one. This relies on the fact
that EWSR and WREN have the same INSIZE and OUTSIZE though. If that is
really seen as an issue, the sizes could be made parameters too.
This patch also changes the wrapper so that it no longer sets the
feature bits of the struct flash(ctx) argument. This may result in
changed output, because it no longer implicitly disables the debug
message in following executions. Since almost all chips had their
feature bits fixed in the previous commit, this is a minor problem.
Also, spi_write_status_enable has been dead code since r658 or so.
Remove it.
Corresponding to flashrom svn r1528.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
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Similar to modules using the opaque programmer framework (e.g. ICH Hardware
Sequencing) this uses a template struct flashchip element in flashchips.c with
a special probe function that fills the obtained values into that struct.
This allows yet unknown SPI chips to be supported (read, erase, write) almost
as if it was already added to flashchips.c.
Documentation used:
http://www.jedec.org/standards-documents/docs/jesd216 (2011-04)
W25Q32BV data sheet Revision F (2011-04-01)
EN25QH16 data sheet Revision F (2011-06-01)
MX25L6436E data sheet Revision 1.8 (2011-12-26)
Tested-by: David Hendricks <dhendrix@google.com>
on W25Q64CV + dediprog
Tested-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
on a 2010 MX25L6436E with preliminary (i.e. incorrect) SFDP implementation + serprog
Thanks also to Michael Karcher for his comments and preliminary review!
Corresponding to flashrom svn r1500.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
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All programmer types (Parallel, SPI, Opaque) now register themselves
into a generic programmer list and probing is now programmer-centric
instead of chip-centric.
Registering multiple SPI/... masters at the same time is now possible
without any problems. Handling multiple flash chips is still unchanged,
but now we have the infrastructure to deal with "dual BIOS" and "one
flash behind southbridge and one flash behind EC" sanely.
A nice side effect is that this patch kills quite a few global variables
and improves the situation for libflashrom.
Hint for developers:
struct {spi,par,opaque}_programmer now have a void *data pointer to
store any additional programmer-specific data, e.g. hardware
configuration info.
Note:
flashrom -f -c FOO -r forced_read.bin
does not work anymore. We have to find an architecturally clean way to
solve this.
Corresponding to flashrom svn r1475.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
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All programmer access function prototypes except init have been made
static and moved to the respective file.
A few internal functions in flash chip drivers had chipaddr parameters
which are no longer needed.
The lines touched by flashctx changes have been adjusted to 80 columns
except in header files.
Corresponding to flashrom svn r1474.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
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Struct flashchip is used only for the flashchips array and for
operations which do not access hardware, e.g. printing a list of
supported flash chips.
struct flashctx (flash context) contains all data available in
struct flashchip, but it also contains runtime information like
mapping addresses. struct flashctx is expected to grow additional
members over time, a prime candidate being programmer info.
struct flashctx contains all of struct flashchip with identical
member layout, but struct flashctx has additional members at the end.
The separation between struct flashchip/flashctx shrinks the memory
requirement of the big flashchips array and allows future extension
of flashctx without having to worry about bloat.
Corresponding to flashrom svn r1473.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
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Push those changes forward where needed to prevent new sign
conversion warnings where possible.
Corresponding to flashrom svn r1470.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
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Tested mainboards:
OK:
- ASUS Crosshair II Formula
http://www.flashrom.org/pipermail/flashrom/2011-September/007888.html
- ASUS K8N
http://paste.flashrom.org/view.php?id=856
- ASUS M2N-E SLI
http://www.flashrom.org/pipermail/flashrom/2011-September/007909.html
- ASUS M3N78-VM
http://www.flashrom.org/pipermail/flashrom/2011-May/006496.html
- ASUS M4A78LT-M LE
http://www.flashrom.org/pipermail/flashrom/2011-September/007869.html
- ASUS M4A89GTD PRO
http://www.flashrom.org/pipermail/flashrom/2011-February/005824.html
- MSI A75MA-G55 (MS-7696)
http://www.flashrom.org/pipermail/flashrom/2011-October/008055.html
- PCCHIPS M598LMR (V9.0)
http://www.flashrom.org/pipermail/flashrom/2011-October/008051.html
- ECS P4VXMS (V1.0A)
http://www.flashrom.org/pipermail/flashrom/2011-September/007986.html
- Foxconn P4M800P7MA-RS2
http://www.flashrom.org/pipermail/flashrom/2011-October/008114.html
- GIGABYTE GA-P67A-UD3P
http://www.flashrom.org/pipermail/flashrom/2011-September/007930.html
- GIGABYTE Z68MX-UD2H-B
http://www.flashrom.org/pipermail/flashrom/2011-October/008080.html
- ZOTAC Fusion-ITX WiFi (FUSION350-A-E)
http://www.flashrom.org/pipermail/flashrom/2011-October/008011.html
NOT OK:
- ASUS P8B-E/4L
http://www.flashrom.org/pipermail/flashrom/2011-October/008047.html
- ASUS P8B WS
http://www.flashrom.org/pipermail/flashrom/2011-October/008081.html
Tested chipsets:
- MCP78S (:075d)
http://www.flashrom.org/pipermail/flashrom/2011-August/007612.html
- VT8233 (:3074)
http://www.flashrom.org/pipermail/flashrom/2011-September/007986.html
- SiS 530 (:0530)
http://www.flashrom.org/pipermail/flashrom/2011-October/008051.html
- P67 (:1c46)
http://www.flashrom.org/pipermail/flashrom/2011-September/007930.html
- Z68 (:1c44)
http://www.flashrom.org/pipermail/flashrom/2011-October/008080.html
Tested flash chips:
- mark AMIC A29002T as TEST_OK_PREW
http://www.flashrom.org/pipermail/flashrom/2011-October/008085.html
- mark Eon EN29F002(A)(N)T as TEST_OK_PREW
http://www.flashrom.org/pipermail/flashrom/2011-October/008053.html
- mark EonEN25F16 as TEST_OK_PREW
http://www.flashrom.org/pipermail/flashrom/2011-February/005824.html
- mark Macronix MX29F002(N)T as TEST_OK_PREW
http://www.flashrom.org/pipermail/flashrom/2011-October/008083.html
- mark Pm39LV040 as TEST_OK_PR
http://www.flashrom.org/pipermail/flashrom/2011-September/007942.html
- mark Pm39LV010 as TEST_OK_PREW
http://www.flashrom.org/pipermail/flashrom/2011-September/007942.html
- mark SST49LF008A as TEST_OK_PREW
http://www.flashrom.org/pipermail/flashrom/2011-September/007989.html
- mark SyncMOS {F,S,V}29C51002T as TEST_OK_PREW
http://www.flashrom.org/pipermail/flashrom/2011-October/008052.html
- mark W39V040B as write tested
http://www.flashrom.org/pipermail/flashrom/2011-October/008114.html
- mark W39V040C as TEST_OK_PREW
http://www.flashrom.org/pipermail/flashrom/2011-October/008114.html
- remove superfluous line break in enable_flash_ich_dc_spi
- m->M in "min" and "max" (voltage) in print_wiki.c
Corresponding to flashrom svn r1454.
- spi25: get rid of unneccessary line breaks (on failed probes)
which is
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
- rayer_spi.c: Remove double word: `s/the the/the/`
which is
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
The parts added until 2011-10-14 (most of this patch) were
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
everything else is
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
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- probe_timing was changed to unsigned although we use negative values
for special cases
- some code was not changed along hence did no longer compile:
* dediprog's read and write functions
* linux_spi's read and write functions
- it introduced a number of new sign conversion warnings
(http://paste.flashrom.org/view.php?id=832)
To be safe this patch reverts all changes made in r1448, a corrected
patch will follow later.
Thanks to idwer for pointing out the problem first!
Corresponding to flashrom svn r1450.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
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Corresponding to flashrom svn r1448.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
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- add Asus E35M1-I DELUXE to boards_known
http://www.flashrom.org/pipermail/flashrom/2011-June/006918.html
- add Asus M3A to boards_known
http://www.flashrom.org/pipermail/flashrom/2011-July/007085.html
- add Freetech P6F91i to boards_known
http://www.flashrom.org/pipermail/flashrom/2011-June/006800.html
- add GA-M720-US3 to boards_known
http://www.flashrom.org/pipermail/flashrom/2011-July/007096.html
- add GA-MA770-UD3 (rev. 2.1) to boards_known
http://www.flashrom.org/pipermail/flashrom/2011-June/006879.html
- add GA-965GM-S2 to boards_known
http://www.flashrom.org/pipermail/flashrom/2011-June/006746.html
- add HP xw4400 (0A68h) to boards_known
http://paste.flashrom.org/view.php?id=686
- add MSI MS-6566 (845 Ultra-C) to boards_known
http://www.flashrom.org/pipermail/flashrom/2011-June/006908.html
- add MSI MS-7698 (E350IA-E45) to boards_known
http://www.flashrom.org/pipermail/flashrom/2011-June/007003.html
- add PCCHIPS M863G (V5.1A) to boards_known
http://www.flashrom.org/pipermail/flashrom/2011-July/007084.html
- modify the X8SIE entry in boards_known with the information from "fuzzy"
http://paste.flashrom.org/view.php?id=669
- mark W29C020(C)/W29C022 as fully tested
http://www.flashrom.org/pipermail/flashrom/2011-June/006800.html
- mark W49V002A as fully tested
http://www.flashrom.org/pipermail/flashrom/2011-July/007084.html
- mark M25P128 as fully tested
http://www.flashrom.org/pipermail/flashrom/2011-June/006843.html
- mark SST39SF010A as fully tested
http://www.flashrom.org/pipermail/flashrom/2011-July/007115.html
- correct entries for GA-K8NS Pro-939 (was ultra before. thanks uwe!)
- another tiny fix for "a small fix"/r1321
Without this you will get broken bus names "Unknow" and "Non-SP".
Note to self: don't self-ack even fairly trivial patches.
- fix spew output of spi_rems in spi25.c
- add URL to ASUS M3A76-CM
- rename all Winbond W25x chips to W25X
- fixes some common misspellings/typos in comments:
lenght->length 2
ocassional->occasional 1
unsucessfull->unsuccessful 1
upto->up to 5
Corresponding to flashrom svn r1367.
the patch for M25P128 is
Signed-off-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
the typos are
Signed-off-by: Peter Huewe <peterhuewe@gmx.de>
everything else is
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
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Erase functions are no longer called from chip drivers and thus their
internal erase verification can be moved to generic code. This also
makes it easier to skip the verify step if desired and to differentiate
between failed command submission and failed erase verification.
Corresponding to flashrom svn r1353.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
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