| Commit message (Collapse) | Author | Age | Files | Lines |
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When developing software that has to be flashed to a flash chip to be
executed, it often takes a long time to read the current flash contents
(for flashrom to know what pages to erase and reprogram) each time
when writing the new image. However, when the flash was just reprogrammed,
its current state is known to be the previous image that was flashed
(assuming it was verified).
Thus, it makes sense to provide that image as a file for the flash contents
instead of wasting valuable time read the whole flash each time.
Change-Id: Idf153b6955f37779ae9bfb228a434ed10c304947
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: https://review.coreboot.org/23263
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The ENE Embedded Debug Interface (EDI) is a SPI-based interface for
accessing the memory of ENE embedded controllers.
The ENE KB9012 EC is an embedded controller found on various laptops
such as the Lenovo G505s. It features a 8051 microcontroller and
has 128 KiB of internal storage for program data.
EDI can be accessed on the KB9012 through pins 59-62 (CS-CLK-MOSI-MISO)
when flash direct access is not in use. Some firmwares disable EDI at runtime
so it might be necessary to ground pin 42 to reset the 8051 microcontroller
before accessing the KB9012 via EDI.
The example of flashing KB9012 at Lenovo G505S laptop could be found here:
http://dangerousprototypes.com/docs/Flashing_KB9012_with_Bus_Pirate
Change-Id: Ib8b2eb2feeef5c337d725d15ebf994a299897854
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: https://review.coreboot.org/23259
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Most flash chips are erased to ones and programmed to zeros. However, some
other chips, such as the ENE KB9012 internal flash, work the opposite way.
Change-Id: Ia7b0de8568e31f9bf263ba0ad6b051e837477b6b
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: https://review.coreboot.org/23258
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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By default, we want to probe for SPI25 chips only. Other SPI use cases,
like the ENE/EDI protocol, might use commands that can confuse these
common chips.
Now, flashrom will probe for a chip only if one of these conditions is
true:
1) no chip has been specified AND the chip uses the SPI25 commands
2) this chip has been specified by -c | --chip <chipname>
The CLI can later be extended to probe for a specific class of chips.
Change-Id: I89a53ccaef2791a2ac32904d7ab813da7478a6f0
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/23262
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Kocialkowski <contact@paulk.fr>
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Advertise all 4BA features that are currently supported by flashrom,
plus add a new feature flag for the 4BA fast-read instruction. Also,
list all supported 3BA and 4BA erase-block functions.
As this adds a lot of new code paths that could be taken for these
chips, mark them all as untested again.
Change-Id: I0598496ee7058e3b170684d366f58e4014e0e871
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/22423
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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Instead of arbitrarily deciding whether to enter 4BA mode in the flash
chip's declaration, advertise that entering 4BA mode is supported and
only enter it if the SPI master supports 4-byte addresses. If not, exit
4BA mode (the chip might be in 4BA mode after reset). If we can't assure
the state of 4BA mode, we bail out to simplify the code (we'd have to
ensure that we don't run any instructions that can usually be switched
to 4BA mode otherwise).
Two new feature flags are introduced:
* FEATURE_4BA_ENTER:
Can enter/exit 4BA mode with instructions 0xb7/0xe9 w/o WREN.
* FEATURE_4BA_ENTER_WREN
Can enter/exit 4BA mode with instructions 0xb7/0xe9 after WREN.
FEATURE_4BA_SUPPORT is dropped, it's completely implicit now.
Also, draw the with/without WREN distinction into the enter/exit
functions to reduce code redundancy.
Change-Id: I877fe817f801fc54bd0ee2ce4e3ead324cbb3673
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/22422
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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Get rid of the layering violations around ICH's BBAR. Move all the weird
address handling into (surprise, surprise) `ichspi.c`. Might fix writes
for the `BBAR != 0` case by accident.
Background: Some ICHs have a BBAR (BIOS Base Address Configuration
Register) that, if set, limits the valid address range to [BBAR, 2^24).
Current code lifted addresses for REMS, RES and READ operations by BBAR,
now we do it for all addresses in ichspi. Special care has to be taken
if the BBAR is not aligned by the flash chip's size. In this case, the
lower part of the chip (from BBAR aligned down, up to BBAR) is inacces-
sible (this seems to be the original intend behind BBAR) and has to be
left out in the address offset calculation.
Change-Id: Icbac513c5339e8aff624870252133284ef85ab73
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/22396
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Idb7c576cb159630da2268813388b497cb5f46b43
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/22386
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Prefer the native 4BA instruction when they are supported. In this
case, override our logic to decide to use a 4BA address.
Change-Id: I2f6817ca198bf923671a7aa67e956e5477d71848
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/22385
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Allow 4-byte addresses for instructions usually used with 3-byte
addresses. Decide in which way the 4th byte will be communicated
based on the state of the chip (i.e. have we enabled 4BA mode)
and a new feature bit for an extended address register. If we
are not in 4BA mode and no extended address register is available
or the write to it fails, bail out.
We cache the state of 4BA mode and the extended address register
in the flashctx.
Change-Id: I644600beaab9a571b97b67f7516abe571d3460c1
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/22384
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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spi_simple_write_cmd() executes WREN plus a single byte write and polls
WIP afterwards. It's used to replace current spi_erase_chip_*() imple-
mentations.
Change-Id: Ib244356fa471e15863b52e6037899d19113cb4a9
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/22382
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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TARGET_OS as well as EXEC_SUFFIX were only set when called via the
main makefile and even then __USE_MINGW_ANSI_STDIO was not set
for MinGW.
While at it, also replace the hardcoded gnu_printf printf format
attribute with __MINGW_PRINTF_FORMAT which is set according to
__USE_MINGW_ANSI_STDIO respectively.
Change-Id: Id146f5ba06a0e510397c6f32a2bd7c819a405a25
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: https://review.coreboot.org/21838
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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This allows us to support flash chips in any of the following
configurations, regardless of whether the chip powers up in 3-byte or
4-byte address mode.
- standard commands with extended address register (*_4ba_ereg) or
direct commands (*_4ba_direct) in 3-byte address mode (.set_4ba =
spi_exit_4ba_*)
- standard commands (*_4ba) or direct commands (*_4ba_direct) in
4-byte address mode (.set_4ba = spi_enter_4ba_*)
- direct commands (*_4ba_direct) in either address mode (.set_4ba =
NULL)
Change-Id: I0b25309d731426940fc50956b744b681ab599e87
Signed-off-by: Ed Swierk <eswierk@skyportsystems.com>
Reviewed-on: https://review.coreboot.org/20510
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Large flash chips usually support special instructions to work with
4-bytes address directly from 3-bytes addressing mode and without
do switching to 4-bytes mode. There are 13h (4BA Read), 12h (4BA Program)
and 21h,5Ch,DCh (4BA Erase), correspondingly. However not all these
instructions are supported by all large flash chips. Some chips
support 13h only, some 13h,12h,21h and DCh, but not 5Ch. This depends
on the manufacturer of the chip.
This patch provides code to use direct 4-bytes addressing instructions.
This code should work but it tested partially only. My W25Q256FV has
support for 4BA_Read (13h), but doesn't have support 4BA_Program (12h)
and 4BA_Erase instructions. So, direct 4BA program and erase
should be tested after.
Patched files
-------------
chipdrivers.h
+ added functions declarations for spi4ba.c
flash.h
+ feature definitions added
flashchips.c
+ modified definition of Winbond W25Q256BV/W25Q256FV chips
flashrom.c
+ modified switch to 4-bytes addressing for direct-4BA instructions
spi4ba.h
+ definitions for 4-bytes addressing JEDEC commands
+ functions declarations from spi4ba.c (same as in chipdrivers.h, just to see)
spi4ba.c
+ functions for read/write/erase directly with 4-bytes address (from any mode)
Change-Id: Ib51bcc5de7826b30ad697fcbb9a5152bde2c2ac9
Signed-off-by: Boris Baykov <dev@borisbaykov.com>, Russia, Jan 2014
[clg: ported from
https://www.flashrom.org/pipermail/flashrom/2015-January/013198.html ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-on: https://review.coreboot.org/20508
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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On some flash chips data with addresses more than 24-bit field
can address may be accessed by using Extended Address Register.
The register has 1-byte size and stores high byte of 32-bit address.
Then flash can be read from 3-bytes addressing mode with writing
high byte of address to this Register. By using this way we have
access to full memory of a chip. Some chips may support this method
only.
This patch provides code use Extended Address Register.
Patched files
-------------
chipdrivers.h
+ added functions declarations for spi4ba.c
flash.h
+ feature definitions added
flashrom.c
+ modified switch to 4-bytes addressing to support extended address register
spi4ba.h
+ definitions for 4-bytes addressing JEDEC commands
+ functions declarations from spi4ba.c (same as in chipdrivers.h, just to see)
spi4ba.c
+ functions for write Extended Address Register
+ functions for read/write/erase with Extended Address Register
Change-Id: I09a8aa11de2ca14901f142c67c83c4fa0def4e27
Signed-off-by: Boris Baykov <dev@borisbaykov.com>, Russia, Jan 2014
[clg: ported from
https://www.flashrom.org/pipermail/flashrom/2015-January/013200.html ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-on: https://review.coreboot.org/20507
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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This patch integrates code of the previous patch into Flashrom's code.
All the integrations is around 3 functions spi_nbyte_read, spi_nbyte_program
and spi_byte_program. After this patch then are not static and can be called
by their pointers saved in flashchips array. Also I added to flashrom.c some
code to switch a chip to 4-bytes addressing mode. And one error message is
corrected in spi.c because it's not suitable for 32-bit addresses.
Patched files
-------------
flash.h
+ added set of 4-bytes address functions to flashchip structure definition
flashrom.c
+ added switch to 4-bytes addressing more for chips which support it
serprog.c
+ added 4-bytes addressing spi_nbyte_read call to serprog_spi_read
spi.c
+ fixed flash chip size check in spi_chip_read
spi25.c
+ added 4-bytes addressing spi_nbyte_read call to spi_read_chunked
+ added 4-bytes addressing spi_nbyte_program call to spi_write_chunked
+ added 4-bytes addressing spi_byte_program call to spi_chip_write_1
Conflicts:
serprog.c
Change-Id: Ib051cfc93bd4aa7580519e0e6206d025f3ca8049
Signed-off-by: Boris Baykov <dev@borisbaykov.com>, Russia, Jan 2014
[clg: ported from
https://www.flashrom.org/pipermail/flashrom/2015-January/013205.html ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-on: https://review.coreboot.org/20505
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Fix some whitespace, and braces. Remove sector size from comments that I
could not verify.
Change-Id: I4faaa036fea744135fa37f405686fb9fd0882806
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/21947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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If flash chip is switched to 4-bytes addressing mode then all
read/erase/program instructions will be switched from 3-bytes mode
to 4-bytes mode. Then well known instructions like 03h (Read),
02h (Program) and 20h,52h,D8h (Erase) will become one byte longer
and accept 4-bytes address instead of 3-bytes.
This patch provides support for well known instructions in 4-bytes
addressing mode. Also here is the code to enter 4-bytes addressing
mode by execute the instruction B7h (Enter 4-bytes mode).
Patched files
-------------
chipdrivers.h
+ added functions declarations for spi4ba.c
flash.h
+ feature definitions added
Makefile
+ added spi4ba.c
Added files
-----------
spi4ba.h
+ definitions for 4-bytes addressing JEDEC commands
+ functions declarations from spi4ba.c (same as in chipdrivers.h, just to see)
spi4ba.c
+ functions for enter 4-bytes addressing mode
+ functions for read/write/erase in 4-bytes addressing mode
Change-Id: Ie72e2a89cd75fb4d09f48e81c4c1d927c317b7a7
Signed-off-by: Boris Baykov <dev@borisbaykov.com>, Russia, Jan 2014
[clg: ported from
https://www.flashrom.org/pipermail/flashrom/2015-January/013199.html ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-on: https://review.coreboot.org/20513
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use `enum flashrom_log_level` instead to avoid further confusion.
Change-Id: I1895cb8f60da3abf70c9c2953f52414cd2cc10a9
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20268
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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o Move flashbuses_to_text() to flashrom.c, it's not a cli function.
o Guard `!defined(HAVE_STRNLEN)`. This guard was introduced in
23e10b87 (Add a bunch of new/tested stuff and various small
changes 24) to support older BSDs. It's probably completely
broken because HAVE_STRNLEN is presumably a GNU autotools
thing. But we can't fix it without retesting these older BSDs.
Change-Id: I561135209b819361d125eeaeef9ff886d6bae987
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/18738
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add an option --ifd to read the ROM layout from an Intel Firmware
Descriptor (IFD). Works the same as the -l option, if given, -i
specifies the images to update.
v2: o Rebased on libflashrom, use libflashrom interface.
o Use functions from ich_descriptors.c.
v3: o Move ich_descriptors.o to LIB_OBJS, thus build it independent
of arch and programmers.
o Bail out if we aren't compiled for little endian.
o Update flashrom.8.tmpl.
v4: o Incorporated David's comments.
o Removed single-character `-d` option.
v5: Changed region names to match the output of `ifdtool --layout ...`
Change-Id: Ifafff2bf6d5c5e62283416b3269723f81fdc0fa3
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/17953
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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No words can describe this feeling.
v2: Rejoice while removing more, orphaned code (layout.c).
Change-Id: Id81177c50b4410e68dcf8ebab48386a94cd9b714
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/17949
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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This renames CLI's print() to flashrom_print_cb() and registers it
through the new libflashrom interface.
v2: Add libflashrom.o to LIB_OBJS now that everything can be linked
together.
Change-Id: Idf19978eb8e340d258199193d2978f37409e9983
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/17948
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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This adds a minimal libflashrom interface based on the draft in the
wiki. While the glue code in libflashrom.c is build on top of the
existing code instead on overhauling it, the interface in libflashrom.h
is supposed to be stable. So we can keep the interface and adapt
internals later if favoured, without breaking clients.
A new make target, libinstall, is also added. It installs libflashrom.a
and libflashrom.h in lib/ and include/ dirs respectively.
Hooking this into the build would break linking of the CLI and is post-
poned until that got fixed.
v2: Rebase and fixes by Anton Kochkov.
v3: o fl_image_*() rewritten with layout support (touch only included regions).
o Moved read/erase/write/verify operations to flashrom.c.
o Added layout pointer and flags to the flash context.
v4: Removed libflashrom.o from LIB_OBJS until CLI is adapted.
v5: o Incorporated David's comments.
o Added `fl_flashprog_t` as dummy parameter to hide the fact that
we have global state all around, and for future-proofness ofc.
v6: o Change namespace prefix to flashrom_.
o Remove typedefs.
Change-Id: I00f169990830aa17b7dfae5eb74010d40c476181
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/17946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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Inspired by Lynxis' related work, this implements a foundation for
layout based flash access.
All operations iterate over the given layout regions. Erase and write
then walk, per region, over all erase blocks in an inner loop (which
might not be what we want, see note on optimization below). Special care
has been taken that flash content is merged properly, in case an erase
block is only partially covered by a layout region or even affects mul-
tiple regions.
A note on performance: In the case an erase block affects multiple
regions, it will probably be read, erased and written for each region.
Another approach would be to walk all erase blocks once and check for
each erase block which regions it touches (i.e. for each erase block,
merge data pontentially from the flash and all layout regions, then
flash the combined data). That might result in cleaner code. I haven't
tried it yet, though.
Change-Id: Ic6194cea4c4c430e0cf9d586052508a865b09c86
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/17945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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Introduce `struct flashrom_layout` and refactor layout.c a little, so
we can reuse the layout from there and have other sources of layouts
beside it.
I didn't want to clutter up flash.h any more. So things went into a new
layout.h.
Change-Id: Icea1a58c283131cc9c5fde6f16d783538dc1a4c7
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/17944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
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Tested mainboards:
OK:
- ASRock G31M-GS
Reported by Александр Трубицын
- ASRock G41M-VS3
Reported by Александр Трубицын
- ASRock N68C-S UCC
Reported by Alexey Belyaev
- ASRock AMCP7AION-HT (ION 330HT(-BD))
Reported by Stefan Tauner
- ASUS P5K SE
Reported by Александр Трубицын
- ASUS P5KPL-VM
Reported by Marin Vlah
- ASUS RAMPAGE III GENE
Reported by stevessss on IRC
- GIGABYTE GA-945GM-S2
Reported by Александр Трубицын
- GIGABYTE GA-945GCM-S2 (rev. 3.0)
Reported by Александр Трубицын
- GIGABYTE GA-965P-S3
Reported by Александр Трубицын
- GIGABYTE GA-EG43M-S2H
Reported by Александр Трубицын
- GIGABYTE GA-EP31-DS3L (rev. 1.0)
Reported by Александр Трубицын
- GIGABYTE GA-G33M-S2
Reported by Александр Трубицын
- GIGABYTE GA-G33M-S2L
Reported by Александр Трубицын
- GIGABYTE GA-H55M-S2
Reported by Александр Трубицын
- GIGABYTE GA-J1900N-D3V
Reported by Marcos Truchado and Guillermo von Hünefeld
- GIGABYTE GA-K8NS
Reported by nicolae788
- GIGABYTE GA-M56S-S3
Reported by Estevo Paz Freire
- GIGABYTE GA-P31-DS3L
Reported by Александр Трубицын
- GIGABYTE GA-P31-S3G
Reported by Александр Трубицын
- MSI MS-7336
Reported by Benjamin Bellec
- MSI X79A-GD45 (8D) (MS-7760)"
Reported by mortehu on IRC
- Supermicro A1SAi-2550F
Reported by Bernard Grymonpon
- Supermicro X7DWT
Reported by Steven Stremciuc
Laptop:
- ASUS U38N
Reported by Ultra on IRC
- Dell Latitude D630
Reported by Márton Miklós
- Fujitsu Amilo Xi 3650
Reported by Elmar Stellnberger
- Lenovo T400 (whitelisting only)
Chipsets:
- Mark 8086:1f38 (Intel Avoton/Rangeley) as tested
Reported by Jeremy Porter and Bernard Grymonpon
- Add Intel Sunrise Point IDs but no support yet.
Flash chips:
- Atmel AT45DB321D to PREW (+PREW)
Reported by The Raven
- Eon EN25QH32 to PREW (+PREW)
Reported by Josua Mayer
- Eon EN25QH64 to PREW (+EW)
Reported by David s. Alessio
- GigaDevice GD25LQ64(B) to PREW (+PREW)
Reported by Greg Tippit
- Intel 28F001BN/BX-T to PREW (+EW)
Reported by Lu Xie
- Micron M25P10-A to PREW (+W)
Reported by the Raven
- Micron M25PE40
Reported by David Wood
- Micron N25Q128..3E to PREW (+PREW)
Reported by Miklós Márton
- Macronix MX25L3273E to PREW (+PREW)
Reported by Roklobsta on IRC
- Macronix MX23L6454 to PR (+PR)
Reported by Steven Honeyman
- Macronix MX25U6435E/F to PREW (+PREW)
Reported by Marcos Truchado and Guillermo von Hünefeld
- PMC Pm25LQ032C to PREW (+EW)
Reported by Dirk Knop
- Spansion S25FL016A to PREW (+EW)
Reported by Márton Miklós
- Spansion S25FL128S......0 to PREW (+PREW)
Reported by Jim Houston
- Spansion S25FL204K to PR (+PR)
Reported by Thomas Debrunner
- SST SST49LF016C to PREW (+EW)
Reported by Steven Stremciuc
- SST SST39VF040 to PREW (+PREW)
Reported by Xavier Bourgeois
- SST SST49LF040B to PREW (+EW)
Reported by Rikard Åhlund
- ST M25P10-A to PREW (+W)
Reported by Martijn Schiedon
- Winbond W39V040FA to PREW (+EW)
Reported by Евгений Черкашин
- Winbond W39V080FA to PREW (+EW)
Reported by protagonist0 on IRC
- Winbond W25Q80.W to PREW (+PREW)
Reported by Miklós Márton
- Winbond W25X64 to PREW (+REW)
Reported by Johannes Krampf and Manuel Dejonghe
- Fix ID of AMIC A25LQ64
Reported by Roman Titov
- Fix page size of Spansion S25FL129P......1
Copy and paste error from the 128S uniform 256kB variant, probably.
- Add Micron/Numonyx phase-change memory IDs
Miscellaneous:
- Detect Android target OS.
No changes are required to build flashrom (excluding programmers
with NEED_PCI) on Android.
- Update rayerspi (spipgm) URL
- Fix max_data_write handling of at45db.
- Minor refinement of the README
- Mark board enable for the GA-K8NS variants as tested.
Tested by "nicolae788" on a board with socket 754.
- Mark "Multi-system" chassis as non-laptop case.
- Remove W836xx log requests.
We got enough (and no one is looking at them for the time being anyway).
- serprog: improve invalid reply error message, contributed by Urja Rannikko.
- Remove default include paths for MinGW.
- Disable implicit rules in the Makefile because we don't need them and they
just make the build (imperceptibly) slower.
- Enable our own strnlen() implementation not only on DJGPP but also if
HAVE_STRNLEN is not defined. This is needed to get older BSDs
(e.g. NetBSD 6.0, FreeBSD < 8.0) to work.
- Tiny other stuff.
Corresponding to flashrom svn r1917.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
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Some chips such as the ENE KB9012 internal flash require a write
granularity of 128 bytes.
Corresponding to flashrom svn r1897.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Acked-by: Nico Huber <nico.h@gmx.de>
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Tested mainboards:
OK:
- AOpen UK79G-1394 (used in EZ18 barebones)
Reported by Lawrence Gough
- ASUS M4N78 SE
Reported by Dima Veselov
- ASUS P5LD2-VM
Mark board enable as tested (reported by Dima Veselov)
- GIGABYTE GA-970A-UD3P (rev. 2.0)
Reported by trucmar on IRC
- GIGABYTE GA-990FXA-UD3 (rev. 4.0)
Reported by ROKO__ on IRC
- GIGABYTE GA-H77-DS3H (rev. 1.1)
Reported by Evgeniy Edigarev
- GIGABYTE GA-P55-USB3 (rev. 2.0)
Reported by Måns Thörnqvist
- MSI MS-7817 (H81M-E33)
Reported by Igor Kolker
Chipsets:
- Marked Intel Bay Trail (0x0f1c) as tested OK
Reported by Antonio Ospite
- Refine Intel IDs
* Add IDs for Braswell
* Add IDs for 9 Series PCHs (e.g. H97, Z97)
* Rename Wellsburg devices slightly
Flash chips:
- Atmel AT25DF041A to PREW (+PREW)
Reported by Tai-hwa Liang
- Atmel AT26DF161 to PREW (+EW)
Reported by Steve Shenton
- Atmel AT45DB011D to PREW (+PREW)
Reported by The Raven
- Atmel AT45DB642D to PREW (+PREW)
Reported by Mahesh Mokal
- Eon EN25F32 to PREW (+PREW)
Reported by Arman Khodabande
- Eon EN25F40 to PREW (+REW)
Reported by Jerrad Pierce
- Eon EN25QH16 to PREW (+EW)
Reported by Ben Johnson
- GigaDevice GD25Q20(B) to PREW (+PREW)
Reported by Gilles Aurejac
- Macronix MX25U6435E/F to PR (+PR)
Reported by Matt Taggart
- PMC Pm25LV512(A) to PREW (+PREW)
Reported by The Raven
- SST SST39VF020 to PREW (+PREW)
Reported by Urja Rannikko
- Winbond W25Q40.V to PREW (+EW)
Reported by Torben Nielsen
- Add E variants of MX25Lx006 (MX25L2006E, MX25L4006E, MX25L8006E).
- Add MX25L6465E variant.
- There was never a MX25L12805 AFAICT.
- Split MX25L12805 from models with the same ID but an additional 32 kB
eraser: MX25L12835F/MX25L12845E/MX25L12865E.
- Add a bunch of ST parallel NOR flash chip IDs.
Miscellaneous:
- Whitelist ThinkPad X200.
- Constify master parameter of register_master().
- Remove FEATURE_BYTEWRITES because it was never used at all.
- Refine hwseq messages and make them less prominent.
- Fix the yet unused PRIxCHIPADDR format string thingy.
- Fix copy&paste error in spi_prettyprint_status_register_bp().
Spotted by Pablo Cases.
- Add an additional SMBus controller revision to identify another Yangtze
model. Thanks to Dan Christensen for reporting this issue.
- dediprog: add missing include for stdlib.h.
This fixes (at least) building on FreeBSD and DragonflyBSD with gcc.
- Remove references to struct pci_filter from programmer.h.
It is only needed in internal.c where it has a complete type. Having
it in programmer.h provokes a warning by some old versions of gcc.
- Tiny other stuff.
Corresponding to flashrom svn r1879.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
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Strnlen() is in POSIX 2008 but was a GNU extension up to glibc 2.10
requiring to define _GNU_SOURCE. This fixes compilation on CentOS 4.9.
Also, move our implementation of strnlen() that was added to support
DJGPP to helpers.c.
Corresponding to flashrom svn r1878.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
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We do CPU architecture checks once for the makefile in arch.h and
once for HW access abstraction in hwaccess.c. This patch unifies
related files so that they can share the checks to improve
maintainability and reduce the chance of inconsistencies.
Furthermore, it refines some of the definitions, which
- adds "support" for AARCH64 and PPC64,
- adds big-endian handling on arm as well as LE handling on PPC64,
- fixes compilation of internal.c on AARCH64 and PPC64.
Additionally, this patch continues to unify all OS checks in
flashrom by adding a new helper macro IS_WINDOWS.
The old header file for architecture checking is renamed to platform.h
to reflect its broader scope and all new macros are add in there.
Corresponding to flashrom svn r1864.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
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Corresponding to flashrom svn r1853.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
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- Introduce a variable in doit() that allows to influence
read-before-write and its consequences.
- Modify build_new_image so that it still works even if the old content
is not read before.
- Add copy_old_content() to ease the pain for future patches.
Corresponding to flashrom svn r1851.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
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The former will be useful in cases where cleanup equals a simple call to free().
Corresponding to flashrom svn r1848.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
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- Create distinct functions for mapping and unmapping for flash chips.
- Map only when needed: map before probing and unmap immediately
after it. Map again when a single chip was probed successfully before
taking any actual actions and clean up afterwards.
- Map special function chip registers centrally together with flash space
instead of within (some) probing methods after successful probes.
- Save the used base addresses of the mappings in struct flashctx as well.
- Do not try to (un)map the zero-sized chip definitions that are merely hacks.
This also fixes the printing of wrong warnings for these chip definitions
introduced in r1765.
Corresponding to flashrom svn r1847.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
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Begin to move functions that clearly belong to the (command line)
user interface out of flashrom's core files like flashrom.c.
- Refine messages within check_chip_supported(), rename it to
print_chip_support_status() and move it to newly created cli_common.c.
- Move flashbuses_to_text() to cli_common.c as well.
- Move global verbosity variables to cli_output.c.
Corresponding to flashrom svn r1841.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
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Tested mainboards:
OK:
- ASUS F2A85-M
Reported by various corebooters
- ASUS M2N-MX SE Plus
Reported by Antonio
- ASUS P5LD2
Reported by François Revol
- Lenovo ThinkPad T530
Reported and partially authored by Edward O'Callaghan
- MSI MS-7502 (Medion MD8833)
Reported by naq on IRC
- Shuttle AB61
Reported by olofolleola4
- ZOTAC IONITX-F-E
Reported by Bernardo Kuri
Flash chips:
- Atmel AT45DB021D to PREW (+PREW)
Reported by The Raven
- Atmel AT25F4096 to PREW (+PREW)
Reported by 공준혁
- GigaDevice GD25Q16(B) to PREW (+PREW)
Reported by luxflow@live.com using a GD25Q16BSIG
- Catalyst CAT28F512
Mark erase and write as known bad (not implemented)
Miscellaneous:
- Various spelling corrections by Daniele Forsi.
- Added and refined a bunch of chips originally investigated by Carl-Daniel.
- Marked the ARM-USB-OCD-H programmer as tested
(reported by Ruud Schramp).
- Tiny other stuff.
Corresponding to flashrom svn r1839.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
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Register_programmer suggests that we register a programmer. However,
that function registers a master for a given bus type, and a programmer
may support multiple masters (e.g. SPI, FWH). Rename a few other
functions to be more consistent.
Corresponding to flashrom svn r1831.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
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Add support for EEPROMs with 1 byte granularity and implicit erase on
write. flashrom will not try to erase before write on these chips.
Explicitly requested erase with -E is done by writing 0xff.
Corresponding to flashrom svn r1822.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
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Move some suitable functions there, add it to the Makefile, but leave the
declarations in flash.h for now.
Corresponding to flashrom svn r1819.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
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Stefan Reinauer has reported ridiculous NULL checks for arrays in our
self_check function found by Coverity (CID1130005). This patch removes
the useless checks but keeps and fixes the one responsible for the
flashchips array by exporting the array size in a new constant.
Corresponding to flashrom svn r1799.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
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The new enum test_state looks like this:
enum test_state {
OK = 0,
NT = 1, /* Not tested */
BAD, /* Known to not work */
DEP, /* Support depends on configuration (e.g. Intel flash descriptor) */
NA, /* Not applicable (e.g. write support on ROM chips) */
};
The second new state 'NA' is introduced, among other things, to indicate
the erase and write states of real ROMs correctly. This is also implemented
by this patch and required to exchange the previous bit mask in struct
flashchip with a new struct containing an enum test_state for each operation.
The -L output is changed accordingly to print '-' in the case of an N/A state
and the wiki output uses a new template producing a greyed out cell.
Previous users of enum test_state are not affected by this change (yet).
Corresponding to flashrom svn r1798.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
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Corresponding to flashrom svn r1789.
Inspired by and mostly based on a patch
Signed-off-by: Mark Marshall <mark.marshall@omicron.at>
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
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Corresponding to flashrom svn r1784.
Signed-off-by: Michael Coppola <michael.n.coppola@gmail.com>
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
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There is no reason for negative delays in our use cases:
- We don't need it (to work around any quirks).
- sleep() (POSIX) uses an unsigned argument.
- usleep() (POSIX) uses an unsigned argument.
- Sleep() (Windows) uses an unsigned argument.
Change all callees as well (without any complications).
Corresponding to flashrom svn r1782.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
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This fixes a SEGFAULT if a layout entry is included that addresses memory
outside the current chip's address range. flashrom will only abort if the
offending region(s) is/are included else it will just warn.
It will print warnings for regions with negative or zero-length address ranges
and bail out after checking all of them.
Also, abort for non-write operations if a layout file is given because there is
no layout support for other operations yet.
Corresponding to flashrom svn r1751.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
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Add layout_cleanup() to layout.c and hook it up in cli_classic.c.
Corresponding to flashrom svn r1749.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
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Tested mainboards:
OK:
- ASUS C60M1-I
http://www.flashrom.org/pipermail/flashrom/2013-February/010578.html
- ASUS P8H77-I
http://www.flashrom.org/pipermail/flashrom/2013-March/010607.html
- ASUS P8H77-M
http://www.flashrom.org/pipermail/flashrom/2013-May/010994.html
- ASUS P8P67 LE (B2)
http://www.flashrom.org/pipermail/flashrom/2013-May/010972.html
- Elitegroup GeForce6100PM-M2 (V3.0)
http://www.flashrom.org/pipermail/flashrom/2013-July/011177.html
- GIGABYTE GA-P55A-UD7
http://www.flashrom.org/pipermail/flashrom/2013-July/011302.html
- MSI B75MA-E33 (MS-7808)
http://www.flashrom.org/pipermail/flashrom/2013-March/010659.html
- MSI H77MA-G43 (MS-7756)
http://www.flashrom.org/pipermail/flashrom/2013-April/010853.html
- MSI KA780G (MS-7551)
http://paste.flashrom.org/view.php?id=1617
- SAPPHIRE IPC-E350M1
Reported by xvilka on IRC
- Supermicro X8DTG-D
http://www.flashrom.org/pipermail/flashrom/2013-July/011305.html
NOT OK:
- ASRock Fatal1ty Z77 Performance
http://www.flashrom.org/pipermail/flashrom/2013-January/010467.html
- ASRock Z68 Extreme4
http://www.flashrom.org/pipermail/flashrom/2013-May/010984.html
- ASUS P8B75-M LE
http://www.flashrom.org/pipermail/flashrom/2013-April/010867.html
- ASUS P8P67-M PRO
http://www.flashrom.org/pipermail/flashrom/2013-February/010541.html
- ASUS P8Z68-V LE
http://www.flashrom.org/pipermail/flashrom/2013-February/010582.html
- Intel DQ77MK
http://paste.flashrom.org/view.php?id=1603
- Supermicro X9DRD-7LN4F
http://paste.flashrom.org/view.php?id=1582
- Supermicro X9SCE-F
http://www.flashrom.org/pipermail/flashrom/2013-February/010588.html
- Supermicro X9SCM-F
http://www.flashrom.org/pipermail/flashrom/2013-February/010527.html
- Tyan S7066
http://www.flashrom.org/pipermail/flashrom/2013-March/010630.html
Chipsets:
- Marked Intel B75 as tested
http://www.flashrom.org/pipermail/flashrom/2013-March/010659.html
- Marked Intel H77 as tested
http://www.flashrom.org/pipermail/flashrom/2013-March/010607.html
- Removed 10de:03e2 because it is apparently the MCP61 host bridge.
It was reclassified to Host Bridge in the PCI device ID database and there
is at least one report suggesting this configuration too:
http://www.flashrom.org/pipermail/flashrom/2012-August/009716.html
- Added MCP89 which hopefully works with the code for previous versions.
Thanks to James Laird for submitting this change.
Tested flash chips:
- Atmel AT25DF641(A) to PREW (+PREW)
http://www.flashrom.org/pipermail/flashrom/2013-June/011113.html
- Atmel AT25F512 to PREW (+PREW)
http://www.flashrom.org/pipermail/flashrom/2013-April/010904.html
Also, change its ID according to Modification of PCN SC040401A:
"There has been a change in the returned value of the Product Identification
(RDID) command, the AT25F512A RDID code is 65h compared to 60h from
the AT25F512 product."
It seems to be quite likely that all AT25F512 are fully functional relabeled
AT25F1024 chips. There are even some hints in the datasheet:
in table 6 they stress that address pin 16 needs to be low under all circum-
stances; while continuous reads can wrap around on the AT25F1024 the DS
notes "For the AT25F512, the read command must be terminated when the
highest address (00FFFF) is reached." OTOH the lock bit semantics are
different, but this has not been tested thoroughly
- Atmel AT25F512A to PREW (+PREW)
http://paste.flashrom.org/view.php?id=1569
- Eon EN25F05 to PREW (+PREW)
http://paste.flashrom.org/view.php?id=1571
- Macronix MX25L12805(D) to PREW (+REW)
http://www.flashrom.org/pipermail/flashrom/2013-April/010913.html
- Spansion S25FL256S......0 and S25FL512S to P/!R!E!W (+P)
Tested by Stefan Tauner
- Micron/Numonyx/ST M25PX80 to PREW (+PREW)
Tested by Stefan Tauner
- Micron/Numonyx/ST N25Q032..3E and N25Q128..3E to PREW (+PREW)
Tested by Stefan Tauner
- Micron/Numonyx/ST N25Q256..3E and N25Q512..3G to P/!R!E!W (+P)
Tested by Stefan Tauner
- SST SST25VF040B to PREW (+PREW)
http://paste.flashrom.org/view.php?id=1574
- SST SST25VF040B.REMS to PREW (+EW)
http://paste.flashrom.org/view.php?id=1575
- ST M25P05-A to PREW (+PREW)
http://paste.flashrom.org/view.php?id=1576
- ST M29W512B to PREW (+W)
http://www.flashrom.org/pipermail/flashrom/2013-March/010635.html
- Winbond W25Q64.W to PREW (+PREW)
Tested by the chromiumos guys.
- Winbond W25Q128.V to PREW (+REW)
http://www.flashrom.org/pipermail/flashrom/2013-June/011108.html
- Winbond W25X20 to PREW (+PREW)
http://www.flashrom.org/pipermail/flashrom/2013-May/010990.html
Miscellaneous:
- Add Lenovo X201 to the laptop whitelist.
- Add chip IDs for the ESMT F25L..QA family.
- Add chip IDs for a few Macronix MX25 models.
- The list of flashchips is not sorted strictly alphabetically and should not be
either. Refine the comment explaining the scheme on top of the list.
- Support -L output of chip sizes with up to 6 decimal places (up to 4 Gb).
- Use z length modifier in (more) prints for size_t types.
- Remove chips >16MB again because our current implementation of memory mapping
the flash chip violates common rules by mapping a window as large as the chip.
This leads to failing mmaps as can be seen here:
http://paste.flashrom.org/view.php?id=1695
- Document spispeed parameter of linux_spi (and fix some leaks).
- Rephrase the "multiple chips detected" message because it was confusing.
- Skip verification step if the image is equal to the flash contents.
- Tiny other stuff.
Corresponding to flashrom svn r1702.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
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Unsigned long is not the right type for manipulating pointer values.
Since C99 there are suitable unsigned and signed types available, namely
uintptr_t and intptr_t respectively.
Use them in functions assigned to programmers' map_flash_region fields and
their callers where applicable.
This patch also changes the display width of all associated address values in
physmap.c to 16/8 hex characters depending on the actual size by
introducing a macro PRIxPTR_WIDTH and exploiting printf's * field width
specifier.
Corresponding to flashrom svn r1701.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
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Corresponding to flashrom svn r1698.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
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