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* flashchips: Add Macronix MX25V1635F supportPoroCYon2023-03-262-0/+36
| | | | | | | | | | | | | | | See https://www.mxic.com.tw/Lists/Datasheet/Attachments/8662/MX25V1635F,%202.5V,%2016Mb,%20v1.4.pdf . I've tested this patch with the MX25V1635F I have here, using serprog and ftdi by (re)writing a few images to the flash and seeing if changes were stored correctly. This also included erasing and rewriting the memory with completely different data, so erase is tested, too. Change-Id: I58ddaaa96ef410d50dde3aaa20376c5bbf0f370b Signed-off-by: PoroCYon <p@pcy.be> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* flashchips: Add Macronix MX25V8035F supportPoroCYon2023-03-262-0/+36
| | | | | | | | | | | | | | | See https://www.macronix.com/Lists/Datasheet/Attachments/8405/MX25V8035F,%202.5V,%208Mb,%20v1.0.pdf . I've only tested this patch with the MX25V1635F I have here, though other chips in the series exist as well. Tested using serprog and ftdi by writing a few images to the flash and seeing if changes were stored correctly. Change-Id: Ic5be2da4cfa2a2ff044a519bb6f367f21c15e4b8 Signed-off-by: PoroCYon <p@pcy.be> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* flashchips: Add Macronix MX25V4035F supportPoroCYon2023-03-262-0/+37
| | | | | | | | | | | | | | | See https://www.macronix.com/Lists/Datasheet/Attachments/8670/MX25V4035F,%202.5V,%204Mb,%20v1.2.pdf . I've only tested this patch with the MX25V1635F I have here, though other chips in the series exist as well. Tested using serprog and ftdi by writing a few images to the flash and seeing if changes were stored correctly. Change-Id: I8b26926c354b840ca7b14b4c5cb000e3c02f5137 Signed-off-by: PoroCYon <p@pcy.be> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73582 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* MAINTAINERS: Re-order programmer entries alphabeticallyAnastasia Klimchuk2023-03-241-5/+5
| | | | | | | | | Change-Id: I7e9013fd4cd3b9ea6ecdb45fabbc3c57c4076a17 Signed-off-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73965 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Miklós Márton <martonmiklosqdev@gmail.com>
* tree/: Convert printlock func ptr into enumerate valuesEdward O'Callaghan2023-03-224-97/+135
| | | | | | | | | | | | | | | | | | | Converting the printlock function pointer within the flashchip struct into enum values allows for the flashchips db to be turn into pure, declarative data. A nice side-effect of this is to reduce link-time symbol space of chipdrivers and increase modularity of the spi25_statusreg.c and related implementations. BUG=none TEST=ninja test. Change-Id: I9131348f72c1010e2c213dca4dc4b675a8d8681e Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/69934 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Nikolai Artemiev <nartemiev@google.com>
* Revert "pcidev: remove pcidev_getdevfn() function"Thomas Heijligen2023-03-203-2/+10
| | | | | | | | | | | | | | | As Edward pointed out correctly this function does more than abstracting the different versions of `pci_get_dev()`. It also hide the usage of the global `struct pci_access pacc` from the caller. This reverts commit 0e8902f1ff2b927bb91a5e89e4fde3d8d71f6692. Change-Id: I0cd2f54cb6a6e35dc353476e0f5e502cbbd06cba Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73730 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* tree/: Convert unlock func ptr into enumerate valuesEdward O'Callaghan2023-03-208-74/+130
| | | | | | | | | | | | | | | | | | | Converting the blockprotect unlock function pointer within the flashchip struct into enum values allows for the flashchips db to be turn into pure, declarative data. A nice side-effect of this is to reduce link-time symbol space of chipdrivers and increase modularity of the spi25_statusreg.c and related implementations. BUG=none TEST=ninja test. Change-Id: Ie5c5db1b09d07e1a549990d6f5a622fae4c83233 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/69933 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* tests: Add wrap for __fstat50 to fix tests for NetBSDAnastasia Klimchuk2023-03-163-0/+8
| | | | | | | | | | | | | | Tested by running unit tests on NetBSD 9.2 Ubuntu 22.04.1 (still pass) Change-Id: Icb8e453328cb40ab9d628f01ecdc3886a233dad5 Signed-off-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Tested-by: Thomas Heijligen <src@posteo.de> Reviewed-by: Thomas Heijligen <src@posteo.de> Reviewed-by: Peter Marheine <pmarheine@chromium.org>
* MAINTAINERS: Add Nikolai Artemiev for raiden_debug_spiNikolai Artemiev2023-03-141-0/+5
| | | | | | | | | | | | | | BUG=none BRANCH=none TEST=none Change-Id: Ie70eafb301b3363caa8e670b67a16cd25c7e15a8 Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73697 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* MAINTAINERS: Add Aarya Chaumal for erasure_layoutAarya Chaumal2023-03-141-0/+6
| | | | | | | | | Change-Id: Id0188add883336f2fb494e4169a668e8b502682f Signed-off-by: Aarya Chaumal <aarya.chaumal@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73642 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* fmap: ignore areas with zero sizePeter Marheine2023-03-141-0/+10
| | | | | | | | | | | | | | | | | | | | | | | It's impossible for flashrom_layout to represent zero-sized flash regions but it is possible for a fmap to contain a zero-sized region which causes the resulting layout to fail layout_sanity_checks(), preventing use of that fmap. Because it would very rarely make sense to be able to operate on zero-sized regions anyway and changing layouts to be able to support zero-size regions would entail large changes, instead ignore zero-size regions when present in fmap. TEST=Warning is now printed when using fmap that contains a zero-sized area, and operations on other regions are allowed to proceed. BUG=b:271933192 Change-Id: Ie20971f779acece7a0b3b8f38796fff128ce689a Signed-off-by: Peter Marheine <pmarheine@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73571 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* pcidev: remove pcidev_getdevfn() functionThomas Heijligen2023-03-103-10/+2
| | | | | | | | | | | This function is only called once. Move the content of the function into the caller. Change-Id: Id2983420080f75ae6992edfb032bf5c83b29c803 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73570 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* libpci: drop support for pciutils < 2.2.0Thomas Heijligen2023-03-105-40/+16
| | | | | | | | | | | | | | This version was released in september 2005 and had a breaking api change. Drop it so that we don't need to maintain the old codepath any longer. Beside that, we have already a second codepath which is using the new `pci_get_dev` variant exclusively. Change-Id: If943db350b561a005d8292a53d9255223db3d571 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73293 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* include/pci.h: Use __has_include() macro to test pci.h pathThomas Heijligen2023-03-101-3/+7
| | | | | | | | | | | | | | | Some NetBSDs have the pci.h under pciutils/ instead of pci/. But we can't say for sure which variants uses which include path. Just test them with the __has_include() compiler macro. https://gcc.gnu.org/onlinedocs/cpp/_005f_005fhas_005finclude.html Change-Id: Ib20de6bffede910b89937f554b4d56f4799f0762 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73292 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* MAINTAINERS: Add Jean THOMAS for DirtyJTAGJean THOMAS2023-03-101-0/+5
| | | | | | | | | Signed-off-by: Jean THOMAS <virgule@jeanthomas.me> Change-Id: I0d45b9c634dd6f7509e366723e7fe727f0d087cd Reviewed-on: https://review.coreboot.org/c/flashrom/+/73552 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* flashchips: Mark AM29LV040B as write-testedAnastasia Klimchuk2023-03-061-1/+1
| | | | | | | | | | | | | Reported by Alex Perez on the mailing list, write operation done successfully with satasii programmer. https://mail.coreboot.org/hyperkitty/list/flashrom@flashrom.org/thread/67OX4CSBGWAGMNGEOATBJGFJCKFD64SU/ Change-Id: I8a42f8214b09c455a10a1f1e9e69feaeca2c62a1 Signed-off-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73429 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* flashchips: Mark XMC XM25QH64C as TEST_OK_PREWThomas Heijligen2023-03-061-1/+1
| | | | | | | | | | | | | As reported on the mailing list[0] this flashchip was successfully probed, read, erased and written with a ch341a programmer. [0] https://mail.coreboot.org/hyperkitty/list/flashrom@flashrom.org/message/SMIHEXHZBSCGE2Y2EG75XQHWSKEQ3PP6 Change-Id: Ifca84d9a44bb20091293356f5b1643de41220b64 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73363 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* flashchips: Mark XMC XM25QH256C as TEST_OK_PRThomas Heijligen2023-03-061-1/+1
| | | | | | | | | | | | | As reported on the mailing list[0] this flashchip was successfully probed and read with a ch341a programmer. [0] https://mail.coreboot.org/hyperkitty/list/flashrom@flashrom.org/message/BFBKAJKURZHYQ6OTV3UAA7V5O2ZSJWGN Change-Id: I68d0315f7b29f27ac84374ea7cc69dca207bbacb Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73362 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* meson: fix typo "documtation" -> "documentation"Thomas Heijligen2023-03-031-1/+1
| | | | | | | | | | | | When building with -Ddocumentation=enabled/disabled this typo terminates meson because meson can't find the misspellt option. Change-Id: Ia4205b89fd0d7e77ecbcd29392187d8911dd1049 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73394 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* meson: revert to meson version 0.53.0Thomas Heijligen2023-03-033-6/+3
| | | | | | | | | | | | | | | | Debian Bullseye, current stable release, ships only with meson 0.56.2. To go back to an older meson version pass the project_version info as parameter to `sphinx-build` instead of using an environment variable. This is done by overriding the `release` variable in conf.py with `-Drelease=meson.project_version()` at the command line call. Change-Id: Iff9b8307c741a247a652cf666935c9485fa493fa Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73361 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Alexander Goncharov <chat@joursoir.net> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* tree/: Drop default_spi_probe_opcode for NULL caseEdward O'Callaghan2023-03-0329-35/+10
| | | | | | | | | | | | | | | | | | | A NULL func pointer is necessary and sufficient for the condition `NULL func pointer => true' as to not need this boilerplate as it implies default behaviour of a supported opcode within the `check_block_eraser()` match supported loop. Ran; ``` $ find . -name '*.[c,h]' -exec sed -i '/.probe_opcode = default_spi_probe_opcode,/d' '{}' \; ``` Change-Id: Id502c5d2596ad1db52faf05723083620e4c52c12 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/70264 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* spi: Make default cmd helpers static internalEdward O'Callaghan2023-03-032-23/+19
| | | | | | | | | | | | | | | | | | | | Avoid these leaking into driver implementations as a NULL field now implies their implementation. This removes one source of a driver bug where both `mst->command` AND `mst->multicommand` are set to default implementations which is actually a cyclical control flow condition. The driver however must still have either `mst->command` OR `mst->multicommand` defined and so both cannot be NULL. This simplifies the code and driver development. Change-Id: I4ef95846c2f005cf4aa727f31548c6877d2d4801 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73337 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* writeprotect: Add function to get register values and WP bit masksNikolai Artemiev2023-03-035-0/+101
| | | | | | | | | | | | | | | | | | | | | | | Add a new wp_cfg_to_reg_values() function that takes a generic wp_cfg instance and returns the chip-specific values that need to be written to the chip's registers to enable the specified protection range/mode. The function returns three values for each chip register: - reg_values[reg] - Value writeprotect will write to reg - bit_masks[reg] - Bit mask for WP-related bits in reg - write_masks[reg] - Bit mask for writable WP-related bits in reg (i.e. the ones writeprotect will try to write) BUG=b:260019525,b:259013033,260020006 BRANCH=none TEST=ninja test Change-Id: Ib2a47153b230c9f82bb4eca357c335f2abbacc20 Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/69847 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
* dummyflasher: Add basic WP support for opaque VARIABLE_SIZE chipNikolai Artemiev2023-03-021-0/+30
| | | | | | | | | | | | | | | | | | | | | | | Since VARIABLE_SIZE emulated chips do not correspond to actual flash chip models, no active protection modes are supported: - read_wp_cfg always returns mode=disabled,range=0,0 - write_wp_cfg only accepts mode=disabled,range=0,0 However this is sufficient to support use cases where the user just needs to verify that write protection is not enabled, as is the case in some futility unit tests. BUG=b:238694831,b:260531154 BRANCH=none TEST=none Change-Id: I4348e0175b8c743365904f5e61fdb69e3f4f4db5 Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73289 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Thomas Heijligen <src@posteo.de> Tested-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* spi: Make 'default_spi_send_multicommand' the default unless definedEdward O'Callaghan2023-03-0125-30/+5
| | | | | | | | | | | | | | | | | | | A NULL func pointer is necessary and sufficient for the condition `NULL func pointer => default_spi_send_multicommand' as to not need this explicit specification of 'default'. Therefore drop the explicit need to specify the 'default_spi_send_multicommand' callback function pointer in the spi_master struct. This is a reasonable default for every other driver in the tree with only a few exceptions. This simplifies the code and driver development. Change-Id: I6cc24bf982da3d5251d391eb397db43dd10280e8 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/67481 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* doc/classic_cli_manpage: add missing chip for ft2232_spi programmerAlexander Goncharov2023-03-011-1/+1
| | | | | | | | | | | FTDI FT4233H chip was added in commit bc2e3b6b79dd1383cdf3d965df2fc5c0d6596b02 Change-Id: Id25f6444bfe871f7b01ae2caff23ce973b44567a Signed-off-by: Alexander Goncharov <chat@joursoir.net> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73260 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* move manpage to sphinxThomas Heijligen2023-03-019-1870/+1468
| | | | | | | | | | | | | | | | | | | | | | | | | Use sphinx (sphinx-doc.org) to generate the UNIX man page from an reStructuredText file instead of dealing with plain groff. Use `meson setup -Dman-pages=enabled` to build the man page, and `meson setup -Ddocumentation=enabled` to build the web documentation explicitly. Both are enabled automatically if sphinx-build is found. The man page will be installed as `<meson_mandir>/man8/flashrom.8` and The html documentation in <meson_datadir>/doc/flashrom/html`. The Makefile builds only the man-page format. Increase the minimum version of meson from 0.53.0 to 0.57.0 to be able to pass environment variables to the custom_target() command. That is needed to pass the FLASHROM_VERSION to the documentation. Change-Id: Iee9f1164c5913e47385e6f7d51dc7775a58b5a67 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/72619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Alexander Goncharov <chat@joursoir.net>
* spi: Make 'default_spi_send_command' the default unless definedEdward O'Callaghan2023-02-272-5/+5
| | | | | | | | | | | | | | | | | A NULL func pointer is necessary and sufficient for the condition `NULL func pointer => default_spi_send_command' as to not need this explicit specification of 'default'. Therefore drop the explicit need to specify the 'default_spi_send_command' callback function pointer in the spi_master struct. This is a reasonable default for every other driver in the tree with only a few exceptions. This simplifies the code and driver development. Change-Id: I63abcb8c64f233cdbf58a149a31051fa648305a2 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/67480 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* jedec.c: Provide better lexical scope to itermediatesEdward O'Callaghan2023-02-271-10/+6
| | | | | | | | | Change-Id: I8e01d471bb33a933b80760df2c69a4bf3589ba76 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73285 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* jedec.c: Tidy up whitespace and line wrapsEdward O'Callaghan2023-02-271-7/+6
| | | | | | | | | Change-Id: I3f18609709e59cdfc5a853c6e1ae5f53aecacc1a Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73284 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* jedec.c: Add a little more const correctnessEdward O'Callaghan2023-02-271-5/+4
| | | | | | | | | Change-Id: Ic9a76ce3734bd83399c95478a7c0bfc081211124 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73283 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* jedec.c: Rename func to jedec_write_page()Edward O'Callaghan2023-02-271-2/+2
| | | | | | | | | Change-Id: I1be83d5974e305bddceaa34b64e982b774ade0d2 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73282 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* jedec.c: Drop branching non-zero programmer_delay() operandsEdward O'Callaghan2023-02-271-10/+5
| | | | | | | | | | | | | The programmer_delay() function is already tolerant upon zero delay values and will simply just return with a NOP. Therefore there is no need to branch. Change-Id: Ic547669bb16e6ace4fe283e07345fc2d7075d63e Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/72692 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* ch347_spi: Add initial support for the WCH CH347Nicholas Chin2023-02-279-10/+386
| | | | | | | | | | | | | | | | | | | | | | | Add support for the WCH CH347, a high-speed USB to bus converter supporting multiple protocols interfaces including SPI. Currently only mode 1 (vendor defined communication interface) is supported, mode 2 (USB HID communication interface) support will be added later. The code is currently hard coded to use CS1 and a SPI clock of 15 MHz, though there are 2 CS lines and 6 other GPIO lines available, as well as a configurable clock divisor for up to 60MHz operation. Support for these will be exposed through programmer parameters in later commits. This currently uses the synchronous libusb API. Performance seems to be alright so far, if it becomes an issue I may switch to the asynchronous API. Tested with a MX25L1606E flash chip Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Change-Id: I31b86c41076cc45d4a416a73fa1131350fb745ba Reviewed-on: https://review.coreboot.org/c/flashrom/+/70573 Reviewed-by: Thomas Heijligen <src@posteo.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* asm106x: add programmer for ASM106x SATA controllersAlex Badea2023-02-278-9/+190
| | | | | | | | | | | | | | | | | | | | The ASMedia ASM106x series is a PCIe-SATA controller chip. It supports an attached SPI flash chip that can contain configuration and PCI option ROM. The interface is a simple shifter accessed via PCI config space, up to 4 bytes at a time. Add a programmer driver for it. Tested on a G536PCE1061V11 IO-PCE1061-V1.1 PCIe card, and a MPCE2ST-A01 VER006S mini-PCIe card, both with chips marked ASM1061, both enumerate as: 01:00.0 SATA controller [0106]: ASMedia Technology Inc. ASM1062 Serial ATA Controller [1b21:0612] (rev 02) (prog-if 01 [AHCI 1.0]) Subsystem: ASMedia Technology Inc. ASM1062 Serial ATA Controller [1b21:1060] Change-Id: I591b117be911bdb8249247c20530c1cf70f6e70d Signed-off-by: Alex Badea <vamposdecampos@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73037 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* MAINTAINERS: Update unit tests from Supported to MaintainedAnastasia Klimchuk2023-02-271-1/+1
| | | | | | | | Change-Id: I13853c6c48eb4054d2ed7d79bcfc768684914797 Signed-off-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73277 Reviewed-by: Thomas Heijligen <src@posteo.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* MAINTAINERS: flashrom_tester: Change emailEvan Benn2023-02-261-1/+1
| | | | | | | | | | Change-Id: Ic1a53ddbc38e7d63f7b15aa2b31c63a5b65746f9 Signed-off-by: Evan Benn <evanbenn@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* erasure_layout.c: Test erasefn_count before using it to allocate memoryThomas Heijligen2023-02-231-6/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | In erasure_layout.c:create_erase_layout() the layout will be allocated based on erasefn_count, But calling calloc with 0 is unspecified behavior. Also it is not freed when erasefn_count is 0. So test first if erasefn_count is 0, and only when not allocate the memory for *layout. Reported by Coverty Scan: *** CID 1505171: Resource leaks (RESOURCE_LEAK) /erasure_layout.c: 105 in create_erase_layout() 98 if(!layout) { 99 msg_gerr("Out of memory!\n"); 100 return -1; 101 } 102 103 if (!erasefn_count) { 104 msg_gerr("No erase functions supported\n"); >>> CID 1505171: Resource leaks (RESOURCE_LEAK) >>> Variable "layout" going out of scope leaks the storage it points to. 105 return 0; 106 } Change-Id: If13b050ac8525fee44d3f3bf74a9c9b6a8d38399 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73041 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* jedec.c: Move probe_timings decode into sep funcEdward O'Callaghan2023-02-221-11/+19
| | | | | | | | | | | | The chip data structure packed from the flashchips db should have the probe_timing field decoded by its own function. Change-Id: I638518cd537954172eb774f6d15af0db7e06d1ba Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/72609 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* jedec.c: Fold up mask param into funcEdward O'Callaghan2023-02-211-9/+8
| | | | | | | | Change-Id: Iee4b1d5bc850cbeec0de9a1603fe04a3a1855330 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/72631 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* jedec.c: Rewrite control flow procedurallyEdward O'Callaghan2023-02-211-35/+33
| | | | | | | | | | Drop goto usage in fav of loop constructs. Change-Id: I0927ed40e54cc7e114a57dc40e3614f4825a0ca9 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/72608 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* jedec.c: Move printlock stuff into printlock.cEdward O'Callaghan2023-02-214-190/+215
| | | | | | | | | Change-Id: Iacaa16c81e141aac30feb6871700c4fdc9eec8e9 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/72607 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashchips.c: Add reg_bits for W25Q256JW_DTRKapil Porwal2023-02-211-2/+13
| | | | | | | | | | | | | | | | | | | | | | | | Add reg_bits for W25Q256JW_DTR as per the datasheet. BUG=b:263410331 TEST=Verified on google/rex. w/o this patch: Failed to get WP status: WP operations are not implemented for this chip w/ this patch: flashrom -p internal --wp-range 0x0,0x2000000 flashrom -p internal --wp-enable flashrom -p internal --wp-status flashrom -p internal -E <---- failed to erase the flash as WP (which is expected) Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I8ac23f706d4293a7d7d11ad6b2f62526fb075367 Reviewed-on: https://review.coreboot.org/c/flashrom/+/70549 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* jedec.c: Fold up dst into toggle_ready_jedec()Edward O'Callaghan2023-02-211-10/+5
| | | | | | | | | Change-Id: Ib7a3fdbc6e0a888093dc8da6f5567a7301ec5040 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/72691 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* dummyflasher: use new API to register shutdown functionAlexander Goncharov2023-02-201-15/+26
| | | | | | | | | | | | | | | | | | | | | This allows masters to register shutdown function in *_master struct, which means there is no need to call register_shutdown in init function, since this call is now a part of register_*_master. A dummy programmer can register masters for multiple buses that share a programmer's data (a pointer to struct emu_data) with each other. To avoid unexpected memory freeing by shutdown function, we need to keep track of how many buses are using the shared resource. Use the reference counting technique to achieve this. TEST=ninja test Change-Id: I0c67c25b0f53cd8c564c4ea0f09f2728e856f6ea Signed-off-by: Alexander Goncharov <chat@joursoir.net> Ticket: https://ticket.coreboot.org/issues/391 Reviewed-on: https://review.coreboot.org/c/flashrom/+/72408 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* flashrom.c: Trivial code style fixEdward O'Callaghan2023-02-171-2/+1
| | | | | | | | Change-Id: Iacdb62067a8d22261d4eabe73ad96168eb11417c Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/72968 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
* cli_classic.c: Drop spurious castEdward O'Callaghan2023-02-171-2/+1
| | | | | | | | | | This cast should not be required. Change-Id: Ia3a658dd6f4986eb6da84a11bce66f53e1571469 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/72966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
* jedec.c: Consolidate op,operand sequencing into funcEdward O'Callaghan2023-02-161-52/+19
| | | | | | | | Change-Id: I9a1b211b49777f6d7f62a052975c1759e036c8df Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/72502 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* serial: Add Darwin/macOS support for custom and >230400 baudratesPeter Stuge2023-02-164-0/+71
| | | | | | | | | | | This change is based on the patch proposed by Denis Ahrens in https://review.coreboot.org/c/flashrom/+/67822 Change-Id: I3e6b88d2b4c2a130b16456752681fd9f807bf6f0 Signed-off-by: Peter Stuge <peter@stuge.se> Reviewed-on: https://review.coreboot.org/c/flashrom/+/70571 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* serial: Call set_custom_baudrate() thricePeter Stuge2023-02-164-6/+27
| | | | | | | | | | | | | | | | | | | | | | | Call the function before tcsetattr() settings are known, then again with settings prepared but not yet applied and finally a third time after tcsetattr(). Darwin support needs this change; there custom_baud code must be called to modify the settings passed to tcsetattr() and then again after tcsetattr() returns. The change should be non-functional on all currently supported systems; current code calls set_custom_baudrate() before any tcsetattr() settings are prepared, so we have three stages in total. This change originates from discussion of the macOS patch proposed by Denis Ahrens in https://review.coreboot.org/c/flashrom/+/67822 Change-Id: I40cc443cfb7bf6b212b31826d437b898cc13c427 Signed-off-by: Peter Stuge <peter@stuge.se> Reviewed-on: https://review.coreboot.org/c/flashrom/+/70569 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-26 16:44:51 +0000