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- required time support
- printing ABC version/platform in the output files
- improve AIG rewriting package
- high-effort logic synthesis for hard miters (cofactoring, Boolean division)
- SAT solver with linear constraints
- specialized synthesis for EXORs and large MUXes
- parser for Verilog netlists
- required time based on all cuts
- comparing tts of differently derived the same cut
- area flow based AIG rewriting
- cut frontier adjustment
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