From ec0b9b6b6ed44181aa938dfb581648cf34f4bd28 Mon Sep 17 00:00:00 2001 From: Alan Mishchenko Date: Tue, 16 Sep 2014 22:08:22 -0700 Subject: Improvements to word-level Verilog parser. --- src/base/wlc/wlcWriteVer.c | 1 + 1 file changed, 1 insertion(+) (limited to 'src/base/wlc/wlcWriteVer.c') diff --git a/src/base/wlc/wlcWriteVer.c b/src/base/wlc/wlcWriteVer.c index f7a218e1..3086011a 100644 --- a/src/base/wlc/wlcWriteVer.c +++ b/src/base/wlc/wlcWriteVer.c @@ -87,6 +87,7 @@ void Wlc_WriteVerInt( FILE * pFile, Wlc_Ntk_t * p ) int nDigits = Abc_Base10Log(pObj->End+1) + Abc_Base10Log(pObj->Beg+1); sprintf( Range, "%s[%d:%d]%*s", pObj->Signed ? "signed ":" ", pObj->End, pObj->Beg, 8-nDigits, "" ); fprintf( pFile, " " ); + assert( pObj->Type != WLC_OBJ_TABLE ); if ( pObj->Type == WLC_OBJ_PI ) fprintf( pFile, "input wire %s %-16s", Range, pName ); else if ( pObj->Type == WLC_OBJ_PO ) -- cgit v1.2.3