From de71e5f61038748b59bcbb2bf6f0c8666b45190a Mon Sep 17 00:00:00 2001 From: Alan Mishchenko Date: Mon, 26 Apr 2021 18:52:44 -0700 Subject: Passing node labels. --- src/base/io/ioWriteVerilog.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'src/base/io/ioWriteVerilog.c') diff --git a/src/base/io/ioWriteVerilog.c b/src/base/io/ioWriteVerilog.c index ad49e93a..4c55b599 100644 --- a/src/base/io/ioWriteVerilog.c +++ b/src/base/io/ioWriteVerilog.c @@ -567,6 +567,14 @@ void Io_WriteVerilogObjects( FILE * pFile, Abc_Ntk_t * pNtk, int fOnlyAnds ) Hop_IthVar((Hop_Man_t *)pNtk->pManFunc, k)->pData = Extra_UtilStrsav(Io_WriteVerilogGetName(Abc_ObjName(pFanin))); // write the formula Hop_ObjPrintVerilog( pFile, pFunc, vLevels, 0, fOnlyAnds ); + if ( pObj->fPersist ) + { + Abc_Obj_t * pFan0 = Abc_ObjFanin0(Abc_ObjFanin(pObj, 0)); + Abc_Obj_t * pFan1 = Abc_ObjFanin0(Abc_ObjFanin(pObj, 1)); + int Cond = Abc_ObjIsNode(pFan0) && Abc_ObjIsNode(pFan1) && !pFan0->fPersist && !pFan1->fPersist; + fprintf( pFile, "; // MUXF7 %s\n", Cond ? "":"to be legalized" ); + } + else fprintf( pFile, ";\n" ); // clear the input names Abc_ObjForEachFanin( pObj, pFanin, k ) -- cgit v1.2.3