iCE40/abc - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Changes to LUT mappers.	Alan Mishchenko	2014-02-28	1	-1/+7
*	Changes to LUT mappers.	Alan Mishchenko	2014-02-28	1	-1/+2
*	Changes to LUT mappers.	Alan Mishchenko	2014-02-27	1	-3/+4
*	Changes to LUT mappers.	Alan Mishchenko	2014-02-25	1	-4/+6
*	Changes to LUT mappers.	Alan Mishchenko	2014-02-25	1	-1/+1
*	Changes to LUT mappers.	Alan Mishchenko	2014-02-19	1	-0/+1
*	Changes to LUT mappers.	Alan Mishchenko	2014-02-17	1	-2/+7
*	Changes to LUT mappers.	Alan Mishchenko	2014-02-17	1	-3/+2
*	Removing unused LMS code.	Alan Mishchenko	2014-02-16	1	-12/+0
*	Significant improvement to LUT mappers (if, &if).	Alan Mishchenko	2014-02-16	1	-19/+24
*	Structural mapper into structures.	Alan Mishchenko	2013-11-12	1	-0/+1
*	Changes in specialized matching.	Alan Mishchenko	2013-10-01	1	-0/+1
*	Experiments with exact matching into LUT structures.	Alan Mishchenko	2013-09-23	1	-0/+1
*	Adding new switch to &if to relax the delay.	Alan Mishchenko	2013-09-16	1	-0/+2
*	Removing some old useless code.	Alan Mishchenko	2013-09-02	1	-1/+0
*	Removing some old useless code.	Alan Mishchenko	2013-09-02	1	-2/+1
*	Adding code to count statistics about decomposable LUT5.	Alan Mishchenko	2013-08-18	1	-0/+1
*	Enabling additional matching feature in the LUT mapper.	Alan Mishchenko	2013-08-12	1	-0/+5
*	Saving delay information after mapping.	Alan Mishchenko	2013-06-26	1	-0/+1
*	Improving integration of the 'if' mapper with GIA.	Alan Mishchenko	2013-06-25	1	-0/+1
*	Adding a wrapper around clock() for more accurate time counting in ABC.	Alan Mishchenko	2013-05-27	1	-1/+1
*	Integrating box library.	Alan Mishchenko	2013-03-08	1	-0/+1
*	Improvements to the hierarchy/timing manager.	Alan Mishchenko	2013-03-05	1	-1/+6
*	Improvements to the hierarchy/timing manager.	Alan Mishchenko	2013-03-05	1	-1/+2
*	Renaming If_Lut_t into If_LibLut_t.	Alan Mishchenko	2012-12-10	1	-15/+15
*	Adding box library.	Alan Mishchenko	2012-12-10	1	-1/+26
*	DSD manager.	Alan Mishchenko	2012-11-20	1	-0/+1
*	DSD manager.	Alan Mishchenko	2012-11-19	1	-2/+4
*	DSD manager.	Alan Mishchenko	2012-11-13	1	-1/+3
*	Improved DSD.	Alan Mishchenko	2012-11-10	1	-1/+6
*	Performance bug fix in choice generation.	Alan Mishchenko	2012-11-09	1	-1/+1
*	Improvements to LMS code.	Alan Mishchenko	2012-11-01	1	-0/+2
*	Move truth table code into a separte file.	Alan Mishchenko	2012-10-28	1	-1/+1
*	Improvements to LMS code.	Alan Mishchenko	2012-10-28	1	-1/+4
*	Improvements to LMS code.	Alan Mishchenko	2012-10-27	1	-0/+1
*	Improvements to the truth table computation in 'if' package.	Alan Mishchenko	2012-10-26	1	-2/+4
*	Added new API to traverse the cut in the mapper.	Alan Mishchenko	2012-10-25	1	-0/+1
*	Integrating GIA with LUT mapping.	Alan Mishchenko	2012-10-24	1	-1/+1
*	Upgrading hierarchy timing manager.	Alan Mishchenko	2012-09-21	1	-3/+2
*	Updated code for lazy man's synthesis.	Alan Mishchenko	2012-07-20	1	-0/+4
*	Updated code for lazy man's synthesis.	Alan Mishchenko	2012-07-15	1	-1/+5
*	Updating project settings to have simpler include paths.	Alan Mishchenko	2012-07-07	1	-3/+3
*	Fixing time primtouts throughout the code.	Alan Mishchenko	2012-07-07	1	-2/+2
*	Changing 'if' to allow for delay optimization on sequential paths only.	Alan Mishchenko	2012-05-20	1	-5/+7
*	Changing 'if' to allow for delay optimization on sequential paths only.	Alan Mishchenko	2012-05-20	1	-7/+8
*	Misc changes.	Alan Mishchenko	2012-05-03	1	-0/+2
*	Adding on-the-fly truth-table minimization.	Alan Mishchenko	2012-04-28	1	-0/+2
*	Enabling mapping into multi-input AND/OR gates.	Alan Mishchenko	2012-03-27	1	-0/+3
*	Alternative way of computing delay in SOP balancing.	Alan Mishchenko	2012-03-16	1	-0/+1
*	Experiment with technology mapping.	Alan Mishchenko	2012-02-22	1	-0/+13