| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | Adding cyclicity check for netlist with boxes. | Alan Mishchenko | 2014-11-10 | 6 | -3/+403 | |
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| * | Removing unauthorized printout in 'pdr'. | Alan Mishchenko | 2014-11-09 | 1 | -1/+1 | |
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| * | Detecting full-adder chains and putting them into white boxes. | Alan Mishchenko | 2014-11-09 | 1 | -0/+60 | |
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| * | Experimental implementation of BMC-related procedures. | Alan Mishchenko | 2014-11-04 | 1 | -0/+86 | |
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| * | Added switches '-c' and '-n' to 'init'. | Alan Mishchenko | 2014-11-02 | 2 | -13/+49 | |
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| * | Compiler warnings. | Alan Mishchenko | 2014-10-28 | 1 | -1/+1 | |
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| * | Changes to enable building external code. | Alan Mishchenko | 2014-10-28 | 3 | -32/+2 | |
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| * | Changes to enable building external code. | Alan Mishchenko | 2014-10-27 | 3 | -378/+376 | |
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| * | Changing switch -v in 'qbf' and '&qbf' to be non-verbose by default. | Alan Mishchenko | 2014-10-26 | 1 | -2/+2 | |
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| * | New command &satenum to enumerate SAT assignments of a miter in a naive way. | Alan Mishchenko | 2014-10-25 | 1 | -0/+69 | |
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| * | Adding switch &fftest -N <num> to detect fixed vars after each <num> iterations. | Alan Mishchenko | 2014-10-25 | 1 | -2/+14 | |
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| * | Merged in sterin/abc (pull request #9) | Alan Mishchenko | 2014-10-23 | 2 | -0/+45 | |
| |\ | | | | | | | make it easy to add intialization functions to Abc_FrameInit()/Abc_FrameEnd() | |||||
| | * | make it easy to add intialization functions to Abc_FrameInit()/Abc_FrameEnd() | Baruch Sterin | 2014-10-22 | 2 | -0/+45 | |
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| * | | One bug fix and two small changes. | Alan Mishchenko | 2014-10-22 | 1 | -2/+2 | |
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| * | | One bug fix and two small changes. | Alan Mishchenko | 2014-10-22 | 2 | -7/+13 | |
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| * | Disabling MiniSAT 2.2 for now. | Alan Mishchenko | 2014-10-21 | 1 | -1/+1 | |
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| * | Compiler problems. | Alan Mishchenko | 2014-10-21 | 1 | -1/+5 | |
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| * | Preparing to work with C++ code. | Alan Mishchenko | 2014-10-21 | 2 | -0/+44 | |
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| * | Adding commands backup/restore. | Alan Mishchenko | 2014-10-21 | 3 | -0/+84 | |
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| * | Adding switch &qbf -q to quantify functional variables. | Alan Mishchenko | 2014-10-20 | 1 | -2/+20 | |
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| * | Improved QBF solver. | Alan Mishchenko | 2014-10-18 | 1 | -2/+125 | |
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| * | Fixed "bm" command hang issue. | grigora | 2014-10-11 | 1 | -7/+6 | |
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| * | Improvements to the parser. | Alan Mishchenko | 2014-10-10 | 1 | -7/+86 | |
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| * | Naive (SAT-only) CEC option. | Alan Mishchenko | 2014-10-10 | 1 | -2/+6 | |
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| * | Bug fix in the bit-blaster. | Alan Mishchenko | 2014-10-10 | 1 | -3/+3 | |
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| * | Improvements to ISOP. | Alan Mishchenko | 2014-10-10 | 2 | -5/+7 | |
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| * | Improvements to ISOP. | Alan Mishchenko | 2014-10-10 | 2 | -4/+10 | |
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| * | Detection of threshold functions. | Alan Mishchenko | 2014-10-08 | 2 | -3/+25 | |
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| * | Bug fix in move_names. | Alan Mishchenko | 2014-10-05 | 1 | -0/+1 | |
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| * | Deriving cell mapping with &if -kz. | Alan Mishchenko | 2014-10-04 | 1 | -1/+6 | |
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| * | Deriving cell mapping with &if -kz. | Alan Mishchenko | 2014-10-04 | 1 | -1/+14 | |
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| * | Deriving AIG after cell mapping. | Alan Mishchenko | 2014-10-03 | 2 | -2/+29 | |
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| * | Bug fix in Verilog writer. | Alan Mishchenko | 2014-10-02 | 1 | -8/+8 | |
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| * | Adding switch -R to 'if'. | Alan Mishchenko | 2014-10-02 | 1 | -27/+39 | |
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| * | Improvements to bit-blaster. | Alan Mishchenko | 2014-10-01 | 2 | -23/+88 | |
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| * | Improvements to bit-blaster. | Alan Mishchenko | 2014-09-30 | 1 | -1/+1 | |
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| * | Improvements to bit-blaster. | Alan Mishchenko | 2014-09-30 | 3 | -75/+120 | |
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| * | Adding options to &flow. | Alan Mishchenko | 2014-09-29 | 1 | -4/+9 | |
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| * | Adding options to &flow2. | Alan Mishchenko | 2014-09-29 | 1 | -4/+9 | |
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| * | Adding options to &flow. | Alan Mishchenko | 2014-09-29 | 1 | -4/+9 | |
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| * | Command to rename files in the same directory. | Alan Mishchenko | 2014-09-28 | 1 | -0/+191 | |
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| * | Adding out-of-bounds checks to AIGER readers. | Alan Mishchenko | 2014-09-28 | 1 | -1/+1 | |
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| * | Adding features to CNF generation. | Alan Mishchenko | 2014-09-28 | 1 | -6/+16 | |
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| * | Renaming DSD commands (dsd_tune -> dsd_match; dsd_clean -> dsd_filter). | Alan Mishchenko | 2014-09-28 | 3 | -11/+51 | |
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| * | Support for sequential designs in word-level Verilog. | Alan Mishchenko | 2014-09-26 | 5 | -79/+196 | |
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| * | Enabling print-out, for each operator, of the percetage of AND nodes after ↵ | Alan Mishchenko | 2014-09-25 | 4 | -14/+35 | |
| | | | | | bit-blasting. | |||||
| * | Printing node type statistics. | Alan Mishchenko | 2014-09-24 | 1 | -33/+57 | |
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| * | Printing node type statistics. | Alan Mishchenko | 2014-09-24 | 1 | -10/+10 | |
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| * | Printing node type statistics. | Alan Mishchenko | 2014-09-24 | 2 | -2/+106 | |
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| * | Bug fix in handling MUXes in Verilog parser, induced by recent changes. | Alan Mishchenko | 2014-09-24 | 1 | -0/+2 | |
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index : iCE40/abc | |
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