| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| ... | |
| * | Preprocessing for multi-output PLA tables. | Alan Mishchenko | 2015-01-31 | 1 | -22/+93 |
| * | Preprocessing for multi-output PLA tables. | Alan Mishchenko | 2015-01-31 | 1 | -45/+61 |
| * | Preprocessing for multi-output PLA tables. | Alan Mishchenko | 2015-01-31 | 1 | -0/+124 |
| * | Integrating barrier buffers. | Alan Mishchenko | 2014-12-13 | 1 | -2/+1 |
| * | Generation of barrier-buffers for hierarchical design. | Alan Mishchenko | 2014-11-11 | 2 | -7/+10 |
| * | Adding cyclicity check for netlist with boxes. | Alan Mishchenko | 2014-11-10 | 2 | -3/+34 |
| * | Deriving AIG after cell mapping. | Alan Mishchenko | 2014-10-03 | 1 | -1/+1 |
| * | Adding out-of-bounds checks to AIGER readers. | Alan Mishchenko | 2014-09-28 | 1 | -1/+1 |
| * | Adding features to CNF generation. | Alan Mishchenko | 2014-09-28 | 1 | -6/+16 |
| * | New word-level representation package. | Alan Mishchenko | 2014-09-12 | 1 | -57/+0 |
| * | Bug fix in transferring timing info. | Alan Mishchenko | 2014-09-09 | 1 | -0/+57 |
| * | Compiler warning. | Alan Mishchenko | 2014-08-27 | 1 | -2/+2 |
| * | Improvements BLIF parser. | Alan Mishchenko | 2014-08-27 | 1 | -0/+126 |
| * | Improvements to power-aware mapping. | Alan Mishchenko | 2014-06-23 | 1 | -1/+1 |
| * | Improvements to CNF generation. | Alan Mishchenko | 2014-06-23 | 1 | -1/+1 |
| * | Improvements to CNF generation. | Alan Mishchenko | 2014-06-23 | 1 | -9/+35 |
| * | Added quick GIG parser. | Alan Mishchenko | 2014-06-19 | 1 | -0/+59 |
| * | Bug fix in writing latch init values in 'write_aiger'. | Alan Mishchenko | 2014-06-17 | 1 | -3/+3 |
| * | Fix PLA reader to correctly report error file numbers. | Alan Mishchenko | 2014-06-02 | 1 | -5/+6 |
| * | add an option to write_cex to write the CEX in AIGER 1.9 format. | Baruch Sterin | 2014-05-12 | 1 | -1/+11 |
| * | Added dumping original object names into a file. | Alan Mishchenko | 2014-04-26 | 1 | -2/+12 |
| * | Renamed Abc_Lib_t into Abc_Des_t and removed some dead code. | Alan Mishchenko | 2014-04-09 | 3 | -249/+17 |
| * | Better CEX minimization and renaming of write_counter into write_cex. | Alan Mishchenko | 2014-04-04 | 1 | -12/+27 |
| * | Adding functionally observable fault testing. | Alan Mishchenko | 2014-03-31 | 1 | -2/+5 |
| * | Improving network visualization in show/&show. | Alan Mishchenko | 2014-03-28 | 1 | -2/+26 |
| * | Adding barrier buffers. | Alan Mishchenko | 2014-03-18 | 3 | -11/+33 |
| * | Adding barrier buffers. | Alan Mishchenko | 2014-03-16 | 3 | -21/+51 |
| * | Changes to LUT mappers. | Alan Mishchenko | 2014-03-09 | 1 | -0/+4 |
| * | Adding check for the presence of precomputed data. | Alan Mishchenko | 2013-12-29 | 1 | -0/+5 |
| * | New command &write_cnf. | Alan Mishchenko | 2013-12-18 | 1 | -0/+66 |
| * | Bug fixes in the above patches. | Alan Mishchenko | 2013-12-03 | 1 | -4/+4 |
| * | Suggested patch of AIG writers. | Alan Mishchenko | 2013-12-03 | 1 | -30/+106 |
| * | Bug fix in writing constants in write_verilog. | Alan Mishchenko | 2013-11-21 | 1 | -1/+1 |
| * | Compiler warnings. | Alan Mishchenko | 2013-10-17 | 1 | -4/+8 |
| * | Debugging and finetuning the flow. | Alan Mishchenko | 2013-09-17 | 2 | -1/+3 |
| * | Unifying standard cell library representations. | Alan Mishchenko | 2013-09-17 | 1 | -1/+1 |
| * | Adding switch 'ps -s' to skip counting buffers/inverters as nodes. | Alan Mishchenko | 2013-09-02 | 1 | -2/+0 |
| * | Removing some old useless code. | Alan Mishchenko | 2013-09-02 | 1 | -4/+0 |
| * | Removing some old useless code. | Alan Mishchenko | 2013-09-02 | 2 | -257/+2 |
| * | Adding support for input slew and output capacitance to timer and gate-sizer ... | Alan Mishchenko | 2013-07-24 | 1 | -2/+20 |
| * | Tuning standard-cell mapping flow. | Alan Mishchenko | 2013-07-23 | 1 | -1/+1 |
| * | Improvements to post-mapping re-sizing. | Alan Mishchenko | 2013-07-21 | 1 | -14/+16 |
| * | Memory leaks. | Alan Mishchenko | 2013-07-21 | 1 | -1/+1 |
| * | Adding support for input slew (.input_drive) and output capacitance (.output_... | Alan Mishchenko | 2013-07-21 | 2 | -0/+211 |
| * | Adding a wrapper around clock() for more accurate time counting in ABC. | Alan Mishchenko | 2013-05-27 | 1 | -18/+18 |
| * | New MFS package. | Alan Mishchenko | 2013-05-24 | 1 | -4/+4 |
| * | Commenting assertion that does not hold in AIGER 1.9, accoring to Baruch Sterin. | Alan Mishchenko | 2013-05-13 | 1 | -1/+1 |
| * | Enabled 'cec' to be applied to networks derived from BLIF with EXDCs. | Alan Mishchenko | 2013-04-18 | 1 | -3/+4 |
| * | Enabled reading the EXDC network by the default BLIF reader. | Alan Mishchenko | 2013-04-18 | 2 | -5/+29 |
| * | Fixing both AIGER readers (read_aiger and &r) to work with AIGER 1.9 (except ... | Alan Mishchenko | 2013-04-18 | 1 | -2/+8 |
