index
:
iCE40/abc
yosys-experimental
[no description]
summary
refs
log
tree
commit
diff
stats
log msg
author
committer
range
Commit message (
Expand
)
Author
Age
Files
Lines
...
*
|
Adding input/output/flop name reading in command &r.
Alan Mishchenko
2021-08-22
4
-2
/
+153
*
|
Support of pair-wise miter and other changes.
Alan Mishchenko
2021-08-22
6
-4
/
+582
*
|
Merge pull request #132 from jamesjer/aliasing
alanminko
2021-08-19
1
-1
/
+3
|
\
\
|
*
|
Fix violation of C strict aliasing rules.
Jerry James
2021-08-09
1
-1
/
+3
*
|
|
Merge pull request #133 from twier/inv_get_name_mangling_fix
alanminko
2021-08-19
2
-9
/
+43
|
\
\
\
|
*
|
|
Add comment to Wlc_NtkGetInv about vNamesIn's role
Tobias Wiersema
2021-08-19
1
-0
/
+2
|
*
|
|
Fix typo inifity -> infinity in inv_get help
Tobias Wiersema
2021-08-19
1
-1
/
+1
|
*
|
|
Add inv_get -f to read flop names from GIA
Tobias Wiersema
2021-08-19
2
-8
/
+40
*
|
|
|
Extending &trim to trim structurally equivalent primary outputs.
Alan Mishchenko
2021-08-19
3
-3
/
+141
|
/
/
/
*
|
|
Improving AIG to Verilog converter.
Alan Mishchenko
2021-08-17
4
-28
/
+76
*
|
|
Suggested changes to collect and pass timing information (unused variable).
Alan Mishchenko
2021-08-12
1
-1
/
+1
*
|
|
Suggested changes to collect and pass timing information (compiler issues).
Alan Mishchenko
2021-08-12
2
-8
/
+6
*
|
|
Suggested changes to collect and pass timing information.
Alan Mishchenko
2021-08-12
2
-13
/
+64
|
/
/
*
|
Making &cec support the miter circuit.
Alan Mishchenko
2021-08-05
1
-0
/
+14
*
|
Supporting simple operators in NDR.
Alan Mishchenko
2021-08-05
4
-13
/
+53
*
|
Adding node ordering options to command &dfs.
Alan Mishchenko
2021-08-05
3
-29
/
+45
*
|
Bug fix.
Alan Mishchenko
2021-08-03
1
-1
/
+1
*
|
Experiments with LUT mapping for small functions.
Alan Mishchenko
2021-08-02
1
-1
/
+0
*
|
Experiments with LUT mapping for small functions.
Alan Mishchenko
2021-08-02
4
-12
/
+275
*
|
Experiments with LUT mapping for small functions.
Alan Mishchenko
2021-08-01
1
-1
/
+1
*
|
Experiments with LUT mapping for small functions.
Alan Mishchenko
2021-08-01
4
-32
/
+255
*
|
Allow retiming to skip some logic.
Alan Mishchenko
2021-07-31
4
-9
/
+69
*
|
Upgrading choice computation.
Alan Mishchenko
2021-07-31
5
-27
/
+38
*
|
Experiments with cofactoring.
Alan Mishchenko
2021-07-31
2
-6
/
+288
*
|
Experimental simulation commands.
Alan Mishchenko
2021-07-25
6
-67
/
+575
*
|
Command to move CI/CO names.
Alan Mishchenko
2021-07-16
1
-2
/
+3
*
|
Command to move CI/CO names.
Alan Mishchenko
2021-07-16
3
-7
/
+237
*
|
Several unrelated changes.
Alan Mishchenko
2021-07-15
4
-9
/
+186
*
|
Experiments with LUT mapping for small functions.
Alan Mishchenko
2021-07-13
5
-4
/
+479
*
|
Experiments with MUX decomposition.
Alan Mishchenko
2021-07-11
1
-1
/
+1
*
|
Experiments with CEC.
Alan Mishchenko
2021-07-10
4
-9
/
+171
*
|
Simple AIGER reader/writer.
Alan Mishchenko
2021-07-09
1
-0
/
+141
*
|
Experiments with MUX decomposition.
Alan Mishchenko
2021-07-08
2
-2
/
+1
*
|
Experiments with MUX decomposition.
Alan Mishchenko
2021-07-08
2
-4
/
+5
*
|
Experiments with MUX decomposition.
Alan Mishchenko
2021-07-08
3
-2
/
+135
*
|
Potential upgrade to 'dsec'.
Alan Mishchenko
2021-06-25
1
-0
/
+24
*
|
Adding place holder file for resub experiments.
Alan Mishchenko
2021-06-24
5
-7
/
+67
*
|
Experiments with LUT mapping for small functions.
Alan Mishchenko
2021-06-19
8
-67
/
+967
*
|
Experiments with cut computation.
Alan Mishchenko
2021-06-08
2
-2
/
+44
*
|
Experiments with cut computation.
Alan Mishchenko
2021-06-05
2
-4
/
+144
*
|
Disabled special handling of 2-input LUTs.
Alan Mishchenko
2021-06-03
1
-1
/
+1
*
|
Disabled special handling of 2-input LUTs.
Alan Mishchenko
2021-06-02
1
-2
/
+4
*
|
Updating LUT synthesis code.
Alan Mishchenko
2021-05-26
4
-7
/
+7
*
|
Updating LUT synthesis code.
Alan Mishchenko
2021-05-25
3
-66
/
+287
*
|
Adding command &extract.
Alan Mishchenko
2021-05-18
2
-1
/
+84
*
|
Fixing memory leak in the SAT sweeper.
Alan Mishchenko
2021-05-16
1
-1
/
+1
*
|
Updating LUT synthesis code.
Alan Mishchenko
2021-05-16
1
-1
/
+2
*
|
Updating LUT synthesis code.
Alan Mishchenko
2021-05-16
8
-127
/
+604
*
|
Adding switch muxes -a to create networks of ADDs.
Alan Mishchenko
2021-05-15
4
-15
/
+38
*
|
Updating LUT synthesis code.
Alan Mishchenko
2021-05-11
2
-38
/
+102
[prev]
[next]