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| author | Alan Mishchenko <alanmi@berkeley.edu> | 2008-07-06 08:01:00 -0700 |
|---|---|---|
| committer | Alan Mishchenko <alanmi@berkeley.edu> | 2008-07-06 08:01:00 -0700 |
| commit | c7b331efcf42c94450d7590eeb0c71c525569c11 (patch) | |
| tree | 6e97476339c41f96ead0825fcc6a3f9bc974acfb /todo.txt | |
| parent | 7b734f23fc23694ccffdb7e3cd31335ffe6cb272 (diff) | |
| download | abc-c7b331efcf42c94450d7590eeb0c71c525569c11.tar.gz abc-c7b331efcf42c94450d7590eeb0c71c525569c11.tar.bz2 abc-c7b331efcf42c94450d7590eeb0c71c525569c11.zip | |
Version abc80706
Diffstat (limited to 'todo.txt')
| -rw-r--r-- | todo.txt | 11 |
1 files changed, 0 insertions, 11 deletions
@@ -1,21 +1,10 @@ - required time support - printing ABC version/platform in the output files -- fix gcc compiler warnings -- port "mfs" from MVSIS - improve AIG rewriting package -- unify functional representation of local functions -- additional rewriting options for delay optimization -- experiment with yield-aware standard-cell mapping -- improving area recovery in integrated sequential synthesis - high-effort logic synthesis for hard miters (cofactoring, Boolean division) -- mapping into MV cells - SAT solver with linear constraints - specialized synthesis for EXORs and large MUXes -- sequential AIG rewriting initial state computation -- placement-aware mapping -- sequential equivalence checking - parser for Verilog netlists -- hierarchy manager (hierarchical BLIF/BLIF-MV parser) - required time based on all cuts - comparing tts of differently derived the same cut |