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| author | Alan Mishchenko <alanmi@berkeley.edu> | 2008-01-30 20:01:00 -0800 |
|---|---|---|
| committer | Alan Mishchenko <alanmi@berkeley.edu> | 2008-01-30 20:01:00 -0800 |
| commit | 0c6505a26a537dc911b6566f82d759521e527c08 (patch) | |
| tree | f2687995efd4943fe3b1307fce7ef5942d0a57b3 /todo.txt | |
| parent | 4d30a1e4f1edecff86d5066ce4653a370e59e5e1 (diff) | |
| download | abc-0c6505a26a537dc911b6566f82d759521e527c08.tar.gz abc-0c6505a26a537dc911b6566f82d759521e527c08.tar.bz2 abc-0c6505a26a537dc911b6566f82d759521e527c08.zip | |
Version abc80130_2
Diffstat (limited to 'todo.txt')
| -rw-r--r-- | todo.txt | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/todo.txt b/todo.txt new file mode 100644 index 00000000..3ab59b8c --- /dev/null +++ b/todo.txt @@ -0,0 +1,26 @@ +- required time support +- printing ABC version/platform in the output files +- fix gcc compiler warnings +- port "mfs" from MVSIS +- improve AIG rewriting package +- unify functional representation of local functions +- additional rewriting options for delay optimization +- experiment with yield-aware standard-cell mapping +- improving area recovery in integrated sequential synthesis +- high-effort logic synthesis for hard miters (cofactoring, Boolean division) +- mapping into MV cells +- SAT solver with linear constraints +- specialized synthesis for EXORs and large MUXes +- sequential AIG rewriting initial state computation +- placement-aware mapping +- sequential equivalence checking +- parser for Verilog netlists +- hierarchy manager (hierarchical BLIF/BLIF-MV parser) + +- required time based on all cuts +- comparing tts of differently derived the same cut +- area flow based AIG rewriting +- cut frontier adjustment + + + |