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| author | Baruch Sterin <baruchs@gmail.com> | 2015-11-05 01:23:31 -0800 | 
|---|---|---|
| committer | Baruch Sterin <baruchs@gmail.com> | 2015-11-05 01:23:31 -0800 | 
| commit | c0ba25a69388765d7057ae8729e12b8a85435e35 (patch) | |
| tree | 98c999fed9d9cf65b6425334e819c8b339fc6025 /src | |
| parent | 8ee49ff150a12f7183fe25e0a8d8e845391c100b (diff) | |
| download | abc-c0ba25a69388765d7057ae8729e12b8a85435e35.tar.gz abc-c0ba25a69388765d7057ae8729e12b8a85435e35.tar.bz2 abc-c0ba25a69388765d7057ae8729e12b8a85435e35.zip  | |
silence clang errors when compiling as C++
Diffstat (limited to 'src')
| -rw-r--r-- | src/aig/gia/giaMuxes.c | 2 | ||||
| -rw-r--r-- | src/base/abc/abc.h | 2 | ||||
| -rw-r--r-- | src/base/abc/abcSop.c | 2 | ||||
| -rw-r--r-- | src/base/bac/bacWriteVer.c | 2 | ||||
| -rw-r--r-- | src/base/cba/cbaNtk.c | 7 | ||||
| -rw-r--r-- | src/base/cba/cbaReadVer.c | 6 | ||||
| -rw-r--r-- | src/base/cba/cbaWriteVer.c | 4 | ||||
| -rw-r--r-- | src/bdd/extrab/extraBddThresh.c | 8 | ||||
| -rw-r--r-- | src/map/scl/sclCon.h | 2 | ||||
| -rw-r--r-- | src/opt/fret/fretInit.c | 32 | ||||
| -rw-r--r-- | src/opt/fret/fretMain.c | 6 | ||||
| -rw-r--r-- | src/opt/fret/fretTime.c | 4 | 
12 files changed, 39 insertions, 38 deletions
diff --git a/src/aig/gia/giaMuxes.c b/src/aig/gia/giaMuxes.c index 50084c8b..3a55d6ca 100644 --- a/src/aig/gia/giaMuxes.c +++ b/src/aig/gia/giaMuxes.c @@ -692,7 +692,7 @@ int Gia_ManEncodeFanin( Gia_Man_t * p, int iLit )  //        return iANDp;  }  // find fanout code -int Gia_ManEncodeFanout( Gia_Man_t * p, Gia_Obj_t * pObj, int i ) +Gia_ObjType_t Gia_ManEncodeFanout( Gia_Man_t * p, Gia_Obj_t * pObj, int i )  {  //    int iLit;      if ( Gia_ObjIsPo(p, pObj) ) diff --git a/src/base/abc/abc.h b/src/base/abc/abc.h index 01aff0aa..55624ec2 100644 --- a/src/base/abc/abc.h +++ b/src/base/abc/abc.h @@ -869,7 +869,7 @@ extern ABC_DLL int                Abc_NtkRewrite( Abc_Ntk_t * pNtk, int fUpdateL  extern ABC_DLL int                Abc_NtkMiterSat( Abc_Ntk_t * pNtk, ABC_INT64_T nConfLimit, ABC_INT64_T nInsLimit, int fVerbose, ABC_INT64_T * pNumConfs, ABC_INT64_T * pNumInspects );  extern ABC_DLL void *             Abc_NtkMiterSatCreate( Abc_Ntk_t * pNtk, int fAllPrimes );  /*=== abcSop.c ==========================================================*/ -extern ABC_DLL char *             Abc_SopRegister( Mem_Flex_t * pMan, char * pName ); +extern ABC_DLL char *             Abc_SopRegister( Mem_Flex_t * pMan, const char * pName );  extern ABC_DLL char *             Abc_SopStart( Mem_Flex_t * pMan, int nCubes, int nVars );  extern ABC_DLL char *             Abc_SopCreateConst0( Mem_Flex_t * pMan );  extern ABC_DLL char *             Abc_SopCreateConst1( Mem_Flex_t * pMan ); diff --git a/src/base/abc/abcSop.c b/src/base/abc/abcSop.c index 1a803c32..62c3ba06 100644 --- a/src/base/abc/abcSop.c +++ b/src/base/abc/abcSop.c @@ -53,7 +53,7 @@ ABC_NAMESPACE_IMPL_START    SeeAlso     []  ***********************************************************************/ -char * Abc_SopRegister( Mem_Flex_t * pMan, char * pName ) +char * Abc_SopRegister( Mem_Flex_t * pMan, const char * pName )  {      char * pRegName;      if ( pName == NULL ) return NULL; diff --git a/src/base/bac/bacWriteVer.c b/src/base/bac/bacWriteVer.c index 45742850..0f00eeef 100644 --- a/src/base/bac/bacWriteVer.c +++ b/src/base/bac/bacWriteVer.c @@ -110,7 +110,7 @@ static void Psr_ManWriteVerilogBoxes( FILE * pFile, Psr_Ntk_t * p )      Vec_Int_t * vBox; int i;      Psr_NtkForEachBox( p, vBox, i )      { -        Bac_ObjType_t NtkId = Psr_BoxNtk(p, i); +        Bac_ObjType_t NtkId = (Bac_ObjType_t)Psr_BoxNtk(p, i);          if ( NtkId == BAC_BOX_MUX )              Psr_ManWriteVerilogMux( pFile, p, vBox );          else if ( Psr_BoxIsNode(p, i) ) // node   ------- check order of fanins diff --git a/src/base/cba/cbaNtk.c b/src/base/cba/cbaNtk.c index d3ed96f5..fee91192 100644 --- a/src/base/cba/cbaNtk.c +++ b/src/base/cba/cbaNtk.c @@ -90,7 +90,8 @@ void Cba_NtkPrintDistrib( Cba_Ntk_t * p, int fVerbose )      Vec_Ptr_t * vTypes, * vOccurs;      Vec_Int_t * vAnds = Vec_IntStart( CBA_BOX_LAST );      int iRnObj = -1, nCountRange = 0; -    int i, k, s, s0, s1, Type;  word Sign; +    int i, k, s, s0, s1;  word Sign; +    Cba_ObjType_t Type;      char * pTypeNames[CBA_BOX_LAST];      Cba_ManCreatePrimMap( pTypeNames );      // allocate statistics arrays @@ -1060,7 +1061,7 @@ Cba_Man_t * Cba_ManDeriveFromGia( Gia_Man_t * pGia, int fUseXor )      Cba_NtkCleanObjNames( pNtk );      Gia_ManForEachCiId( pGia, iObj, i )      { -        NameId = pGia->vNamesIn? Abc_NamStrFindOrAdd(p->pStrs, Vec_PtrEntry(pGia->vNamesIn, i), NULL) : Cba_NtkNewStrId(pNtk, "i%d", i); +        NameId = pGia->vNamesIn? Abc_NamStrFindOrAdd(p->pStrs, (char*)Vec_PtrEntry(pGia->vNamesIn, i), NULL) : Cba_NtkNewStrId(pNtk, "i%d", i);          iObjNew = Cba_ObjAlloc( pNtk, CBA_OBJ_PI, 0, 1 );          Cba_ObjSetName( pNtk, iObjNew, NameId );          Vec_IntWriteEntry( vLit2Fon, Abc_Var2Lit(iObj, 0), Cba_ObjFon0(pNtk, iObjNew) ); @@ -1082,7 +1083,7 @@ Cba_Man_t * Cba_ManDeriveFromGia( Gia_Man_t * pGia, int fUseXor )          iObjNew = Cba_ObjAlloc( pNtk, CBA_BOX_BUF, 1, 1 );          Cba_ObjSetFinFon( pNtk, iObjNew, 0, iFon0 );          iFon0 = Cba_ObjFon0(pNtk, iObjNew); // non-const fon unique for this output -        NameId = pGia->vNamesOut? Abc_NamStrFindOrAdd(p->pStrs, Vec_PtrEntry(pGia->vNamesOut, i), NULL) : Cba_NtkNewStrId(pNtk, "o%d", i); +        NameId = pGia->vNamesOut? Abc_NamStrFindOrAdd(p->pStrs, (char*)Vec_PtrEntry(pGia->vNamesOut, i), NULL) : Cba_NtkNewStrId(pNtk, "o%d", i);          iObjNew = Cba_ObjAlloc( pNtk, CBA_OBJ_PO, 1, 0 );          Cba_ObjSetName( pNtk, iObjNew, NameId );          Cba_ObjSetFinFon( pNtk, iObjNew, 0, iFon0 ); diff --git a/src/base/cba/cbaReadVer.c b/src/base/cba/cbaReadVer.c index 1cbf6b19..ec22e195 100644 --- a/src/base/cba/cbaReadVer.c +++ b/src/base/cba/cbaReadVer.c @@ -1879,7 +1879,7 @@ int Prs_CreateVerilogNtk( Cba_Ntk_t * p, Prs_Ntk_t * pNtk )          if ( Prs_BoxIsNode(pNtk, i) ) // node          {              Type = Prs_BoxNtk(pNtk, i); -            iObj = Cba_ObjAlloc( p, Type, Prs_BoxIONum(pNtk, i)-1, Type == CBA_BOX_ADD ? 2 : 1 ); +            iObj = Cba_ObjAlloc( p, (Cba_ObjType_t)Type, Prs_BoxIONum(pNtk, i)-1, Type == CBA_BOX_ADD ? 2 : 1 );              Prs_CreateSignalOut( p, Cba_ObjFon0(p, iObj), pNtk, Vec_IntEntry(vBox, 1) ); // node output          }          else // box @@ -1921,7 +1921,7 @@ int Prs_CreateVerilogNtk( Cba_Ntk_t * p, Prs_Ntk_t * pNtk )              else if ( (Type == CBA_BOX_DFFRS || Type == CBA_BOX_LATCHRS) && !strncmp(pNtkName, "wide_", strlen("wide_")) && !Prs_CreateFlopSetReset(p, pNtk, vBox, NULL, NULL, NULL, NULL) )                  nInputs = atoi(pNtkName+strlen(Type == CBA_BOX_DFFRS ? "wide_dffrs_" : "wide_latchrs_")), nOutputs = 1, Type = CBA_BOX_CONCAT;              // create object -            iObj = Cba_ObjAlloc( p, Type, nInputs, nOutputs ); +            iObj = Cba_ObjAlloc( p, (Cba_ObjType_t)Type, nInputs, nOutputs );              if ( pBox ) Cba_ObjSetFunc( p, iObj, Cba_NtkId(pBox) );              // mark PO objects              Cba_NtkCleanMap2( p ); @@ -2002,7 +2002,7 @@ int Prs_CreateVerilogNtk( Cba_Ntk_t * p, Prs_Ntk_t * pNtk )                      for ( w = 0; w < Width; w++ )                      {                          // create bit-level flop -                        int iObjNew = Cba_ObjAlloc( p, Type, 4, 1 ); +                        int iObjNew = Cba_ObjAlloc( p, (Cba_ObjType_t)Type, 4, 1 );                          if ( Prs_BoxName(pNtk, i) )                          {                              NameId = Cba_NtkNewStrId( p, "%s[%d]", Prs_NtkStr(pNtk, Prs_BoxName(pNtk, i)), w ); diff --git a/src/base/cba/cbaWriteVer.c b/src/base/cba/cbaWriteVer.c index c6f7b2ac..45c8ed99 100644 --- a/src/base/cba/cbaWriteVer.c +++ b/src/base/cba/cbaWriteVer.c @@ -233,7 +233,7 @@ static void Prs_ManWriteVerilogBoxes( FILE * pFile, Prs_Ntk_t * p, char ** pType      Vec_Int_t * vBox; int i, k;      Prs_NtkForEachBox( p, vBox, i )      { -        Cba_ObjType_t NtkId = Prs_BoxNtk(p, i); +        Cba_ObjType_t NtkId = (Cba_ObjType_t)Prs_BoxNtk(p, i);          //char * pNtkName = Prs_ObjGetName(p, Prs_BoxName(p, i));          if ( NtkId == CBA_BOX_MUX && Prs_BoxIsNode(p, i) )              Prs_ManWriteVerilogMux( pFile, p, vBox ); @@ -918,7 +918,7 @@ void Cba_ManWriteVerilogNtk( Cba_Ntk_t * p, int fInlineConcat )                  Vec_StrPush( vStr, ' ' );                  Cba_ManWriteFonName( p, Cba_ObjFinFon(p, iObj, 2), fInlineConcat, 0 );              } -            else if ( Cba_TypeIsUnary(Type) ) +            else if ( Cba_TypeIsUnary((Cba_ObjType_t)Type) )              {                  Vec_StrPrintStr( vStr, Cba_NtkTypeName(p, Type) );                  Cba_ManWriteFonName( p, Cba_ObjFinFon(p, iObj, 0), fInlineConcat, 0 ); diff --git a/src/bdd/extrab/extraBddThresh.c b/src/bdd/extrab/extraBddThresh.c index 511fc24b..4ac13c68 100644 --- a/src/bdd/extrab/extraBddThresh.c +++ b/src/bdd/extrab/extraBddThresh.c @@ -444,13 +444,13 @@ int Extra_ThreshAssignWeights(word * t, char * pIsop, char * pIsopFneg,      unsigned long **pGreaters;      unsigned long **pSmallers; -    pGreaters = malloc(nCubesIsop * nCubesIsopFneg * sizeof *pGreaters); +    pGreaters = (unsigned long **)malloc(nCubesIsop * nCubesIsopFneg * sizeof *pGreaters);      for (i = 0; i < nCubesIsop * nCubesIsopFneg; i++) { -        pGreaters[i] = malloc(nChows * sizeof *pGreaters[i]); +        pGreaters[i] = (unsigned long *)malloc(nChows * sizeof *pGreaters[i]);      } -    pSmallers = malloc(nCubesIsop * nCubesIsopFneg * sizeof *pSmallers); +    pSmallers = (unsigned long **)malloc(nCubesIsop * nCubesIsopFneg * sizeof *pSmallers);      for (i = 0; i < nCubesIsop * nCubesIsopFneg; i++) { -        pSmallers[i] = malloc(nChows * sizeof *pSmallers[i]); +        pSmallers[i] = (unsigned long *)malloc(nChows * sizeof *pSmallers[i]);      }      //****************************** diff --git a/src/map/scl/sclCon.h b/src/map/scl/sclCon.h index 982b4641..7a7be1b2 100644 --- a/src/map/scl/sclCon.h +++ b/src/map/scl/sclCon.h @@ -236,7 +236,7 @@ static inline int    Scl_ConHasInLoads_( Scl_Con_t * p )        { return Vec_Wrd  static inline int    Scl_ConHasOutReqs_( Scl_Con_t * p )        { return Vec_WrdCountZero(&p->vOutReqs)  != Vec_WrdSize(&p->vOutReqs);  }  static inline int    Scl_ConHasOutLoads_( Scl_Con_t * p )       { return Vec_WrdCountZero(&p->vOutLoads) != Vec_WrdSize(&p->vOutLoads); } -static inline char * Scl_ConGetInCell_( Scl_Con_t * p, int i )  { return Vec_PtrEntry( &p->vInCells,  i ); } +static inline char * Scl_ConGetInCell_( Scl_Con_t * p, int i )  { return (char*)Vec_PtrEntry( &p->vInCells,  i ); }  static inline word   Scl_ConGetInArr_( Scl_Con_t * p, int i )   { return Vec_WrdEntry( &p->vInArrs,   i ); }  static inline word   Scl_ConGetInSlew_( Scl_Con_t * p, int i )  { return Vec_WrdEntry( &p->vInSlews,  i ); }  static inline word   Scl_ConGetInLoad_( Scl_Con_t * p, int i )  { return Vec_WrdEntry( &p->vInLoads,  i ); } diff --git a/src/opt/fret/fretInit.c b/src/opt/fret/fretInit.c index b007ad99..1a937203 100644 --- a/src/opt/fret/fretInit.c +++ b/src/opt/fret/fretInit.c @@ -295,10 +295,10 @@ void Abc_FlowRetime_SimulateNode( Abc_Obj_t * pObj ) {    Abc_Obj_t * pFanin;    int i, rAnd, rVar, dcAnd, dcVar;  #ifdef ABC_USE_CUDD -  DdManager * dd = pNtk->pManFunc; -  DdNode *pBdd = pObj->pData, *pVar; +  DdManager * dd = (DdManager*)pNtk->pManFunc; +  DdNode *pBdd = (DdNode*)pObj->pData, *pVar;  #endif -  Hop_Man_t *pHop = pNtk->pManFunc; +  Hop_Man_t *pHop = (Hop_Man_t*)pNtk->pManFunc;    assert(!Abc_ObjIsLatch(pObj));    assert(Abc_ObjRegular(pObj)); @@ -376,7 +376,7 @@ void Abc_FlowRetime_SimulateNode( Abc_Obj_t * pObj ) {        Hop_ManPi(pHop, i)->fMarkB = FTEST(pFanin, INIT_CARE)?1:0;      } -    Abc_FlowRetime_EvalHop_rec( pHop, pObj->pData, &rVar, &dcVar ); +    Abc_FlowRetime_EvalHop_rec( pHop, (Hop_Obj_t*)pObj->pData, &rVar, &dcVar );      Abc_FlowRetime_SetInitValue(pObj, rVar, dcVar); @@ -415,7 +415,7 @@ void Abc_FlowRetime_SimulateNode( Abc_Obj_t * pObj ) {    // ------ MAPPED network    else if ( Abc_NtkHasMapping( pNtk )) { -    Abc_FlowRetime_SimulateSop( pObj, (char *)Mio_GateReadSop(pObj->pData) ); +    Abc_FlowRetime_SimulateSop( pObj, (char *)Mio_GateReadSop((Mio_Gate_t*)pObj->pData) );      return;    } @@ -622,7 +622,7 @@ int Abc_FlowRetime_SolveBackwardInit( Abc_Ntk_t * pNtk ) {    // clear initial values, associate PIs to latches    Abc_NtkForEachPi( pManMR->pInitNtk, pInitObj, i ) Abc_ObjSetCopy( pInitObj, NULL );    Abc_NtkForEachLatch( pNtk, pObj, i ) { -    pInitObj = Abc_ObjData( pObj ); +    pInitObj = (Abc_Obj_t*)Abc_ObjData( pObj );      assert( Abc_ObjIsPi( pInitObj ));      Abc_ObjSetCopy( pInitObj, pObj );      Abc_LatchSetInitNone( pObj ); @@ -699,7 +699,7 @@ void Abc_FlowRetime_UpdateBackwardInit( Abc_Ntk_t * pNtk ) {    // add PIs to to latches    Abc_NtkForEachLatch( pNtk, pOrigObj, i ) {      assert(Vec_PtrSize(vPi) > 0); -    pInitObj = Vec_PtrPop(vPi); +    pInitObj = (Abc_Obj_t*)Vec_PtrPop(vPi);      // DEBUG      // printf("update : mapping latch %d to PI %d\n", pOrigObj->Id, pInitObj->Id); @@ -773,7 +773,7 @@ Abc_Obj_t *Abc_FlowRetime_CopyNodeToInitNtk( Abc_Obj_t *pOrigObj ) {      pData =  Abc_SopCreateAnd( (Mem_Flex_t *)pInitNtk->pManFunc, 2, fCompl );      assert(pData); -    pInitObj->pData = Abc_SopRegister( (Mem_Flex_t *)pInitNtk->pManFunc, pData ); +    pInitObj->pData = Abc_SopRegister( (Mem_Flex_t *)pInitNtk->pManFunc, (const char*)pData );    }     // (ii) mapped node -> SOP node @@ -787,11 +787,11 @@ Abc_Obj_t *Abc_FlowRetime_CopyNodeToInitNtk( Abc_Obj_t *pOrigObj ) {        return pInitObj;      } -    pInitObj = Abc_NtkCreateObj( pInitNtk, Abc_ObjType(pOrigObj) ); -    pData = Mio_GateReadSop(pOrigObj->pData); -    assert( Abc_SopGetVarNum(pData) == Abc_ObjFaninNum(pOrigObj) ); +    pInitObj = Abc_NtkCreateObj( pInitNtk, (Abc_ObjType_t)Abc_ObjType(pOrigObj) ); +    pData = Mio_GateReadSop((Mio_Gate_t*)pOrigObj->pData); +    assert( Abc_SopGetVarNum((char*)pData) == Abc_ObjFaninNum(pOrigObj) ); -    pInitObj->pData = Abc_SopRegister( (Mem_Flex_t *)pInitNtk->pManFunc, pData ); +    pInitObj->pData = Abc_SopRegister( (Mem_Flex_t *)pInitNtk->pManFunc, (const char*)pData );    }     // (iii) otherwise, duplicate obj @@ -1069,7 +1069,7 @@ void Abc_FlowRetime_ConstrainInit( ) {  #endif      // mark its TFO -    pObj = Vec_PtrEntry( vNodes, low ); +    pObj = (Abc_Obj_t*)Vec_PtrEntry( vNodes, low );      Abc_NtkMarkCone_rec( pObj, 1 );      vprintf("   conflict term = %d ", low); @@ -1170,7 +1170,7 @@ static void Abc_FlowRetime_ConnectBiasNode(Abc_Obj_t *pBiasNode, Abc_Obj_t *pObj    Abc_NtkIncrementTravId( pNtk );    while (Vec_PtrSize( vNodes )) { -    pCur = Vec_PtrPop( vNodes ); +    pCur = (Abc_Obj_t*)Vec_PtrPop( vNodes );      lag = Vec_IntPop( vLags );      if (Abc_NodeIsTravIdCurrent( pCur )) continue; @@ -1262,7 +1262,7 @@ void Abc_FlowRetime_ClearInitToOrig( Abc_Obj_t *pInit )    if (id >= pManMR->sizeInitToOrig) {      int oldSize = pManMR->sizeInitToOrig;      pManMR->sizeInitToOrig = 1.5*id + 10; -    pManMR->pInitToOrig = realloc(pManMR->pInitToOrig, sizeof(NodeLag_t)*pManMR->sizeInitToOrig); +    pManMR->pInitToOrig = (NodeLag_t*)realloc(pManMR->pInitToOrig, sizeof(NodeLag_t)*pManMR->sizeInitToOrig);      memset( &(pManMR->pInitToOrig[oldSize]), 0, sizeof(NodeLag_t)*(pManMR->sizeInitToOrig-oldSize) );    }    assert( pManMR->pInitToOrig ); @@ -1291,7 +1291,7 @@ void Abc_FlowRetime_SetInitToOrig( Abc_Obj_t *pInit, Abc_Obj_t *pOrig)    if (id >= pManMR->sizeInitToOrig) {      int oldSize = pManMR->sizeInitToOrig;      pManMR->sizeInitToOrig = 1.5*id + 10; -    pManMR->pInitToOrig = realloc(pManMR->pInitToOrig, sizeof(NodeLag_t)*pManMR->sizeInitToOrig); +    pManMR->pInitToOrig = (NodeLag_t*)realloc(pManMR->pInitToOrig, sizeof(NodeLag_t)*pManMR->sizeInitToOrig);      memset( &(pManMR->pInitToOrig[oldSize]), 0, sizeof(NodeLag_t)*(pManMR->sizeInitToOrig-oldSize) );    }    assert( pManMR->pInitToOrig ); diff --git a/src/opt/fret/fretMain.c b/src/opt/fret/fretMain.c index 2dd2bc03..2367007d 100644 --- a/src/opt/fret/fretMain.c +++ b/src/opt/fret/fretMain.c @@ -188,7 +188,7 @@ Abc_FlowRetime_MinReg( Abc_Ntk_t * pNtk, int fVerbose,    if (pManMR->vSinkDistHist) Vec_IntFree(pManMR->vSinkDistHist);    if (pManMR->maxDelay) Abc_FlowRetime_FreeTiming( pNtk );    while( Vec_PtrSize( pManMR->vInitConstraints )) { -    pData = Vec_PtrPop( pManMR->vInitConstraints ); +    pData = (InitConstraint_t*)Vec_PtrPop( pManMR->vInitConstraints );      //assert( pData->pBiasNode );      //Abc_NtkDeleteObj( pData->pBiasNode );      ABC_FREE( pData->vNodes.pArray ); @@ -791,7 +791,7 @@ Abc_FlowRetime_CopyInitState( Abc_Obj_t * pSrc, Abc_Obj_t * pDest ) {    }    if (!pManMR->fIsForward) { -    pObj = Abc_ObjData(pSrc); +    pObj = (Abc_Obj_t*)Abc_ObjData(pSrc);      assert(Abc_ObjIsPi(pObj));      FDATA(pDest)->pInitObj = pObj;    } @@ -1373,7 +1373,7 @@ void Abc_ObjPrintNeighborhood( Abc_Obj_t *pObj, int depth ) {    Abc_ObjPrintNeighborhood_rec( pObj, vNodes, depth );    while(Vec_PtrSize(vNodes)) { -    pObj2 = Vec_PtrPop(vNodes); +    pObj2 = (Abc_Obj_t*)Vec_PtrPop(vNodes);      pObj2->fMarkC = 0;    } diff --git a/src/opt/fret/fretTime.c b/src/opt/fret/fretTime.c index 0614ab6e..475320e3 100644 --- a/src/opt/fret/fretTime.c +++ b/src/opt/fret/fretTime.c @@ -95,7 +95,7 @@ void Abc_FlowRetime_ConstrainConserv( Abc_Ntk_t * pNtk ) {    // clear all exact constraints    pManMR->nExactConstraints = 0;    while( Vec_PtrSize( pManMR->vExactNodes )) { -    pObj = Vec_PtrPop( pManMR->vExactNodes ); +    pObj = (Abc_Obj_t*)Vec_PtrPop( pManMR->vExactNodes );      if ( Vec_PtrSize( FTIMEEDGES(pObj) )) {        pArray =  Vec_PtrReleaseArray( FTIMEEDGES(pObj) ); @@ -619,7 +619,7 @@ void Abc_FlowRetime_FreeTiming( Abc_Ntk_t *pNtk ) {    void *pArray;    while( Vec_PtrSize( pManMR->vExactNodes )) { -    pObj = Vec_PtrPop( pManMR->vExactNodes ); +    pObj = (Abc_Obj_t*)Vec_PtrPop( pManMR->vExactNodes );      if ( Vec_PtrSize( FTIMEEDGES(pObj) )) {        pArray =  Vec_PtrReleaseArray( FTIMEEDGES(pObj) );  | 
