Adding a wrapper around clock() for more accurate time counting in ABC.

102 files changed, 1090 insertions, 1090 deletions

diff --git a/src/proof/abs/absGla.c b/src/proof/abs/absGla.c
index 4063757c..5daa953f 100644
--- a/src/proof/abs/absGla.c
+++ b/src/proof/abs/absGla.c
@@ -73,12 +73,12 @@ struct Ga2_Man_t_
     Vec_Int_t *    vIsopMem;
     char * pSopSizes, ** pSops;  // CNF representation
     // statistics  
-    clock_t        timeStart;
-    clock_t        timeInit;
-    clock_t        timeSat;
-    clock_t        timeUnsat;
-    clock_t        timeCex;
-    clock_t        timeOther;
+    abctime        timeStart;
+    abctime        timeInit;
+    abctime        timeSat;
+    abctime        timeUnsat;
+    abctime        timeCex;
+    abctime        timeOther;
 };
 
 static inline int         Ga2_ObjId( Ga2_Man_t * p, Gia_Obj_t * pObj )           { return Vec_IntEntry(p->vIds, Gia_ObjId(p->pGia, pObj));                                                  }
@@ -243,7 +243,7 @@ void Ga2_ManCollectLeaves_rec( Gia_Man_t * p, Gia_Obj_t * pObj, Vec_Int_t * vLea
 int Ga2_ManMarkup( Gia_Man_t * p, int N, int fSimple )
 {
     static unsigned uTruth5[5] = { 0xAAAAAAAA, 0xCCCCCCCC, 0xF0F0F0F0, 0xFF00FF00, 0xFFFF0000 };
-//    clock_t clk = clock();
+//    abctime clk = Abc_Clock();
     Vec_Int_t * vLeaves;
     Gia_Obj_t * pObj;
     int i, k, Leaf, CountMarks;
@@ -330,20 +330,20 @@ int Ga2_ManMarkup( Gia_Man_t * p, int N, int fSimple )
         Vec_IntPush( p->vMapping, -1 );  // placeholder for ref counter
         CountMarks++;
     }
-//    Abc_PrintTime( 1, "Time", clock() - clk );
+//    Abc_PrintTime( 1, "Time", Abc_Clock() - clk );
     Vec_IntFree( vLeaves );
     Gia_ManCleanValue( p );
     return CountMarks;
 }
 void Ga2_ManComputeTest( Gia_Man_t * p )
 {
-    clock_t clk;
+    abctime clk;
 //    unsigned uTruth;
     Gia_Obj_t * pObj;
     int i, Counter = 0;
-    clk = clock();
+    clk = Abc_Clock();
     Ga2_ManMarkup( p, 5, 0 );
-    Abc_PrintTime( 1, "Time", clock() - clk );
+    Abc_PrintTime( 1, "Time", Abc_Clock() - clk );
     Gia_ManForEachAnd( p, pObj, i )
     {
         if ( !pObj->fPhase )
@@ -355,7 +355,7 @@ void Ga2_ManComputeTest( Gia_Man_t * p )
         Counter++;
     }
     Abc_Print( 1, "Marked AND nodes = %6d.  ", Counter );
-    Abc_PrintTime( 1, "Time", clock() - clk );
+    Abc_PrintTime( 1, "Time", Abc_Clock() - clk );
 }
 
 /**Function*************************************************************
@@ -373,7 +373,7 @@ Ga2_Man_t * Ga2_ManStart( Gia_Man_t * pGia, Abs_Par_t * pPars )
 {
     Ga2_Man_t * p;
     p = ABC_CALLOC( Ga2_Man_t, 1 );
-    p->timeStart = clock();
+    p->timeStart = Abc_Clock();
     p->fUseNewLine = 1;
     // user data
     p->pGia      = pGia;
@@ -1366,7 +1366,7 @@ int Ga2_GlaAbsCount( Ga2_Man_t * p, int fRo, int fAnd )
   SeeAlso     []
 
 ***********************************************************************/
-void Ga2_ManAbsPrintFrame( Ga2_Man_t * p, int nFrames, int nConfls, int nCexes, clock_t Time, int fFinal )
+void Ga2_ManAbsPrintFrame( Ga2_Man_t * p, int nFrames, int nConfls, int nCexes, abctime Time, int fFinal )
 {
     int fUseNewLine = ((fFinal && nCexes) || p->pPars->fVeryVerbose);
     if ( Abc_FrameIsBatchMode() && !fUseNewLine )
@@ -1502,7 +1502,7 @@ int Gia_ManPerformGla( Gia_Man_t * pAig, Abs_Par_t * pPars )
     int fUseSecondCore = 1;
     Ga2_Man_t * p;
     Vec_Int_t * vCore, * vPPis;
-    clock_t clk2, clk = clock();
+    abctime clk2, clk = Abc_Clock();
     int Status = l_Undef, RetValue = -1, iFrameTryToProve = -1, fOneIsSent = 0;
     int i, c, f, Lit;
     pPars->iFrame = -1;
@@ -1529,7 +1529,7 @@ int Gia_ManPerformGla( Gia_Man_t * pAig, Abs_Par_t * pPars )
     }
     // start the manager
     p = Ga2_ManStart( pAig, pPars );
-    p->timeInit = clock() - clk;
+    p->timeInit = Abc_Clock() - clk;
     // perform initial abstraction
     if ( p->pPars->fVerbose )
     {
@@ -1600,12 +1600,12 @@ int Gia_ManPerformGla( Gia_Man_t * pAig, Abs_Par_t * pPars )
                     break;
                 }
                 // perform SAT solving
-                clk2 = clock();
+                clk2 = Abc_Clock();
                 Status = sat_solver2_solve( p->pSat, &Lit, &Lit+1, (ABC_INT64_T)pPars->nConfLimit, (ABC_INT64_T)0, (ABC_INT64_T)0, (ABC_INT64_T)0 );
                 if ( Status == l_True ) // perform refinement
                 {
                     p->nCexes++;
-                    p->timeSat += clock() - clk2;
+                    p->timeSat += Abc_Clock() - clk2;
 
                     // cancel old one if it was sent
                     if ( Abc_FrameIsBridgeMode() && fOneIsSent )
@@ -1620,14 +1620,14 @@ int Gia_ManPerformGla( Gia_Man_t * pAig, Abs_Par_t * pPars )
                     }
 
                     // perform refinement
-                    clk2 = clock();
+                    clk2 = Abc_Clock();
                     Rnm_ManSetRefId( p->pRnm, c );
                     vPPis = Ga2_ManRefine( p );
-                    p->timeCex += clock() - clk2;
+                    p->timeCex += Abc_Clock() - clk2;
                     if ( vPPis == NULL )
                     {
                         if ( pPars->fVerbose )
-                            Ga2_ManAbsPrintFrame( p, f, sat_solver2_nconflicts(p->pSat)-nConflsBeg, c, clock() - clk, 1 );
+                            Ga2_ManAbsPrintFrame( p, f, sat_solver2_nconflicts(p->pSat)-nConflsBeg, c, Abc_Clock() - clk, 1 );
                         goto finish;
                     }
 
@@ -1657,13 +1657,13 @@ int Gia_ManPerformGla( Gia_Man_t * pAig, Abs_Par_t * pPars )
                     Ga2_ManAddToAbs( p, vPPis );
                     Vec_IntFree( vPPis );
                     if ( pPars->fVerbose )
-                        Ga2_ManAbsPrintFrame( p, f, sat_solver2_nconflicts(p->pSat)-nConflsBeg, c+1, clock() - clk, 0 );
+                        Ga2_ManAbsPrintFrame( p, f, sat_solver2_nconflicts(p->pSat)-nConflsBeg, c+1, Abc_Clock() - clk, 0 );
                     continue;
                 }
-                p->timeUnsat += clock() - clk2;
+                p->timeUnsat += Abc_Clock() - clk2;
                 if ( Status == l_Undef ) // ran out of resources
                     goto finish;
-                if ( p->pSat->nRuntimeLimit && clock() > p->pSat->nRuntimeLimit ) // timeout
+                if ( p->pSat->nRuntimeLimit && Abc_Clock() > p->pSat->nRuntimeLimit ) // timeout
                     goto finish;
                 if ( c == 0 )
                 {
@@ -1706,12 +1706,12 @@ int Gia_ManPerformGla( Gia_Man_t * pAig, Abs_Par_t * pPars )
                         Vec_IntFree( vCore );
                     }
                     // run SAT solver
-                    clk2 = clock();
+                    clk2 = Abc_Clock();
                     Status = sat_solver2_solve( p->pSat, &Lit, &Lit+1, (ABC_INT64_T)pPars->nConfLimit, (ABC_INT64_T)0, (ABC_INT64_T)0, (ABC_INT64_T)0 );
                     if ( Status == l_Undef )
                         goto finish;
                     assert( Status == l_False );
-                    p->timeUnsat += clock() - clk2;
+                    p->timeUnsat += Abc_Clock() - clk2;
 
                     // derive the core
                     assert( p->pSat->pPrf2 != NULL );
@@ -1734,7 +1734,7 @@ int Gia_ManPerformGla( Gia_Man_t * pAig, Abs_Par_t * pPars )
                 p->pPars->iFrameProved = f;
             // print statistics
             if ( pPars->fVerbose )
-                Ga2_ManAbsPrintFrame( p, f, sat_solver2_nconflicts(p->pSat)-nConflsBeg, c, clock() - clk, 1 );
+                Ga2_ManAbsPrintFrame( p, f, sat_solver2_nconflicts(p->pSat)-nConflsBeg, c, Abc_Clock() - clk, 1 );
             // check if abstraction was proved
             if ( Gia_GlaProveCheck( pPars->fVerbose ) )
             {
@@ -1817,7 +1817,7 @@ finish:
     {
         Vec_IntFreeP( &pAig->vGateClasses );
         pAig->vGateClasses = Ga2_ManAbsTranslate( p );
-        if ( p->pPars->nTimeOut && clock() >= p->pSat->nRuntimeLimit ) 
+        if ( p->pPars->nTimeOut && Abc_Clock() >= p->pSat->nRuntimeLimit ) 
             Abc_Print( 1, "GLA reached timeout %d sec in frame %d with a %d-stable abstraction.    ", p->pPars->nTimeOut, p->pPars->iFrameProved+1, p->pPars->nFramesNoChange );
         else if ( pPars->nConfLimit && sat_solver2_nconflicts(p->pSat) >= pPars->nConfLimit )
             Abc_Print( 1, "GLA exceeded %d conflicts in frame %d with a %d-stable abstraction.  ", pPars->nConfLimit, p->pPars->iFrameProved+1, p->pPars->nFramesNoChange );
@@ -1838,16 +1838,16 @@ finish:
         Vec_IntFreeP( &pAig->vGateClasses );
         RetValue = 0;
     }
-    Abc_PrintTime( 1, "Time", clock() - clk );
+    Abc_PrintTime( 1, "Time", Abc_Clock() - clk );
     if ( p->pPars->fVerbose )
     {
-        p->timeOther = (clock() - clk) - p->timeUnsat - p->timeSat - p->timeCex - p->timeInit;
-        ABC_PRTP( "Runtime: Initializing", p->timeInit,   clock() - clk );
-        ABC_PRTP( "Runtime: Solver UNSAT", p->timeUnsat,  clock() - clk );
-        ABC_PRTP( "Runtime: Solver SAT  ", p->timeSat,    clock() - clk );
-        ABC_PRTP( "Runtime: Refinement  ", p->timeCex,    clock() - clk );
-        ABC_PRTP( "Runtime: Other       ", p->timeOther,  clock() - clk );
-        ABC_PRTP( "Runtime: TOTAL       ", clock() - clk, clock() - clk );
+        p->timeOther = (Abc_Clock() - clk) - p->timeUnsat - p->timeSat - p->timeCex - p->timeInit;
+        ABC_PRTP( "Runtime: Initializing", p->timeInit,   Abc_Clock() - clk );
+        ABC_PRTP( "Runtime: Solver UNSAT", p->timeUnsat,  Abc_Clock() - clk );
+        ABC_PRTP( "Runtime: Solver SAT  ", p->timeSat,    Abc_Clock() - clk );
+        ABC_PRTP( "Runtime: Refinement  ", p->timeCex,    Abc_Clock() - clk );
+        ABC_PRTP( "Runtime: Other       ", p->timeOther,  Abc_Clock() - clk );
+        ABC_PRTP( "Runtime: TOTAL       ", Abc_Clock() - clk, Abc_Clock() - clk );
         Ga2_ManReportMemory( p );
     }
 //    Ga2_ManDumpStats( p->pGia, p->pPars, p->pSat, p->pPars->iFrameProved, 0 );
diff --git a/src/proof/abs/absGlaOld.c b/src/proof/abs/absGlaOld.c
index e2f83e96..70bd2e91 100644
--- a/src/proof/abs/absGlaOld.c
+++ b/src/proof/abs/absGlaOld.c
@@ -93,11 +93,11 @@ struct Gla_Man_t_
     Gia_Man_t *    pGia2;
     Rnm_Man_t *    pRnm;
     // statistics  
-    clock_t        timeInit;
-    clock_t        timeSat;
-    clock_t        timeUnsat;
-    clock_t        timeCex;
-    clock_t        timeOther;
+    abctime        timeInit;
+    abctime        timeSat;
+    abctime        timeUnsat;
+    abctime        timeCex;
+    abctime        timeOther;
 };
 
 // declarations
@@ -1447,7 +1447,7 @@ Vec_Int_t * Gla_ManUnsatCore( Gla_Man_t * p, int f, sat_solver2 * pSat, int nCon
     Vec_Int_t * vCore = NULL;
     int nConfPrev = pSat->stats.conflicts;
     int RetValue, iLit = Gla_ManGetOutLit( p, f );
-    clock_t clk = clock();
+    abctime clk = Abc_Clock();
     if ( piRetValue )
         *piRetValue = 1;
     // consider special case when PO points to the flop
@@ -1478,18 +1478,18 @@ Vec_Int_t * Gla_ManUnsatCore( Gla_Man_t * p, int f, sat_solver2 * pSat, int nCon
     {
 //        Abc_Print( 1, "%6d", (int)pSat->stats.conflicts - nConfPrev );
 //        Abc_Print( 1, "UNSAT after %7d conflicts.      ", pSat->stats.conflicts );
-//        Abc_PrintTime( 1, "Time", clock() - clk );
+//        Abc_PrintTime( 1, "Time", Abc_Clock() - clk );
     }
     assert( RetValue == l_False );
     // derive the UNSAT core
-    clk = clock();
+    clk = Abc_Clock();
     vCore = (Vec_Int_t *)Sat_ProofCore( pSat );
     if ( vCore )
         Vec_IntSort( vCore, 1 );
     if ( fVerbose )
     {
 //        Abc_Print( 1, "Core is %8d vars    (out of %8d).   ", Vec_IntSize(vCore), sat_solver2_nvars(pSat) );
-//        Abc_PrintTime( 1, "Time", clock() - clk );
+//        Abc_PrintTime( 1, "Time", Abc_Clock() - clk );
     }
     return vCore;
 }
@@ -1506,7 +1506,7 @@ Vec_Int_t * Gla_ManUnsatCore( Gla_Man_t * p, int f, sat_solver2 * pSat, int nCon
   SeeAlso     []
 
 ***********************************************************************/
-void Gla_ManAbsPrintFrame( Gla_Man_t * p, int nCoreSize, int nFrames, int nConfls, int nCexes, clock_t Time )
+void Gla_ManAbsPrintFrame( Gla_Man_t * p, int nCoreSize, int nFrames, int nConfls, int nCexes, abctime Time )
 {
     if ( Abc_FrameIsBatchMode() && nCoreSize <= 0 )
         return;
@@ -1643,7 +1643,7 @@ int Gia_ManPerformGlaOld( Gia_Man_t * pAig, Abs_Par_t * pPars, int fStartVta )
     Vec_Int_t * vPPis, * vCore;//, * vCore2 = NULL;
     Abc_Cex_t * pCex = NULL;
     int f, i, iPrev, nConfls, Status, nVarsOld = 0, nCoreSize, fOneIsSent = 0, RetValue = -1;
-    clock_t clk2, clk = clock();
+    abctime clk2, clk = Abc_Clock();
     // preconditions
     assert( Gia_ManPoNum(pAig) == 1 );
     assert( pPars->nFramesMax == 0 || pPars->nFramesStart <= pPars->nFramesMax );
@@ -1696,10 +1696,10 @@ int Gia_ManPerformGlaOld( Gia_Man_t * pAig, Abs_Par_t * pPars, int fStartVta )
     }
     // start the manager
     p = Gla_ManStart( pAig, pPars );
-    p->timeInit = clock() - clk;
+    p->timeInit = Abc_Clock() - clk;
     // set runtime limit
     if ( p->pPars->nTimeOut )
-        sat_solver2_set_runtime_limit( p->pSat, p->pPars->nTimeOut * CLOCKS_PER_SEC + clock() );
+        sat_solver2_set_runtime_limit( p->pSat, p->pPars->nTimeOut * CLOCKS_PER_SEC + Abc_Clock() );
     // perform initial abstraction
     if ( p->pPars->fVerbose )
     {
@@ -1721,10 +1721,10 @@ int Gia_ManPerformGlaOld( Gia_Man_t * pAig, Abs_Par_t * pPars, int fStartVta )
         // iterate as long as there are counter-examples
         for ( i = 0; ; i++ )
         { 
-            clk2 = clock();
+            clk2 = Abc_Clock();
             vCore = Gla_ManUnsatCore( p, f, p->pSat, pPars->nConfLimit, pPars->fVerbose, &Status, &nConfls );
 //            assert( (vCore != NULL) == (Status == 1) );
-            if ( Status == -1 || (p->pSat->nRuntimeLimit && clock() > p->pSat->nRuntimeLimit) ) // resource limit is reached
+            if ( Status == -1 || (p->pSat->nRuntimeLimit && Abc_Clock() > p->pSat->nRuntimeLimit) ) // resource limit is reached
             {
                 Prf_ManStopP( &p->pSat->pPrf2 );
 //                if ( Gia_ManRegNum(p->pGia) > 1 ) // for comb cases, return the abstraction
@@ -1734,10 +1734,10 @@ int Gia_ManPerformGlaOld( Gia_Man_t * pAig, Abs_Par_t * pPars, int fStartVta )
             if ( Status == 1 )
             {
                 Prf_ManStopP( &p->pSat->pPrf2 );
-                p->timeUnsat += clock() - clk2;
+                p->timeUnsat += Abc_Clock() - clk2;
                 break;
             } 
-            p->timeSat += clock() - clk2;
+            p->timeSat += Abc_Clock() - clk2;
             assert( Status == 0 );
             p->nCexes++;
 
@@ -1749,7 +1749,7 @@ int Gia_ManPerformGlaOld( Gia_Man_t * pAig, Abs_Par_t * pPars, int fStartVta )
             }
 
             // perform the refinement
-            clk2 = clock();
+            clk2 = Abc_Clock();
             if ( pPars->fAddLayer )
             {
                 vPPis = Gla_ManCollectPPis( p, NULL );
@@ -1803,7 +1803,7 @@ int Gia_ManPerformGlaOld( Gia_Man_t * pAig, Abs_Par_t * pPars, int fStartVta )
 
             // print the result (do not count it towards change)
             if ( p->pPars->fVerbose )
-            Gla_ManAbsPrintFrame( p, -1, f+1, sat_solver2_nconflicts(p->pSat)-nConflsBeg, i, clock() - clk );
+            Gla_ManAbsPrintFrame( p, -1, f+1, sat_solver2_nconflicts(p->pSat)-nConflsBeg, i, Abc_Clock() - clk );
         }
         if ( pCex != NULL )
             break;
@@ -1836,9 +1836,9 @@ int Gia_ManPerformGlaOld( Gia_Man_t * pAig, Abs_Par_t * pPars, int fStartVta )
             Gia_GlaAddOneSlice( p, f, vCore );
             Vec_IntFree( vCore );
             // run SAT solver
-            clk2 = clock();
+            clk2 = Abc_Clock();
             vCore = Gla_ManUnsatCore( p, f, p->pSat, pPars->nConfLimit, p->pPars->fVerbose, &Status, &nConfls );
-            p->timeUnsat += clock() - clk2;
+            p->timeUnsat += Abc_Clock() - clk2;
 //            assert( (vCore != NULL) == (Status == 1) );
             Vec_IntFreeP( &vCore );
             if ( Status == -1 ) // resource limit is reached
@@ -1855,7 +1855,7 @@ int Gia_ManPerformGlaOld( Gia_Man_t * pAig, Abs_Par_t * pPars, int fStartVta )
         }
         // print the result
         if ( p->pPars->fVerbose )
-        Gla_ManAbsPrintFrame( p, nCoreSize, f+1, sat_solver2_nconflicts(p->pSat)-nConflsBeg, i, clock() - clk );
+        Gla_ManAbsPrintFrame( p, nCoreSize, f+1, sat_solver2_nconflicts(p->pSat)-nConflsBeg, i, Abc_Clock() - clk );
 
         if ( f > 2 && iPrev > 0 && i == 0 ) // change has happened
         {
@@ -1901,7 +1901,7 @@ finish:
         pAig->vGateClasses = Gla_ManTranslate( p );
         if ( Status == -1 )
         {
-            if ( p->pPars->nTimeOut && clock() >= p->pSat->nRuntimeLimit ) 
+            if ( p->pPars->nTimeOut && Abc_Clock() >= p->pSat->nRuntimeLimit ) 
                 Abc_Print( 1, "Timeout %d sec in frame %d with a %d-stable abstraction.    ", p->pPars->nTimeOut, f, p->pPars->nFramesNoChange );
             else if ( pPars->nConfLimit && sat_solver2_nconflicts(p->pSat) >= pPars->nConfLimit )
                 Abc_Print( 1, "Exceeded %d conflicts in frame %d with a %d-stable abstraction.  ", pPars->nConfLimit, f, p->pPars->nFramesNoChange );
@@ -1929,16 +1929,16 @@ finish:
         Vec_IntFreeP( &pAig->vGateClasses );
         RetValue = 0;
     }
-    Abc_PrintTime( 1, "Time", clock() - clk );
+    Abc_PrintTime( 1, "Time", Abc_Clock() - clk );
     if ( p->pPars->fVerbose )
     {
-        p->timeOther = (clock() - clk) - p->timeUnsat - p->timeSat - p->timeCex - p->timeInit;
-        ABC_PRTP( "Runtime: Initializing", p->timeInit,   clock() - clk );
-        ABC_PRTP( "Runtime: Solver UNSAT", p->timeUnsat,  clock() - clk );
-        ABC_PRTP( "Runtime: Solver SAT  ", p->timeSat,    clock() - clk );
-        ABC_PRTP( "Runtime: Refinement  ", p->timeCex,    clock() - clk );
-        ABC_PRTP( "Runtime: Other       ", p->timeOther,  clock() - clk );
-        ABC_PRTP( "Runtime: TOTAL       ", clock() - clk, clock() - clk );
+        p->timeOther = (Abc_Clock() - clk) - p->timeUnsat - p->timeSat - p->timeCex - p->timeInit;
+        ABC_PRTP( "Runtime: Initializing", p->timeInit,   Abc_Clock() - clk );
+        ABC_PRTP( "Runtime: Solver UNSAT", p->timeUnsat,  Abc_Clock() - clk );
+        ABC_PRTP( "Runtime: Solver SAT  ", p->timeSat,    Abc_Clock() - clk );
+        ABC_PRTP( "Runtime: Refinement  ", p->timeCex,    Abc_Clock() - clk );
+        ABC_PRTP( "Runtime: Other       ", p->timeOther,  Abc_Clock() - clk );
+        ABC_PRTP( "Runtime: TOTAL       ", Abc_Clock() - clk, Abc_Clock() - clk );
         Gla_ManReportMemory( p );
     }
 //    Ga2_ManDumpStats( pAig, p->pPars, p->pSat, p->pPars->iFrame, 1 );
diff --git a/src/proof/abs/absIter.c b/src/proof/abs/absIter.c
index e8e5730b..7b660359 100644
--- a/src/proof/abs/absIter.c
+++ b/src/proof/abs/absIter.c
@@ -70,7 +70,7 @@ Gia_Man_t * Gia_ManShrinkGla( Gia_Man_t * p, int nFrameMax, int nTimeOut, int fU
     int i, iFrame0, iFrame;
     int nTotal = 0, nRemoved = 0;
     Vec_Int_t * vGScopy;
-    clock_t clk, clkTotal = clock();
+    abctime clk, clkTotal = Abc_Clock();
     assert( Gia_ManPoNum(p) == 1 );
     assert( p->vGateClasses != NULL );
     vGScopy = Vec_IntDup( p->vGateClasses );
@@ -99,7 +99,7 @@ Gia_Man_t * Gia_ManShrinkGla( Gia_Man_t * p, int nFrameMax, int nTimeOut, int fU
                 if ( Gia_ObjIsInGla(p, Gia_ObjFanin0(Gia_ObjRoToRi(p, pObj))) )
                     continue;
             }        
-            clk = clock();
+            clk = Abc_Clock();
             printf( "%5d : ", nTotal );
             printf( "Obj =%7d   ", i );
             Gia_ObjRemFromGla( p, pObj );
@@ -122,7 +122,7 @@ Gia_Man_t * Gia_ManShrinkGla( Gia_Man_t * p, int nFrameMax, int nTimeOut, int fU
                 printf( "Removing   " );
                 Vec_IntWriteEntry( vGScopy, Gia_ObjId(p, pObj), 0 );
             }
-            Abc_PrintTime( 1, "Time", clock() - clk );
+            Abc_PrintTime( 1, "Time", Abc_Clock() - clk );
             nTotal++;
             // update the classes
             Vec_IntFreeP( &p->vGateClasses );
@@ -135,7 +135,7 @@ Gia_Man_t * Gia_ManShrinkGla( Gia_Man_t * p, int nFrameMax, int nTimeOut, int fU
     Vec_IntFree( vGScopy );
     printf( "Tried = %d.  ",     nTotal );
     printf( "Removed = %d. (%.2f %%)  ",  nRemoved, 100.0 * nRemoved / Vec_IntCountPositive(p->vGateClasses) );
-    Abc_PrintTime( 1, "Time",  clock() - clkTotal );
+    Abc_PrintTime( 1, "Time",  Abc_Clock() - clkTotal );
     return NULL;
 }
 
diff --git a/src/proof/abs/absOldCex.c b/src/proof/abs/absOldCex.c
index e5eaee27..c57d8ed9 100644
--- a/src/proof/abs/absOldCex.c
+++ b/src/proof/abs/absOldCex.c
@@ -720,9 +720,9 @@ Abc_Cex_t * Saig_ManCbaFindCexCareBits( Aig_Man_t * pAig, Abc_Cex_t * pCex, int
     Saig_ManCba_t * p;
     Vec_Int_t * vReasons;
     Abc_Cex_t * pCare;
-    clock_t clk = clock();
+    abctime clk = Abc_Clock();
 
-    clk = clock();
+    clk = Abc_Clock();
     p = Saig_ManCbaStart( pAig, pCex, nInputs, fVerbose );
 
 //    p->vReg2Frame = Vec_VecStart( pCex->iFrame );
@@ -743,7 +743,7 @@ Abc_Cex_t * Saig_ManCbaFindCexCareBits( Aig_Man_t * pAig, Abc_Cex_t * pCex, int
             Aig_ManCiNum(p->pFrames), Vec_IntSize(vReasons), 
             Saig_ManPiNum(p->pAig) - p->nInputs, Vec_IntSize(vRes) );
         Vec_IntFree( vRes );
-ABC_PRT( "Time", clock() - clk );
+ABC_PRT( "Time", Abc_Clock() - clk );
     }
 
     pCare = Saig_ManCbaReason2Cex( p, vReasons );
@@ -786,7 +786,7 @@ Vec_Int_t * Saig_ManCbaFilterInputs( Aig_Man_t * pAig, int iFirstFlopPi, Abc_Cex
 {
     Saig_ManCba_t * p;
     Vec_Int_t * vRes, * vReasons;
-    clock_t clk;
+    abctime clk;
     if ( Saig_ManPiNum(pAig) != pCex->nPis )
     {
         printf( "Saig_ManCbaFilterInputs(): The PI count of AIG (%d) does not match that of cex (%d).\n", 
@@ -794,7 +794,7 @@ Vec_Int_t * Saig_ManCbaFilterInputs( Aig_Man_t * pAig, int iFirstFlopPi, Abc_Cex
         return NULL;
     }
 
-clk = clock();
+clk = Abc_Clock();
     p = Saig_ManCbaStart( pAig, pCex, iFirstFlopPi, fVerbose );
     p->pFrames = Saig_ManCbaUnrollWithCex( pAig, pCex, iFirstFlopPi, &p->vMapPiF2A, &p->vReg2Frame );
     vReasons = Saig_ManCbaFindReason( p );
@@ -804,7 +804,7 @@ clk = clock();
         printf( "Frame PIs = %4d (essential = %4d)   AIG PIs = %4d (essential = %4d)   ",
             Aig_ManCiNum(p->pFrames), Vec_IntSize(vReasons), 
             Saig_ManPiNum(p->pAig) - p->nInputs, Vec_IntSize(vRes) );
-ABC_PRT( "Time", clock() - clk );
+ABC_PRT( "Time", Abc_Clock() - clk );
     }
 
     Vec_IntFree( vReasons );
@@ -831,7 +831,7 @@ Vec_Int_t * Saig_ManCbaPerform( Aig_Man_t * pAbs, int nInputs, Saig_ParBmc_t * p
 {
     Vec_Int_t * vAbsFfsToAdd;
     int RetValue;
-    clock_t clk = clock();
+    abctime clk = Abc_Clock();
 //    assert( pAbs->nRegs > 0 );
     // perform BMC
     RetValue = Saig_ManBmcScalable( pAbs, pPars );
@@ -859,7 +859,7 @@ Vec_Int_t * Saig_ManCbaPerform( Aig_Man_t * pAbs, int nInputs, Saig_ParBmc_t * p
     {
         printf( "Adding %d registers to the abstraction (total = %d).  ", 
             Vec_IntSize(vAbsFfsToAdd), Aig_ManRegNum(pAbs)+Vec_IntSize(vAbsFfsToAdd) );
-        Abc_PrintTime( 1, "Time", clock() - clk );
+        Abc_PrintTime( 1, "Time", Abc_Clock() - clk );
     }
     return vAbsFfsToAdd;
 }
diff --git a/src/proof/abs/absOldRef.c b/src/proof/abs/absOldRef.c
index 6cc5ff6d..b42053dd 100644
--- a/src/proof/abs/absOldRef.c
+++ b/src/proof/abs/absOldRef.c
@@ -257,7 +257,7 @@ int Saig_ManCexRefineStep( Aig_Man_t * p, Vec_Int_t * vFlops, Vec_Int_t * vFlopC
     Aig_Man_t * pAbs;
     Vec_Int_t * vFlopsNew;
     int i, Entry;
-    clock_t clk = clock();
+    abctime clk = Abc_Clock();
     pAbs = Saig_ManDupAbstraction( p, vFlops );
     if ( fSensePath )
         vFlopsNew = Saig_ManExtendCounterExampleTest2( pAbs, Saig_ManCexFirstFlopPi(p, pAbs), pCex, fVerbose );
@@ -281,7 +281,7 @@ int Saig_ManCexRefineStep( Aig_Man_t * p, Vec_Int_t * vFlops, Vec_Int_t * vFlopC
     if ( fVerbose )
     {
         printf( "Adding %d registers to the abstraction (total = %d).  ", Vec_IntSize(vFlopsNew), Aig_ManRegNum(p)+Vec_IntSize(vFlopsNew) );
-        Abc_PrintTime( 1, "Time", clock() - clk );
+        Abc_PrintTime( 1, "Time", Abc_Clock() - clk );
     }
     // vFlopsNew contains PI numbers that should be kept in pAbs
     // select the most useful flops among those to be added
@@ -411,7 +411,7 @@ Vec_Int_t * Saig_ManCexAbstractionFlops( Aig_Man_t * p, Gia_ParAbs_t * pPars )
     int nUseStart = 0;
     Aig_Man_t * pAbs, * pTemp;
     Vec_Int_t * vFlops;
-    int Iter;//, clk = clock(), clk2 = clock();//, iFlop;
+    int Iter;//, clk = Abc_Clock(), clk2 = Abc_Clock();//, iFlop;
     assert( Aig_ManRegNum(p) > 0 );
     if ( pPars->fVerbose )
         printf( "Performing counter-example-based refinement.\n" );
diff --git a/src/proof/abs/absOldSat.c b/src/proof/abs/absOldSat.c
index 14f59667..7ee54b29 100644
--- a/src/proof/abs/absOldSat.c
+++ b/src/proof/abs/absOldSat.c
@@ -510,7 +510,7 @@ Abc_Cex_t * Saig_RefManRunSat( Saig_RefMan_t * p, int fNewOrder )
     Vec_Int_t * vAssumps, * vVar2PiId;
     int i, k, Entry, RetValue;//, f = 0, Counter = 0;
     int nCoreLits, * pCoreLits;
-    clock_t clk = clock();
+    abctime clk = Abc_Clock();
     // create CNF
     assert( Aig_ManRegNum(p->pFrames) == 0 );
 //    pCnf = Cnf_Derive( p->pFrames, 0 ); // too slow
@@ -530,7 +530,7 @@ Abc_Cex_t * Saig_RefManRunSat( Saig_RefMan_t * p, int fNewOrder )
         Cnf_DataFree( pCnf );
         return NULL;
     }
-//Abc_PrintTime( 1, "Preparing", clock() - clk );
+//Abc_PrintTime( 1, "Preparing", Abc_Clock() - clk );
     // look for a true counter-example
     if ( p->nInputs > 0 )
     {
@@ -582,10 +582,10 @@ Abc_Cex_t * Saig_RefManRunSat( Saig_RefMan_t * p, int fNewOrder )
     }
 
     // solve
-clk = clock();
+clk = Abc_Clock();
     RetValue = sat_solver_solve( pSat, Vec_IntArray(vAssumps), Vec_IntArray(vAssumps) + Vec_IntSize(vAssumps), 
         (ABC_INT64_T)nConfLimit, (ABC_INT64_T)0, (ABC_INT64_T)0, (ABC_INT64_T)0 );
-//Abc_PrintTime( 1, "Solving", clock() - clk );
+//Abc_PrintTime( 1, "Solving", Abc_Clock() - clk );
     if ( RetValue != l_False )
     {
         if ( RetValue == l_True )
@@ -868,9 +868,9 @@ Abc_Cex_t * Saig_ManFindCexCareBits( Aig_Man_t * pAig, Abc_Cex_t * pCex, int nIn
     Saig_RefMan_t * p;
     Vec_Int_t * vReasons;
     Abc_Cex_t * pCare;
-    clock_t clk = clock();
+    abctime clk = Abc_Clock();
 
-    clk = clock();
+    clk = Abc_Clock();
     p = Saig_RefManStart( pAig, pCex, nInputs, fVerbose );
     vReasons = Saig_RefManFindReason( p );
 
@@ -883,7 +883,7 @@ Aig_ManPrintStats( p->pFrames );
         printf( "Frame PIs = %4d (essential = %4d)   AIG PIs = %4d (essential = %4d)   ",
             Aig_ManCiNum(p->pFrames), Vec_IntSize(vReasons), 
             Saig_ManPiNum(p->pAig) - p->nInputs, Vec_IntSize(vRes) );
-ABC_PRT( "Time", clock() - clk );
+ABC_PRT( "Time", Abc_Clock() - clk );
 
         Vec_IntFree( vRes );
 
@@ -900,7 +900,7 @@ ABC_PRT( "Time", clock() - clk );
             Saig_ManPiNum(p->pAig) - p->nInputs, Vec_IntSize(vRes) );
 
         Vec_IntFree( vRes );
-ABC_PRT( "Time", clock() - clk );
+ABC_PRT( "Time", Abc_Clock() - clk );
 */
     }
 
@@ -931,7 +931,7 @@ Vec_Int_t * Saig_ManExtendCounterExampleTest3( Aig_Man_t * pAig, int iFirstFlopP
 {
     Saig_RefMan_t * p;
     Vec_Int_t * vRes, * vReasons;
-    clock_t clk;
+    abctime clk;
     if ( Saig_ManPiNum(pAig) != pCex->nPis )
     {
         printf( "Saig_ManExtendCounterExampleTest3(): The PI count of AIG (%d) does not match that of cex (%d).\n", 
@@ -939,7 +939,7 @@ Vec_Int_t * Saig_ManExtendCounterExampleTest3( Aig_Man_t * pAig, int iFirstFlopP
         return NULL;
     }
 
-clk = clock();
+clk = Abc_Clock();
 
     p = Saig_RefManStart( pAig, pCex, iFirstFlopPi, fVerbose );
     vReasons = Saig_RefManFindReason( p );
@@ -950,7 +950,7 @@ clk = clock();
         printf( "Frame PIs = %4d (essential = %4d)   AIG PIs = %4d (essential = %4d)   ",
             Aig_ManCiNum(p->pFrames), Vec_IntSize(vReasons), 
             Saig_ManPiNum(p->pAig) - p->nInputs, Vec_IntSize(vRes) );
-ABC_PRT( "Time", clock() - clk );
+ABC_PRT( "Time", Abc_Clock() - clk );
     }
 
 /*
@@ -967,7 +967,7 @@ ABC_PRT( "Time", clock() - clk );
         printf( "Frame PIs = %4d (essential = %4d)   AIG PIs = %4d (essential = %4d)   ",
             Aig_ManCiNum(p->pFrames), Vec_IntSize(vReasons), 
             Saig_ManPiNum(p->pAig) - p->nInputs, Vec_IntSize(vRes) );
-ABC_PRT( "Time", clock() - clk );
+ABC_PRT( "Time", Abc_Clock() - clk );
     }
 */
 
diff --git a/src/proof/abs/absOldSim.c b/src/proof/abs/absOldSim.c
index e5c1e938..5d316935 100644
--- a/src/proof/abs/absOldSim.c
+++ b/src/proof/abs/absOldSim.c
@@ -444,7 +444,7 @@ Vec_Int_t * Saig_ManExtendCounterExampleTest2( Aig_Man_t * p, int iFirstFlopPi,
 {
     Vec_Int_t * vRes;
     Vec_Ptr_t * vSimInfo;
-    clock_t clk;
+    abctime clk;
     if ( Saig_ManPiNum(p) != pCex->nPis )
     {
         printf( "Saig_ManExtendCounterExampleTest2(): The PI count of AIG (%d) does not match that of cex (%d).\n", 
@@ -455,12 +455,12 @@ Vec_Int_t * Saig_ManExtendCounterExampleTest2( Aig_Man_t * p, int iFirstFlopPi,
     vSimInfo = Vec_PtrAllocSimInfo( Aig_ManObjNumMax(p), Abc_BitWordNum(2*(pCex->iFrame+1)) );
     Vec_PtrCleanSimInfo( vSimInfo, 0, Abc_BitWordNum(2*(pCex->iFrame+1)) );
 
-clk = clock();
+clk = Abc_Clock();
     vRes = Saig_ManProcessCex( p, iFirstFlopPi, pCex, vSimInfo, fVerbose );
     if ( fVerbose )
     {
         printf( "Total new PIs = %3d. Non-removable PIs = %3d.  ", Saig_ManPiNum(p)-iFirstFlopPi, Vec_IntSize(vRes) );
-ABC_PRT( "Time", clock() - clk );
+ABC_PRT( "Time", Abc_Clock() - clk );
     }
     Vec_PtrFree( vSimInfo );
     Aig_ManFanoutStop( p );
diff --git a/src/proof/abs/absOut.c b/src/proof/abs/absOut.c
index c230acb4..0cd9e0e2 100644
--- a/src/proof/abs/absOut.c
+++ b/src/proof/abs/absOut.c
@@ -97,7 +97,7 @@ int Gia_ManGlaRefine( Gia_Man_t * p, Abc_Cex_t * pCex, int fMinCut, int fVerbose
     Abc_Cex_t * pCare;
     Vec_Int_t * vPis, * vPPis;
     int f, i, iObjId;
-    clock_t clk = clock();
+    abctime clk = Abc_Clock();
     int nOnes = 0, Counter = 0;
     if ( p->vGateClasses == NULL )
     {
@@ -175,7 +175,7 @@ int Gia_ManGlaRefine( Gia_Man_t * p, Abc_Cex_t * pCex, int fMinCut, int fVerbose
             if ( fVerbose )
             {
                 Abc_Print( 1, "Additional objects = %d.  ", Vec_IntSize(vPPis) );
-                Abc_PrintTime( 1, "Time", clock() - clk );
+                Abc_PrintTime( 1, "Time", Abc_Clock() - clk );
             }
         }
     }
@@ -209,7 +209,7 @@ int Gia_ManGlaRefine( Gia_Man_t * p, Abc_Cex_t * pCex, int fMinCut, int fVerbose
         if ( fVerbose )
         {
             Abc_Print( 1, "Essential bits = %d.  Additional objects = %d.  ", nOnes, Counter );
-            Abc_PrintTime( 1, "Time", clock() - clk );
+            Abc_PrintTime( 1, "Time", Abc_Clock() - clk );
         }
         // consider the case of SAT
         if ( iObjId == -1 )
@@ -375,7 +375,7 @@ int Gia_ManNewRefine( Gia_Man_t * p, Abc_Cex_t * pCex, int iFrameStart, int iFra
     Gia_Man_t * pAbs, * pNew;
     Vec_Int_t * vFlops, * vInit;
     Vec_Int_t * vCopy;
-//    clock_t clk = clock();
+//    abctime clk = Abc_Clock();
     int RetValue;
     ABC_FREE( p->pCexSeq );
     if ( p->vGateClasses == NULL )
diff --git a/src/proof/abs/absRef.c b/src/proof/abs/absRef.c
index f72d86e2..dda0c8cb 100644
--- a/src/proof/abs/absRef.c
+++ b/src/proof/abs/absRef.c
@@ -290,7 +290,7 @@ void Rnm_ManStop( Rnm_Man_t * p, int fProfile )
     {
         double MemGia = sizeof(Gia_Man_t) + sizeof(Gia_Obj_t) * p->pGia->nObjsAlloc + sizeof(int) * p->pGia->nTravIdsAlloc;
         double MemOther = sizeof(Rnm_Man_t) + sizeof(Rnm_Obj_t) * p->nObjsAlloc + sizeof(int) * Vec_IntCap(p->vObjs);
-        clock_t timeOther = p->timeTotal - p->timeFwd - p->timeBwd - p->timeVer;
+        abctime timeOther = p->timeTotal - p->timeFwd - p->timeBwd - p->timeVer;
         printf( "Abstraction refinement runtime statistics:\n" );
         ABC_PRTP( "Sensetization", p->timeFwd,   p->timeTotal );
         ABC_PRTP( "Justification", p->timeBwd,   p->timeTotal );
@@ -674,7 +674,7 @@ Vec_Int_t * Rnm_ManRefine( Rnm_Man_t * p, Abc_Cex_t * pCex, Vec_Int_t * vMap, in
 {
     int fVerify = 1;
     Vec_Int_t * vGoodPPis, * vNewPPis;
-    clock_t clk, clk2 = clock();
+    abctime clk, clk2 = Abc_Clock();
     int RetValue;
     p->nCalls++;
 //    Gia_ManCleanValue( p->pGia );
@@ -692,27 +692,27 @@ Vec_Int_t * Rnm_ManRefine( Rnm_Man_t * p, Abc_Cex_t * pCex, Vec_Int_t * vMap, in
         p->pObjs = ABC_REALLOC( Rnm_Obj_t, p->pObjs, (p->nObjsAlloc = p->nObjs + 10000) );
     memset( p->pObjs, 0, sizeof(Rnm_Obj_t) * p->nObjs );
     // propagate priorities
-    clk = clock();
+    clk = Abc_Clock();
     vGoodPPis = Vec_IntAlloc( 100 );
     if ( Rnm_ManSensitize( p ) ) // the CEX is not a true CEX
     {
-        p->timeFwd += clock() - clk;
+        p->timeFwd += Abc_Clock() - clk;
         // select refinement
-        clk = clock();
+        clk = Abc_Clock();
         p->nVisited = 0;
         Rnm_ManJustify_rec( p, Gia_ObjFanin0(Gia_ManPo(p->pGia, 0)), pCex->iFrame, vGoodPPis );
         RetValue = Vec_IntUniqify( vGoodPPis );
 //        assert( RetValue == 0 );
-        p->timeBwd += clock() - clk;
+        p->timeBwd += Abc_Clock() - clk;
     }
 
     // verify (empty) refinement
     // (only works when post-processing is not applied)
     if ( fVerify )
     {
-        clk = clock();
+        clk = Abc_Clock();
         Rnm_ManVerifyUsingTerSim( p->pGia, p->pCex, p->vMap, p->vObjs, vGoodPPis );
-        p->timeVer += clock() - clk;
+        p->timeVer += Abc_Clock() - clk;
     }
 
     // at this point array vGoodPPis contains the set of important PPIs
@@ -737,7 +737,7 @@ Vec_Int_t * Rnm_ManRefine( Rnm_Man_t * p, Abc_Cex_t * pCex, Vec_Int_t * vMap, in
     Rnm_ManCleanValues( p );
 
 //    Vec_IntReverseOrder( vGoodPPis );
-    p->timeTotal += clock() - clk2;
+    p->timeTotal += Abc_Clock() - clk2;
     p->nRefines += Vec_IntSize(vGoodPPis);
     return vGoodPPis;
 }
diff --git a/src/proof/abs/absRef.h b/src/proof/abs/absRef.h
index 9bae40a3..93c054aa 100644
--- a/src/proof/abs/absRef.h
+++ b/src/proof/abs/absRef.h
@@ -83,10 +83,10 @@ struct Rnm_Man_t_
     int             nRefines;        // total refined objects
     int             nVisited;        // visited during justification
     // statistics  
-    clock_t         timeFwd;         // forward propagation
-    clock_t         timeBwd;         // backward propagation
-    clock_t         timeVer;         // ternary simulation
-    clock_t         timeTotal;       // other time
+    abctime         timeFwd;         // forward propagation
+    abctime         timeBwd;         // backward propagation
+    abctime         timeVer;         // ternary simulation
+    abctime         timeTotal;       // other time
 };
 
 // accessing the refinement object
diff --git a/src/proof/abs/absRpm.c b/src/proof/abs/absRpm.c
index edb60083..ef5747c1 100644
--- a/src/proof/abs/absRpm.c
+++ b/src/proof/abs/absRpm.c
@@ -110,7 +110,7 @@ void Gia_ManTestDoms2( Gia_Man_t * p )
 {
     Vec_Int_t * vNodes;
     Gia_Obj_t * pObj, * pDom;
-    clock_t clk = clock();
+    abctime clk = Abc_Clock();
     int i;
     assert( p->vDoms == NULL );
     Gia_ManComputeDoms( p );
@@ -119,7 +119,7 @@ void Gia_ManTestDoms2( Gia_Man_t * p )
         if ( Gia_ObjId(p, pObj) != Gia_ObjDom(p, pObj) )
             printf( "PI =%6d  Id =%8d. Dom =%8d.\n", i, Gia_ObjId(p, pObj), Gia_ObjDom(p, pObj) );
 */
-    Abc_PrintTime( 1, "Time", clock() - clk );
+    Abc_PrintTime( 1, "Time", Abc_Clock() - clk );
     // for each dominated PI, when if the PIs is in a leaf of the MFFC of the dominator
     Gia_ManCleanMark1( p );
     Gia_ManForEachPi( p, pObj, i )
diff --git a/src/proof/abs/absVta.c b/src/proof/abs/absVta.c
index 4b943870..01680a3f 100644
--- a/src/proof/abs/absVta.c
+++ b/src/proof/abs/absVta.c
@@ -71,10 +71,10 @@ struct Vta_Man_t_
     sat_solver2 * pSat;         // incremental SAT solver
     Vec_Int_t *   vAddedNew;    // the IDs of variables added to the solver
     // statistics 
-    clock_t       timeSat;
-    clock_t       timeUnsat;
-    clock_t       timeCex;
-    clock_t       timeOther;
+    abctime       timeSat;
+    abctime       timeUnsat;
+    abctime       timeCex;
+    abctime       timeOther;
 };
 
 
@@ -1082,7 +1082,7 @@ static inline int Vga_ManGetOutLit( Vta_Man_t * p, int f )
 ***********************************************************************/
 Vec_Int_t * Vta_ManUnsatCore( int iLit, sat_solver2 * pSat, int nConfMax, int fVerbose, int * piRetValue, int * pnConfls )
 {
-    clock_t clk = clock();
+    abctime clk = Abc_Clock();
     Vec_Int_t * vCore;
     int RetValue, nConfPrev = pSat->stats.conflicts;
     if ( piRetValue )
@@ -1115,16 +1115,16 @@ Vec_Int_t * Vta_ManUnsatCore( int iLit, sat_solver2 * pSat, int nConfMax, int fV
     {
 //        Abc_Print( 1, "%6d", (int)pSat->stats.conflicts - nConfPrev );
 //        Abc_Print( 1, "UNSAT after %7d conflicts.      ", pSat->stats.conflicts );
-//        Abc_PrintTime( 1, "Time", clock() - clk );
+//        Abc_PrintTime( 1, "Time", Abc_Clock() - clk );
     }
     assert( RetValue == l_False );
     // derive the UNSAT core
-    clk = clock();
+    clk = Abc_Clock();
     vCore = (Vec_Int_t *)Sat_ProofCore( pSat );
     if ( fVerbose )
     {
 //        Abc_Print( 1, "Core is %8d vars    (out of %8d).   ", Vec_IntSize(vCore), sat_solver2_nvars(pSat) );
-//        Abc_PrintTime( 1, "Time", clock() - clk );
+//        Abc_PrintTime( 1, "Time", Abc_Clock() - clk );
     }
     return vCore;
 }
@@ -1140,7 +1140,7 @@ Vec_Int_t * Vta_ManUnsatCore( int iLit, sat_solver2 * pSat, int nConfMax, int fV
   SeeAlso     []
 
 ***********************************************************************/
-int Vta_ManAbsPrintFrame( Vta_Man_t * p, Vec_Int_t * vCore, int nFrames, int nConfls, int nCexes, clock_t Time, int fVerbose )
+int Vta_ManAbsPrintFrame( Vta_Man_t * p, Vec_Int_t * vCore, int nFrames, int nConfls, int nCexes, abctime Time, int fVerbose )
 {
     unsigned * pInfo;
     int * pCountAll = NULL, * pCountUni = NULL;
@@ -1495,7 +1495,7 @@ int Gia_VtaPerformInt( Gia_Man_t * pAig, Abs_Par_t * pPars )
     Vec_Int_t * vCore;
     Abc_Cex_t * pCex = NULL;
     int i, f, nConfls, Status, nObjOld, RetValue = -1, nCountNoChange = 0, fOneIsSent = 0;
-    clock_t clk = clock(), clk2;
+    abctime clk = Abc_Clock(), clk2;
     // preconditions
     assert( Gia_ManPoNum(pAig) == 1 );
     assert( pPars->nFramesMax == 0 || pPars->nFramesStart <= pPars->nFramesMax );
@@ -1525,7 +1525,7 @@ int Gia_VtaPerformInt( Gia_Man_t * pAig, Abs_Par_t * pPars )
     p = Vga_ManStart( pAig, pPars );
     // set runtime limit
     if ( p->pPars->nTimeOut )
-        sat_solver2_set_runtime_limit( p->pSat, p->pPars->nTimeOut * CLOCKS_PER_SEC + clock() );
+        sat_solver2_set_runtime_limit( p->pSat, p->pPars->nTimeOut * CLOCKS_PER_SEC + Abc_Clock() );
     // perform initial abstraction
     if ( p->pPars->fVerbose )
     {
@@ -1564,7 +1564,7 @@ int Gia_VtaPerformInt( Gia_Man_t * pAig, Abs_Par_t * pPars )
         // iterate as long as there are counter-examples
         for ( i = 0; ; i++ )
         { 
-            clk2 = clock();
+            clk2 = Abc_Clock();
             vCore = Vta_ManUnsatCore( Vga_ManGetOutLit(p, f), p->pSat, pPars->nConfLimit, pPars->fVerbose, &Status, &nConfls );
             assert( (vCore != NULL) == (Status == 1) );
             if ( Status == -1 ) // resource limit is reached
@@ -1573,27 +1573,27 @@ int Gia_VtaPerformInt( Gia_Man_t * pAig, Abs_Par_t * pPars )
                 goto finish;
             }
             // check timeout
-            if ( p->pSat->nRuntimeLimit && clock() > p->pSat->nRuntimeLimit )
+            if ( p->pSat->nRuntimeLimit && Abc_Clock() > p->pSat->nRuntimeLimit )
             {
                 Vga_ManRollBack( p, nObjOld );
                 goto finish;
             }
             if ( vCore != NULL )
             {
-                p->timeUnsat += clock() - clk2;
+                p->timeUnsat += Abc_Clock() - clk2;
                 break;
             }
-            p->timeSat += clock() - clk2;
+            p->timeSat += Abc_Clock() - clk2;
             assert( Status == 0 );
             p->nCexes++;
             // perform the refinement
-            clk2 = clock();
+            clk2 = Abc_Clock();
             pCex = Vta_ManRefineAbstraction( p, f );
-            p->timeCex += clock() - clk2;
+            p->timeCex += Abc_Clock() - clk2;
             if ( pCex != NULL )
                 goto finish;
             // print the result (do not count it towards change)
-            Vta_ManAbsPrintFrame( p, NULL, f+1, sat_solver2_nconflicts(p->pSat)-nConflsBeg, i, clock() - clk, p->pPars->fVerbose );
+            Vta_ManAbsPrintFrame( p, NULL, f+1, sat_solver2_nconflicts(p->pSat)-nConflsBeg, i, Abc_Clock() - clk, p->pPars->fVerbose );
         }
         assert( Status == 1 );
         // valid core is obtained
@@ -1608,9 +1608,9 @@ int Gia_VtaPerformInt( Gia_Man_t * pAig, Abs_Par_t * pPars )
         Vec_IntFree( vCore );
 
         // run SAT solver
-        clk2 = clock();
+        clk2 = Abc_Clock();
         vCore = Vta_ManUnsatCore( Vga_ManGetOutLit(p, f), p->pSat, pPars->nConfLimit, p->pPars->fVerbose, &Status, &nConfls );
-        p->timeUnsat += clock() - clk2;
+        p->timeUnsat += Abc_Clock() - clk2;
         assert( (vCore != NULL) == (Status == 1) );
         if ( Status == -1 ) // resource limit is reached
             break;
@@ -1628,7 +1628,7 @@ int Gia_VtaPerformInt( Gia_Man_t * pAig, Abs_Par_t * pPars )
         Vec_IntSort( vCore, 1 );
         Vec_PtrPush( p->vCores, vCore );
         // print the result
-        if ( Vta_ManAbsPrintFrame( p, vCore, f+1, sat_solver2_nconflicts(p->pSat)-nConflsBeg, i, clock() - clk, p->pPars->fVerbose ) )
+        if ( Vta_ManAbsPrintFrame( p, vCore, f+1, sat_solver2_nconflicts(p->pSat)-nConflsBeg, i, Abc_Clock() - clk, p->pPars->fVerbose ) )
         {
             // reset the counter of frames without change
             nCountNoChange = 1;
@@ -1682,7 +1682,7 @@ finish:
             pAig->vObjClasses = Gia_VtaFramesToAbs( (Vec_Vec_t *)p->vCores );
             if ( Status == -1 )
             {
-                if ( p->pPars->nTimeOut && clock() >= p->pSat->nRuntimeLimit ) 
+                if ( p->pPars->nTimeOut && Abc_Clock() >= p->pSat->nRuntimeLimit ) 
                     Abc_Print( 1, "Timeout %d sec in frame %d with a %d-stable abstraction.    ", p->pPars->nTimeOut, f, p->pPars->nFramesNoChange );
                 else if ( pPars->nConfLimit && sat_solver2_nconflicts(p->pSat) >= pPars->nConfLimit )
                     Abc_Print( 1, "Exceeded %d conflicts in frame %d with a %d-stable abstraction.  ", pPars->nConfLimit, f, p->pPars->nFramesNoChange );
@@ -1711,16 +1711,16 @@ finish:
         Vec_IntFreeP( &pAig->vObjClasses );
         RetValue = 0;
     }
-    Abc_PrintTime( 1, "Time", clock() - clk );
+    Abc_PrintTime( 1, "Time", Abc_Clock() - clk );
 
     if ( p->pPars->fVerbose )
     {
-        p->timeOther = (clock() - clk) - p->timeUnsat - p->timeSat - p->timeCex;
-        ABC_PRTP( "Runtime: Solver UNSAT", p->timeUnsat,  clock() - clk );
-        ABC_PRTP( "Runtime: Solver SAT  ", p->timeSat,    clock() - clk );
-        ABC_PRTP( "Runtime: Refinement  ", p->timeCex,    clock() - clk );
-        ABC_PRTP( "Runtime: Other       ", p->timeOther,  clock() - clk );
-        ABC_PRTP( "Runtime: TOTAL       ", clock() - clk, clock() - clk );
+        p->timeOther = (Abc_Clock() - clk) - p->timeUnsat - p->timeSat - p->timeCex;
+        ABC_PRTP( "Runtime: Solver UNSAT", p->timeUnsat,  Abc_Clock() - clk );
+        ABC_PRTP( "Runtime: Solver SAT  ", p->timeSat,    Abc_Clock() - clk );
+        ABC_PRTP( "Runtime: Refinement  ", p->timeCex,    Abc_Clock() - clk );
+        ABC_PRTP( "Runtime: Other       ", p->timeOther,  Abc_Clock() - clk );
+        ABC_PRTP( "Runtime: TOTAL       ", Abc_Clock() - clk, Abc_Clock() - clk );
         Gia_VtaPrintMemory( p );
     }
 
diff --git a/src/proof/bbr/bbrCex.c b/src/proof/bbr/bbrCex.c
index 60fef07c..31a46d61 100644
--- a/src/proof/bbr/bbrCex.c
+++ b/src/proof/bbr/bbrCex.c
@@ -55,7 +55,7 @@ Abc_Cex_t * Aig_ManVerifyUsingBddsCountExample( Aig_Man_t * p, DdManager * dd,
     DdNode * bTemp, * bVar, * bRing;
     int i, v, RetValue, nPiOffset;
     char * pValues;
-    clock_t clk = clock();
+    abctime clk = Abc_Clock();
 //printf( "\nDeriving counter-example.\n" );
 
     // allocate room for the counter-example
@@ -158,7 +158,7 @@ Abc_Cex_t * Aig_ManVerifyUsingBddsCountExample( Aig_Man_t * p, DdManager * dd,
     }
     if ( fVerbose && !fSilent )
     {
-    ABC_PRT( "Counter-example generation time", clock() - clk );
+    ABC_PRT( "Counter-example generation time", Abc_Clock() - clk );
     }
     return pCex;
 }
diff --git a/src/proof/bbr/bbrReach.c b/src/proof/bbr/bbrReach.c
index 0becaa39..b5125ec7 100644
--- a/src/proof/bbr/bbrReach.c
+++ b/src/proof/bbr/bbrReach.c
@@ -247,7 +247,7 @@ int Aig_ManComputeReachable( DdManager * dd, Aig_Man_t * p, DdNode ** pbParts, D
     Cudd_ReorderingType method;
     int i, nIters, nBddSize = 0, status;
     int nThreshold = 10000;
-    clock_t clk = clock();
+    abctime clk = Abc_Clock();
     Vec_Ptr_t * vOnionRings;
     int fixedPoint = 0;
 
@@ -282,7 +282,7 @@ int Aig_ManComputeReachable( DdManager * dd, Aig_Man_t * p, DdNode ** pbParts, D
     for ( nIters = 0; nIters < pPars->nIterMax; nIters++ )
     { 
         // check the runtime limit
-        if ( pPars->TimeLimit && pPars->TimeLimit <= (clock()-clk)/CLOCKS_PER_SEC )
+        if ( pPars->TimeLimit && pPars->TimeLimit <= (Abc_Clock()-clk)/CLOCKS_PER_SEC )
         {
             printf( "Reached timeout after image computation (%d seconds).\n",  pPars->TimeLimit );
             Vec_PtrFree( vOnionRings );
@@ -442,7 +442,7 @@ int Aig_ManVerifyUsingBdds_int( Aig_Man_t * p, Saig_ParBbr_t * pPars )
     DdNode ** pbParts, ** pbOutputs;
     DdNode * bInitial, * bTemp;
     int RetValue, i;
-    clock_t clk = clock();
+    abctime clk = Abc_Clock();
     Vec_Ptr_t * vOnionRings;
 
     assert( Saig_ManRegNum(p) > 0 );
@@ -459,7 +459,7 @@ int Aig_ManVerifyUsingBdds_int( Aig_Man_t * p, Saig_ParBbr_t * pPars )
         printf( "Shared BDD size is %6d nodes.\n", Cudd_ReadKeys(dd) - Cudd_ReadDead(dd) );
 
     // check the runtime limit
-    if ( pPars->TimeLimit && pPars->TimeLimit <= (clock()-clk)/CLOCKS_PER_SEC )
+    if ( pPars->TimeLimit && pPars->TimeLimit <= (Abc_Clock()-clk)/CLOCKS_PER_SEC )
     {
         printf( "Reached timeout after constructing global BDDs (%d seconds).\n",  pPars->TimeLimit );
         Cudd_Quit( dd );
@@ -524,7 +524,7 @@ int Aig_ManVerifyUsingBdds_int( Aig_Man_t * p, Saig_ParBbr_t * pPars )
     // report the runtime
     if ( !pPars->fSilent )
     {
-    ABC_PRT( "Time", clock() - clk );
+    ABC_PRT( "Time", Abc_Clock() - clk );
     fflush( stdout );
     }
     return RetValue;
diff --git a/src/proof/cec/cecCec.c b/src/proof/cec/cecCec.c
index 37df4d8d..aa6d753a 100644
--- a/src/proof/cec/cecCec.c
+++ b/src/proof/cec/cecCec.c
@@ -73,7 +73,7 @@ int Cec_ManVerifyOld( Gia_Man_t * pMiter, int fVerbose, int * piOutFail )
     Gia_Man_t * pTemp = Gia_ManTransformMiter( pMiter );
     Aig_Man_t * pMiterCec = Gia_ManToAig( pTemp, 0 );
     int RetValue, iOut, nOuts;
-    clock_t clkTotal = clock();
+    abctime clkTotal = Abc_Clock();
     if ( piOutFail )
         *piOutFail = -1;
     Gia_ManStop( pTemp );
@@ -83,12 +83,12 @@ int Cec_ManVerifyOld( Gia_Man_t * pMiter, int fVerbose, int * piOutFail )
     if ( RetValue == 1 )
     {
         Abc_Print( 1, "Networks are equivalent.   " );
-Abc_PrintTime( 1, "Time", clock() - clkTotal );
+Abc_PrintTime( 1, "Time", Abc_Clock() - clkTotal );
     }
     else if ( RetValue == 0 )
     {
         Abc_Print( 1, "Networks are NOT EQUIVALENT.   " );
-Abc_PrintTime( 1, "Time", clock() - clkTotal );
+Abc_PrintTime( 1, "Time", Abc_Clock() - clkTotal );
         if ( pMiterCec->pData == NULL )
             Abc_Print( 1, "Counter-example is not available.\n" );
         else
@@ -113,7 +113,7 @@ Abc_PrintTime( 1, "Time", clock() - clkTotal );
     else
     {
         Abc_Print( 1, "Networks are UNDECIDED.   " );
-Abc_PrintTime( 1, "Time", clock() - clkTotal );
+Abc_PrintTime( 1, "Time", Abc_Clock() - clkTotal );
     }
     fflush( stdout );
     Aig_ManStop( pMiterCec );
@@ -136,7 +136,7 @@ int Cec_ManHandleSpecialCases( Gia_Man_t * p, Cec_ParCec_t * pPars )
     Gia_Obj_t * pObj1, * pObj2;
     Gia_Obj_t * pDri1, * pDri2;
     int i;
-    clock_t clk = clock();
+    abctime clk = Abc_Clock();
     Gia_ManSetPhase( p );
     Gia_ManForEachPo( p, pObj1, i )
     {
@@ -146,7 +146,7 @@ int Cec_ManHandleSpecialCases( Gia_Man_t * p, Cec_ParCec_t * pPars )
         if ( Gia_ObjPhase(pObj1) != Gia_ObjPhase(pObj2) )
         {
             Abc_Print( 1, "Networks are NOT EQUIVALENT. Outputs %d trivially differ (different phase).  ", i/2 );
-            Abc_PrintTime( 1, "Time", clock() - clk );
+            Abc_PrintTime( 1, "Time", Abc_Clock() - clk );
             pPars->iOutFail = i/2;
             Cec_ManTransformPattern( p, i/2, NULL );
             return 0;
@@ -158,7 +158,7 @@ int Cec_ManHandleSpecialCases( Gia_Man_t * p, Cec_ParCec_t * pPars )
         if ( Gia_ObjIsPi(p, pDri1) && Gia_ObjIsPi(p, pDri2) && pDri1 != pDri2 )
         {
             Abc_Print( 1, "Networks are NOT EQUIVALENT. Outputs %d trivially differ (different PIs).  ", i/2 );
-            Abc_PrintTime( 1, "Time", clock() - clk );
+            Abc_PrintTime( 1, "Time", Abc_Clock() - clk );
             pPars->iOutFail = i/2;
             Cec_ManTransformPattern( p, i/2, NULL );
             // if their compl attributes are the same - one should be complemented
@@ -171,7 +171,7 @@ int Cec_ManHandleSpecialCases( Gia_Man_t * p, Cec_ParCec_t * pPars )
              (Gia_ObjIsPi(p, pDri2) && Gia_ObjIsConst0(pDri1)) )
         {
             Abc_Print( 1, "Networks are NOT EQUIVALENT. Outputs %d trivially differ (PI vs. constant).  ", i/2 );
-            Abc_PrintTime( 1, "Time", clock() - clk );
+            Abc_PrintTime( 1, "Time", Abc_Clock() - clk );
             pPars->iOutFail = i/2;
             Cec_ManTransformPattern( p, i/2, NULL );
             // the compl attributes are the same - the PI should be complemented
@@ -186,7 +186,7 @@ int Cec_ManHandleSpecialCases( Gia_Man_t * p, Cec_ParCec_t * pPars )
     if ( Gia_ManAndNum(p) == 0 )
     {
         Abc_Print( 1, "Networks are equivalent.  " );
-        Abc_PrintTime( 1, "Time", clock() - clk );
+        Abc_PrintTime( 1, "Time", Abc_Clock() - clk );
         return 1;
     }
     return -1;
@@ -209,8 +209,8 @@ int Cec_ManVerify( Gia_Man_t * pInit, Cec_ParCec_t * pPars )
     Cec_ParFra_t ParsFra, * pParsFra = &ParsFra;
     Gia_Man_t * p, * pNew;
     int RetValue;
-    clock_t clk = clock();
-    clock_t clkTotal = clock();
+    abctime clk = Abc_Clock();
+    abctime clkTotal = Abc_Clock();
     // consider special cases:
     // 1) (SAT) a pair of POs have different value under all-0 pattern
     // 2) (SAT) a pair of POs has different PI/Const drivers
@@ -245,7 +245,7 @@ int Cec_ManVerify( Gia_Man_t * pInit, Cec_ParCec_t * pPars )
             if ( p->pCexComb && !Gia_ManVerifyCex( p, p->pCexComb, 1 ) )
                 Abc_Print( 1, "Counter-example simulation has failed.\n" );
             Abc_Print( 1, "Networks are NOT EQUIVALENT.  " );
-            Abc_PrintTime( 1, "Time", clock() - clk );
+            Abc_PrintTime( 1, "Time", Abc_Clock() - clk );
             return 0;
         }
         p = Gia_ManDup( pInit );
@@ -257,7 +257,7 @@ int Cec_ManVerify( Gia_Man_t * pInit, Cec_ParCec_t * pPars )
     if ( pPars->fVerbose )
     {
         Abc_Print( 1, "Networks are UNDECIDED after the new CEC engine.  " );
-        Abc_PrintTime( 1, "Time", clock() - clk );
+        Abc_PrintTime( 1, "Time", Abc_Clock() - clk );
     }
     if ( fDumpUndecided )
     {
@@ -266,7 +266,7 @@ int Cec_ManVerify( Gia_Man_t * pInit, Cec_ParCec_t * pPars )
         Gia_AigerWrite( pNew, "gia_cec_undecided.aig", 0, 0 );
         Abc_Print( 1, "The result is written into file \"%s\".\n", "gia_cec_undecided.aig" );
     }
-    if ( pPars->TimeLimit && (clock() - clkTotal)/CLOCKS_PER_SEC >= pPars->TimeLimit )
+    if ( pPars->TimeLimit && (Abc_Clock() - clkTotal)/CLOCKS_PER_SEC >= pPars->TimeLimit )
     {
         Gia_ManStop( pNew );
         return -1;
diff --git a/src/proof/cec/cecChoice.c b/src/proof/cec/cecChoice.c
index c07b9112..01b5adec 100644
--- a/src/proof/cec/cecChoice.c
+++ b/src/proof/cec/cecChoice.c
@@ -209,8 +209,8 @@ int Cec_ManChoiceComputation_int( Gia_Man_t * pAig, Cec_ParChc_t * pPars )
     Cec_ManSim_t * pSim;
     Gia_Man_t * pSrm;
     int r, RetValue;
-    clock_t clkSat = 0, clkSim = 0, clkSrm = 0, clkTotal = clock();
-    clock_t clk2, clk = clock();
+    abctime clkSat = 0, clkSim = 0, clkSrm = 0, clkTotal = Abc_Clock();
+    abctime clk2, clk = Abc_Clock();
     ABC_FREE( pAig->pReprs );
     ABC_FREE( pAig->pNexts );
     Gia_ManRandom( 1 );
@@ -233,51 +233,51 @@ int Cec_ManChoiceComputation_int( Gia_Man_t * pAig, Cec_ParChc_t * pPars )
     {
         Abc_Print( 1, "Obj = %7d. And = %7d. Conf = %5d. Ring = %d. CSat = %d.\n",
             Gia_ManObjNum(pAig), Gia_ManAndNum(pAig), pPars->nBTLimit, pPars->fUseRings, pPars->fUseCSat );
-        Cec_ManRefinedClassPrintStats( pAig, NULL, 0, clock() - clk );
+        Cec_ManRefinedClassPrintStats( pAig, NULL, 0, Abc_Clock() - clk );
     }
     // perform refinement of equivalence classes
     for ( r = 0; r < nItersMax; r++ )
     { 
-        clk = clock();
+        clk = Abc_Clock();
         // perform speculative reduction
-        clk2 = clock();
+        clk2 = Abc_Clock();
         pSrm = Cec_ManCombSpecReduce( pAig, &vOutputs, pPars->fUseRings );
         assert( Gia_ManRegNum(pSrm) == 0 && Gia_ManCiNum(pSrm) == Gia_ManCiNum(pAig) );
-        clkSrm += clock() - clk2;
+        clkSrm += Abc_Clock() - clk2;
         if ( Gia_ManCoNum(pSrm) == 0 )
         {
             if ( pPars->fVerbose )
-                Cec_ManRefinedClassPrintStats( pAig, NULL, r+1, clock() - clk );
+                Cec_ManRefinedClassPrintStats( pAig, NULL, r+1, Abc_Clock() - clk );
             Vec_IntFree( vOutputs );
             Gia_ManStop( pSrm );            
             break;
         }
 //Gia_DumpAiger( pSrm, "choicesrm", r, 2 );
         // found counter-examples to speculation
-        clk2 = clock();
+        clk2 = Abc_Clock();
         if ( pPars->fUseCSat )
             vCexStore = Cbs_ManSolveMiterNc( pSrm, pPars->nBTLimit, &vStatus, 0 );
         else
             vCexStore = Cec_ManSatSolveMiter( pSrm, pParsSat, &vStatus );
         Gia_ManStop( pSrm );
-        clkSat += clock() - clk2;
+        clkSat += Abc_Clock() - clk2;
         if ( Vec_IntSize(vCexStore) == 0 )
         {
             if ( pPars->fVerbose )
-                Cec_ManRefinedClassPrintStats( pAig, vStatus, r+1, clock() - clk );
+                Cec_ManRefinedClassPrintStats( pAig, vStatus, r+1, Abc_Clock() - clk );
             Vec_IntFree( vCexStore );
             Vec_StrFree( vStatus );
             Vec_IntFree( vOutputs );
             break;
         }
         // refine classes with these counter-examples
-        clk2 = clock();
+        clk2 = Abc_Clock();
         RetValue = Cec_ManResimulateCounterExamplesComb( pSim, vCexStore );
         Vec_IntFree( vCexStore );
-        clkSim += clock() - clk2;
+        clkSim += Abc_Clock() - clk2;
         Gia_ManCheckRefinements( pAig, vStatus, vOutputs, pSim, pPars->fUseRings );
         if ( pPars->fVerbose )
-            Cec_ManRefinedClassPrintStats( pAig, vStatus, r+1, clock() - clk );
+            Cec_ManRefinedClassPrintStats( pAig, vStatus, r+1, Abc_Clock() - clk );
         Vec_StrFree( vStatus );
         Vec_IntFree( vOutputs );
 //Gia_ManEquivPrintClasses( pAig, 1, 0 );
@@ -286,7 +286,7 @@ int Cec_ManChoiceComputation_int( Gia_Man_t * pAig, Cec_ParChc_t * pPars )
     if ( r == nItersMax )
         Abc_Print( 1, "The refinement was not finished. The result may be incorrect.\n" );
     Cec_ManSimStop( pSim );
-    clkTotal = clock() - clkTotal;
+    clkTotal = Abc_Clock() - clkTotal;
     // report the results
     if ( pPars->fVerbose )
     {
diff --git a/src/proof/cec/cecCore.c b/src/proof/cec/cecCore.c
index 40d5fba6..051a5126 100644
--- a/src/proof/cec/cecCore.c
+++ b/src/proof/cec/cecCore.c
@@ -258,14 +258,14 @@ int Cec_ManSimulationOne( Gia_Man_t * pAig, Cec_ParSim_t * pPars )
 {
     Cec_ManSim_t * pSim;
     int RetValue = 0;
-    clock_t clkTotal = clock();
+    abctime clkTotal = Abc_Clock();
     pSim = Cec_ManSimStart( pAig, pPars );
     if ( (pAig->pReprs == NULL && (RetValue = Cec_ManSimClassesPrepare( pSim, -1 ))) ||
          (RetValue == 0 &&        (RetValue = Cec_ManSimClassesRefine( pSim ))) )
         Abc_Print( 1, "The number of failed outputs of the miter = %6d. (Words = %4d. Frames = %4d.)\n", 
             pSim->nOuts, pPars->nWords, pPars->nFrames );
     if ( pPars->fVerbose )
-        Abc_PrintTime( 1, "Time", clock() - clkTotal );
+        Abc_PrintTime( 1, "Time", Abc_Clock() - clkTotal );
     Cec_ManSimStop( pSim );
     return RetValue;
 }
@@ -344,7 +344,7 @@ Gia_Man_t * Cec_ManSatSweeping( Gia_Man_t * pAig, Cec_ParFra_t * pPars )
     Cec_ManSim_t * pSim;
     Cec_ManPat_t * pPat;
     int i, fTimeOut = 0, nMatches = 0;
-    clock_t clk, clk2, clkTotal = clock();
+    abctime clk, clk2, clkTotal = Abc_Clock();
 
     // duplicate AIG and transfer equivalence classes
     Gia_ManRandom( 1 );
@@ -374,7 +374,7 @@ Gia_Man_t * Cec_ManSatSweeping( Gia_Man_t * pAig, Cec_ParFra_t * pPars )
     pPat->fVerbose = pPars->fVeryVerbose;
 
     // start equivalence classes
-clk = clock();
+clk = Abc_Clock();
     if ( p->pAig->pReprs == NULL )
     {
         if ( Cec_ManSimClassesPrepare(pSim, -1) || Cec_ManSimClassesRefine(pSim) )
@@ -384,11 +384,11 @@ clk = clock();
             goto finalize;
         }
     }
-p->timeSim += clock() - clk;
+p->timeSim += Abc_Clock() - clk;
     // perform solving
     for ( i = 1; i <= pPars->nItersMax; i++ )
     {
-        clk2 = clock();
+        clk2 = Abc_Clock();
         nMatches = 0;
         if ( pPars->fDualOut )
         {
@@ -425,9 +425,9 @@ p->timeSim += clock() - clk;
             }
             break;
         }
-clk = clock();
+clk = Abc_Clock();
         Cec_ManSatSolve( pPat, pSrm, pParsSat ); 
-p->timeSat += clock() - clk;
+p->timeSat += Abc_Clock() - clk;
         if ( Cec_ManFraClassesUpdate( p, pSim, pPat, pSrm ) )
         {
             Gia_ManStop( pSrm );
@@ -449,7 +449,7 @@ p->timeSat += clock() - clk;
         {
             Abc_Print( 1, "%3d : P =%7d. D =%7d. F =%6d. M = %7d. And =%8d. ", 
                 i, p->nAllProved, p->nAllDisproved, p->nAllFailed, nMatches, Gia_ManAndNum(p->pAig) );
-            Abc_PrintTime( 1, "Time", clock() - clk2 );
+            Abc_PrintTime( 1, "Time", Abc_Clock() - clk2 );
         }
         if ( Gia_ManAndNum(p->pAig) == 0 )
         {
@@ -458,7 +458,7 @@ p->timeSat += clock() - clk;
             break;
         }
         // check resource limits
-        if ( p->pPars->TimeLimit && (clock() - clkTotal)/CLOCKS_PER_SEC >= p->pPars->TimeLimit )
+        if ( p->pPars->TimeLimit && (Abc_Clock() - clkTotal)/CLOCKS_PER_SEC >= p->pPars->TimeLimit )
         {
             fTimeOut = 1;
             break;
@@ -509,10 +509,10 @@ finalize:
             100.0*(Gia_ManAndNum(pAig)-Gia_ManAndNum(p->pAig))/(Gia_ManAndNum(pAig)?Gia_ManAndNum(pAig):1), 
             Gia_ManRegNum(pAig), Gia_ManRegNum(p->pAig), 
             100.0*(Gia_ManRegNum(pAig)-Gia_ManRegNum(p->pAig))/(Gia_ManRegNum(pAig)?Gia_ManRegNum(pAig):1) );
-        Abc_PrintTimeP( 1, "Sim ", p->timeSim, clock() - (int)clkTotal );
-        Abc_PrintTimeP( 1, "Sat ", p->timeSat-pPat->timeTotalSave, clock() - (int)clkTotal );
-        Abc_PrintTimeP( 1, "Pat ", p->timePat+pPat->timeTotalSave, clock() - (int)clkTotal );
-        Abc_PrintTime( 1, "Time", (int)(clock() - clkTotal) );
+        Abc_PrintTimeP( 1, "Sim ", p->timeSim, Abc_Clock() - (int)clkTotal );
+        Abc_PrintTimeP( 1, "Sat ", p->timeSat-pPat->timeTotalSave, Abc_Clock() - (int)clkTotal );
+        Abc_PrintTimeP( 1, "Pat ", p->timePat+pPat->timeTotalSave, Abc_Clock() - (int)clkTotal );
+        Abc_PrintTime( 1, "Time", (int)(Abc_Clock() - clkTotal) );
     }
 
     pTemp = p->pAig; p->pAig = NULL;
@@ -524,7 +524,7 @@ finalize:
     else if ( pSim->pCexes )
         Abc_Print( 1, "Disproved %d outputs of the miter.\n", pSim->nOuts );
     if ( fTimeOut )
-        Abc_Print( 1, "Timed out after %d seconds.\n", (int)((double)clock() - clkTotal)/CLOCKS_PER_SEC );
+        Abc_Print( 1, "Timed out after %d seconds.\n", (int)((double)Abc_Clock() - clkTotal)/CLOCKS_PER_SEC );
 
     pAig->pCexComb = pSim->pCexComb; pSim->pCexComb = NULL;
     Cec_ManSimStop( pSim );
diff --git a/src/proof/cec/cecCorr.c b/src/proof/cec/cecCorr.c
index 4ea79935..fac30004 100644
--- a/src/proof/cec/cecCorr.c
+++ b/src/proof/cec/cecCorr.c
@@ -722,7 +722,7 @@ Gia_Man_t * Gia_ManCorrReduce( Gia_Man_t * p )
   SeeAlso     []
 
 ***********************************************************************/
-void Cec_ManRefinedClassPrintStats( Gia_Man_t * p, Vec_Str_t * vStatus, int iIter, clock_t Time )
+void Cec_ManRefinedClassPrintStats( Gia_Man_t * p, Vec_Str_t * vStatus, int iIter, abctime Time )
 { 
     int nLits, CounterX = 0, Counter0 = 0, Counter = 0;
     int i, Entry, nProve = 0, nDispr = 0, nFail = 0;
@@ -793,7 +793,7 @@ void Cec_ManLSCorrespondenceBmc( Gia_Man_t * pAig, Cec_ParCor_t * pPars, int nPr
     fChanges = 1;
     while ( fChanges )
     {
-        clock_t clkBmc = clock();
+        abctime clkBmc = Abc_Clock();
         fChanges = 0;
         pSrm = Gia_ManCorrSpecReduceInit( pAig, pPars->nFrames, nPrefs, !pPars->fLatchCorr, &vOutputs, pPars->fUseRings );
         if ( Gia_ManPoNum(pSrm) == 0 )
@@ -815,7 +815,7 @@ void Cec_ManLSCorrespondenceBmc( Gia_Man_t * pAig, Cec_ParCor_t * pPars, int nPr
             fChanges = 1;
         }
         if ( pPars->fVerbose )
-            Cec_ManRefinedClassPrintStats( pAig, vStatus, -1, clock() - clkBmc );
+            Cec_ManRefinedClassPrintStats( pAig, vStatus, -1, Abc_Clock() - clkBmc );
         // recycle
         Vec_IntFree( vCexStore );
         Vec_StrFree( vStatus );
@@ -919,9 +919,9 @@ int Cec_ManLSCorrespondenceClasses( Gia_Man_t * pAig, Cec_ParCor_t * pPars )
     Cec_ManSim_t * pSim;
     Gia_Man_t * pSrm;
     int r, RetValue;
-    clock_t clkTotal = clock();
-    clock_t clkSat = 0, clkSim = 0, clkSrm = 0;
-    clock_t clk2, clk = clock();
+    abctime clkTotal = Abc_Clock();
+    abctime clkSat = 0, clkSim = 0, clkSrm = 0;
+    abctime clk2, clk = Abc_Clock();
     if ( Gia_ManRegNum(pAig) == 0 )
     {
         Abc_Print( 1, "Cec_ManLatchCorrespondence(): Not a sequential AIG.\n" );
@@ -955,7 +955,7 @@ int Cec_ManLSCorrespondenceClasses( Gia_Man_t * pAig, Cec_ParCor_t * pPars )
         Abc_Print( 1, "Obj = %7d. And = %7d. Conf = %5d. Fr = %d. Lcorr = %d. Ring = %d. CSat = %d.\n",
             Gia_ManObjNum(pAig), Gia_ManAndNum(pAig), 
             pPars->nBTLimit, pPars->nFrames, pPars->fLatchCorr, pPars->fUseRings, pPars->fUseCSat );
-        Cec_ManRefinedClassPrintStats( pAig, NULL, 0, clock() - clk );
+        Cec_ManRefinedClassPrintStats( pAig, NULL, 0, Abc_Clock() - clk );
     }
     // check the base case
     if ( fRunBmcFirst && (!pPars->fLatchCorr || pPars->nFrames > 1) )
@@ -980,12 +980,12 @@ int Cec_ManLSCorrespondenceClasses( Gia_Man_t * pAig, Cec_ParCor_t * pPars )
             Abc_Print( 1, "Stopped signal correspondence after %d refiment iterations.\n", r );
             return 1;
         }
-        clk = clock();
+        clk = Abc_Clock();
         // perform speculative reduction
-        clk2 = clock();
+        clk2 = Abc_Clock();
         pSrm = Gia_ManCorrSpecReduce( pAig, pPars->nFrames, !pPars->fLatchCorr, &vOutputs, pPars->fUseRings );
         assert( Gia_ManRegNum(pSrm) == 0 && Gia_ManPiNum(pSrm) == Gia_ManRegNum(pAig)+(pPars->nFrames+!pPars->fLatchCorr)*Gia_ManPiNum(pAig) );
-        clkSrm += clock() - clk2;
+        clkSrm += Abc_Clock() - clk2;
         if ( Gia_ManCoNum(pSrm) == 0 )
         {
             Vec_IntFree( vOutputs );
@@ -994,13 +994,13 @@ int Cec_ManLSCorrespondenceClasses( Gia_Man_t * pAig, Cec_ParCor_t * pPars )
         }
 //Gia_DumpAiger( pSrm, "corrsrm", r, 2 );
         // found counter-examples to speculation
-        clk2 = clock();
+        clk2 = Abc_Clock();
         if ( pPars->fUseCSat )
             vCexStore = Cbs_ManSolveMiterNc( pSrm, pPars->nBTLimit, &vStatus, 0 );
         else
             vCexStore = Cec_ManSatSolveMiter( pSrm, pParsSat, &vStatus );
         Gia_ManStop( pSrm );
-        clkSat += clock() - clk2;
+        clkSat += Abc_Clock() - clk2;
         if ( Vec_IntSize(vCexStore) == 0 )
         {
             Vec_IntFree( vCexStore );
@@ -1011,13 +1011,13 @@ int Cec_ManLSCorrespondenceClasses( Gia_Man_t * pAig, Cec_ParCor_t * pPars )
 //        Cec_ManLSCorrAnalyzeDependence( pAig, vOutputs, vStatus );        
 
         // refine classes with these counter-examples
-        clk2 = clock();
+        clk2 = Abc_Clock();
         RetValue = Cec_ManResimulateCounterExamples( pSim, vCexStore, pPars->nFrames + 1 + nAddFrames );
         Vec_IntFree( vCexStore );
-        clkSim += clock() - clk2;
+        clkSim += Abc_Clock() - clk2;
         Gia_ManCheckRefinements( pAig, vStatus, vOutputs, pSim, pPars->fUseRings );
         if ( pPars->fVerbose )
-            Cec_ManRefinedClassPrintStats( pAig, vStatus, r+1, clock() - clk );
+            Cec_ManRefinedClassPrintStats( pAig, vStatus, r+1, Abc_Clock() - clk );
         Vec_StrFree( vStatus );
         Vec_IntFree( vOutputs );
 //Gia_ManEquivPrintClasses( pAig, 1, 0 );
@@ -1033,7 +1033,7 @@ int Cec_ManLSCorrespondenceClasses( Gia_Man_t * pAig, Cec_ParCor_t * pPars )
         }
     }
     if ( pPars->fVerbose )
-        Cec_ManRefinedClassPrintStats( pAig, NULL, r+1, clock() - clk );
+        Cec_ManRefinedClassPrintStats( pAig, NULL, r+1, Abc_Clock() - clk );
     // check the overflow
     if ( r == nIterMax )
         Abc_Print( 1, "The refinement was not finished. The result may be incorrect.\n" );
@@ -1041,7 +1041,7 @@ int Cec_ManLSCorrespondenceClasses( Gia_Man_t * pAig, Cec_ParCor_t * pPars )
     // check the base case
     if ( !fRunBmcFirst && (!pPars->fLatchCorr || pPars->nFrames > 1) )
         Cec_ManLSCorrespondenceBmc( pAig, pPars, 0 );
-    clkTotal = clock() - clkTotal;
+    clkTotal = Abc_Clock() - clkTotal;
     // report the results
     if ( pPars->fVerbose )
     {
diff --git a/src/proof/cec/cecInt.h b/src/proof/cec/cecInt.h
index 36ff3483..dd6dc618 100644
--- a/src/proof/cec/cecInt.h
+++ b/src/proof/cec/cecInt.h
@@ -61,13 +61,13 @@ struct Cec_ManPat_t_
     int              nSeries;        // simulation series
     int              fVerbose;       // verbose stats
     // runtime statistics
-    clock_t          timeFind;       // detecting the pattern  
-    clock_t          timeShrink;     // minimizing the pattern
-    clock_t          timeVerify;     // verifying the result of minimisation
-    clock_t          timeSort;       // sorting literals 
-    clock_t          timePack;       // packing into sim info structures 
-    clock_t          timeTotal;      // total runtime  
-    clock_t          timeTotalSave;  // total runtime for saving  
+    abctime          timeFind;       // detecting the pattern  
+    abctime          timeShrink;     // minimizing the pattern
+    abctime          timeVerify;     // verifying the result of minimisation
+    abctime          timeSort;       // sorting literals 
+    abctime          timePack;       // packing into sim info structures 
+    abctime          timeTotal;      // total runtime  
+    abctime          timeTotalSave;  // total runtime for saving  
 };
 
 // SAT solving manager
@@ -154,10 +154,10 @@ struct Cec_ManFra_t_
     int              nAllDisproved;  // total number of disproved nodes
     int              nAllFailed;     // total number of failed nodes
     // runtime stats
-    clock_t          timeSim;        // unsat
-    clock_t          timePat;        // unsat
-    clock_t          timeSat;        // sat
-    clock_t          timeTotal;      // total runtime
+    abctime          timeSim;        // unsat
+    abctime          timePat;        // unsat
+    abctime          timeSat;        // sat
+    abctime          timeTotal;      // total runtime
 };
 
 ////////////////////////////////////////////////////////////////////////
@@ -169,7 +169,7 @@ struct Cec_ManFra_t_
 ////////////////////////////////////////////////////////////////////////
 
 /*=== cecCorr.c ============================================================*/
-extern void                 Cec_ManRefinedClassPrintStats( Gia_Man_t * p, Vec_Str_t * vStatus, int iIter, clock_t Time );
+extern void                 Cec_ManRefinedClassPrintStats( Gia_Man_t * p, Vec_Str_t * vStatus, int iIter, abctime Time );
 /*=== cecClass.c ============================================================*/
 extern int                  Cec_ManSimClassRemoveOne( Cec_ManSim_t * p, int i );
 extern int                  Cec_ManSimClassesPrepare( Cec_ManSim_t * p, int LevelMax );
diff --git a/src/proof/cec/cecPat.c b/src/proof/cec/cecPat.c
index f372f3bb..c175eaa7 100644
--- a/src/proof/cec/cecPat.c
+++ b/src/proof/cec/cecPat.c
@@ -360,20 +360,20 @@ void Cec_ManPatSavePattern( Cec_ManPat_t * pMan, Cec_ManSat_t *  p, Gia_Obj_t *
 {
     Vec_Int_t * vPat;
     int nPatLits;
-    clock_t clk, clkTotal = clock();
+    abctime clk, clkTotal = Abc_Clock();
     assert( Gia_ObjIsCo(pObj) );
     pMan->nPats++;
     pMan->nPatsAll++;
     // compute values in the cone of influence
-clk = clock();
+clk = Abc_Clock();
     Gia_ManIncrementTravId( p->pAig );
     nPatLits = Cec_ManPatComputePattern_rec( p, p->pAig, Gia_ObjFanin0(pObj) );
     assert( (Gia_ObjFanin0(pObj)->fMark1 ^ Gia_ObjFaninC0(pObj)) == 1 );
     pMan->nPatLits += nPatLits;
     pMan->nPatLitsAll += nPatLits;
-pMan->timeFind += clock() - clk;
+pMan->timeFind += Abc_Clock() - clk;
     // compute sensitizing path
-clk = clock();
+clk = Abc_Clock();
     Vec_IntClear( pMan->vPattern1 );
     Gia_ManIncrementTravId( p->pAig );
     Cec_ManPatComputePattern1_rec( p->pAig, Gia_ObjFanin0(pObj), pMan->vPattern1 );
@@ -385,18 +385,18 @@ clk = clock();
     vPat = Vec_IntSize(pMan->vPattern1) < Vec_IntSize(pMan->vPattern2) ? pMan->vPattern1 : pMan->vPattern2;
     pMan->nPatLitsMin += Vec_IntSize(vPat);
     pMan->nPatLitsMinAll += Vec_IntSize(vPat);
-pMan->timeShrink += clock() - clk;
+pMan->timeShrink += Abc_Clock() - clk;
     // verify pattern using ternary simulation
-clk = clock();
+clk = Abc_Clock();
     Cec_ManPatVerifyPattern( p->pAig, pObj, vPat );
-pMan->timeVerify += clock() - clk;
+pMan->timeVerify += Abc_Clock() - clk;
     // sort pattern
-clk = clock();
+clk = Abc_Clock();
     Vec_IntSort( vPat, 0 );
-pMan->timeSort += clock() - clk;
+pMan->timeSort += Abc_Clock() - clk;
     // save pattern
     Cec_ManPatStore( pMan, vPat );
-    pMan->timeTotal += clock() - clkTotal;
+    pMan->timeTotal += Abc_Clock() - clkTotal;
 }
 
 /**Function*************************************************************
@@ -452,7 +452,7 @@ Vec_Ptr_t * Cec_ManPatCollectPatterns( Cec_ManPat_t *  pMan, int nInputs, int nW
     int iStartOld = pMan->iStart;
     int nWords = nWordsInit;
     int nBits = 32 * nWords;
-    clock_t clk = clock();
+    abctime clk = Abc_Clock();
     vInfo = Vec_PtrAllocSimInfo( nInputs, nWords );
     Gia_ManRandomInfo( vInfo, 0, 0, nWords );
     vPres = Vec_PtrAllocSimInfo( nInputs, nWords );
@@ -477,14 +477,14 @@ Vec_Ptr_t * Cec_ManPatCollectPatterns( Cec_ManPat_t *  pMan, int nInputs, int nW
     }
     Vec_PtrFree( vPres );
     pMan->nSeries = Vec_PtrReadWordsSimInfo(vInfo) / nWordsInit;
-    pMan->timePack += clock() - clk;
-    pMan->timeTotal += clock() - clk;
+    pMan->timePack += Abc_Clock() - clk;
+    pMan->timeTotal += Abc_Clock() - clk;
     pMan->iStart = iStartOld;
     if ( pMan->fVerbose )
     {
         Abc_Print( 1, "Total = %5d. Max used = %5d. Full = %5d. Series = %d. ", 
             nPatterns, kMax, nWordsInit*32, pMan->nSeries );
-        ABC_PRT( "Time", clock() - clk );
+        ABC_PRT( "Time", Abc_Clock() - clk );
         Cec_ManPatPrintStats( pMan );
     }
     return vInfo;
diff --git a/src/proof/cec/cecSeq.c b/src/proof/cec/cecSeq.c
index 43bfa99c..f39fb2a4 100644
--- a/src/proof/cec/cecSeq.c
+++ b/src/proof/cec/cecSeq.c
@@ -185,7 +185,7 @@ int Cec_ManSeqResimulateInfo( Gia_Man_t * pAig, Vec_Ptr_t * vSimInfo, Abc_Cex_t
 {
     Cec_ParSim_t ParsSim, * pParsSim = &ParsSim;
     Cec_ManSim_t * pSim;
-    int RetValue;//, clkTotal = clock();
+    int RetValue;//, clkTotal = Abc_Clock();
     assert( (Vec_PtrSize(vSimInfo) - Gia_ManRegNum(pAig)) % Gia_ManPiNum(pAig) == 0 );
     Cec_ManSimSetDefaultParams( pParsSim );
     pParsSim->nFrames = (Vec_PtrSize(vSimInfo) - Gia_ManRegNum(pAig)) / Gia_ManPiNum(pAig);
@@ -216,7 +216,7 @@ int Cec_ManSeqResimulateCounter( Gia_Man_t * pAig, Cec_ParSim_t * pPars, Abc_Cex
 {
     Vec_Ptr_t * vSimInfo;
     int RetValue;
-    clock_t clkTotal = clock();
+    abctime clkTotal = Abc_Clock();
     if ( pCex == NULL )
     {
         Abc_Print( 1, "Cec_ManSeqResimulateCounter(): Counter-example is not available.\n" );
@@ -251,7 +251,7 @@ int Cec_ManSeqResimulateCounter( Gia_Man_t * pAig, Cec_ParSim_t * pPars, Abc_Cex
         Gia_ManEquivPrintClasses( pAig, 0, 0 );
     Vec_PtrFree( vSimInfo );
     if ( pPars->fVerbose )
-        ABC_PRT( "Time", clock() - clkTotal );
+        ABC_PRT( "Time", Abc_Clock() - clkTotal );
 //    if ( RetValue && pPars->fCheckMiter )
 //        Abc_Print( 1, "Cec_ManSeqResimulateCounter(): An output of the miter is asserted!\n" );
     return RetValue;
diff --git a/src/proof/cec/cecSolve.c b/src/proof/cec/cecSolve.c
index d560c37a..c799d17d 100644
--- a/src/proof/cec/cecSolve.c
+++ b/src/proof/cec/cecSolve.c
@@ -472,7 +472,7 @@ int Cec_ManSatCheckNode( Cec_ManSat_t * p, Gia_Obj_t * pObj )
     Gia_Obj_t * pObjR = Gia_Regular(pObj);
     int nBTLimit = p->pPars->nBTLimit;
     int Lit, RetValue, status, nConflicts;
-    clock_t clk, clk2;
+    abctime clk, clk2;
 
     if ( pObj == Gia_ManConst0(p->pAig) )
         return 1;
@@ -493,14 +493,14 @@ int Cec_ManSatCheckNode( Cec_ManSat_t * p, Gia_Obj_t * pObj )
         Cec_ManSatSolverRecycle( p );
 
     // if the nodes do not have SAT variables, allocate them
-clk2 = clock();
+clk2 = Abc_Clock();
     Cec_CnfNodeAddToSolver( p, pObjR );
-//ABC_PRT( "cnf", clock() - clk2 );
+//ABC_PRT( "cnf", Abc_Clock() - clk2 );
 //Abc_Print( 1, "%d \n", p->pSat->size );
 
-clk2 = clock();
+clk2 = Abc_Clock();
 //    Cec_SetActivityFactors( p, pObjR ); 
-//ABC_PRT( "act", clock() - clk2 );
+//ABC_PRT( "act", Abc_Clock() - clk2 );
 
     // propage unit clauses
     if ( p->pSat->qtail != p->pSat->qhead )
@@ -518,17 +518,17 @@ clk2 = clock();
         if ( pObjR->fPhase )  Lit = lit_neg( Lit );
     }
 //Sat_SolverWriteDimacs( p->pSat, "temp.cnf", pLits, pLits + 2, 1 );
-clk = clock();
+clk = Abc_Clock();
     nConflicts = p->pSat->stats.conflicts;
 
-clk2 = clock();
+clk2 = Abc_Clock();
     RetValue = sat_solver_solve( p->pSat, &Lit, &Lit + 1, 
         (ABC_INT64_T)nBTLimit, (ABC_INT64_T)0, (ABC_INT64_T)0, (ABC_INT64_T)0 );
-//ABC_PRT( "sat", clock() - clk2 );
+//ABC_PRT( "sat", Abc_Clock() - clk2 );
 
     if ( RetValue == l_False )
     {
-p->timeSatUnsat += clock() - clk;
+p->timeSatUnsat += Abc_Clock() - clk;
         Lit = lit_neg( Lit );
         RetValue = sat_solver_addclause( p->pSat, &Lit, &Lit + 1 );
         assert( RetValue );
@@ -539,7 +539,7 @@ p->timeSatUnsat += clock() - clk;
     }
     else if ( RetValue == l_True )
     {
-p->timeSatSat += clock() - clk;
+p->timeSatSat += Abc_Clock() - clk;
         p->nSatSat++;
         p->nConfSat += p->pSat->stats.conflicts - nConflicts;
 //Abc_Print( 1, "SAT after %d conflicts\n", p->pSat->stats.conflicts - nConflicts );
@@ -547,7 +547,7 @@ p->timeSatSat += clock() - clk;
     }
     else // if ( RetValue == l_Undef )
     {
-p->timeSatUndec += clock() - clk;
+p->timeSatUndec += Abc_Clock() - clk;
         p->nSatUndec++;
         p->nConfUndec += p->pSat->stats.conflicts - nConflicts;
 //Abc_Print( 1, "UNDEC after %d conflicts\n", p->pSat->stats.conflicts - nConflicts );
@@ -572,7 +572,7 @@ int Cec_ManSatCheckNodeTwo( Cec_ManSat_t * p, Gia_Obj_t * pObj1, Gia_Obj_t * pOb
     Gia_Obj_t * pObjR2 = Gia_Regular(pObj2);
     int nBTLimit = p->pPars->nBTLimit;
     int Lits[2], RetValue, status, nConflicts;
-    clock_t clk, clk2;
+    abctime clk, clk2;
 
     if ( pObj1 == Gia_ManConst0(p->pAig) || pObj2 == Gia_ManConst0(p->pAig) || pObj1 == Gia_Not(pObj2) )
         return 1;
@@ -593,16 +593,16 @@ int Cec_ManSatCheckNodeTwo( Cec_ManSat_t * p, Gia_Obj_t * pObj1, Gia_Obj_t * pOb
         Cec_ManSatSolverRecycle( p );
 
     // if the nodes do not have SAT variables, allocate them
-clk2 = clock();
+clk2 = Abc_Clock();
     Cec_CnfNodeAddToSolver( p, pObjR1 );
     Cec_CnfNodeAddToSolver( p, pObjR2 );
-//ABC_PRT( "cnf", clock() - clk2 );
+//ABC_PRT( "cnf", Abc_Clock() - clk2 );
 //Abc_Print( 1, "%d \n", p->pSat->size );
 
-clk2 = clock();
+clk2 = Abc_Clock();
 //    Cec_SetActivityFactors( p, pObjR1 ); 
 //    Cec_SetActivityFactors( p, pObjR2 ); 
-//ABC_PRT( "act", clock() - clk2 );
+//ABC_PRT( "act", Abc_Clock() - clk2 );
 
     // propage unit clauses
     if ( p->pSat->qtail != p->pSat->qhead )
@@ -622,17 +622,17 @@ clk2 = clock();
         if ( pObjR2->fPhase )  Lits[1] = lit_neg( Lits[1] );
     }
 //Sat_SolverWriteDimacs( p->pSat, "temp.cnf", pLits, pLits + 2, 1 );
-clk = clock();
+clk = Abc_Clock();
     nConflicts = p->pSat->stats.conflicts;
 
-clk2 = clock();
+clk2 = Abc_Clock();
     RetValue = sat_solver_solve( p->pSat, Lits, Lits + 2, 
         (ABC_INT64_T)nBTLimit, (ABC_INT64_T)0, (ABC_INT64_T)0, (ABC_INT64_T)0 );
-//ABC_PRT( "sat", clock() - clk2 );
+//ABC_PRT( "sat", Abc_Clock() - clk2 );
 
     if ( RetValue == l_False )
     {
-p->timeSatUnsat += clock() - clk;
+p->timeSatUnsat += Abc_Clock() - clk;
         Lits[0] = lit_neg( Lits[0] );
         Lits[1] = lit_neg( Lits[1] );
         RetValue = sat_solver_addclause( p->pSat, Lits, Lits + 2 );
@@ -644,7 +644,7 @@ p->timeSatUnsat += clock() - clk;
     }
     else if ( RetValue == l_True )
     {
-p->timeSatSat += clock() - clk;
+p->timeSatSat += Abc_Clock() - clk;
         p->nSatSat++;
         p->nConfSat += p->pSat->stats.conflicts - nConflicts;
 //Abc_Print( 1, "SAT after %d conflicts\n", p->pSat->stats.conflicts - nConflicts );
@@ -652,7 +652,7 @@ p->timeSatSat += clock() - clk;
     }
     else // if ( RetValue == l_Undef )
     {
-p->timeSatUndec += clock() - clk;
+p->timeSatUndec += Abc_Clock() - clk;
         p->nSatUndec++;
         p->nConfUndec += p->pSat->stats.conflicts - nConflicts;
 //Abc_Print( 1, "UNDEC after %d conflicts\n", p->pSat->stats.conflicts - nConflicts );
@@ -679,7 +679,7 @@ void Cec_ManSatSolve( Cec_ManPat_t * pPat, Gia_Man_t * pAig, Cec_ParSat_t * pPar
     Cec_ManSat_t * p;
     Gia_Obj_t * pObj;
     int i, status;
-    clock_t clk = clock(), clk2;
+    abctime clk = Abc_Clock(), clk2;
     // reset the manager
     if ( pPat )
     {
@@ -702,7 +702,7 @@ void Cec_ManSatSolve( Cec_ManPat_t * pPat, Gia_Man_t * pAig, Cec_ParSat_t * pPar
             continue;
         }
         Bar_ProgressUpdate( pProgress, i, "SAT..." );
-clk2 = clock();
+clk2 = Abc_Clock();
         status = Cec_ManSatCheckNode( p, Gia_ObjChild0(pObj) );
         pObj->fMark0 = (status == 0);
         pObj->fMark1 = (status == 1);
@@ -720,15 +720,15 @@ clk2 = clock();
         // save the pattern
         if ( pPat )
         {
-            clock_t clk3 = clock();
+            abctime clk3 = Abc_Clock();
             Cec_ManPatSavePattern( pPat, p, pObj );
-            pPat->timeTotalSave += clock() - clk3;
+            pPat->timeTotalSave += Abc_Clock() - clk3;
         }
         // quit if one of them is solved
         if ( pPars->fCheckMiter )
             break;
     }
-    p->timeTotal = clock() - clk;
+    p->timeTotal = Abc_Clock() - clk;
     Bar_ProgressStop( pProgress );
     if ( pPars->fVerbose )
         Cec_ManSatPrintStats( p );
@@ -803,7 +803,7 @@ Vec_Str_t * Cec_ManSatSolveSeq( Vec_Ptr_t * vPatts, Gia_Man_t * pAig, Cec_ParSat
     Gia_Obj_t * pObj;
     int iPat = 0, nPatsInit, nPats;
     int i, status;
-    clock_t clk = clock();
+    abctime clk = Abc_Clock();
     nPatsInit = nPats = 32 * Vec_PtrReadWordsSimInfo(vPatts);
     Gia_ManSetPhase( pAig );
     Gia_ManLevelNum( pAig );
@@ -857,7 +857,7 @@ Vec_Str_t * Cec_ManSatSolveSeq( Vec_Ptr_t * vPatts, Gia_Man_t * pAig, Cec_ParSat
 //        if ( iPat == 32 * 15 * 16 - 1 )
 //            break;
     }
-    p->timeTotal = clock() - clk;
+    p->timeTotal = Abc_Clock() - clk;
     Bar_ProgressStop( pProgress );
     if ( pPars->fVerbose )
         Cec_ManSatPrintStats( p );
@@ -962,7 +962,7 @@ Vec_Int_t * Cec_ManSatSolveMiter( Gia_Man_t * pAig, Cec_ParSat_t * pPars, Vec_St
     Cec_ManSat_t * p;
     Gia_Obj_t * pObj;
     int i, status;
-    clock_t clk = clock();
+    abctime clk = Abc_Clock();
     // prepare AIG
     Gia_ManSetPhase( pAig );
     Gia_ManLevelNum( pAig );
@@ -1009,7 +1009,7 @@ Vec_Int_t * Cec_ManSatSolveMiter( Gia_Man_t * pAig, Cec_ParSat_t * pPars, Vec_St
 //        Gia_SatVerifyPattern( pAig, pObj, p->vCex, p->vVisits );
         Cec_ManSatAddToStore( vCexStore, p->vCex, i );
     }
-    p->timeTotal = clock() - clk;
+    p->timeTotal = Abc_Clock() - clk;
     Bar_ProgressStop( pProgress );
 //    if ( pPars->fVerbose )
 //        Cec_ManSatPrintStats( p );
diff --git a/src/proof/cec/cecSweep.c b/src/proof/cec/cecSweep.c
index 9ba2e07e..977ff3a8 100644
--- a/src/proof/cec/cecSweep.c
+++ b/src/proof/cec/cecSweep.c
@@ -190,11 +190,11 @@ int Cec_ManFraClassesUpdate( Cec_ManFra_t * p, Cec_ManSim_t * pSim, Cec_ManPat_t
     Vec_Ptr_t * vInfo;
     Gia_Obj_t * pObj, * pObjOld, * pReprOld;
     int i, k, iRepr, iNode;
-    clock_t clk;
-clk = clock();
+    abctime clk;
+clk = Abc_Clock();
     vInfo = Cec_ManPatCollectPatterns( pPat, Gia_ManCiNum(p->pAig), pSim->nWords );
-p->timePat += clock() - clk;
-clk = clock();
+p->timePat += Abc_Clock() - clk;
+clk = Abc_Clock();
     if ( vInfo != NULL )
     {
         Gia_ManCreateValueRefs( p->pAig );
@@ -209,7 +209,7 @@ clk = clock();
         }
         Vec_PtrFree( vInfo );
     }
-p->timeSim += clock() - clk;
+p->timeSim += Abc_Clock() - clk;
     assert( Vec_IntSize(p->vXorNodes) == 2*Gia_ManCoNum(pNew) );
     // mark the transitive fanout of failed nodes
     if ( p->pPars->nDepthMax != 1 )
diff --git a/src/proof/cec/cecSynth.c b/src/proof/cec/cecSynth.c
index 6ab88cbe..c00723bc 100644
--- a/src/proof/cec/cecSynth.c
+++ b/src/proof/cec/cecSynth.c
@@ -298,7 +298,7 @@ int Cec_SequentialSynthesisPart( Gia_Man_t * p, Cec_ParSeq_t * pPars )
     int * pMapBack, * pReprs;
     int i, nCountPis, nCountRegs;
     int nClasses;
-    clock_t clk = clock();
+    abctime clk = Abc_Clock();
 
     // save parameters
     if ( fPrintParts )
@@ -367,7 +367,7 @@ int Cec_SequentialSynthesisPart( Gia_Man_t * p, Cec_ParSeq_t * pPars )
     ABC_FREE( pReprs );
     if ( pPars->fVerbose )
     {
-        Abc_PrintTime( 1, "Total time", clock() - clk );
+        Abc_PrintTime( 1, "Total time", Abc_Clock() - clk );
     }
     return 1;
 }
diff --git a/src/proof/dch/dch.h b/src/proof/dch/dch.h
index e887ba26..5d644643 100644
--- a/src/proof/dch/dch.h
+++ b/src/proof/dch/dch.h
@@ -55,7 +55,7 @@ struct Dch_Pars_t_
     int              fLightSynth;   // uses lighter version of synthesis
     int              fSkipRedSupp;  // skip choices with redundant support vars
     int              fVerbose;      // verbose stats
-    clock_t          timeSynth;     // synthesis runtime
+    abctime          timeSynth;     // synthesis runtime
     int              nNodesAhead;   // the lookahead in terms of nodes
     int              nCallsRecycle; // calls to perform before recycling SAT solver
 };
diff --git a/src/proof/dch/dchCore.c b/src/proof/dch/dchCore.c
index b92de8a6..0da65bee 100644
--- a/src/proof/dch/dchCore.c
+++ b/src/proof/dch/dchCore.c
@@ -90,21 +90,21 @@ Aig_Man_t * Dch_ComputeChoices( Aig_Man_t * pAig, Dch_Pars_t * pPars )
 {
     Dch_Man_t * p;
     Aig_Man_t * pResult;
-    clock_t clk, clkTotal = clock();
+    abctime clk, clkTotal = Abc_Clock();
     // reset random numbers
     Aig_ManRandom(1);
     // start the choicing manager
     p = Dch_ManCreate( pAig, pPars );
     // compute candidate equivalence classes
-clk = clock(); 
+clk = Abc_Clock(); 
     p->ppClasses = Dch_CreateCandEquivClasses( pAig, pPars->nWords, pPars->fVerbose );
-p->timeSimInit = clock() - clk;
+p->timeSimInit = Abc_Clock() - clk;
 //    Dch_ClassesPrint( p->ppClasses, 0 );
     p->nLits = Dch_ClassesLitNum( p->ppClasses );
     // perform SAT sweeping
     Dch_ManSweep( p );
     // free memory ahead of time
-p->timeTotal = clock() - clkTotal;
+p->timeTotal = Abc_Clock() - clkTotal;
     Dch_ManStop( p );
     // create choices
     ABC_FREE( pAig->pTable );
@@ -134,21 +134,21 @@ p->timeTotal = clock() - clkTotal;
 void Dch_ComputeEquivalences( Aig_Man_t * pAig, Dch_Pars_t * pPars )
 {
     Dch_Man_t * p;
-    clock_t clk, clkTotal = clock();
+    abctime clk, clkTotal = Abc_Clock();
     // reset random numbers
     Aig_ManRandom(1);
     // start the choicing manager
     p = Dch_ManCreate( pAig, pPars );
     // compute candidate equivalence classes
-clk = clock(); 
+clk = Abc_Clock(); 
     p->ppClasses = Dch_CreateCandEquivClasses( pAig, pPars->nWords, pPars->fVerbose );
-p->timeSimInit = clock() - clk;
+p->timeSimInit = Abc_Clock() - clk;
 //    Dch_ClassesPrint( p->ppClasses, 0 );
     p->nLits = Dch_ClassesLitNum( p->ppClasses );
     // perform SAT sweeping
     Dch_ManSweep( p );
     // free memory ahead of time
-p->timeTotal = clock() - clkTotal;
+p->timeTotal = Abc_Clock() - clkTotal;
     Dch_ManStop( p );
 }
 
diff --git a/src/proof/dch/dchInt.h b/src/proof/dch/dchInt.h
index d1dd2c51..7edbc0f9 100644
--- a/src/proof/dch/dchInt.h
+++ b/src/proof/dch/dchInt.h
@@ -84,15 +84,15 @@ struct Dch_Man_t_
     int              nEquivs;        // the number of final equivalences
     int              nChoices;       // the number of final choice nodes
     // runtime stats
-    clock_t          timeSimInit;    // simulation and class computation
-    clock_t          timeSimSat;     // simulation of the counter-examples
-    clock_t          timeSat;        // solving SAT
-    clock_t          timeSatSat;     // sat
-    clock_t          timeSatUnsat;   // unsat
-    clock_t          timeSatUndec;   // undecided
-    clock_t          timeChoice;     // choice computation
-    clock_t          timeOther;      // other runtime
-    clock_t          timeTotal;      // total runtime
+    abctime          timeSimInit;    // simulation and class computation
+    abctime          timeSimSat;     // simulation of the counter-examples
+    abctime          timeSat;        // solving SAT
+    abctime          timeSatSat;     // sat
+    abctime          timeSatUnsat;   // unsat
+    abctime          timeSatUndec;   // undecided
+    abctime          timeChoice;     // choice computation
+    abctime          timeOther;      // other runtime
+    abctime          timeTotal;      // total runtime
 };
 
 ////////////////////////////////////////////////////////////////////////
diff --git a/src/proof/dch/dchSat.c b/src/proof/dch/dchSat.c
index fefd5ce2..9da18564 100644
--- a/src/proof/dch/dchSat.c
+++ b/src/proof/dch/dchSat.c
@@ -46,7 +46,7 @@ int Dch_NodesAreEquiv( Dch_Man_t * p, Aig_Obj_t * pOld, Aig_Obj_t * pNew )
 {
     int nBTLimit = p->pPars->nBTLimit;
     int pLits[2], RetValue, RetValue1, status;
-    clock_t clk;
+    abctime clk;
     p->nSatCalls++;
 
     // sanity checks
@@ -85,13 +85,13 @@ int Dch_NodesAreEquiv( Dch_Man_t * p, Aig_Obj_t * pOld, Aig_Obj_t * pNew )
         if ( pNew->fPhase )  pLits[1] = lit_neg( pLits[1] );
     }
 //Sat_SolverWriteDimacs( p->pSat, "temp.cnf", pLits, pLits + 2, 1 );
-clk = clock();
+clk = Abc_Clock();
     RetValue1 = sat_solver_solve( p->pSat, pLits, pLits + 2, 
         (ABC_INT64_T)nBTLimit, (ABC_INT64_T)0, (ABC_INT64_T)0, (ABC_INT64_T)0 );
-p->timeSat += clock() - clk;
+p->timeSat += Abc_Clock() - clk;
     if ( RetValue1 == l_False )
     {
-p->timeSatUnsat += clock() - clk;
+p->timeSatUnsat += Abc_Clock() - clk;
         pLits[0] = lit_neg( pLits[0] );
         pLits[1] = lit_neg( pLits[1] );
         RetValue = sat_solver_addclause( p->pSat, pLits, pLits + 2 );
@@ -100,13 +100,13 @@ p->timeSatUnsat += clock() - clk;
     }
     else if ( RetValue1 == l_True )
     {
-p->timeSatSat += clock() - clk;
+p->timeSatSat += Abc_Clock() - clk;
         p->nSatCallsSat++;
         return 0;
     }
     else // if ( RetValue1 == l_Undef )
     {
-p->timeSatUndec += clock() - clk;
+p->timeSatUndec += Abc_Clock() - clk;
         p->nSatFailsReal++;
         return -1;
     }
@@ -127,13 +127,13 @@ p->timeSatUndec += clock() - clk;
         if ( pOld->fPhase )  pLits[0] = lit_neg( pLits[0] );
         if ( pNew->fPhase )  pLits[1] = lit_neg( pLits[1] );
     }
-clk = clock();
+clk = Abc_Clock();
     RetValue1 = sat_solver_solve( p->pSat, pLits, pLits + 2, 
         (ABC_INT64_T)nBTLimit, (ABC_INT64_T)0, (ABC_INT64_T)0, (ABC_INT64_T)0 );
-p->timeSat += clock() - clk;
+p->timeSat += Abc_Clock() - clk;
     if ( RetValue1 == l_False )
     {
-p->timeSatUnsat += clock() - clk;
+p->timeSatUnsat += Abc_Clock() - clk;
         pLits[0] = lit_neg( pLits[0] );
         pLits[1] = lit_neg( pLits[1] );
         RetValue = sat_solver_addclause( p->pSat, pLits, pLits + 2 );
@@ -142,13 +142,13 @@ p->timeSatUnsat += clock() - clk;
     }
     else if ( RetValue1 == l_True )
     {
-p->timeSatSat += clock() - clk;
+p->timeSatSat += Abc_Clock() - clk;
         p->nSatCallsSat++;
         return 0;
     }
     else // if ( RetValue1 == l_Undef )
     {
-p->timeSatUndec += clock() - clk;
+p->timeSatUndec += Abc_Clock() - clk;
         p->nSatFailsReal++;
         return -1;
     }
diff --git a/src/proof/dch/dchSimSat.c b/src/proof/dch/dchSimSat.c
index 26de4643..d3dbbe16 100644
--- a/src/proof/dch/dchSimSat.c
+++ b/src/proof/dch/dchSimSat.c
@@ -178,7 +178,7 @@ void Dch_ManResimulateCex( Dch_Man_t * p, Aig_Obj_t * pObj, Aig_Obj_t * pRepr )
 {
     Aig_Obj_t * pRoot, ** ppClass;
     int i, k, nSize, RetValue1, RetValue2;
-    clock_t clk = clock();
+    abctime clk = Abc_Clock();
     // get the equivalence classes
     Dch_ManCollectTfoCands( p, pObj, pRepr );
     // resimulate the cone of influence of the solved nodes
@@ -208,7 +208,7 @@ void Dch_ManResimulateCex( Dch_Man_t * p, Aig_Obj_t * pObj, Aig_Obj_t * pRepr )
         assert( RetValue1 );
     else
         assert( RetValue2 );
-p->timeSimSat += clock() - clk;
+p->timeSimSat += Abc_Clock() - clk;
 }
 
 /**Function*************************************************************
@@ -226,7 +226,7 @@ void Dch_ManResimulateCex2( Dch_Man_t * p, Aig_Obj_t * pObj, Aig_Obj_t * pRepr )
 {
     Aig_Obj_t * pRoot;
     int i, RetValue;
-    clock_t clk = clock();
+    abctime clk = Abc_Clock();
     // get the equivalence class
     if ( Dch_ObjIsConst1Cand(p->pAigTotal, pObj) )
         Dch_ClassesCollectConst1Group( p->ppClasses, pObj, 500, p->vSimRoots );
@@ -248,7 +248,7 @@ void Dch_ManResimulateCex2( Dch_Man_t * p, Aig_Obj_t * pObj, Aig_Obj_t * pRepr )
     else
         RetValue = Dch_ClassesRefineOneClass( p->ppClasses, pRepr, 0 );
     assert( RetValue );
-p->timeSimSat += clock() - clk;
+p->timeSimSat += Abc_Clock() - clk;
 }
 
 ////////////////////////////////////////////////////////////////////////
diff --git a/src/proof/fra/fra.h b/src/proof/fra/fra.h
index b1fdb539..391ba482 100644
--- a/src/proof/fra/fra.h
+++ b/src/proof/fra/fra.h
@@ -237,17 +237,17 @@ struct Fra_Man_t_
     int              nSatCallsRecent;
     int              nSatCallsSkipped;
     // runtime
-    clock_t          timeSim;
-    clock_t          timeTrav;
-    clock_t          timeRwr;
-    clock_t          timeSat;
-    clock_t          timeSatUnsat;
-    clock_t          timeSatSat;
-    clock_t          timeSatFail;
-    clock_t          timeRef;
-    clock_t          timeTotal;
-    clock_t          time1;
-    clock_t          time2;
+    abctime          timeSim;
+    abctime          timeTrav;
+    abctime          timeRwr;
+    abctime          timeSat;
+    abctime          timeSatUnsat;
+    abctime          timeSatSat;
+    abctime          timeSatFail;
+    abctime          timeRef;
+    abctime          timeTotal;
+    abctime          time1;
+    abctime          time2;
 };
 
 ////////////////////////////////////////////////////////////////////////
diff --git a/src/proof/fra/fraBmc.c b/src/proof/fra/fraBmc.c
index 4b68a79a..cc6bb8c0 100644
--- a/src/proof/fra/fraBmc.c
+++ b/src/proof/fra/fraBmc.c
@@ -312,7 +312,7 @@ void Fra_BmcPerform( Fra_Man_t * p, int nPref, int nDepth )
 {
     Aig_Obj_t * pObj;
     int i, nImpsOld = 0;
-    clock_t clk = clock();
+    abctime clk = Abc_Clock();
     assert( p->pBmc == NULL );
     // derive and fraig the frames
     p->pBmc = Fra_BmcStart( p->pManAig, nPref, nDepth );
@@ -337,7 +337,7 @@ void Fra_BmcPerform( Fra_Man_t * p, int nPref, int nDepth )
         printf( "Original AIG = %d. Init %d frames = %d. Fraig = %d.  ", 
             Aig_ManNodeNum(p->pBmc->pAig), p->pBmc->nFramesAll, 
             Aig_ManNodeNum(p->pBmc->pAigFrames), Aig_ManNodeNum(p->pBmc->pAigFraig) );
-        ABC_PRT( "Time", clock() - clk );
+        ABC_PRT( "Time", Abc_Clock() - clk );
         printf( "Before BMC: " );  
 //        Fra_ClassesPrint( p->pCla, 0 );
         printf( "Const = %5d. Class = %5d. Lit = %5d. ", 
@@ -386,10 +386,10 @@ void Fra_BmcPerformSimple( Aig_Man_t * pAig, int nFrames, int nBTLimit, int fRew
     Fra_Man_t * pTemp;
     Fra_Bmc_t * pBmc;
     Aig_Man_t * pAigTemp;
-    clock_t clk;
+    abctime clk;
     int iOutput;
     // derive and fraig the frames
-    clk = clock();
+    clk = Abc_Clock();
     pBmc = Fra_BmcStart( pAig, 0, nFrames );
     pTemp = Fra_LcrAigPrepare( pAig );
     pTemp->pBmc = pBmc;
@@ -402,21 +402,21 @@ void Fra_BmcPerformSimple( Aig_Man_t * pAig, int nFrames, int nBTLimit, int fRew
         printf( "Time-frames (%d):  PI/PO = %d/%d.  Node = %6d. Lev = %5d.  ", 
             nFrames, Aig_ManCiNum(pBmc->pAigFrames), Aig_ManCoNum(pBmc->pAigFrames), 
             Aig_ManNodeNum(pBmc->pAigFrames), Aig_ManLevelNum(pBmc->pAigFrames) );
-        ABC_PRT( "Time", clock() - clk );
+        ABC_PRT( "Time", Abc_Clock() - clk );
     }
     if ( fRewrite )
     {
-        clk = clock();
+        clk = Abc_Clock();
         pBmc->pAigFrames = Dar_ManRwsat( pAigTemp = pBmc->pAigFrames, 1, 0 );
         Aig_ManStop( pAigTemp );
         if ( fVerbose )
         {
             printf( "Time-frames after rewriting:  Node = %6d. Lev = %5d.  ", 
                 Aig_ManNodeNum(pBmc->pAigFrames), Aig_ManLevelNum(pBmc->pAigFrames) );
-            ABC_PRT( "Time", clock() - clk );
+            ABC_PRT( "Time", Abc_Clock() - clk );
         }
     }
-    clk = clock();
+    clk = Abc_Clock();
     iOutput = Fra_FraigMiterAssertedOutput( pBmc->pAigFrames );
     if ( iOutput >= 0 )
         pAig->pSeqModel = Abc_CexMakeTriv( Aig_ManRegNum(pAig), Aig_ManCiNum(pAig)-Aig_ManRegNum(pAig), Aig_ManCoNum(pAig)-Aig_ManRegNum(pAig), iOutput );
@@ -437,7 +437,7 @@ void Fra_BmcPerformSimple( Aig_Man_t * pAig, int nFrames, int nBTLimit, int fRew
         printf( "Fraiged init frames: Node = %6d. Lev = %5d.  ", 
             pBmc->pAigFraig? Aig_ManNodeNum(pBmc->pAigFraig) : -1,
             pBmc->pAigFraig? Aig_ManLevelNum(pBmc->pAigFraig) : -1 );
-        ABC_PRT( "Time", clock() - clk );
+        ABC_PRT( "Time", Abc_Clock() - clk );
     }
     Fra_BmcStop( pBmc );  
     ABC_FREE( pTemp );
diff --git a/src/proof/fra/fraCec.c b/src/proof/fra/fraCec.c
index 3e7addb2..662a1d9e 100644
--- a/src/proof/fra/fraCec.c
+++ b/src/proof/fra/fraCec.c
@@ -54,7 +54,7 @@ int Fra_FraigSat( Aig_Man_t * pMan, ABC_INT64_T nConfLimit, ABC_INT64_T nInsLimi
         sat_solver2 * pSat;
         Cnf_Dat_t * pCnf;
         int status, RetValue;
-        clock_t clk = clock();
+        abctime clk = Abc_Clock();
         Vec_Int_t * vCiIds;
 
         assert( Aig_ManRegNum(pMan) == 0 );
@@ -100,13 +100,13 @@ int Fra_FraigSat( Aig_Man_t * pMan, ABC_INT64_T nConfLimit, ABC_INT64_T nInsLimi
 
 
         printf( "Created SAT problem with %d variable and %d clauses. ", sat_solver2_nvars(pSat), sat_solver2_nclauses(pSat) );
-        ABC_PRT( "Time", clock() - clk );
+        ABC_PRT( "Time", Abc_Clock() - clk );
 
         // simplify the problem
-        clk = clock();
+        clk = Abc_Clock();
         status = sat_solver2_simplify(pSat);
 //        printf( "Simplified the problem to %d variables and %d clauses. ", sat_solver2_nvars(pSat), sat_solver2_nclauses(pSat) );
-//        ABC_PRT( "Time", clock() - clk );
+//        ABC_PRT( "Time", Abc_Clock() - clk );
         if ( status == 0 )
         {
             Vec_IntFree( vCiIds );
@@ -116,7 +116,7 @@ int Fra_FraigSat( Aig_Man_t * pMan, ABC_INT64_T nConfLimit, ABC_INT64_T nInsLimi
         }
 
         // solve the miter
-        clk = clock();
+        clk = Abc_Clock();
         if ( fVerbose )
             pSat->verbosity = 1;
         status = sat_solver2_solve( pSat, NULL, NULL, (ABC_INT64_T)nConfLimit, (ABC_INT64_T)nInsLimit, (ABC_INT64_T)0, (ABC_INT64_T)0 );
@@ -139,7 +139,7 @@ int Fra_FraigSat( Aig_Man_t * pMan, ABC_INT64_T nConfLimit, ABC_INT64_T nInsLimi
             assert( 0 );
 
     //    Abc_Print( 1, "The number of conflicts = %6d.  ", (int)pSat->stats.conflicts );
-    //    Abc_PrintTime( 1, "Solving time", clock() - clk );
+    //    Abc_PrintTime( 1, "Solving time", Abc_Clock() - clk );
  
         // if the problem is SAT, get the counterexample
         if ( status == l_True )
@@ -160,7 +160,7 @@ int Fra_FraigSat( Aig_Man_t * pMan, ABC_INT64_T nConfLimit, ABC_INT64_T nInsLimi
         sat_solver * pSat;
         Cnf_Dat_t * pCnf;
         int status, RetValue;
-        clock_t clk = clock();
+        abctime clk = Abc_Clock();
         Vec_Int_t * vCiIds;
 
         assert( Aig_ManRegNum(pMan) == 0 );
@@ -215,13 +215,13 @@ int Fra_FraigSat( Aig_Man_t * pMan, ABC_INT64_T nConfLimit, ABC_INT64_T nInsLimi
 
 
     //    printf( "Created SAT problem with %d variable and %d clauses. ", sat_solver_nvars(pSat), sat_solver_nclauses(pSat) );
-    //    ABC_PRT( "Time", clock() - clk );
+    //    ABC_PRT( "Time", Abc_Clock() - clk );
 
         // simplify the problem
-        clk = clock();
+        clk = Abc_Clock();
         status = sat_solver_simplify(pSat);
     //    printf( "Simplified the problem to %d variables and %d clauses. ", sat_solver_nvars(pSat), sat_solver_nclauses(pSat) );
-    //    ABC_PRT( "Time", clock() - clk );
+    //    ABC_PRT( "Time", Abc_Clock() - clk );
         if ( status == 0 )
         {
             Vec_IntFree( vCiIds );
@@ -231,7 +231,7 @@ int Fra_FraigSat( Aig_Man_t * pMan, ABC_INT64_T nConfLimit, ABC_INT64_T nInsLimi
         }
 
         // solve the miter
-        clk = clock();
+        clk = Abc_Clock();
 //        if ( fVerbose )
 //            pSat->verbosity = 1;
         status = sat_solver_solve( pSat, NULL, NULL, (ABC_INT64_T)nConfLimit, (ABC_INT64_T)nInsLimit, (ABC_INT64_T)0, (ABC_INT64_T)0 );
@@ -254,7 +254,7 @@ int Fra_FraigSat( Aig_Man_t * pMan, ABC_INT64_T nConfLimit, ABC_INT64_T nInsLimi
             assert( 0 );
 
     //    Abc_Print( 1, "The number of conflicts = %6d.  ", (int)pSat->stats.conflicts );
-    //    Abc_PrintTime( 1, "Solving time", clock() - clk );
+    //    Abc_PrintTime( 1, "Solving time", Abc_Clock() - clk );
  
         // if the problem is SAT, get the counterexample
         if ( status == l_True )
@@ -292,7 +292,7 @@ int Fra_FraigCec( Aig_Man_t ** ppAig, int nConfLimit, int fVerbose )
     Fra_Par_t Params, * pParams = &Params;
     Aig_Man_t * pAig = *ppAig, * pTemp;
     int i, RetValue;
-    clock_t clk;
+    abctime clk;
 
     // report the original miter
     if ( fVerbose )
@@ -309,24 +309,24 @@ int Fra_FraigCec( Aig_Man_t ** ppAig, int nConfLimit, int fVerbose )
     }
 
     // if SAT only, solve without iteration
-clk = clock();
+clk = Abc_Clock();
     RetValue = Fra_FraigSat( pAig, (ABC_INT64_T)2*nBTLimitStart, (ABC_INT64_T)0, 0, 0, 0, 1, 0, 0, 0 );
     if ( fVerbose )
     {
         printf( "Initial SAT:      Nodes = %6d.  ", Aig_ManNodeNum(pAig) );
-ABC_PRT( "Time", clock() - clk );
+ABC_PRT( "Time", Abc_Clock() - clk );
     }
     if ( RetValue >= 0 )
         return RetValue;
 
     // duplicate the AIG
-clk = clock();
+clk = Abc_Clock();
     pAig = Dar_ManRwsat( pTemp = pAig, 1, 0 );
     Aig_ManStop( pTemp );
     if ( fVerbose )
     {
         printf( "Rewriting:        Nodes = %6d.  ", Aig_ManNodeNum(pAig) );
-ABC_PRT( "Time", clock() - clk );
+ABC_PRT( "Time", Abc_Clock() - clk );
     }
 
     // perform the loop
@@ -339,13 +339,13 @@ ABC_PRT( "Time", clock() - clk );
     {
 //printf( "Running fraiging with %d BTnode and %d BTmiter.\n", pParams->nBTLimitNode, pParams->nBTLimitMiter );
         // run fraiging
-clk = clock();
+clk = Abc_Clock();
         pAig = Fra_FraigPerform( pTemp = pAig, pParams );
         Aig_ManStop( pTemp );
         if ( fVerbose )
         {
             printf( "Fraiging (i=%d):   Nodes = %6d.  ", i+1, Aig_ManNodeNum(pAig) );
-ABC_PRT( "Time", clock() - clk );
+ABC_PRT( "Time", Abc_Clock() - clk );
         }
 
         // check the miter status
@@ -354,13 +354,13 @@ ABC_PRT( "Time", clock() - clk );
             break;
 
         // perform rewriting
-clk = clock();
+clk = Abc_Clock();
         pAig = Dar_ManRewriteDefault( pTemp = pAig );
         Aig_ManStop( pTemp );
         if ( fVerbose )
         {
             printf( "Rewriting:        Nodes = %6d.  ", Aig_ManNodeNum(pAig) );
-ABC_PRT( "Time", clock() - clk );
+ABC_PRT( "Time", Abc_Clock() - clk );
         } 
 
         // check the miter status
@@ -377,12 +377,12 @@ ABC_PRT( "Time", clock() - clk );
     // if still unsolved try last gasp
     if ( RetValue == -1 )
     {
-clk = clock();
+clk = Abc_Clock();
         RetValue = Fra_FraigSat( pAig, (ABC_INT64_T)nBTLimitLast, (ABC_INT64_T)0, 0, 0, 0, 1, 0, 0, 0 );
         if ( fVerbose )
         {
             printf( "Final SAT:            Nodes = %6d.  ", Aig_ManNodeNum(pAig) );
-ABC_PRT( "Time", clock() - clk );
+ABC_PRT( "Time", Abc_Clock() - clk );
         }
     }
 
@@ -468,7 +468,7 @@ int Fra_FraigCecTop( Aig_Man_t * pMan1, Aig_Man_t * pMan2, int nConfLimit, int n
     Aig_Man_t * pTemp;
     //Abc_NtkDarCec( pNtk1, pNtk2, fPartition, fVerbose );
     int RetValue;
-    clock_t clkTotal = clock();
+    abctime clkTotal = Abc_Clock();
 
     if ( Aig_ManCiNum(pMan1) != Aig_ManCiNum(pMan1) )
     {
@@ -501,17 +501,17 @@ int Fra_FraigCecTop( Aig_Man_t * pMan1, Aig_Man_t * pMan2, int nConfLimit, int n
     if ( RetValue == 1 )
     {
         printf( "Networks are equivalent.   " );
-ABC_PRT( "Time", clock() - clkTotal );
+ABC_PRT( "Time", Abc_Clock() - clkTotal );
     }
     else if ( RetValue == 0 )
     {
         printf( "Networks are NOT EQUIVALENT.   " );
-ABC_PRT( "Time", clock() - clkTotal );
+ABC_PRT( "Time", Abc_Clock() - clkTotal );
     }
     else
     {
         printf( "Networks are UNDECIDED.   " );
-ABC_PRT( "Time", clock() - clkTotal );
+ABC_PRT( "Time", Abc_Clock() - clkTotal );
     }
     fflush( stdout );
     return RetValue;
diff --git a/src/proof/fra/fraClaus.c b/src/proof/fra/fraClaus.c
index c4f50559..cb41dc5e 100644
--- a/src/proof/fra/fraClaus.c
+++ b/src/proof/fra/fraClaus.c
@@ -606,10 +606,10 @@ int Fra_ClausProcessClauses( Clu_Man_t * p, int fRefs )
     Aig_Obj_t * pObj;
     Dar_Cut_t * pCut;
     int Scores[16], uScores, i, k, j, nCuts = 0;
-    clock_t clk;
+    abctime clk;
 
     // simulate the AIG
-clk = clock();
+clk = Abc_Clock();
 //    srand( 0xAABBAABB );
     Aig_ManRandom(1);
     pSeq = Fra_SmlSimulateSeq( p->pAig, 0, p->nPref + p->nSimFrames, p->nSimWords/p->nSimFrames, 1 );
@@ -621,32 +621,32 @@ clk = clock();
     }
 if ( p->fVerbose )
 {
-ABC_PRT( "Sim-seq", clock() - clk );
+ABC_PRT( "Sim-seq", Abc_Clock() - clk );
 }
 
 
-clk = clock();
+clk = Abc_Clock();
     if ( fRefs )
     {
     Fra_ClausCollectLatchClauses( p, pSeq );
 if ( p->fVerbose )
 {
-ABC_PRT( "Lat-cla", clock() - clk );
+ABC_PRT( "Lat-cla", Abc_Clock() - clk );
 }
     }
 
 
     // generate cuts for all nodes, assign cost, and find best cuts
-clk = clock();
+clk = Abc_Clock();
     pMemCuts = Dar_ManComputeCuts( p->pAig, 10, 0, 1 );
 //    pManCut = Aig_ComputeCuts( p->pAig, 10, 4, 0, 1 );
 if ( p->fVerbose )
 {
-ABC_PRT( "Cuts   ", clock() - clk );
+ABC_PRT( "Cuts   ", Abc_Clock() - clk );
 }
 
     // collect sequential info for each cut
-clk = clock();
+clk = Abc_Clock();
     Aig_ManForEachNode( p->pAig, pObj, i )
         Dar_ObjForEachCut( pObj, pCut, k )
             if ( pCut->nLeaves > 1 )
@@ -660,22 +660,22 @@ clk = clock();
             }
 if ( p->fVerbose )
 {
-ABC_PRT( "Infoseq", clock() - clk );
+ABC_PRT( "Infoseq", Abc_Clock() - clk );
 }
     Fra_SmlStop( pSeq );
 
     // perform combinational simulation
-clk = clock();
+clk = Abc_Clock();
 //    srand( 0xAABBAABB );
     Aig_ManRandom(1);
     pComb = Fra_SmlSimulateComb( p->pAig, p->nSimWords + p->nSimWordsPref, 0 );
 if ( p->fVerbose )
 {
-ABC_PRT( "Sim-cmb", clock() - clk );
+ABC_PRT( "Sim-cmb", Abc_Clock() - clk );
 }
 
     // collect combinational info for each cut
-clk = clock();
+clk = Abc_Clock();
     Aig_ManForEachNode( p->pAig, pObj, i )
         Dar_ObjForEachCut( pObj, pCut, k )
             if ( pCut->nLeaves > 1 )
@@ -696,7 +696,7 @@ clk = clock();
 //    Aig_ManCutStop( pManCut );
 if ( p->fVerbose )
 {
-ABC_PRT( "Infocmb", clock() - clk );
+ABC_PRT( "Infocmb", Abc_Clock() - clk );
 }
 
     if ( p->fVerbose )
@@ -729,12 +729,12 @@ int Fra_ClausProcessClauses2( Clu_Man_t * p, int fRefs )
     Aig_Obj_t * pObj;
     Aig_Cut_t * pCut;
     int i, k, j, nCuts = 0;
-    clock_t clk;
+    abctime clk;
     int ScoresSeq[1<<12], ScoresComb[1<<12];
     assert( p->nLutSize < 13 );
 
     // simulate the AIG
-clk = clock();
+clk = Abc_Clock();
 //    srand( 0xAABBAABB );
     Aig_ManRandom(1);
     pSeq = Fra_SmlSimulateSeq( p->pAig, 0, p->nPref + p->nSimFrames, p->nSimWords/p->nSimFrames, 1  );
@@ -746,42 +746,42 @@ clk = clock();
     }
 if ( p->fVerbose )
 {
-//ABC_PRT( "Sim-seq", clock() - clk );
+//ABC_PRT( "Sim-seq", Abc_Clock() - clk );
 }
 
     // perform combinational simulation
-clk = clock();
+clk = Abc_Clock();
 //    srand( 0xAABBAABB );
     Aig_ManRandom(1);
     pComb = Fra_SmlSimulateComb( p->pAig, p->nSimWords + p->nSimWordsPref, 0 );
 if ( p->fVerbose )
 {
-//ABC_PRT( "Sim-cmb", clock() - clk );
+//ABC_PRT( "Sim-cmb", Abc_Clock() - clk );
 }
 
 
-clk = clock();
+clk = Abc_Clock();
     if ( fRefs )
     {
     Fra_ClausCollectLatchClauses( p, pSeq );
 if ( p->fVerbose )
 {
-//ABC_PRT( "Lat-cla", clock() - clk );
+//ABC_PRT( "Lat-cla", Abc_Clock() - clk );
 }
     }
 
 
     // generate cuts for all nodes, assign cost, and find best cuts
-clk = clock();
+clk = Abc_Clock();
 //    pMemCuts = Dar_ManComputeCuts( p->pAig, 10, 0, 1 );
     pManCut = Aig_ComputeCuts( p->pAig, p->nCutsMax, p->nLutSize, 0, p->fVerbose );
 if ( p->fVerbose )
 {
-//ABC_PRT( "Cuts   ", clock() - clk );
+//ABC_PRT( "Cuts   ", Abc_Clock() - clk );
 }
 
     // collect combinational info for each cut
-clk = clock();
+clk = Abc_Clock();
     Aig_ManForEachNode( p->pAig, pObj, i )
     {
         if ( pObj->Level > (unsigned)p->nLevels )
@@ -810,7 +810,7 @@ clk = clock();
     {
     printf( "Node = %5d. Cuts = %7d. Clauses = %6d. Clause/cut = %6.2f.\n", 
         Aig_ManNodeNum(p->pAig), nCuts, Vec_IntSize(p->vClauses), 1.0*Vec_IntSize(p->vClauses)/nCuts );
-    ABC_PRT( "Processing sim-info to find candidate clauses (unoptimized)", clock() - clk );
+    ABC_PRT( "Processing sim-info to find candidate clauses (unoptimized)", Abc_Clock() - clk );
     }
 
     // filter out clauses that are contained in the already proven clauses
@@ -1624,7 +1624,7 @@ void Fra_ClausEstimateCoverage( Clu_Man_t * p )
     unsigned * pResultTot, * pResultOne;
     int nCovered, Beg, End, i, w;
     int * pStart, * pVar2Id; 
-    clock_t clk = clock();
+    abctime clk = Abc_Clock();
     // simulate the circuit with nCombSimWords * 32 = 64K patterns
 //    srand( 0xAABBAABB );
     Aig_ManRandom(1);
@@ -1664,7 +1664,7 @@ void Fra_ClausEstimateCoverage( Clu_Man_t * p )
     // print the result
     printf( "Care states ratio = %f. ", 1.0 * (nCombSimWords * 32 - nCovered) / (nCombSimWords * 32) );
     printf( "(%d out of %d patterns)  ", nCombSimWords * 32 - nCovered, nCombSimWords * 32 );
-    ABC_PRT( "Time", clock() - clk );
+    ABC_PRT( "Time", Abc_Clock() - clk );
 }
 
 
@@ -1682,7 +1682,7 @@ void Fra_ClausEstimateCoverage( Clu_Man_t * p )
 int Fra_Claus( Aig_Man_t * pAig, int nFrames, int nPref, int nClausesMax, int nLutSize, int nLevels, int nCutsMax, int nBatches, int fStepUp, int fBmc, int fRefs, int fTarget, int fVerbose, int fVeryVerbose )
 {
     Clu_Man_t * p;
-    clock_t clk, clkTotal = clock(), clkInd;
+    abctime clk, clkTotal = Abc_Clock(), clkInd;
     int b, Iter, Counter, nPrefOld;
     int nClausesBeg = 0;
 
@@ -1692,12 +1692,12 @@ if ( p->fVerbose )
 {
     printf( "PARAMETERS: Frames = %d. Pref = %d. Clauses max = %d. Cut size = %d.\n", nFrames, nPref, nClausesMax, nLutSize );
     printf( "Level max = %d. Cuts max = %d. Batches = %d. Increment cut size = %s.\n", nLevels, nCutsMax, nBatches, fStepUp? "yes":"no" );
-//ABC_PRT( "Sim-seq", clock() - clk );
+//ABC_PRT( "Sim-seq", Abc_Clock() - clk );
 }
 
     assert( !p->fTarget || Aig_ManCoNum(pAig) - Aig_ManRegNum(pAig) == 1 );
 
-clk = clock();
+clk = Abc_Clock();
     // derive CNF
 //    if ( p->fTarget )
 //        p->pAig->nRegs++;
@@ -1706,11 +1706,11 @@ clk = clock();
 //        p->pAig->nRegs--;
 if ( fVerbose )
 {
-//ABC_PRT( "CNF    ", clock() - clk );
+//ABC_PRT( "CNF    ", Abc_Clock() - clk );
 }
 
     // check BMC
-clk = clock();
+clk = Abc_Clock();
     p->pSatBmc = (sat_solver *)Cnf_DataWriteIntoSolver( p->pCnf, p->nPref + p->nFrames, 1 );
     if ( p->pSatBmc == NULL )
     {
@@ -1726,11 +1726,11 @@ clk = clock();
     }
 if ( fVerbose )
 {
-//ABC_PRT( "SAT-bmc", clock() - clk );
+//ABC_PRT( "SAT-bmc", Abc_Clock() - clk );
 }
 
     // start the SAT solver
-clk = clock();
+clk = Abc_Clock();
     p->pSatMain = (sat_solver *)Cnf_DataWriteIntoSolver( p->pCnf, p->nFrames+1, 0 );
     if ( p->pSatMain == NULL )
     {
@@ -1757,11 +1757,11 @@ clk = clock();
         }
         if ( fVerbose )
         {
-//        ABC_PRT( "SAT-ind", clock() - clk );
+//        ABC_PRT( "SAT-ind", Abc_Clock() - clk );
         }
  
         // collect the candidate inductive clauses using 4-cuts
-        clk = clock();
+        clk = Abc_Clock();
         nPrefOld = p->nPref; p->nPref = 0; p->nSimWordsPref = 0;
     //    Fra_ClausProcessClauses( p, fRefs );
         Fra_ClausProcessClauses2( p, fRefs );
@@ -1769,25 +1769,25 @@ clk = clock();
         p->nSimWordsPref = p->nPref*p->nSimWords/p->nSimFrames;
         nClausesBeg = p->nClauses;
 
-    //ABC_PRT( "Clauses", clock() - clk );
+    //ABC_PRT( "Clauses", Abc_Clock() - clk );
 
 
         // check clauses using BMC
         if ( fBmc ) 
         {
-            clk = clock();
+            clk = Abc_Clock();
             Counter = Fra_ClausBmcClauses( p );
             p->nClauses -= Counter;
             if ( fVerbose )
             {
                 printf( "BMC disproved %d clauses.  ", Counter );
-                ABC_PRT( "Time", clock() - clk );
+                ABC_PRT( "Time", Abc_Clock() - clk );
             }
         }
 
 
         // prove clauses inductively
-        clkInd = clk = clock();
+        clkInd = clk = Abc_Clock();
         Counter = 1;
         for ( Iter = 0; Counter > 0; Iter++ )
         {
@@ -1800,9 +1800,9 @@ clk = clock();
             {
             printf( "End = %5d. Exs = %5d.  ", p->nClauses, p->nCexes );
     //        printf( "\n" );
-            ABC_PRT( "Time", clock() - clk );
+            ABC_PRT( "Time", Abc_Clock() - clk );
             }
-            clk = clock();
+            clk = Abc_Clock();
         }
         // add proved clauses to storage
         Fra_ClausAddToStorage( p );
@@ -1815,14 +1815,14 @@ clk = clock();
                 printf( "Property FAILS during refinement.  " );
             else
                 printf( "Property HOLDS inductively after strengthening.  " );
-            ABC_PRT( "Time  ", clock() - clkTotal );
+            ABC_PRT( "Time  ", Abc_Clock() - clkTotal );
             if ( !p->fFail )
                 break;
         }
         else
         {
             printf( "Finished proving inductive clauses. " );
-            ABC_PRT( "Time  ", clock() - clkTotal );
+            ABC_PRT( "Time  ", Abc_Clock() - clkTotal );
         }
     }
 
@@ -1857,8 +1857,8 @@ clk = clock();
         fprintf( pTable, "%d ",  p->nClauses );
         fprintf( pTable, "%d ",  Iter );
         fprintf( pTable, "%.2f ", (float)(clkInd-clkTotal)/(float)(CLOCKS_PER_SEC) );
-        fprintf( pTable, "%.2f ", (float)(clock()-clkInd)/(float)(CLOCKS_PER_SEC) );
-        fprintf( pTable, "%.2f ", (float)(clock()-clkTotal)/(float)(CLOCKS_PER_SEC) );
+        fprintf( pTable, "%.2f ", (float)(Abc_Clock()-clkInd)/(float)(CLOCKS_PER_SEC) );
+        fprintf( pTable, "%.2f ", (float)(Abc_Clock()-clkTotal)/(float)(CLOCKS_PER_SEC) );
         fprintf( pTable, "\n" );
         fclose( pTable );
     }
diff --git a/src/proof/fra/fraCore.c b/src/proof/fra/fraCore.c
index 35888f43..1e517e7d 100644
--- a/src/proof/fra/fraCore.c
+++ b/src/proof/fra/fraCore.c
@@ -376,10 +376,10 @@ Aig_Man_t * Fra_FraigPerform( Aig_Man_t * pManAig, Fra_Par_t * pPars )
 {
     Fra_Man_t * p;
     Aig_Man_t * pManAigNew;
-    clock_t clk;
+    abctime clk;
     if ( Aig_ManNodeNum(pManAig) == 0 )
         return Aig_ManDupOrdered(pManAig);
-clk = clock();
+clk = Abc_Clock();
     p = Fra_ManStart( pManAig, pPars );
     p->pManFraig = Fra_ManPrepareComb( p );
     p->pSml = Fra_SmlStart( pManAig, 0, 1, pPars->nSimWords );
@@ -402,7 +402,7 @@ Fra_ClassesPrint( p->pCla, 1 );
     Fra_ManFinalizeComb( p );
     if ( p->pPars->fChoicing )
     { 
-clock_t clk2 = clock();
+abctime clk2 = Abc_Clock();
         Fra_ClassesCopyReprs( p->pCla, p->vTimeouts );
         pManAigNew = Aig_ManDupRepr( p->pManAig, 1 );
         Aig_ManReprStart( pManAigNew, Aig_ManObjNumMax(pManAigNew) );
@@ -410,7 +410,7 @@ clock_t clk2 = clock();
         Aig_ManMarkValidChoices( pManAigNew );
         Aig_ManStop( p->pManFraig );
         p->pManFraig = NULL;
-p->timeTrav += clock() - clk2;
+p->timeTrav += Abc_Clock() - clk2;
     }
     else
     {
@@ -419,7 +419,7 @@ p->timeTrav += clock() - clk2;
         pManAigNew = p->pManFraig;
         p->pManFraig = NULL;
     }
-p->timeTotal = clock() - clk;
+p->timeTotal = Abc_Clock() - clk;
     // collect final stats
     p->nLitsEnd  = Fra_ClassesCountLits( p->pCla );
     p->nNodesEnd = Aig_ManNodeNum(pManAigNew);
diff --git a/src/proof/fra/fraHot.c b/src/proof/fra/fraHot.c
index a91c939f..36bea9e7 100644
--- a/src/proof/fra/fraHot.c
+++ b/src/proof/fra/fraHot.c
@@ -332,7 +332,7 @@ void Fra_OneHotEstimateCoverage( Fra_Man_t * p, Vec_Int_t * vOneHots )
     Vec_Ptr_t * vSimInfo;
     unsigned * pSim1, * pSim2, * pSimTot;
     int i, w, Out1, Out2, nCovered, Counter = 0;
-    clock_t clk = clock();
+    abctime clk = Abc_Clock();
 
     // generate random sim-info at register outputs
     vSimInfo = Vec_PtrAllocSimInfo( nRegs + 1, nSimWords );
@@ -381,7 +381,7 @@ void Fra_OneHotEstimateCoverage( Fra_Man_t * p, Vec_Int_t * vOneHots )
     // print the result
     printf( "Care states ratio = %f. ", 1.0 * (nSimWords * 32 - nCovered) / (nSimWords * 32) );
     printf( "(%d out of %d patterns)  ", nSimWords * 32 - nCovered, nSimWords * 32 );
-    ABC_PRT( "Time", clock() - clk );
+    ABC_PRT( "Time", Abc_Clock() - clk );
 }
 
 /**Function*************************************************************
diff --git a/src/proof/fra/fraImp.c b/src/proof/fra/fraImp.c
index 809ad8e4..027d8eb2 100644
--- a/src/proof/fra/fraImp.c
+++ b/src/proof/fra/fraImp.c
@@ -328,7 +328,7 @@ Vec_Int_t * Fra_ImpDerive( Fra_Man_t * p, int nImpMaxLimit, int nImpUseLimit, in
     int nImpsTotal = 0, nImpsTried = 0, nImpsNonSeq = 0, nImpsComb = 0, nImpsCollected = 0;
     int CostMin = ABC_INFINITY, CostMax = 0;
     int i, k, Imp, CostRange;
-    clock_t clk = clock();
+    abctime clk = Abc_Clock();
     assert( Aig_ManObjNumMax(p->pManAig) < (1 << 15) );
     assert( nImpMaxLimit > 0 && nImpUseLimit > 0 && nImpUseLimit <= nImpMaxLimit );
     // normalize both managers
@@ -403,7 +403,7 @@ printf( "Implications: All = %d. Try = %d. NonSeq = %d. Comb = %d. Res = %d.\n",
     nImpsTotal, nImpsTried, nImpsNonSeq, nImpsComb, nImpsCollected );
 printf( "Implication weight: Min = %d. Pivot = %d. Max = %d.   ", 
        CostMin, CostRange, CostMax );
-ABC_PRT( "Time", clock() - clk );
+ABC_PRT( "Time", Abc_Clock() - clk );
 }
     return vImps;
 }
diff --git a/src/proof/fra/fraInd.c b/src/proof/fra/fraInd.c
index e0a54a4e..012f8fc8 100644
--- a/src/proof/fra/fraInd.c
+++ b/src/proof/fra/fraInd.c
@@ -50,7 +50,7 @@ void Fra_FraigInductionRewrite( Fra_Man_t * p )
     Aig_Man_t * pTemp;
     Aig_Obj_t * pObj, * pObjPo;
     int nTruePis, k, i;
-    clock_t clk = clock();
+    abctime clk = Abc_Clock();
     // perform AIG rewriting on the speculated frames
 //    pTemp = Dar_ManRwsat( pTemp, 1, 0 );
     pTemp = Dar_ManRewriteDefault( p->pManFraig );
@@ -77,7 +77,7 @@ void Fra_FraigInductionRewrite( Fra_Man_t * p )
     // exchange
     Aig_ManStop( p->pManFraig );
     p->pManFraig = pTemp;
-p->timeRwr += clock() - clk;
+p->timeRwr += Abc_Clock() - clk;
 }
 
 /**Function*************************************************************
@@ -260,7 +260,7 @@ Aig_Man_t * Fra_FraigInductionPart( Aig_Man_t * pAig, Fra_Ssw_t * pPars )
     int * pMapBack;
     int i, nCountPis, nCountRegs;
     int nClasses, nPartSize, fVerbose;
-    clock_t clk = clock();
+    abctime clk = Abc_Clock();
 
     // save parameters
     nPartSize = pPars->nPartSize; pPars->nPartSize = 0;
@@ -325,7 +325,7 @@ Aig_Man_t * Fra_FraigInductionPart( Aig_Man_t * pAig, Fra_Ssw_t * pPars )
     pPars->fVerbose = fVerbose;
     if ( fVerbose )
     {
-        ABC_PRT( "Total time", clock() - clk );
+        ABC_PRT( "Total time", Abc_Clock() - clk );
     }
     return pNew;
 }
@@ -359,8 +359,8 @@ Aig_Man_t * Fra_FraigInduction( Aig_Man_t * pManAig, Fra_Ssw_t * pParams )
     int nNodesBeg, nRegsBeg;
     int nIter = -1; // Suppress "might be used uninitialized"
     int i;
-    clock_t clk = clock(), clk2;
-    clock_t TimeToStop = pParams->TimeLimit ? pParams->TimeLimit * CLOCKS_PER_SEC + clock() : 0;
+    abctime clk = Abc_Clock(), clk2;
+    abctime TimeToStop = pParams->TimeLimit ? pParams->TimeLimit * CLOCKS_PER_SEC + Abc_Clock() : 0;
 
     if ( Aig_ManNodeNum(pManAig) == 0 )
     {
@@ -429,7 +429,7 @@ printf( "Simulating %d AIG nodes for %d cycles ... ", Aig_ManNodeNum(pManAig), p
         p->pSml = Fra_SmlSimulateSeq( pManAig, pPars->nFramesP, 32, 1, 1  ); //pPars->nFramesK + 1, 1 );  
 if ( pPars->fVerbose ) 
 {
-ABC_PRT( "Time", clock() - clk );
+ABC_PRT( "Time", Abc_Clock() - clk );
 }
         Fra_ClassesPrepare( p->pCla, p->pPars->fLatchCorr, p->pPars->nMaxLevs );
 //        Fra_ClassesPostprocess( p->pCla );
@@ -445,7 +445,7 @@ ABC_PRT( "Time", clock() - clk );
     if ( pPars->fUseImps )
         p->pCla->vImps = Fra_ImpDerive( p, 5000000, pPars->nMaxImps, pPars->fLatchCorr );
 
-    if ( pParams->TimeLimit != 0.0 && clock() > TimeToStop )
+    if ( pParams->TimeLimit != 0.0 && Abc_Clock() > TimeToStop )
     {
         if ( !pParams->fSilent )
             printf( "Fra_FraigInduction(): Runtime limit exceeded.\n" );
@@ -475,9 +475,9 @@ ABC_PRT( "Time", clock() - clk );
         int nLitsOld = Fra_ClassesCountLits(p->pCla);
         int nImpsOld = p->pCla->vImps? Vec_IntSize(p->pCla->vImps) : 0;
         int nHotsOld = p->vOneHots? Fra_OneHotCount(p, p->vOneHots) : 0;
-        clock_t clk3 = clock();
+        abctime clk3 = Abc_Clock();
 
-        if ( pParams->TimeLimit != 0.0 && clock() > TimeToStop )
+        if ( pParams->TimeLimit != 0.0 && Abc_Clock() > TimeToStop )
         {
             if ( !pParams->fSilent )
                 printf( "Fra_FraigInduction(): Runtime limit exceeded.\n" );
@@ -487,9 +487,9 @@ ABC_PRT( "Time", clock() - clk );
         // mark the classes as non-refined
         p->pCla->fRefinement = 0;
         // derive non-init K-timeframes while implementing e-classes
-clk2 = clock();
+clk2 = Abc_Clock();
         p->pManFraig = Fra_FramesWithClasses( p );
-p->timeTrav += clock() - clk2;
+p->timeTrav += Abc_Clock() - clk2;
 //Aig_ManDumpBlif( p->pManFraig, "testaig.blif", NULL, NULL );
 
         // perform AIG rewriting
@@ -556,13 +556,13 @@ p->timeTrav += clock() - clk2;
         // perform sweeping
         p->nSatCallsRecent = 0;
         p->nSatCallsSkipped = 0;
-clk2 = clock();
+clk2 = Abc_Clock();
         if ( p->pPars->fUse1Hot )
             Fra_OneHotCheck( p, p->vOneHots );
         Fra_FraigSweep( p );
         if ( pPars->fVerbose )
         {
-            ABC_PRT( "T", clock() - clk3 );
+            ABC_PRT( "T", Abc_Clock() - clk3 );
         } 
 
 //        Sat_SolverPrintStats( stdout, p->pSat );
@@ -591,17 +591,17 @@ clk2 = clock();
     if ( p->pCla->vImps && Vec_IntSize(p->pCla->vImps) )
     {
         int Temp;
-        clock_t clk = clock();
+        abctime clk = Abc_Clock();
         if ( Temp = Fra_ImpVerifyUsingSimulation( p ) )
             printf( "Implications failing the simulation test = %d (out of %d).  ", Temp, Vec_IntSize(p->pCla->vImps) );
         else
             printf( "All %d implications have passed the simulation test.  ", Vec_IntSize(p->pCla->vImps) );
-        ABC_PRT( "Time", clock() - clk );
+        ABC_PRT( "Time", Abc_Clock() - clk );
     }
 */
 
     // move the classes into representatives and reduce AIG
-clk2 = clock();
+clk2 = Abc_Clock();
     if ( p->pPars->fWriteImps && p->vOneHots && Fra_OneHotCount(p, p->vOneHots) )
     {
         extern void Ioa_WriteAiger( Aig_Man_t * pMan, char * pFileName, int fWriteSymbols, int fCompact );
@@ -630,8 +630,8 @@ clk2 = clock();
 //        if ( pObj->pData && Aig_ObjIsNone(pObj->pData) )
 //            pObj->pData = NULL;
 //    Aig_ManCountMergeRegs( pManAigNew );
-p->timeTrav += clock() - clk2;
-p->timeTotal = clock() - clk;
+p->timeTrav += Abc_Clock() - clk2;
+p->timeTotal = Abc_Clock() - clk;
     // get the final stats
     p->nLitsEnd  = Fra_ClassesCountLits( p->pCla );
     p->nNodesEnd = Aig_ManNodeNum(pManAigNew);
diff --git a/src/proof/fra/fraIndVer.c b/src/proof/fra/fraIndVer.c
index 26b64647..a219ec52 100644
--- a/src/proof/fra/fraIndVer.c
+++ b/src/proof/fra/fraIndVer.c
@@ -50,7 +50,7 @@ int Fra_InvariantVerify( Aig_Man_t * pAig, int nFrames, Vec_Int_t * vClauses, Ve
     int * pStart;
     int RetValue, Beg, End, i, k;
     int CounterBase = 0, CounterInd = 0;
-    clock_t clk = clock();
+    abctime clk = Abc_Clock();
 
     if ( nFrames != 1 )
     {
@@ -153,7 +153,7 @@ int Fra_InvariantVerify( Aig_Man_t * pAig, int nFrames, Vec_Int_t * vClauses, Ve
     if ( CounterBase || CounterInd )
         return 0;
     printf( "Invariant verification: %d clauses verified correctly.  ", Vec_IntSize(vClauses) );
-    ABC_PRT( "Time", clock() - clk );
+    ABC_PRT( "Time", Abc_Clock() - clk );
     return 1;
 }
 
diff --git a/src/proof/fra/fraLcr.c b/src/proof/fra/fraLcr.c
index 9d573bee..2d8b3d64 100644
--- a/src/proof/fra/fraLcr.c
+++ b/src/proof/fra/fraLcr.c
@@ -54,12 +54,12 @@ struct Fra_Lcr_t_
     int              nRegsBeg;
     int              nRegsEnd;
     // runtime
-    clock_t          timeSim;
-    clock_t          timePart;
-    clock_t          timeTrav;
-    clock_t          timeFraig;
-    clock_t          timeUpdate;
-    clock_t          timeTotal;
+    abctime          timeSim;
+    abctime          timePart;
+    abctime          timeTrav;
+    abctime          timeFraig;
+    abctime          timeUpdate;
+    abctime          timeTotal;
 };
 
 ////////////////////////////////////////////////////////////////////////
@@ -538,8 +538,8 @@ Aig_Man_t * Fra_FraigLatchCorrespondence( Aig_Man_t * pAig, int nFramesP, int nC
     Aig_Man_t * pAigPart, * pAigTemp, * pAigNew = NULL;
     Vec_Int_t * vPart;
     int i, nIter;
-    clock_t timeSim, clk2, clk3, clk = clock();
-    clock_t TimeToStop = TimeLimit ? TimeLimit * CLOCKS_PER_SEC + clock() : 0;
+    abctime timeSim, clk2, clk3, clk = Abc_Clock();
+    abctime TimeToStop = TimeLimit ? TimeLimit * CLOCKS_PER_SEC + Abc_Clock() : 0;
     if ( Aig_ManNodeNum(pAig) == 0 )
     {
         if ( pnIter ) *pnIter = 0;
@@ -550,15 +550,15 @@ Aig_Man_t * Fra_FraigLatchCorrespondence( Aig_Man_t * pAig, int nFramesP, int nC
     assert( Aig_ManRegNum(pAig) > 0 ); 
 
     // simulate the AIG 
-clk2 = clock();
+clk2 = Abc_Clock();
 if ( fVerbose )
 printf( "Simulating AIG with %d nodes for %d cycles ...  ", Aig_ManNodeNum(pAig), nFramesP + 32 );
     pSml = Fra_SmlSimulateSeq( pAig, nFramesP, 32, 1, 1  ); 
 if ( fVerbose ) 
 {
-ABC_PRT( "Time", clock() - clk2 );
+ABC_PRT( "Time", Abc_Clock() - clk2 );
 }
-timeSim = clock() - clk2;
+timeSim = Abc_Clock() - clk2;
 
     // check if simulation discovered non-constant-0 POs
     if ( fProve && pSml->fNonConstOut )
@@ -586,7 +586,7 @@ timeSim = clock() - clk2;
     Fra_SmlStop( pTemp->pSml );
 
     // partition the AIG for latch correspondence computation
-clk2 = clock();
+clk2 = Abc_Clock();
 if ( fVerbose )
 printf( "Partitioning AIG ...  " );
     pAigPart = Fra_LcrDeriveAigForPartitioning( p );
@@ -595,8 +595,8 @@ printf( "Partitioning AIG ...  " );
     Aig_ManStop( pAigPart );
 if ( fVerbose ) 
 {
-ABC_PRT( "Time", clock() - clk2 );
-p->timePart += clock() - clk2;
+ABC_PRT( "Time", Abc_Clock() - clk2 );
+p->timePart += Abc_Clock() - clk2;
 }
 
     // get the initial stats
@@ -609,13 +609,13 @@ p->timePart += clock() - clk2;
     for ( nIter = 0; p->fRefining; nIter++ )
     {
         p->fRefining = 0;
-        clk3 = clock();
+        clk3 = Abc_Clock();
         // derive AIGs for each partition
         Fra_ClassNodesMark( p );
         Vec_PtrClear( p->vFraigs );
         Vec_PtrForEachEntry( Vec_Int_t *, p->vParts, vPart, i )
         {
-            if ( TimeLimit != 0.0 && clock() > TimeToStop )
+            if ( TimeLimit != 0.0 && Abc_Clock() > TimeToStop )
             {
                 Vec_PtrForEachEntry( Aig_Man_t *, p->vFraigs, pAigPart, i )
                     Aig_ManStop( pAigPart );
@@ -624,12 +624,12 @@ p->timePart += clock() - clk2;
                 printf( "Fra_FraigLatchCorrespondence(): Runtime limit exceeded.\n" );
                 goto finish;
             }
-clk2 = clock();
+clk2 = Abc_Clock();
             pAigPart = Fra_LcrCreatePart( p, vPart );
-p->timeTrav += clock() - clk2;
-clk2 = clock();
+p->timeTrav += Abc_Clock() - clk2;
+clk2 = Abc_Clock();
             pAigTemp  = Fra_FraigEquivence( pAigPart, nConfMax, 0 );
-p->timeFraig += clock() - clk2;
+p->timeFraig += Abc_Clock() - clk2;
             Vec_PtrPush( p->vFraigs, pAigTemp );
 /*
             {
@@ -638,7 +638,7 @@ p->timeFraig += clock() - clk2;
                 Aig_ManDumpBlif( pAigPart, Name, NULL, NULL );
             }
 printf( "Finished part %4d (out of %4d).  ", i, Vec_PtrSize(p->vParts) );
-ABC_PRT( "Time", clock() - clk3 );
+ABC_PRT( "Time", Abc_Clock() - clk3 );
 */
 
             Aig_ManStop( pAigPart );
@@ -650,7 +650,7 @@ ABC_PRT( "Time", clock() - clk3 );
             printf( "%3d : Const = %6d. Class = %6d.  L = %6d. Part = %3d.  ", 
                 nIter, Vec_PtrSize(p->pCla->vClasses1), Vec_PtrSize(p->pCla->vClasses), 
                 Fra_ClassesCountLits(p->pCla), Vec_PtrSize(p->vParts) );
-            ABC_PRT( "T", clock() - clk3 );
+            ABC_PRT( "T", Abc_Clock() - clk3 );
         }
         // refine the classes
         Fra_LcrAigPrepareTwo( p->pAig, pTemp );
@@ -665,19 +665,19 @@ ABC_PRT( "Time", clock() - clk3 );
         // repartition if needed
         if ( 1 )
         {
-clk2 = clock();
+clk2 = Abc_Clock();
             Vec_VecFree( (Vec_Vec_t *)p->vParts );
             pAigPart = Fra_LcrDeriveAigForPartitioning( p );
             p->vParts = (Vec_Ptr_t *)Aig_ManPartitionSmart( pAigPart, nPartSize, 0, NULL );
             Fra_LcrRemapPartitions( p->vParts, p->pCla, p->pInToOutPart, p->pInToOutNum );
             Aig_ManStop( pAigPart );
-p->timePart += clock() - clk2;
+p->timePart += Abc_Clock() - clk2;
         }
     }
     p->nIters = nIter;
 
     // move the classes into representatives and reduce AIG
-clk2 = clock();
+clk2 = Abc_Clock();
 //    Fra_ClassesPrint( p->pCla, 1 );
     if ( fReprSelect )
         Fra_ClassesSelectRepr( p->pCla );
@@ -685,8 +685,8 @@ clk2 = clock();
     pAigNew = Aig_ManDupRepr( p->pAig, 0 );
     Aig_ManSeqCleanup( pAigNew );
 //    Aig_ManCountMergeRegs( pAigNew );
-p->timeUpdate += clock() - clk2;
-p->timeTotal = clock() - clk;
+p->timeUpdate += Abc_Clock() - clk2;
+p->timeTotal = Abc_Clock() - clk;
     // get the final stats
     p->nLitsEnd  = Fra_ClassesCountLits( p->pCla );
     p->nNodesEnd = Aig_ManNodeNum(pAigNew);
diff --git a/src/proof/fra/fraPart.c b/src/proof/fra/fraPart.c
index e1c8ddf4..34d6cce2 100644
--- a/src/proof/fra/fraPart.c
+++ b/src/proof/fra/fraPart.c
@@ -53,16 +53,16 @@ void Fra_ManPartitionTest( Aig_Man_t * p, int nComLim )
     int i, k, nCommon, CountOver, CountQuant;
     int nTotalSupp, nTotalSupp2, Entry, Largest;//, iVar;
     double Ratio, R;
-    clock_t clk;
+    abctime clk;
 
     nTotalSupp = 0;
     nTotalSupp2 = 0;
     Ratio = 0.0;
  
     // compute supports
-clk = clock();
+clk = Abc_Clock();
     vSupps = (Vec_Vec_t *)Aig_ManSupports( p );
-ABC_PRT( "Supports", clock() - clk );
+ABC_PRT( "Supports", Abc_Clock() - clk );
     // remove last entry
     Aig_ManForEachCo( p, pObj, i )
     {
@@ -73,7 +73,7 @@ ABC_PRT( "Supports", clock() - clk );
     }
 
     // create reverse supports
-clk = clock();
+clk = Abc_Clock();
     vSuppsIn = Vec_VecStart( Aig_ManCiNum(p) );
     Aig_ManForEachCo( p, pObj, i )
     {
@@ -81,9 +81,9 @@ clk = clock();
         Vec_IntForEachEntry( vSup, Entry, k )
             Vec_VecPush( vSuppsIn, Entry, (void *)(ABC_PTRUINT_T)i );
     }
-ABC_PRT( "Inverse ", clock() - clk );
+ABC_PRT( "Inverse ", Abc_Clock() - clk );
 
-clk = clock();
+clk = Abc_Clock();
     // compute extended supports
     Largest = 0;
     vSuppsNew = Vec_PtrAlloc( Aig_ManCoNum(p) );
@@ -156,7 +156,7 @@ clk = clock();
 */
     }
 //    Bar_ProgressStop( pProgress );
-ABC_PRT( "Scanning", clock() - clk );
+ABC_PRT( "Scanning", Abc_Clock() - clk );
 
     // print cumulative statistics
     printf( "PIs = %6d. POs = %6d. Lim = %3d.   AveS = %3d. SN = %3d. R = %4.2f Max = %5d.\n",
@@ -191,13 +191,13 @@ void Fra_ManPartitionTest2( Aig_Man_t * p )
     Aig_Obj_t * pObj;
     int Entry, Entry2, Entry3, Counter;
     int i, k, m, n;
-    clock_t clk;
+    abctime clk;
     char * pSupp;
  
     // compute supports
-clk = clock();
+clk = Abc_Clock();
     vSupps = (Vec_Vec_t *)Aig_ManSupports( p );
-ABC_PRT( "Supports", clock() - clk );
+ABC_PRT( "Supports", Abc_Clock() - clk );
     // remove last entry
     Aig_ManForEachCo( p, pObj, i )
     {
@@ -208,7 +208,7 @@ ABC_PRT( "Supports", clock() - clk );
     }
 
     // create reverse supports
-clk = clock();
+clk = Abc_Clock();
     vSuppsIn = Vec_VecStart( Aig_ManCiNum(p) );
     Aig_ManForEachCo( p, pObj, i )
     {
@@ -218,10 +218,10 @@ clk = clock();
         Vec_IntForEachEntry( vSup, Entry, k )
             Vec_VecPush( vSuppsIn, Entry, (void *)(ABC_PTRUINT_T)i );
     }
-ABC_PRT( "Inverse ", clock() - clk );
+ABC_PRT( "Inverse ", Abc_Clock() - clk );
 
     // create affective supports
-clk = clock();
+clk = Abc_Clock();
     pSupp = ABC_ALLOC( char, Aig_ManCiNum(p) );
     Aig_ManForEachCo( p, pObj, i )
     {
@@ -252,7 +252,7 @@ clk = clock();
         printf( "%d(%d) ", Vec_IntSize(vSup), Counter );
     }
     printf( "\n" );
-ABC_PRT( "Extension ", clock() - clk );
+ABC_PRT( "Extension ", Abc_Clock() - clk );
 
     ABC_FREE( pSupp );
     Vec_VecFree( vSupps );
diff --git a/src/proof/fra/fraSat.c b/src/proof/fra/fraSat.c
index fc95fd62..e1e1c57f 100644
--- a/src/proof/fra/fraSat.c
+++ b/src/proof/fra/fraSat.c
@@ -48,7 +48,7 @@ static int Fra_SetActivityFactors( Fra_Man_t * p, Aig_Obj_t * pOld, Aig_Obj_t *
 int Fra_NodesAreEquiv( Fra_Man_t * p, Aig_Obj_t * pOld, Aig_Obj_t * pNew )
 {
     int pLits[4], RetValue, RetValue1, nBTLimit;
-    clock_t clk;//, clk2 = clock();
+    abctime clk;//, clk2 = Abc_Clock();
     int status;
 
     // make sure the nodes are not complemented
@@ -100,17 +100,17 @@ int Fra_NodesAreEquiv( Fra_Man_t * p, Aig_Obj_t * pOld, Aig_Obj_t * pNew )
 
     // solve under assumptions
     // A = 1; B = 0     OR     A = 1; B = 1 
-clk = clock();
+clk = Abc_Clock();
     pLits[0] = toLitCond( Fra_ObjSatNum(pOld), 0 );
     pLits[1] = toLitCond( Fra_ObjSatNum(pNew), pOld->fPhase == pNew->fPhase );
 //Sat_SolverWriteDimacs( p->pSat, "temp.cnf", pLits, pLits + 2, 1 );
     RetValue1 = sat_solver_solve( p->pSat, pLits, pLits + 2, 
         (ABC_INT64_T)nBTLimit, (ABC_INT64_T)0, 
         p->nBTLimitGlobal, p->nInsLimitGlobal );
-p->timeSat += clock() - clk;
+p->timeSat += Abc_Clock() - clk;
     if ( RetValue1 == l_False )
     {
-p->timeSatUnsat += clock() - clk;
+p->timeSatUnsat += Abc_Clock() - clk;
         pLits[0] = lit_neg( pLits[0] );
         pLits[1] = lit_neg( pLits[1] );
         RetValue = sat_solver_addclause( p->pSat, pLits, pLits + 2 );
@@ -120,14 +120,14 @@ p->timeSatUnsat += clock() - clk;
     }
     else if ( RetValue1 == l_True )
     {
-p->timeSatSat += clock() - clk;
+p->timeSatSat += Abc_Clock() - clk;
         Fra_SmlSavePattern( p );
         p->nSatCallsSat++;
         return 0;
     }
     else // if ( RetValue1 == l_Undef )
     {
-p->timeSatFail += clock() - clk;
+p->timeSatFail += Abc_Clock() - clk;
         // mark the node as the failed node
         if ( pOld != p->pManFraig->pConst1 ) 
             pOld->fMarkB = 1;
@@ -145,16 +145,16 @@ p->timeSatFail += clock() - clk;
 
     // solve under assumptions
     // A = 0; B = 1     OR     A = 0; B = 0 
-clk = clock();
+clk = Abc_Clock();
     pLits[0] = toLitCond( Fra_ObjSatNum(pOld), 1 );
     pLits[1] = toLitCond( Fra_ObjSatNum(pNew), pOld->fPhase ^ pNew->fPhase );
     RetValue1 = sat_solver_solve( p->pSat, pLits, pLits + 2, 
         (ABC_INT64_T)nBTLimit, (ABC_INT64_T)0, 
         p->nBTLimitGlobal, p->nInsLimitGlobal );
-p->timeSat += clock() - clk;
+p->timeSat += Abc_Clock() - clk;
     if ( RetValue1 == l_False )
     {
-p->timeSatUnsat += clock() - clk;
+p->timeSatUnsat += Abc_Clock() - clk;
         pLits[0] = lit_neg( pLits[0] );
         pLits[1] = lit_neg( pLits[1] );
         RetValue = sat_solver_addclause( p->pSat, pLits, pLits + 2 );
@@ -163,14 +163,14 @@ p->timeSatUnsat += clock() - clk;
     }
     else if ( RetValue1 == l_True )
     {
-p->timeSatSat += clock() - clk;
+p->timeSatSat += Abc_Clock() - clk;
         Fra_SmlSavePattern( p );
         p->nSatCallsSat++;
         return 0;
     }
     else // if ( RetValue1 == l_Undef )
     {
-p->timeSatFail += clock() - clk;
+p->timeSatFail += Abc_Clock() - clk;
         // mark the node as the failed node
         pOld->fMarkB = 1;
         pNew->fMarkB = 1;
@@ -181,12 +181,12 @@ p->timeSatFail += clock() - clk;
     // check BDD proof
     {
         int RetVal;
-        ABC_PRT( "Sat", clock() - clk2 );
-        clk2 = clock();
+        ABC_PRT( "Sat", Abc_Clock() - clk2 );
+        clk2 = Abc_Clock();
         RetVal = Fra_NodesAreEquivBdd( pOld, pNew );
 //        printf( "%d ", RetVal );
         assert( RetVal );
-        ABC_PRT( "Bdd", clock() - clk2 );
+        ABC_PRT( "Bdd", Abc_Clock() - clk2 );
         printf( "\n" );
     }
 */
@@ -209,7 +209,7 @@ p->timeSatFail += clock() - clk;
 int Fra_NodesAreImp( Fra_Man_t * p, Aig_Obj_t * pOld, Aig_Obj_t * pNew, int fComplL, int fComplR )
 {
     int pLits[4], RetValue, RetValue1, nBTLimit;
-    clock_t clk;//, clk2 = clock();
+    abctime clk;//, clk2 = Abc_Clock();
     int status;
 
     // make sure the nodes are not complemented
@@ -261,7 +261,7 @@ int Fra_NodesAreImp( Fra_Man_t * p, Aig_Obj_t * pOld, Aig_Obj_t * pNew, int fCom
 
     // solve under assumptions
     // A = 1; B = 0     OR     A = 1; B = 1 
-clk = clock();
+clk = Abc_Clock();
 //    pLits[0] = toLitCond( Fra_ObjSatNum(pOld), 0 );
 //    pLits[1] = toLitCond( Fra_ObjSatNum(pNew), pOld->fPhase == pNew->fPhase );
     pLits[0] = toLitCond( Fra_ObjSatNum(pOld),  fComplL );
@@ -270,10 +270,10 @@ clk = clock();
     RetValue1 = sat_solver_solve( p->pSat, pLits, pLits + 2, 
         (ABC_INT64_T)nBTLimit, (ABC_INT64_T)0, 
         p->nBTLimitGlobal, p->nInsLimitGlobal );
-p->timeSat += clock() - clk;
+p->timeSat += Abc_Clock() - clk;
     if ( RetValue1 == l_False )
     {
-p->timeSatUnsat += clock() - clk;
+p->timeSatUnsat += Abc_Clock() - clk;
         pLits[0] = lit_neg( pLits[0] );
         pLits[1] = lit_neg( pLits[1] );
         RetValue = sat_solver_addclause( p->pSat, pLits, pLits + 2 );
@@ -283,14 +283,14 @@ p->timeSatUnsat += clock() - clk;
     }
     else if ( RetValue1 == l_True )
     {
-p->timeSatSat += clock() - clk;
+p->timeSatSat += Abc_Clock() - clk;
         Fra_SmlSavePattern( p );
         p->nSatCallsSat++;
         return 0;
     }
     else // if ( RetValue1 == l_Undef )
     {
-p->timeSatFail += clock() - clk;
+p->timeSatFail += Abc_Clock() - clk;
         // mark the node as the failed node
         if ( pOld != p->pManFraig->pConst1 ) 
             pOld->fMarkB = 1;
@@ -317,7 +317,7 @@ p->timeSatFail += clock() - clk;
 int Fra_NodesAreClause( Fra_Man_t * p, Aig_Obj_t * pOld, Aig_Obj_t * pNew, int fComplL, int fComplR )
 {
     int pLits[4], RetValue, RetValue1, nBTLimit;
-    clock_t clk;//, clk2 = clock();
+    abctime clk;//, clk2 = Abc_Clock();
     int status;
 
     // make sure the nodes are not complemented
@@ -369,7 +369,7 @@ int Fra_NodesAreClause( Fra_Man_t * p, Aig_Obj_t * pOld, Aig_Obj_t * pNew, int f
 
     // solve under assumptions
     // A = 1; B = 0     OR     A = 1; B = 1 
-clk = clock();
+clk = Abc_Clock();
 //    pLits[0] = toLitCond( Fra_ObjSatNum(pOld), 0 );
 //    pLits[1] = toLitCond( Fra_ObjSatNum(pNew), pOld->fPhase == pNew->fPhase );
     pLits[0] = toLitCond( Fra_ObjSatNum(pOld), !fComplL );
@@ -378,10 +378,10 @@ clk = clock();
     RetValue1 = sat_solver_solve( p->pSat, pLits, pLits + 2, 
         (ABC_INT64_T)nBTLimit, (ABC_INT64_T)0, 
         p->nBTLimitGlobal, p->nInsLimitGlobal );
-p->timeSat += clock() - clk;
+p->timeSat += Abc_Clock() - clk;
     if ( RetValue1 == l_False )
     {
-p->timeSatUnsat += clock() - clk;
+p->timeSatUnsat += Abc_Clock() - clk;
         pLits[0] = lit_neg( pLits[0] );
         pLits[1] = lit_neg( pLits[1] );
         RetValue = sat_solver_addclause( p->pSat, pLits, pLits + 2 );
@@ -391,14 +391,14 @@ p->timeSatUnsat += clock() - clk;
     }
     else if ( RetValue1 == l_True )
     {
-p->timeSatSat += clock() - clk;
+p->timeSatSat += Abc_Clock() - clk;
         Fra_SmlSavePattern( p );
         p->nSatCallsSat++;
         return 0;
     }
     else // if ( RetValue1 == l_Undef )
     {
-p->timeSatFail += clock() - clk;
+p->timeSatFail += Abc_Clock() - clk;
         // mark the node as the failed node
         if ( pOld != p->pManFraig->pConst1 ) 
             pOld->fMarkB = 1;
@@ -425,7 +425,7 @@ p->timeSatFail += clock() - clk;
 int Fra_NodeIsConst( Fra_Man_t * p, Aig_Obj_t * pNew )
 {
     int pLits[2], RetValue1, RetValue;
-    clock_t clk;
+    abctime clk;
 
     // make sure the nodes are not complemented
     assert( !Aig_IsComplement(pNew) );
@@ -451,15 +451,15 @@ int Fra_NodeIsConst( Fra_Man_t * p, Aig_Obj_t * pNew )
         Fra_SetActivityFactors( p, NULL, pNew ); 
 
     // solve under assumptions
-clk = clock();
+clk = Abc_Clock();
     pLits[0] = toLitCond( Fra_ObjSatNum(pNew), pNew->fPhase );
     RetValue1 = sat_solver_solve( p->pSat, pLits, pLits + 1, 
         (ABC_INT64_T)p->pPars->nBTLimitMiter, (ABC_INT64_T)0, 
         p->nBTLimitGlobal, p->nInsLimitGlobal );
-p->timeSat += clock() - clk;
+p->timeSat += Abc_Clock() - clk;
     if ( RetValue1 == l_False )
     {
-p->timeSatUnsat += clock() - clk;
+p->timeSatUnsat += Abc_Clock() - clk;
         pLits[0] = lit_neg( pLits[0] );
         RetValue = sat_solver_addclause( p->pSat, pLits, pLits + 1 );
         assert( RetValue );
@@ -468,7 +468,7 @@ p->timeSatUnsat += clock() - clk;
     }
     else if ( RetValue1 == l_True )
     {
-p->timeSatSat += clock() - clk;
+p->timeSatSat += Abc_Clock() - clk;
         if ( p->pPatWords )
             Fra_SmlSavePattern( p );
         p->nSatCallsSat++;
@@ -476,7 +476,7 @@ p->timeSatSat += clock() - clk;
     }
     else // if ( RetValue1 == l_Undef )
     {
-p->timeSatFail += clock() - clk;
+p->timeSatFail += Abc_Clock() - clk;
         // mark the node as the failed node
         pNew->fMarkB = 1;
         p->nSatFailsReal++;
@@ -540,9 +540,9 @@ int Fra_SetActivityFactors_rec( Fra_Man_t * p, Aig_Obj_t * pObj, int LevelMin, i
 int Fra_SetActivityFactors( Fra_Man_t * p, Aig_Obj_t * pOld, Aig_Obj_t * pNew )
 {
     int LevelMin, LevelMax;
-    clock_t clk;
+    abctime clk;
     assert( pOld || pNew );
-clk = clock(); 
+clk = Abc_Clock(); 
     // reset the active variables
     veci_resize(&p->pSat->act_vars, 0);
     // prepare for traversal
@@ -557,7 +557,7 @@ clk = clock();
     if ( pNew && !Aig_ObjIsConst1(pNew) )
         Fra_SetActivityFactors_rec( p, pNew, LevelMin, LevelMax );
 //Fra_PrintActivity( p );
-p->timeTrav += clock() - clk;
+p->timeTrav += Abc_Clock() - clk;
     return 1;
 }
 
diff --git a/src/proof/fra/fraSec.c b/src/proof/fra/fraSec.c
index 04c9d668..dea2c3dc 100644
--- a/src/proof/fra/fraSec.c
+++ b/src/proof/fra/fraSec.c
@@ -99,7 +99,7 @@ int Fra_FraigSec( Aig_Man_t * p, Fra_Sec_t * pParSec, Aig_Man_t ** ppResult )
     Fra_Sml_t * pSml;
     Aig_Man_t * pNew, * pTemp;
     int nFrames, RetValue, nIter;
-    clock_t clk, clkTotal = clock();
+    abctime clk, clkTotal = Abc_Clock();
     int TimeOut = 0;
     int fLatchCorr = 0;
     float TimeLeft = 0.0;
@@ -123,7 +123,7 @@ int Fra_FraigSec( Aig_Man_t * p, Fra_Sec_t * pParSec, Aig_Man_t ** ppResult )
 //Aig_ManDumpBlif( pNew, "after.blif", NULL, NULL );
 
     // perform sequential cleanup
-clk = clock();
+clk = Abc_Clock();
     if ( pNew->nRegs )
     pNew = Aig_ManReduceLaches( pNew, 0 );
     if ( pNew->nRegs )
@@ -132,14 +132,14 @@ clk = clock();
     {
         printf( "Sequential cleanup:   Latches = %5d. Nodes = %6d. ", 
             Aig_ManRegNum(pNew), Aig_ManNodeNum(pNew) );
-ABC_PRT( "Time", clock() - clk );
+ABC_PRT( "Time", Abc_Clock() - clk );
     }
     RetValue = Fra_FraigMiterStatus( pNew );
     if ( RetValue >= 0 )
         goto finish;
 
     // perform phase abstraction
-clk = clock();
+clk = Abc_Clock();
     if ( pParSec->fPhaseAbstract )
     {
         extern Aig_Man_t * Saig_ManPhaseAbstractAuto( Aig_Man_t * p, int fVerbose );
@@ -151,14 +151,14 @@ clk = clock();
         {
             printf( "Phase abstraction:    Latches = %5d. Nodes = %6d. ", 
                 Aig_ManRegNum(pNew), Aig_ManNodeNum(pNew) );
-ABC_PRT( "Time", clock() - clk );
+ABC_PRT( "Time", Abc_Clock() - clk );
         }
     }
 
     // perform forward retiming
     if ( pParSec->fRetimeFirst && pNew->nRegs )
     {
-clk = clock();
+clk = Abc_Clock();
 //    pNew = Rtm_ManRetime( pTemp = pNew, 1, 1000, 0 );
     pNew = Saig_ManRetimeForward( pTemp = pNew, 100, 0 );
     Aig_ManStop( pTemp );
@@ -166,12 +166,12 @@ clk = clock();
     {
         printf( "Forward retiming:     Latches = %5d. Nodes = %6d. ", 
             Aig_ManRegNum(pNew), Aig_ManNodeNum(pNew) );
-ABC_PRT( "Time", clock() - clk );
+ABC_PRT( "Time", Abc_Clock() - clk );
     }
     }
      
     // run latch correspondence
-clk = clock();
+clk = Abc_Clock();
     if ( pNew->nRegs )
     {
     pNew = Aig_ManDupOrdered( pTemp = pNew );
@@ -180,7 +180,7 @@ clk = clock();
 /*
     if ( RetValue == -1 && pParSec->TimeLimit )
     {
-        TimeLeft = (float)pParSec->TimeLimit - ((float)(clock()-clkTotal)/(float)(CLOCKS_PER_SEC));
+        TimeLeft = (float)pParSec->TimeLimit - ((float)(Abc_Clock()-clkTotal)/(float)(CLOCKS_PER_SEC));
         TimeLeft = Abc_MaxInt( TimeLeft, 0.0 );
         if ( TimeLeft == 0.0 )
         {
@@ -223,12 +223,12 @@ clk = clock();
             if ( !pParSec->fSilent )
             {
                 printf( "Networks are NOT EQUIVALENT after simulation.   " );
-ABC_PRT( "Time", clock() - clkTotal );
+ABC_PRT( "Time", Abc_Clock() - clkTotal );
             }
             if ( pParSec->fReportSolution && !pParSec->fRecursive )
             {
             printf( "SOLUTION: FAIL       " );
-ABC_PRT( "Time", clock() - clkTotal );
+ABC_PRT( "Time", Abc_Clock() - clkTotal );
             }
             Aig_ManStop( pTemp );
             return RetValue;
@@ -244,13 +244,13 @@ ABC_PRT( "Time", clock() - clkTotal );
     {
         printf( "Latch-corr (I=%3d):   Latches = %5d. Nodes = %6d. ", 
             nIter, Aig_ManRegNum(pNew), Aig_ManNodeNum(pNew) );
-ABC_PRT( "Time", clock() - clk );
+ABC_PRT( "Time", Abc_Clock() - clk );
     }
     }
 /*
     if ( RetValue == -1 && pParSec->TimeLimit )
     {
-        TimeLeft = (float)pParSec->TimeLimit - ((float)(clock()-clkTotal)/(float)(CLOCKS_PER_SEC));
+        TimeLeft = (float)pParSec->TimeLimit - ((float)(Abc_Clock()-clkTotal)/(float)(CLOCKS_PER_SEC));
         TimeLeft = Abc_MaxInt( TimeLeft, 0.0 );
         if ( TimeLeft == 0.0 )
         {
@@ -265,14 +265,14 @@ ABC_PRT( "Time", clock() - clk );
     // perform fraiging
     if ( pParSec->fFraiging )
     {
-clk = clock();
+clk = Abc_Clock();
     pNew = Fra_FraigEquivence( pTemp = pNew, 100, 0 );
     Aig_ManStop( pTemp );
     if ( pParSec->fVerbose )
     {
         printf( "Fraiging:             Latches = %5d. Nodes = %6d. ", 
             Aig_ManRegNum(pNew), Aig_ManNodeNum(pNew) );
-ABC_PRT( "Time", clock() - clk );
+ABC_PRT( "Time", Abc_Clock() - clk );
     }
     }
 
@@ -285,7 +285,7 @@ ABC_PRT( "Time", clock() - clk );
 /*
     if ( RetValue == -1 && pParSec->TimeLimit )
     {
-        TimeLeft = (float)pParSec->TimeLimit - ((float)(clock()-clkTotal)/(float)(CLOCKS_PER_SEC));
+        TimeLeft = (float)pParSec->TimeLimit - ((float)(Abc_Clock()-clkTotal)/(float)(CLOCKS_PER_SEC));
         TimeLeft = Abc_MaxInt( TimeLeft, 0.0 );
         if ( TimeLeft == 0.0 )
         {
@@ -301,7 +301,7 @@ ABC_PRT( "Time", clock() - clk );
     if ( pParSec->fRetimeRegs && pNew->nRegs )
     {
 //    extern Aig_Man_t * Saig_ManRetimeMinArea( Aig_Man_t * p, int nMaxIters, int fForwardOnly, int fBackwardOnly, int fInitial, int fVerbose );
-clk = clock();
+clk = Abc_Clock();
     pNew->nTruePis = Aig_ManCiNum(pNew) - Aig_ManRegNum(pNew); 
     pNew->nTruePos = Aig_ManCoNum(pNew) - Aig_ManRegNum(pNew); 
 //        pNew = Rtm_ManRetime( pTemp = pNew, 1, 1000, 0 );
@@ -313,7 +313,7 @@ clk = clock();
     {
     printf( "Min-reg retiming:     Latches = %5d. Nodes = %6d. ", 
         Aig_ManRegNum(pNew), Aig_ManNodeNum(pNew) );
-ABC_PRT( "Time", clock() - clk );
+ABC_PRT( "Time", Abc_Clock() - clk );
     }
     }
 
@@ -325,7 +325,7 @@ ABC_PRT( "Time", clock() - clk );
 /*
         if ( RetValue == -1 && pParSec->TimeLimit )
         {
-            TimeLeft = (float)pParSec->TimeLimit - ((float)(clock()-clkTotal)/(float)(CLOCKS_PER_SEC));
+            TimeLeft = (float)pParSec->TimeLimit - ((float)(Abc_Clock()-clkTotal)/(float)(CLOCKS_PER_SEC));
             TimeLeft = Abc_MaxInt( TimeLeft, 0.0 );
             if ( TimeLeft == 0.0 )
             {
@@ -338,7 +338,7 @@ ABC_PRT( "Time", clock() - clk );
         }
 */ 
 
-clk = clock();
+clk = Abc_Clock();
         pPars->nFramesK = nFrames;
         pPars->TimeLimit = TimeLeft;
         pPars->fSilent = pParSec->fSilent;
@@ -381,7 +381,7 @@ clk = clock();
         { 
             printf( "K-step (K=%2d,I=%3d):  Latches = %5d. Nodes = %6d. ", 
                 nFrames, pPars2->nIters, Aig_ManRegNum(pNew), Aig_ManNodeNum(pNew) );
-ABC_PRT( "Time", clock() - clk );
+ABC_PRT( "Time", Abc_Clock() - clk );
         }
         if ( RetValue != -1 )
             break;
@@ -391,7 +391,7 @@ ABC_PRT( "Time", clock() - clk );
         if ( pNew->nRegs )
         {
 //        extern Aig_Man_t * Saig_ManRetimeMinArea( Aig_Man_t * p, int nMaxIters, int fForwardOnly, int fBackwardOnly, int fInitial, int fVerbose );
-clk = clock();
+clk = Abc_Clock();
         pNew->nTruePis = Aig_ManCiNum(pNew) - Aig_ManRegNum(pNew); 
         pNew->nTruePos = Aig_ManCoNum(pNew) - Aig_ManRegNum(pNew); 
 //        pNew = Rtm_ManRetime( pTemp = pNew, 1, 1000, 0 );
@@ -403,7 +403,7 @@ clk = clock();
         {
             printf( "Min-reg retiming:     Latches = %5d. Nodes = %6d. ", 
                 Aig_ManRegNum(pNew), Aig_ManNodeNum(pNew) );
-ABC_PRT( "Time", clock() - clk );
+ABC_PRT( "Time", Abc_Clock() - clk );
         }
         }  
 
@@ -411,7 +411,7 @@ ABC_PRT( "Time", clock() - clk );
             pNew = Aig_ManConstReduce( pNew, 0, -1, -1, 0, 0 );
 
         // perform rewriting
-clk = clock();
+clk = Abc_Clock();
         pNew = Aig_ManDupOrdered( pTemp = pNew );
         Aig_ManStop( pTemp );
 //        pNew = Dar_ManRewriteDefault( pTemp = pNew );
@@ -421,19 +421,19 @@ clk = clock();
         {
             printf( "Rewriting:            Latches = %5d. Nodes = %6d. ", 
                 Aig_ManRegNum(pNew), Aig_ManNodeNum(pNew) );
-ABC_PRT( "Time", clock() - clk );
+ABC_PRT( "Time", Abc_Clock() - clk );
         } 
 
         // perform sequential simulation
         if ( pNew->nRegs )
         {
-clk = clock();
+clk = Abc_Clock();
         pSml = Fra_SmlSimulateSeq( pNew, 0, 128 * nFrames, 1 + 16/(1+Aig_ManNodeNum(pNew)/1000), 1  ); 
         if ( pParSec->fVerbose )
         {
             printf( "Seq simulation  :     Latches = %5d. Nodes = %6d. ", 
                 Aig_ManRegNum(pNew), Aig_ManNodeNum(pNew) );
-ABC_PRT( "Time", clock() - clk );
+ABC_PRT( "Time", Abc_Clock() - clk );
         }
         if ( pSml->fNonConstOut )
         {
@@ -454,12 +454,12 @@ ABC_PRT( "Time", clock() - clk );
             if ( !pParSec->fSilent )
             {
                 printf( "Networks are NOT EQUIVALENT after simulation.   " );
-ABC_PRT( "Time", clock() - clkTotal );
+ABC_PRT( "Time", Abc_Clock() - clkTotal );
             }
             if ( pParSec->fReportSolution && !pParSec->fRecursive )
             {
             printf( "SOLUTION: FAIL       " );
-ABC_PRT( "Time", clock() - clkTotal );
+ABC_PRT( "Time", Abc_Clock() - clkTotal );
             }
             return RetValue;
         }
@@ -471,7 +471,7 @@ ABC_PRT( "Time", clock() - clkTotal );
     RetValue = Fra_FraigMiterStatus( pNew );
 
     // try interplation
-clk = clock();
+clk = Abc_Clock();
     Aig_ManSetRegNum( pNew, Aig_ManRegNum(pNew) );
     if ( pParSec->fInterpolation && RetValue == -1 && Aig_ManRegNum(pNew) > 0 )
     {
@@ -564,7 +564,7 @@ clk = clock();
             printf( "Property UNDECIDED after interpolation.  " );
         else
             assert( 0 ); 
-ABC_PRT( "Time", clock() - clk );
+ABC_PRT( "Time", Abc_Clock() - clk );
         }
     }
 
@@ -607,12 +607,12 @@ finish:
         if ( !pParSec->fSilent )
         {
             printf( "Networks are equivalent.   " );
-ABC_PRT( "Time", clock() - clkTotal );
+ABC_PRT( "Time", Abc_Clock() - clkTotal );
         }
         if ( pParSec->fReportSolution && !pParSec->fRecursive )
         {
         printf( "SOLUTION: PASS       " );
-ABC_PRT( "Time", clock() - clkTotal );
+ABC_PRT( "Time", Abc_Clock() - clkTotal );
         }
     }
     else if ( RetValue == 0 )
@@ -631,12 +631,12 @@ ABC_PRT( "Time", clock() - clkTotal );
         if ( !pParSec->fSilent )
         {
             printf( "Networks are NOT EQUIVALENT.   " );
-ABC_PRT( "Time", clock() - clkTotal );
+ABC_PRT( "Time", Abc_Clock() - clkTotal );
         }
         if ( pParSec->fReportSolution && !pParSec->fRecursive )
         {
         printf( "SOLUTION: FAIL       " );
-ABC_PRT( "Time", clock() - clkTotal );
+ABC_PRT( "Time", Abc_Clock() - clkTotal );
         }
     }
     else 
@@ -649,12 +649,12 @@ ABC_PRT( "Time", clock() - clkTotal );
         if ( !pParSec->fSilent )
         {
             printf( "Networks are UNDECIDED.   " );
-ABC_PRT( "Time", clock() - clkTotal );
+ABC_PRT( "Time", Abc_Clock() - clkTotal );
         }
         if ( pParSec->fReportSolution && !pParSec->fRecursive )
         {
         printf( "SOLUTION: UNDECIDED  " );
-ABC_PRT( "Time", clock() - clkTotal );
+ABC_PRT( "Time", Abc_Clock() - clkTotal );
         }
         if ( !TimeOut && !pParSec->fSilent )
         {
diff --git a/src/proof/fra/fraSim.c b/src/proof/fra/fraSim.c
index bbe68717..2d2ee93f 100644
--- a/src/proof/fra/fraSim.c
+++ b/src/proof/fra/fraSim.c
@@ -664,8 +664,8 @@ void Fra_SmlSimulateOne( Fra_Sml_t * p )
 {
     Aig_Obj_t * pObj, * pObjLi, * pObjLo;
     int f, i;
-    clock_t clk;
-clk = clock();
+    abctime clk;
+clk = Abc_Clock();
     for ( f = 0; f < p->nFrames; f++ )
     {
         // simulate the nodes
@@ -684,7 +684,7 @@ clk = clock();
         Aig_ManForEachLiLoSeq( p->pAig, pObjLi, pObjLo, i )
             Fra_SmlNodeTransferNext( p, pObjLi, pObjLo, f );
     }
-p->timeSim += clock() - clk;
+p->timeSim += Abc_Clock() - clk;
 p->nSimRounds++;
 }
 
@@ -703,21 +703,21 @@ p->nSimRounds++;
 void Fra_SmlResimulate( Fra_Man_t * p )
 {
     int nChanges;
-    clock_t clk;
+    abctime clk;
     Fra_SmlAssignDist1( p->pSml, p->pPatWords );
     Fra_SmlSimulateOne( p->pSml );
 //    if ( p->pPars->fPatScores )
 //        Fra_CleanPatScores( p );
     if ( p->pPars->fProve && Fra_SmlCheckOutput(p) )
         return;
-clk = clock();
+clk = Abc_Clock();
     nChanges = Fra_ClassesRefine( p->pCla );
     nChanges += Fra_ClassesRefine1( p->pCla, 1, NULL );
     if ( p->pCla->vImps )
         nChanges += Fra_ImpRefineUsingCex( p, p->pCla->vImps );
     if ( p->vOneHots )
         nChanges += Fra_OneHotRefineUsingCex( p, p->vOneHots );
-p->timeRef += clock() - clk;
+p->timeRef += Abc_Clock() - clk;
     if ( !p->pPars->nFramesK && nChanges < 1 )
         printf( "Error: A counter-example did not refine classes!\n" );
 //    assert( nChanges >= 1 );
@@ -739,7 +739,7 @@ void Fra_SmlSimulate( Fra_Man_t * p, int fInit )
 {
     int fVerbose = 0;
     int nChanges, nClasses;
-    clock_t clk;
+    abctime clk;
     assert( !fInit || Aig_ManRegNum(p->pManAig) );
     // start the classes
     Fra_SmlInitialize( p->pSml, fInit );
@@ -759,10 +759,10 @@ printf( "Starting classes = %5d.   Lits = %6d.\n", Vec_PtrSize(p->pCla->vClasses
     Fra_SmlSimulateOne( p->pSml );
     if ( p->pPars->fProve && Fra_SmlCheckOutput(p) )
         return;
-clk = clock();
+clk = Abc_Clock();
     nChanges = Fra_ClassesRefine( p->pCla );
     nChanges += Fra_ClassesRefine1( p->pCla, 1, NULL );
-p->timeRef += clock() - clk;
+p->timeRef += Abc_Clock() - clk;
 if ( fVerbose )
 printf( "Refined classes  = %5d.   Changes = %4d.   Lits = %6d.\n", Vec_PtrSize(p->pCla->vClasses), nChanges, Fra_ClassesCountLits(p->pCla) );
     Fra_SmlSavePattern1( p, fInit );
@@ -770,10 +770,10 @@ printf( "Refined classes  = %5d.   Changes = %4d.   Lits = %6d.\n", Vec_PtrSize(
     Fra_SmlSimulateOne( p->pSml );
     if ( p->pPars->fProve && Fra_SmlCheckOutput(p) )
         return;
-clk = clock();
+clk = Abc_Clock();
     nChanges = Fra_ClassesRefine( p->pCla );
     nChanges += Fra_ClassesRefine1( p->pCla, 1, NULL );
-p->timeRef += clock() - clk;
+p->timeRef += Abc_Clock() - clk;
 
 if ( fVerbose )
 printf( "Refined classes  = %5d.   Changes = %4d.   Lits = %6d.\n", Vec_PtrSize(p->pCla->vClasses), nChanges, Fra_ClassesCountLits(p->pCla) );
@@ -784,10 +784,10 @@ printf( "Refined classes  = %5d.   Changes = %4d.   Lits = %6d.\n", Vec_PtrSize(
         nClasses = Vec_PtrSize(p->pCla->vClasses);
         if ( p->pPars->fProve && Fra_SmlCheckOutput(p) )
             return;
-clk = clock();
+clk = Abc_Clock();
         nChanges = Fra_ClassesRefine( p->pCla );
         nChanges += Fra_ClassesRefine1( p->pCla, 1, NULL );
-p->timeRef += clock() - clk;
+p->timeRef += Abc_Clock() - clk;
 if ( fVerbose )
 printf( "Refined classes  = %5d.   Changes = %4d.   Lits = %6d.\n", Vec_PtrSize(p->pCla->vClasses), nChanges, Fra_ClassesCountLits(p->pCla) );
     } while ( (double)nChanges / nClasses > p->pPars->dSimSatur );
diff --git a/src/proof/fraig/fraigChoice.c b/src/proof/fraig/fraigChoice.c
index e1d6e8a7..4e6a225b 100644
--- a/src/proof/fraig/fraigChoice.c
+++ b/src/proof/fraig/fraigChoice.c
@@ -45,7 +45,7 @@ void Fraig_ManAddChoices( Fraig_Man_t * pMan, int fVerbose, int nLimit )
 {
 //    ProgressBar * pProgress;
     char Buffer[100];
-    clock_t clkTotal = clock();
+    abctime clkTotal = Abc_Clock();
     int i, nNodesBefore, nNodesAfter, nInputs, nMaxNodes;
     int /*nMaxLevel,*/ nDistributive;
     Fraig_Node_t *pNode, *pRepr;
diff --git a/src/proof/fraig/fraigFeed.c b/src/proof/fraig/fraigFeed.c
index 4cb1276b..020caefa 100644
--- a/src/proof/fraig/fraigFeed.c
+++ b/src/proof/fraig/fraigFeed.c
@@ -81,7 +81,7 @@ void Fraig_FeedBack( Fraig_Man_t * p, int * pModel, Msat_IntVec_t * vVars, Fraig
 {
     int nVarsPi, nWords;
     int i;
-    clock_t clk = clock();
+    abctime clk = Abc_Clock();
 
     // get the number of PI vars in the feedback (also sets the PI values)
     nVarsPi = Fraig_FeedBackPrepare( p, pModel, vVars );
@@ -107,7 +107,7 @@ void Fraig_FeedBack( Fraig_Man_t * p, int * pModel, Msat_IntVec_t * vVars, Fraig
     else  // otherwise, update the starting word
         p->iWordStart += nWords;
 
-p->timeFeed += clock() - clk;
+p->timeFeed += Abc_Clock() - clk;
 }
 
 /**Function*************************************************************
diff --git a/src/proof/fraig/fraigInt.h b/src/proof/fraig/fraigInt.h
index 0decf6ff..37f00720 100644
--- a/src/proof/fraig/fraigInt.h
+++ b/src/proof/fraig/fraigInt.h
@@ -189,18 +189,18 @@ struct Fraig_ManStruct_t_
     int                   nImplies1;
 
     // runtime statistics
-    clock_t               timeToAig;     // time to transfer to the mapping structure
-    clock_t               timeSims;      // time to compute k-feasible cuts
-    clock_t               timeTrav;      // time to traverse the network
-    clock_t               timeFeed;      // time for solver feedback (recording and resimulating)
-    clock_t               timeImply;     // time to analyze implications
-    clock_t               timeSat;       // time to compute the truth table for each cut
-    clock_t               timeToNet;     // time to transfer back to the network
-    clock_t               timeTotal;     // the total mapping time
-    clock_t               time1;         // time to perform one task
-    clock_t               time2;         // time to perform another task
-    clock_t               time3;         // time to perform another task
-    clock_t               time4;         // time to perform another task
+    abctime               timeToAig;     // time to transfer to the mapping structure
+    abctime               timeSims;      // time to compute k-feasible cuts
+    abctime               timeTrav;      // time to traverse the network
+    abctime               timeFeed;      // time for solver feedback (recording and resimulating)
+    abctime               timeImply;     // time to analyze implications
+    abctime               timeSat;       // time to compute the truth table for each cut
+    abctime               timeToNet;     // time to transfer back to the network
+    abctime               timeTotal;     // the total mapping time
+    abctime               time1;         // time to perform one task
+    abctime               time2;         // time to perform another task
+    abctime               time3;         // time to perform another task
+    abctime               time4;         // time to perform another task
 };
 
 // the mapping node
diff --git a/src/proof/fraig/fraigMan.c b/src/proof/fraig/fraigMan.c
index dab3b08d..90c009ef 100644
--- a/src/proof/fraig/fraigMan.c
+++ b/src/proof/fraig/fraigMan.c
@@ -25,8 +25,8 @@ ABC_NAMESPACE_IMPL_START
 ///                        DECLARATIONS                              ///
 ////////////////////////////////////////////////////////////////////////
 
-clock_t timeSelect;
-clock_t timeAssign;
+abctime timeSelect;
+abctime timeAssign;
 
 ////////////////////////////////////////////////////////////////////////
 ///                     FUNCTION DEFINITIONS                         ///
@@ -324,8 +324,8 @@ void Fraig_ManFree( Fraig_Man_t * p )
 ***********************************************************************/
 void Fraig_ManCreateSolver( Fraig_Man_t * p )
 {
-    extern clock_t timeSelect;
-    extern clock_t timeAssign;
+    extern abctime timeSelect;
+    extern abctime timeAssign;
     assert( p->pSat == NULL );
     // allocate data for SAT solving
     p->pSat       = Msat_SolverAlloc( 500, 1, 1, 1, 1, 0 );
diff --git a/src/proof/fraig/fraigNode.c b/src/proof/fraig/fraigNode.c
index 5310534b..9bf64bd2 100644
--- a/src/proof/fraig/fraigNode.c
+++ b/src/proof/fraig/fraigNode.c
@@ -88,7 +88,7 @@ Fraig_Node_t * Fraig_NodeCreatePi( Fraig_Man_t * p )
 {
     Fraig_Node_t * pNode, * pNodeRes;
     int i;
-    clock_t clk;
+    abctime clk;
 
     // create the node
     pNode = (Fraig_Node_t *)Fraig_MemFixedEntryFetch( p->mmNodes );
@@ -110,7 +110,7 @@ Fraig_Node_t * Fraig_NodeCreatePi( Fraig_Man_t * p )
     pNode->fInv  =  0;  // the simulation info of the PI is not complemented
 
     // derive the simulation info for the new node
-clk = clock();
+clk = Abc_Clock();
     // set the random simulation info for the primary input
     pNode->uHashR = 0;
     for ( i = 0; i < p->nWordsRand; i++ )
@@ -136,7 +136,7 @@ clk = clock();
         // compute the hash key
         pNode->uHashD ^= pNode->puSimD[i] * s_FraigPrimes[i];
     }
-p->timeSims += clock() - clk;
+p->timeSims += Abc_Clock() - clk;
 
     // insert it into the hash table
     pNodeRes = Fraig_HashTableLookupF( p, pNode );
@@ -160,7 +160,7 @@ p->timeSims += clock() - clk;
 Fraig_Node_t * Fraig_NodeCreate( Fraig_Man_t * p, Fraig_Node_t * p1, Fraig_Node_t * p2 )
 {
     Fraig_Node_t * pNode;
-    clock_t clk;
+    abctime clk;
 
     // create the node
     pNode = (Fraig_Node_t *)Fraig_MemFixedEntryFetch( p->mmNodes );
@@ -183,7 +183,7 @@ Fraig_Node_t * Fraig_NodeCreate( Fraig_Man_t * p, Fraig_Node_t * p1, Fraig_Node_
     pNode->fFailTfo = Fraig_Regular(p1)->fFailTfo | Fraig_Regular(p2)->fFailTfo;
 
     // derive the simulation info 
-clk = clock();
+clk = Abc_Clock();
     // allocate memory for the simulation info
     pNode->puSimR = (unsigned *)Fraig_MemFixedEntryFetch( p->mmSims );
     pNode->puSimD = pNode->puSimR + p->nWordsRand;
@@ -198,7 +198,7 @@ clk = clock();
     if ( pNode->fInv )
         pNode->nOnes = p->nWordsRand * 32 - pNode->nOnes;
     // add to the runtime of simulation
-p->timeSims += clock() - clk;
+p->timeSims += Abc_Clock() - clk;
 
 #ifdef FRAIG_ENABLE_FANOUTS
     // create the fanout info
diff --git a/src/proof/fraig/fraigSat.c b/src/proof/fraig/fraigSat.c
index fb3f1fec..3c1b2a1b 100644
--- a/src/proof/fraig/fraigSat.c
+++ b/src/proof/fraig/fraigSat.c
@@ -86,12 +86,12 @@ void Fraig_ManProveMiter( Fraig_Man_t * p )
 {
     Fraig_Node_t * pNode;
     int i;
-    clock_t clk;
+    abctime clk;
 
     if ( !p->fTryProve )
         return;
  
-    clk = clock();
+    clk = Abc_Clock();
     // consider all outputs of the multi-output miter
     for ( i = 0; i < p->vOutputs->nSize; i++ )
     {
@@ -112,7 +112,7 @@ void Fraig_ManProveMiter( Fraig_Man_t * p )
     }
     if ( p->fVerboseP ) 
     {
-//        ABC_PRT( "Final miter proof time", clock() - clk );
+//        ABC_PRT( "Final miter proof time", Abc_Clock() - clk );
     }
 }
 
@@ -302,7 +302,7 @@ void Fraig_VarsStudy( Fraig_Man_t * p, Fraig_Node_t * pOld, Fraig_Node_t * pNew
 int Fraig_NodeIsEquivalent( Fraig_Man_t * p, Fraig_Node_t * pOld, Fraig_Node_t * pNew, int nBTLimit, int nTimeLimit )
 {
     int RetValue, RetValue1, i, fComp;
-    clock_t clk;
+    abctime clk;
     int fVerbose = 0;
     int fSwitch = 0;
 
@@ -349,14 +349,14 @@ int Fraig_NodeIsEquivalent( Fraig_Man_t * p, Fraig_Node_t * pOld, Fraig_Node_t *
 
 
     // get the logic cone
-clk = clock();
+clk = Abc_Clock();
 //    Fraig_VarsStudy( p, pOld, pNew );
     Fraig_OrderVariables( p, pOld, pNew );
 //    Fraig_PrepareCones( p, pOld, pNew );
-p->timeTrav += clock() - clk;
+p->timeTrav += Abc_Clock() - clk;
 
 //    printf( "The number of MUXes detected = %d (%5.2f %% of logic).  ", nMuxes, 300.0*nMuxes/(p->vNodes->nSize - p->vInputs->nSize) );
-//    ABC_PRT( "Time", clock() - clk );
+//    ABC_PRT( "Time", Abc_Clock() - clk );
 
 if ( fVerbose )
     printf( "%d(%d) - ", Fraig_CountPis(p,p->vVarsInt), Msat_IntVecReadSize(p->vVarsInt) );
@@ -371,9 +371,9 @@ if ( fVerbose )
 
     ////////////////////////////////////////////
     // prepare the solver to run incrementally on these variables
-//clk = clock();
+//clk = Abc_Clock();
     Msat_SolverPrepare( p->pSat, p->vVarsInt );
-//p->time3 += clock() - clk;
+//p->time3 += Abc_Clock() - clk;
 
 
     // solve under assumptions
@@ -385,18 +385,18 @@ if ( fVerbose )
 //Msat_SolverWriteDimacs( p->pSat, "temp_fraig.cnf" );
 
     // run the solver
-clk = clock();
+clk = Abc_Clock();
     RetValue1 = Msat_SolverSolve( p->pSat, p->vProj, nBTLimit, nTimeLimit );
-p->timeSat += clock() - clk;
+p->timeSat += Abc_Clock() - clk;
 
     if ( RetValue1 == MSAT_FALSE )
     {
-//p->time1 += clock() - clk;
+//p->time1 += Abc_Clock() - clk;
 
 if ( fVerbose )
 {
 //    printf( "unsat  %d  ", Msat_SolverReadBackTracks(p->pSat) );
-//ABC_PRT( "time", clock() - clk );
+//ABC_PRT( "time", Abc_Clock() - clk );
 }
 
         // add the clause
@@ -409,12 +409,12 @@ if ( fVerbose )
     }
     else if ( RetValue1 == MSAT_TRUE )
     {
-//p->time2 += clock() - clk;
+//p->time2 += Abc_Clock() - clk;
 
 if ( fVerbose )
 {
 //    printf( "sat  %d  ", Msat_SolverReadBackTracks(p->pSat) );
-//ABC_PRT( "time", clock() - clk );
+//ABC_PRT( "time", Abc_Clock() - clk );
 }
 
         // record the counter example
@@ -430,7 +430,7 @@ if ( fVerbose )
     }
     else // if ( RetValue1 == MSAT_UNKNOWN )
     {
-p->time3 += clock() - clk;
+p->time3 += Abc_Clock() - clk;
 
 //        if ( pOld->fFailTfo || pNew->fFailTfo )
 //            printf( "*" );
@@ -453,27 +453,27 @@ p->time3 += clock() - clk;
 
     ////////////////////////////////////////////
     // prepare the solver to run incrementally 
-//clk = clock();
+//clk = Abc_Clock();
     Msat_SolverPrepare( p->pSat, p->vVarsInt );
-//p->time3 += clock() - clk;
+//p->time3 += Abc_Clock() - clk;
     // solve under assumptions
     // A = 0; B = 1     OR     A = 0; B = 0 
     Msat_IntVecClear( p->vProj );
     Msat_IntVecPush( p->vProj, MSAT_VAR2LIT(pOld->Num, 1) );
     Msat_IntVecPush( p->vProj, MSAT_VAR2LIT(pNew->Num, fComp) );
     // run the solver
-clk = clock();
+clk = Abc_Clock();
     RetValue1 = Msat_SolverSolve( p->pSat, p->vProj, nBTLimit, nTimeLimit );
-p->timeSat += clock() - clk;
+p->timeSat += Abc_Clock() - clk;
 
     if ( RetValue1 == MSAT_FALSE )
     {
-//p->time1 += clock() - clk;
+//p->time1 += Abc_Clock() - clk;
 
 if ( fVerbose )
 {
 //    printf( "unsat  %d  ", Msat_SolverReadBackTracks(p->pSat) );
-//ABC_PRT( "time", clock() - clk );
+//ABC_PRT( "time", Abc_Clock() - clk );
 }
 
         // add the clause
@@ -486,12 +486,12 @@ if ( fVerbose )
     }
     else if ( RetValue1 == MSAT_TRUE )
     {
-//p->time2 += clock() - clk;
+//p->time2 += Abc_Clock() - clk;
 
 if ( fVerbose )
 {
 //    printf( "sat  %d  ", Msat_SolverReadBackTracks(p->pSat) );
-//ABC_PRT( "time", clock() - clk );
+//ABC_PRT( "time", Abc_Clock() - clk );
 }
 
         // record the counter example
@@ -507,7 +507,7 @@ if ( fVerbose )
     }
     else // if ( RetValue1 == MSAT_UNKNOWN )
     {
-p->time3 += clock() - clk;
+p->time3 += Abc_Clock() - clk;
 
 //        if ( pOld->fFailTfo || pNew->fFailTfo )
 //            printf( "*" );
@@ -551,7 +551,7 @@ p->time3 += clock() - clk;
 int Fraig_NodeIsImplication( Fraig_Man_t * p, Fraig_Node_t * pOld, Fraig_Node_t * pNew, int nBTLimit )
 {
     int RetValue, RetValue1, i, fComp;
-    clock_t clk;
+    abctime clk;
     int fVerbose = 0;
 
     // make sure the nodes are not complemented
@@ -569,10 +569,10 @@ int Fraig_NodeIsImplication( Fraig_Man_t * p, Fraig_Node_t * pOld, Fraig_Node_t
         Msat_SolverAddVar( p->pSat, p->vNodes->pArray[i]->Level );
 
    // get the logic cone
-clk = clock();
+clk = Abc_Clock();
     Fraig_OrderVariables( p, pOld, pNew );
 //    Fraig_PrepareCones( p, pOld, pNew );
-p->timeTrav += clock() - clk;
+p->timeTrav += Abc_Clock() - clk;
 
 if ( fVerbose )
     printf( "%d(%d) - ", Fraig_CountPis(p,p->vVarsInt), Msat_IntVecReadSize(p->vVarsInt) );
@@ -584,9 +584,9 @@ if ( fVerbose )
 
     ////////////////////////////////////////////
     // prepare the solver to run incrementally on these variables
-//clk = clock();
+//clk = Abc_Clock();
     Msat_SolverPrepare( p->pSat, p->vVarsInt );
-//p->time3 += clock() - clk;
+//p->time3 += Abc_Clock() - clk;
 
     // solve under assumptions
     // A = 1; B = 0     OR     A = 1; B = 1 
@@ -594,18 +594,18 @@ if ( fVerbose )
     Msat_IntVecPush( p->vProj, MSAT_VAR2LIT(pOld->Num, 0) );
     Msat_IntVecPush( p->vProj, MSAT_VAR2LIT(pNew->Num, !fComp) );
     // run the solver
-clk = clock();
+clk = Abc_Clock();
     RetValue1 = Msat_SolverSolve( p->pSat, p->vProj, nBTLimit, 1000000 );
-p->timeSat += clock() - clk;
+p->timeSat += Abc_Clock() - clk;
 
     if ( RetValue1 == MSAT_FALSE )
     {
-//p->time1 += clock() - clk;
+//p->time1 += Abc_Clock() - clk;
 
 if ( fVerbose )
 {
 //    printf( "unsat  %d  ", Msat_SolverReadBackTracks(p->pSat) );
-//ABC_PRT( "time", clock() - clk );
+//ABC_PRT( "time", Abc_Clock() - clk );
 }
 
         // add the clause
@@ -619,12 +619,12 @@ if ( fVerbose )
     }
     else if ( RetValue1 == MSAT_TRUE )
     {
-//p->time2 += clock() - clk;
+//p->time2 += Abc_Clock() - clk;
 
 if ( fVerbose )
 {
 //    printf( "sat  %d  ", Msat_SolverReadBackTracks(p->pSat) );
-//ABC_PRT( "time", clock() - clk );
+//ABC_PRT( "time", Abc_Clock() - clk );
 }
         // record the counter example
         Fraig_FeedBack( p, Msat_SolverReadModelArray(p->pSat), p->vVarsInt, pOld, pNew );
@@ -633,7 +633,7 @@ if ( fVerbose )
     }
     else // if ( RetValue1 == MSAT_UNKNOWN )
     {
-p->time3 += clock() - clk;
+p->time3 += Abc_Clock() - clk;
         p->nSatFailsImp++;
         return 0;
     }
@@ -654,7 +654,7 @@ int Fraig_ManCheckClauseUsingSat( Fraig_Man_t * p, Fraig_Node_t * pNode1, Fraig_
 {
     Fraig_Node_t * pNode1R, * pNode2R;
     int RetValue, RetValue1, i;
-    clock_t clk;
+    abctime clk;
     int fVerbose = 0;
 
     pNode1R = Fraig_Regular(pNode1);
@@ -669,16 +669,16 @@ int Fraig_ManCheckClauseUsingSat( Fraig_Man_t * p, Fraig_Node_t * pNode1, Fraig_
         Msat_SolverAddVar( p->pSat, p->vNodes->pArray[i]->Level );
 
    // get the logic cone
-clk = clock();
+clk = Abc_Clock();
     Fraig_OrderVariables( p, pNode1R, pNode2R );
 //    Fraig_PrepareCones( p, pNode1R, pNode2R );
-p->timeTrav += clock() - clk;
+p->timeTrav += Abc_Clock() - clk;
 
     ////////////////////////////////////////////
     // prepare the solver to run incrementally on these variables
-//clk = clock();
+//clk = Abc_Clock();
     Msat_SolverPrepare( p->pSat, p->vVarsInt );
-//p->time3 += clock() - clk;
+//p->time3 += Abc_Clock() - clk;
 
     // solve under assumptions
     // A = 1; B = 0     OR     A = 1; B = 1 
@@ -686,18 +686,18 @@ p->timeTrav += clock() - clk;
     Msat_IntVecPush( p->vProj, MSAT_VAR2LIT(pNode1R->Num, !Fraig_IsComplement(pNode1)) );
     Msat_IntVecPush( p->vProj, MSAT_VAR2LIT(pNode2R->Num, !Fraig_IsComplement(pNode2)) );
     // run the solver
-clk = clock();
+clk = Abc_Clock();
     RetValue1 = Msat_SolverSolve( p->pSat, p->vProj, nBTLimit, 1000000 );
-p->timeSat += clock() - clk;
+p->timeSat += Abc_Clock() - clk;
 
     if ( RetValue1 == MSAT_FALSE )
     {
-//p->time1 += clock() - clk;
+//p->time1 += Abc_Clock() - clk;
 
 if ( fVerbose )
 {
 //    printf( "unsat  %d  ", Msat_SolverReadBackTracks(p->pSat) );
-//ABC_PRT( "time", clock() - clk );
+//ABC_PRT( "time", Abc_Clock() - clk );
 }
 
         // add the clause
@@ -711,12 +711,12 @@ if ( fVerbose )
     }
     else if ( RetValue1 == MSAT_TRUE )
     {
-//p->time2 += clock() - clk;
+//p->time2 += Abc_Clock() - clk;
 
 if ( fVerbose )
 {
 //    printf( "sat  %d  ", Msat_SolverReadBackTracks(p->pSat) );
-//ABC_PRT( "time", clock() - clk );
+//ABC_PRT( "time", Abc_Clock() - clk );
 }
         // record the counter example
 //        Fraig_FeedBack( p, Msat_SolverReadModelArray(p->pSat), p->vVarsInt, pNode1R, pNode2R );
@@ -725,7 +725,7 @@ if ( fVerbose )
     }
     else // if ( RetValue1 == MSAT_UNKNOWN )
     {
-p->time3 += clock() - clk;
+p->time3 += Abc_Clock() - clk;
         p->nSatFailsImp++;
         return 0;
     }
diff --git a/src/proof/fraig/fraigTable.c b/src/proof/fraig/fraigTable.c
index d184ab7f..03a2ac10 100644
--- a/src/proof/fraig/fraigTable.c
+++ b/src/proof/fraig/fraigTable.c
@@ -261,10 +261,10 @@ void Fraig_TableResizeS( Fraig_HashTable_t * p )
     Fraig_Node_t ** pBinsNew;
     Fraig_Node_t * pEnt, * pEnt2;
     int nBinsNew, Counter, i;
-    clock_t clk;
+    abctime clk;
     unsigned Key;
 
-clk = clock();
+clk = Abc_Clock();
     // get the new table size
     nBinsNew = Abc_PrimeCudd(2 * p->nBins); 
     // allocate a new array
@@ -282,7 +282,7 @@ clk = clock();
         }
     assert( Counter == p->nEntries );
 //    printf( "Increasing the structural table size from %6d to %6d. ", p->nBins, nBinsNew );
-//    ABC_PRT( "Time", clock() - clk );
+//    ABC_PRT( "Time", Abc_Clock() - clk );
     // replace the table and the parameters
     ABC_FREE( p->pBins );
     p->pBins = pBinsNew;
@@ -305,10 +305,10 @@ void Fraig_TableResizeF( Fraig_HashTable_t * p, int fUseSimR )
     Fraig_Node_t ** pBinsNew;
     Fraig_Node_t * pEnt, * pEnt2;
     int nBinsNew, Counter, i;
-    clock_t clk;
+    abctime clk;
     unsigned Key;
 
-clk = clock();
+clk = Abc_Clock();
     // get the new table size
     nBinsNew = Abc_PrimeCudd(2 * p->nBins); 
     // allocate a new array
@@ -329,7 +329,7 @@ clk = clock();
         }
     assert( Counter == p->nEntries );
 //    printf( "Increasing the functional table size from %6d to %6d. ", p->nBins, nBinsNew );
-//    ABC_PRT( "Time", clock() - clk );
+//    ABC_PRT( "Time", Abc_Clock() - clk );
     // replace the table and the parameters
     ABC_FREE( p->pBins );
     p->pBins = pBinsNew;
diff --git a/src/proof/fraig/fraigUtil.c b/src/proof/fraig/fraigUtil.c
index 316b492e..7869c6d6 100644
--- a/src/proof/fraig/fraigUtil.c
+++ b/src/proof/fraig/fraigUtil.c
@@ -844,7 +844,7 @@ int Fraig_ManPrintRefs( Fraig_Man_t * pMan )
     Fraig_NodeVec_t * vPivots;
     Fraig_Node_t * pNode, * pNode2;
     int i, k, Counter, nProved;
-    clock_t clk;
+    abctime clk;
 
     vPivots = Fraig_NodeVecAlloc( 1000 );
     for ( i = 0; i < pMan->vNodes->nSize; i++ )
@@ -862,7 +862,7 @@ int Fraig_ManPrintRefs( Fraig_Man_t * pMan )
     }
     printf( "Total nodes = %d. Referenced nodes = %d.\n", pMan->vNodes->nSize, vPivots->nSize );
 
-clk = clock();
+clk = Abc_Clock();
     // count implications
     Counter = nProved = 0;
     for ( i = 0; i < vPivots->nSize; i++ )
@@ -884,7 +884,7 @@ clk = clock();
             }
         }
     printf( "Number of candidate pairs = %d.  Proved = %d.\n", Counter, nProved );
-//ABC_PRT( "Time", clock() - clk );
+//ABC_PRT( "Time", Abc_Clock() - clk );
     return 0;
 }
 
diff --git a/src/proof/int/intCheck.c b/src/proof/int/intCheck.c
index 28ef54a7..4e58440b 100644
--- a/src/proof/int/intCheck.c
+++ b/src/proof/int/intCheck.c
@@ -217,7 +217,7 @@ void Inter_CheckAddEqual( Inter_Check_t * p, int iVarA, int iVarB )
   SeeAlso     []
 
 ***********************************************************************/
-int Inter_CheckPerform( Inter_Check_t * p, Cnf_Dat_t * pCnfInt, clock_t nTimeNewOut )
+int Inter_CheckPerform( Inter_Check_t * p, Cnf_Dat_t * pCnfInt, abctime nTimeNewOut )
 {
     Aig_Obj_t * pObj, * pObj2;
     int i, f, VarA, VarB, RetValue, Entry, status;
diff --git a/src/proof/int/intCore.c b/src/proof/int/intCore.c
index cfab05dc..dedf987e 100644
--- a/src/proof/int/intCore.c
+++ b/src/proof/int/intCore.c
@@ -83,8 +83,8 @@ int Inter_ManPerformInterpolation( Aig_Man_t * pAig, Inter_ManParams_t * pPars,
     Inter_Check_t * pCheck = NULL;
     Aig_Man_t * pAigTemp;
     int s, i, RetValue, Status;
-    clock_t clk, clk2, clkTotal = clock(), timeTemp = 0;
-    clock_t nTimeNewOut = pPars->nSecLimit ? pPars->nSecLimit * CLOCKS_PER_SEC + clock() : 0;
+    abctime clk, clk2, clkTotal = Abc_Clock(), timeTemp = 0;
+    abctime nTimeNewOut = pPars->nSecLimit ? pPars->nSecLimit * CLOCKS_PER_SEC + Abc_Clock() : 0;
 
     // enable ORing of the interpolants, if containment check is performed inductively with K > 1
     if ( pPars->nFramesK > 1 )
@@ -118,9 +118,9 @@ int Inter_ManPerformInterpolation( Aig_Man_t * pAig, Inter_ManParams_t * pPars,
     else
         p->pAigTrans = Inter_ManStartDuplicated( pAig );
     // derive CNF for the transformed AIG
-clk = clock();
+clk = Abc_Clock();
     p->pCnfAig = Cnf_Derive( p->pAigTrans, Aig_ManRegNum(p->pAigTrans) ); 
-p->timeCnf += clock() - clk;    
+p->timeCnf += Abc_Clock() - clk;    
     if ( pPars->fVerbose )
     { 
         printf( "AIG: PI/PO/Reg = %d/%d/%d. And = %d. Lev = %d.  CNF: Var/Cla = %d/%d.\n",
@@ -136,19 +136,19 @@ p->timeCnf += clock() - clk;
     {
         Cnf_Dat_t * pCnfInter2;
 
-clk2 = clock();
+clk2 = Abc_Clock();
         // initial state
         if ( pPars->fUseBackward )
             p->pInter = Inter_ManStartOneOutput( pAig, 1 );
         else
             p->pInter = Inter_ManStartInitState( Aig_ManRegNum(pAig) );
         assert( Aig_ManCoNum(p->pInter) == 1 );
-clk = clock();
+clk = Abc_Clock();
         p->pCnfInter = Cnf_Derive( p->pInter, 0 );  
-p->timeCnf += clock() - clk;    
+p->timeCnf += Abc_Clock() - clk;    
         // timeframes
         p->pFrames = Inter_ManFramesInter( pAig, p->nFrames, pPars->fUseBackward, pPars->fUseTwoFrames );
-clk = clock();
+clk = Abc_Clock();
         if ( pPars->fRewrite )
         {
             p->pFrames = Dar_ManRwsat( pAigTemp = p->pFrames, 1, 0 );
@@ -156,21 +156,21 @@ clk = clock();
 //        p->pFrames = Fra_FraigEquivence( pAigTemp = p->pFrames, 100, 0 );
 //        Aig_ManStop( pAigTemp );
         }
-p->timeRwr += clock() - clk;
+p->timeRwr += Abc_Clock() - clk;
         // can also do SAT sweeping on the timeframes...
-clk = clock();
+clk = Abc_Clock();
         if ( pPars->fUseBackward )
             p->pCnfFrames = Cnf_Derive( p->pFrames, Aig_ManCoNum(p->pFrames) );  
         else
 //            p->pCnfFrames = Cnf_Derive( p->pFrames, 0 );  
             p->pCnfFrames = Cnf_DeriveSimple( p->pFrames, 0 );  
-p->timeCnf += clock() - clk;    
+p->timeCnf += Abc_Clock() - clk;    
         // report statistics
         if ( pPars->fVerbose )
         {
             printf( "Step = %2d. Frames = 1 + %d. And = %5d. Lev = %5d.  ", 
                 s+1, p->nFrames, Aig_ManNodeNum(p->pFrames), Aig_ManLevelNum(p->pFrames) );
-            ABC_PRT( "Time", clock() - clk2 );
+            ABC_PRT( "Time", Abc_Clock() - clk2 );
         }
 
 
@@ -180,12 +180,12 @@ p->timeCnf += clock() - clk;
         {
             pCheck = Inter_CheckStart( p->pAigTrans, pPars->nFramesK );
             // try new containment check for the initial state
-clk = clock();
+clk = Abc_Clock();
             pCnfInter2 = Cnf_Derive( p->pInter, 1 );  
-p->timeCnf += clock() - clk;    
-clk = clock();
+p->timeCnf += Abc_Clock() - clk;    
+clk = Abc_Clock();
             RetValue = Inter_CheckPerform( pCheck, pCnfInter2, nTimeNewOut );
-p->timeEqu += clock() - clk;
+p->timeEqu += Abc_Clock() - clk;
 //            assert( RetValue == 0 );
             Cnf_DataFree( pCnfInter2 );
             if ( p->vInters )
@@ -200,14 +200,14 @@ p->timeEqu += clock() - clk;
             { 
                 if ( pPars->fVerbose )
                     printf( "Reached limit (%d) on the number of timeframes.\n", pPars->nFramesMax );
-                p->timeTotal = clock() - clkTotal;
+                p->timeTotal = Abc_Clock() - clkTotal;
                 Inter_ManStop( p, 0 );
                 Inter_CheckStop( pCheck );
                 return -1;
             }
 
             // perform interpolation
-            clk = clock();
+            clk = Abc_Clock();
 #ifdef ABC_USE_LIBRARIES
             if ( pPars->fUseMiniSat )
             {
@@ -222,7 +222,7 @@ p->timeEqu += clock() - clk;
             {
                 printf( "   I = %2d. Bmc =%3d. IntAnd =%6d. IntLev =%5d. Conf =%6d.  ", 
                     i+1, i + 1 + p->nFrames, Aig_ManNodeNum(p->pInter), Aig_ManLevelNum(p->pInter), p->nConfCur );
-                ABC_PRT( "Time", clock() - clk );
+                ABC_PRT( "Time", Abc_Clock() - clk );
             }
             // remember the number of timeframes completed
             pPars->iFrameMax = i - 1 + p->nFrames;
@@ -232,7 +232,7 @@ p->timeEqu += clock() - clk;
                 {
                     if ( pPars->fVerbose )
                         printf( "Found a real counterexample in frame %d.\n", p->nFrames );
-                    p->timeTotal = clock() - clkTotal;
+                    p->timeTotal = Abc_Clock() - clkTotal;
                     *piFrame = p->nFrames;
 //                    pAig->pSeqModel = (Abc_Cex_t *)Inter_ManGetCounterExample( pAig, p->nFrames+1, pPars->fVerbose );
                     {
@@ -259,7 +259,7 @@ p->timeEqu += clock() - clk;
             }
             else if ( RetValue == -1 ) 
             {
-                if ( pPars->nSecLimit && clock() > nTimeNewOut ) // timed out
+                if ( pPars->nSecLimit && Abc_Clock() > nTimeNewOut ) // timed out
                 {
                     if ( pPars->fVerbose )
                         printf( "Reached timeout (%d seconds).\n",  pPars->nSecLimit );
@@ -270,14 +270,14 @@ p->timeEqu += clock() - clk;
                     if ( pPars->fVerbose )
                         printf( "Reached limit (%d) on the number of conflicts.\n", p->nConfLimit );
                 }
-                p->timeTotal = clock() - clkTotal;
+                p->timeTotal = Abc_Clock() - clkTotal;
                 Inter_ManStop( p, 0 );
                 Inter_CheckStop( pCheck );
                 return -1;
             }
             assert( RetValue == 1 ); // found new interpolant
             // compress the interpolant
-clk = clock();
+clk = Abc_Clock();
             if ( p->pInterNew )
             {
 //                Ioa_WriteAiger( p->pInterNew, "interpol.aig", 0, 0 );
@@ -285,7 +285,7 @@ clk = clock();
 //                p->pInterNew = Dar_ManRwsat( pAigTemp = p->pInterNew, 0, 0 );
                 Aig_ManStop( pAigTemp );
             }
-p->timeRwr += clock() - clk;
+p->timeRwr += Abc_Clock() - clk;
 
             // check if interpolant is trivial
             if ( p->pInterNew == NULL || Aig_ObjChild0(Aig_ManCo(p->pInterNew,0)) == Aig_ManConst0(p->pInterNew) )
@@ -293,30 +293,30 @@ p->timeRwr += clock() - clk;
 //                printf( "interpolant is constant 0\n" );
                 if ( pPars->fVerbose )
                     printf( "The problem is trivially true for all states.\n" );
-                p->timeTotal = clock() - clkTotal;
+                p->timeTotal = Abc_Clock() - clkTotal;
                 Inter_ManStop( p, 1 );
                 Inter_CheckStop( pCheck );
                 return 1;
             }
 
             // check containment of interpolants
-clk = clock();
+clk = Abc_Clock();
             if ( pPars->fCheckKstep ) // k-step unique-state induction
             {
                 if ( Aig_ManCiNum(p->pInterNew) == Aig_ManCiNum(p->pInter) )
                 {
                     if ( pPars->fTransLoop || pPars->fUseBackward || pPars->nFramesK > 1 )
                     {
-clk2 = clock();
+clk2 = Abc_Clock();
                         Status = Inter_ManCheckInductiveContainment( p->pAigTrans, p->pInterNew, Abc_MinInt(i + 1, pPars->nFramesK), pPars->fUseBackward );
-timeTemp = clock() - clk2;
+timeTemp = Abc_Clock() - clk2;
                     }
                     else
                     {   // new containment check
-clk2 = clock();
+clk2 = Abc_Clock();
                         pCnfInter2 = Cnf_Derive( p->pInterNew, 1 );  
-p->timeCnf += clock() - clk2;
-timeTemp = clock() - clk2;
+p->timeCnf += Abc_Clock() - clk2;
+timeTemp = Abc_Clock() - clk2;
             
                         Status = Inter_CheckPerform( pCheck, pCnfInter2, nTimeNewOut );
                         Cnf_DataFree( pCnfInter2 );
@@ -334,20 +334,20 @@ timeTemp = clock() - clk2;
                 else
                     Status = 0;
             }
-p->timeEqu += clock() - clk - timeTemp;
+p->timeEqu += Abc_Clock() - clk - timeTemp;
             if ( Status ) // contained
             {
                 if ( pPars->fVerbose )
                     printf( "Proved containment of interpolants.\n" );
-                p->timeTotal = clock() - clkTotal;
+                p->timeTotal = Abc_Clock() - clkTotal;
                 Inter_ManStop( p, 1 );
                 Inter_CheckStop( pCheck );
                 return 1;
             }
-            if ( pPars->nSecLimit && clock() > nTimeNewOut )
+            if ( pPars->nSecLimit && Abc_Clock() > nTimeNewOut )
             {
                 printf( "Reached timeout (%d seconds).\n",  pPars->nSecLimit );
-                p->timeTotal = clock() - clkTotal;
+                p->timeTotal = Abc_Clock() - clkTotal;
                 Inter_ManStop( p, 1 );
                 Inter_CheckStop( pCheck );
                 return -1;
@@ -366,10 +366,10 @@ p->timeEqu += clock() - clk - timeTemp;
                     Aig_ManStop( pAigTemp );
                     Aig_ManStop( p->pInterNew );
                     // compress the interpolant
-clk = clock();
+clk = Abc_Clock();
                     p->pInter = Dar_ManRwsat( pAigTemp = p->pInter, 1, 0 );
                     Aig_ManStop( pAigTemp );
-p->timeRwr += clock() - clk;
+p->timeRwr += Abc_Clock() - clk;
                 }
                 else // forward with the new containment checking (using only the frontier)
                 {
@@ -379,9 +379,9 @@ p->timeRwr += clock() - clk;
             }
             p->pInterNew = NULL;
             Cnf_DataFree( p->pCnfInter );
-clk = clock();
+clk = Abc_Clock();
             p->pCnfInter = Cnf_Derive( p->pInter, 0 );  
-p->timeCnf += clock() - clk;
+p->timeCnf += Abc_Clock() - clk;
         }
 
         // start containment checking
diff --git a/src/proof/int/intCtrex.c b/src/proof/int/intCtrex.c
index 9b2946e9..91740e6c 100644
--- a/src/proof/int/intCtrex.c
+++ b/src/proof/int/intCtrex.c
@@ -100,7 +100,7 @@ void * Inter_ManGetCounterExample( Aig_Man_t * pAig, int nFrames, int fVerbose )
     sat_solver * pSat;
     Cnf_Dat_t * pCnf;
     int status;
-    clock_t clk = clock();
+    abctime clk = Abc_Clock();
     Vec_Int_t * vCiIds;
     // create timeframes
     assert( Saig_ManPoNum(pAig) == 1 );
@@ -152,7 +152,7 @@ void * Inter_ManGetCounterExample( Aig_Man_t * pAig, int nFrames, int fVerbose )
     // report the results
     if ( fVerbose )
     {
-        ABC_PRT( "Total ctrex generation time", clock() - clk );
+        ABC_PRT( "Total ctrex generation time", Abc_Clock() - clk );
     }
     return pCtrex;
 
diff --git a/src/proof/int/intInt.h b/src/proof/int/intInt.h
index bf591b7a..37bcf51c 100644
--- a/src/proof/int/intInt.h
+++ b/src/proof/int/intInt.h
@@ -71,13 +71,13 @@ struct Inter_Man_t_
     int              fVerbose;     // the verbosiness flag
     char *           pFileName;
     // runtime
-    clock_t          timeRwr;
-    clock_t          timeCnf;
-    clock_t          timeSat;
-    clock_t          timeInt;
-    clock_t          timeEqu;
-    clock_t          timeOther;
-    clock_t          timeTotal;
+    abctime          timeRwr;
+    abctime          timeCnf;
+    abctime          timeSat;
+    abctime          timeInt;
+    abctime          timeEqu;
+    abctime          timeOther;
+    abctime          timeTotal;
 };
 
 // containment checking manager
@@ -94,7 +94,7 @@ typedef struct Inter_Check_t_ Inter_Check_t;
 /*=== intCheck.c ============================================================*/
 extern Inter_Check_t * Inter_CheckStart( Aig_Man_t * pTrans, int nFramesK );
 extern void            Inter_CheckStop( Inter_Check_t * p );
-extern int             Inter_CheckPerform( Inter_Check_t * p, Cnf_Dat_t * pCnf, clock_t nTimeNewOut );
+extern int             Inter_CheckPerform( Inter_Check_t * p, Cnf_Dat_t * pCnf, abctime nTimeNewOut );
 
 /*=== intContain.c ============================================================*/
 extern int             Inter_ManCheckContainment( Aig_Man_t * pNew, Aig_Man_t * pOld );
@@ -118,7 +118,7 @@ extern void            Inter_ManClean( Inter_Man_t * p );
 extern void            Inter_ManStop( Inter_Man_t * p, int fProved );
 
 /*=== intM114.c ============================================================*/
-extern int             Inter_ManPerformOneStep( Inter_Man_t * p, int fUseBias, int fUseBackward, clock_t nTimeNewOut );
+extern int             Inter_ManPerformOneStep( Inter_Man_t * p, int fUseBias, int fUseBackward, abctime nTimeNewOut );
 
 /*=== intM114p.c ============================================================*/
 #ifdef ABC_USE_LIBRARIES
diff --git a/src/proof/int/intM114.c b/src/proof/int/intM114.c
index bf44696d..64b18ae0 100644
--- a/src/proof/int/intM114.c
+++ b/src/proof/int/intM114.c
@@ -200,7 +200,7 @@ sat_solver * Inter_ManDeriveSatSolver(
   SeeAlso     []
 
 ***********************************************************************/
-int Inter_ManPerformOneStep( Inter_Man_t * p, int fUseBias, int fUseBackward, clock_t nTimeNewOut )
+int Inter_ManPerformOneStep( Inter_Man_t * p, int fUseBias, int fUseBackward, abctime nTimeNewOut )
 {
     sat_solver * pSat;
     void * pSatCnf = NULL;
@@ -209,7 +209,7 @@ int Inter_ManPerformOneStep( Inter_Man_t * p, int fUseBias, int fUseBackward, cl
     int * pGlobalVars;
     int status, RetValue;
     int i, Var;
-    clock_t clk;
+    abctime clk;
 //    assert( p->pInterNew == NULL );
 
     // derive the SAT solver
@@ -231,10 +231,10 @@ int Inter_ManPerformOneStep( Inter_Man_t * p, int fUseBias, int fUseBackward, cl
     pSat->pGlobalVars = fUseBias? pGlobalVars : NULL;
 
     // solve the problem
-clk = clock();
+clk = Abc_Clock();
     status = sat_solver_solve( pSat, NULL, NULL, (ABC_INT64_T)p->nConfLimit, (ABC_INT64_T)0, (ABC_INT64_T)0, (ABC_INT64_T)0 );
     p->nConfCur = pSat->stats.conflicts;
-p->timeSat += clock() - clk;
+p->timeSat += Abc_Clock() - clk;
 
     pSat->pGlobalVars = NULL;
     ABC_FREE( pGlobalVars );
@@ -256,7 +256,7 @@ p->timeSat += clock() - clk;
         return RetValue;
 
     // create the resulting manager
-clk = clock();
+clk = Abc_Clock();
 /*
     if ( !fUseIp )
     {
@@ -307,7 +307,7 @@ clk = clock();
     p->pInterNew = (Aig_Man_t *)Inta_ManInterpolate( pManInterA, (Sto_Man_t *)pSatCnf, p->vVarsAB, 0 );
     Inta_ManFree( pManInterA );
 
-p->timeInt += clock() - clk;
+p->timeInt += Abc_Clock() - clk;
     Sto_ManFree( (Sto_Man_t *)pSatCnf );
     return RetValue;
 }
diff --git a/src/proof/int/intUtil.c b/src/proof/int/intUtil.c
index b93a7453..b7e18f09 100644
--- a/src/proof/int/intUtil.c
+++ b/src/proof/int/intUtil.c
@@ -49,7 +49,7 @@ int Inter_ManCheckInitialState( Aig_Man_t * p )
     Aig_Obj_t * pObj;
     sat_solver * pSat;
     int i, status;
-    clock_t clk = clock();
+    abctime clk = Abc_Clock();
     pCnf = Cnf_Derive( p, Saig_ManRegNum(p) ); 
     pSat = (sat_solver *)Cnf_DataWriteIntoSolver( pCnf, 1, 1 );
     if ( pSat == NULL )
@@ -58,7 +58,7 @@ int Inter_ManCheckInitialState( Aig_Man_t * p )
         return 0;
     }
     status = sat_solver_solve( pSat, NULL, NULL, (ABC_INT64_T)0, (ABC_INT64_T)0, (ABC_INT64_T)0, (ABC_INT64_T)0 );
-    ABC_PRT( "Time", clock() - clk );
+    ABC_PRT( "Time", Abc_Clock() - clk );
     if ( status == l_True )
     {
         p->pSeqModel = Abc_CexAlloc( Aig_ManRegNum(p), Saig_ManPiNum(p), 1 );
@@ -87,7 +87,7 @@ int Inter_ManCheckAllStates( Aig_Man_t * p )
     Cnf_Dat_t * pCnf;
     sat_solver * pSat;
     int status;
-    clock_t clk = clock();
+    abctime clk = Abc_Clock();
     pCnf = Cnf_Derive( p, Saig_ManRegNum(p) ); 
     pSat = (sat_solver *)Cnf_DataWriteIntoSolver( pCnf, 1, 0 );
     Cnf_DataFree( pCnf );
@@ -95,7 +95,7 @@ int Inter_ManCheckAllStates( Aig_Man_t * p )
         return 1;
     status = sat_solver_solve( pSat, NULL, NULL, (ABC_INT64_T)0, (ABC_INT64_T)0, (ABC_INT64_T)0, (ABC_INT64_T)0 );
     sat_solver_delete( pSat );
-    ABC_PRT( "Time", clock() - clk );
+    ABC_PRT( "Time", Abc_Clock() - clk );
     return status == l_False;
 }
 
diff --git a/src/proof/live/kliveness.c b/src/proof/live/kliveness.c
index 7ba67155..d9bc416b 100644
--- a/src/proof/live/kliveness.c
+++ b/src/proof/live/kliveness.c
@@ -534,7 +534,7 @@ int Abc_CommandCS_kLiveness( Abc_Frame_t * pAbc, int argc, char ** argv )
     int directive = -1;
     int c;
     int safetyInvariantPO = -1;
-    clock_t beginTime, endTime;
+    abctime beginTime, endTime;
     double time_spent;
     Vec_Ptr_t *vMasterBarrierDisjuncts = NULL;
     Aig_Man_t *pWorkingAig;
@@ -606,9 +606,9 @@ int Abc_CommandCS_kLiveness( Abc_Frame_t * pAbc, int argc, char ** argv )
 
     if(directive == kCS_WITH_DISCOVER_MONOTONE_SIGNALS)
     {
-        beginTime = clock();
+        beginTime = Abc_Clock();
         vMasterBarrierDisjuncts = findDisjunctiveMonotoneSignals( pNtk );
-        endTime = clock();
+        endTime = Abc_Clock();
         time_spent = (double)(endTime - beginTime)/CLOCKS_PER_SEC;
         printf("pre-processing time = %f\n",time_spent); 
         return 0;
@@ -619,9 +619,9 @@ int Abc_CommandCS_kLiveness( Abc_Frame_t * pAbc, int argc, char ** argv )
         safetyInvariantPO = collectSafetyInvariantPOIndex(pNtkTemp);            
         assert( safetyInvariantPO != -1 );
 
-        beginTime = clock();
+        beginTime = Abc_Clock();
         vMasterBarrierDisjuncts = findDisjunctiveMonotoneSignals( pNtk );
-        endTime = clock();
+        endTime = Abc_Clock();
         time_spent = (double)(endTime - beginTime)/CLOCKS_PER_SEC;
         printf("pre-processing time = %f\n",time_spent); 
 
@@ -634,9 +634,9 @@ int Abc_CommandCS_kLiveness( Abc_Frame_t * pAbc, int argc, char ** argv )
         safetyInvariantPO = collectSafetyInvariantPOIndex(pNtkTemp);            
         assert( safetyInvariantPO != -1 );
 
-        beginTime = clock();
+        beginTime = Abc_Clock();
         vMasterBarrierDisjuncts = collectUserGivenDisjunctiveMonotoneSignals( pNtk );
-        endTime = clock();
+        endTime = Abc_Clock();
         time_spent = (double)(endTime - beginTime)/CLOCKS_PER_SEC;
         printf("pre-processing time = %f\n",time_spent); 
 
diff --git a/src/proof/llb/llb.h b/src/proof/llb/llb.h
index 464f4526..f465359d 100644
--- a/src/proof/llb/llb.h
+++ b/src/proof/llb/llb.h
@@ -65,7 +65,7 @@ struct Gia_ParLlb_t_
     int         TimeLimit;     // time limit for one reachability run
     int         TimeLimitGlo;  // time limit for all reachability runs
     // internal parameters
-    clock_t     TimeTarget;    // the time to stop
+    abctime     TimeTarget;    // the time to stop
     int         iFrame;        // explored up to this frame
 };
 
diff --git a/src/proof/llb/llb1Core.c b/src/proof/llb/llb1Core.c
index 3aa7a6e5..213f2cd9 100644
--- a/src/proof/llb/llb1Core.c
+++ b/src/proof/llb/llb1Core.c
@@ -114,7 +114,7 @@ int Llb_ManModelCheckAig( Aig_Man_t * pAigGlo, Gia_ParLlb_t * pPars, Vec_Int_t *
     Llb_Man_t * p = NULL; 
     Aig_Man_t * pAig;
     int RetValue = -1;
-    clock_t clk = clock();
+    abctime clk = Abc_Clock();
 
     if ( pPars->fIndConstr )
     {
@@ -176,7 +176,7 @@ int Llb_ManModelCheckAig( Aig_Man_t * pAigGlo, Gia_ParLlb_t * pPars, Vec_Int_t *
         RetValue = Llb_ManReachability( p, vHints, pddGlo );
     Llb_ManStop( p );
 
-    Abc_PrintTime( 1, "Time", clock() - clk );
+    Abc_PrintTime( 1, "Time", Abc_Clock() - clk );
 
     if ( pPars->fIndConstr )
         Vec_IntFreeP( &vHints );
diff --git a/src/proof/llb/llb1Hint.c b/src/proof/llb/llb1Hint.c
index 07877a98..353b4c69 100644
--- a/src/proof/llb/llb1Hint.c
+++ b/src/proof/llb/llb1Hint.c
@@ -165,7 +165,7 @@ int Llb_ManModelCheckAigWithHints( Aig_Man_t * pAigGlo, Gia_ParLlb_t * pPars )
     Vec_Int_t * vHints;
     Vec_Int_t * vHFCands;
     int i, Entry, RetValue = -1;
-    clock_t clk = clock();
+    abctime clk = Abc_Clock();
     assert( pPars->nHintDepth > 0 );
 /*
     // perform reachability without hints
@@ -212,7 +212,7 @@ Finish:
     Vec_IntFreeP( &vHFCands );
     Vec_IntFreeP( &vHints );
     if ( pPars->fVerbose )
-        Abc_PrintTime( 1, "Total runtime", clock() - clk );
+        Abc_PrintTime( 1, "Total runtime", Abc_Clock() - clk );
     return RetValue;
 }
 
diff --git a/src/proof/llb/llb1Reach.c b/src/proof/llb/llb1Reach.c
index b7d79994..2acd3020 100644
--- a/src/proof/llb/llb1Reach.c
+++ b/src/proof/llb/llb1Reach.c
@@ -48,7 +48,7 @@ DdNode * Llb_ManConstructOutBdd( Aig_Man_t * pAig, Aig_Obj_t * pNode, DdManager
     Vec_Ptr_t * vNodes;
     Aig_Obj_t * pObj;
     int i;
-    clock_t TimeStop;
+    abctime TimeStop;
     if ( Aig_ObjFanin0(pNode) == Aig_ManConst1(pAig) )
         return Cudd_NotCond( Cudd_ReadOne(dd), Aig_ObjFaninC0(pNode) );
     TimeStop = dd->TimeStop;  dd->TimeStop = 0;
@@ -157,7 +157,7 @@ DdNode * Llb_ManConstructQuantCubeIntern( Llb_Man_t * p, Llb_Grp_t * pGroup, int
     Aig_Obj_t * pObj;
     DdNode * bRes, * bTemp, * bVar;
     int i, iGroupFirst, iGroupLast;
-    clock_t TimeStop;
+    abctime TimeStop;
     TimeStop = p->dd->TimeStop; p->dd->TimeStop = 0;
     bRes = Cudd_ReadOne( p->dd );   Cudd_Ref( bRes );
     Vec_PtrForEachEntry( Aig_Obj_t *, pGroup->vIns, pObj, i )
@@ -207,7 +207,7 @@ DdNode * Llb_ManConstructQuantCubeFwd( Llb_Man_t * p, Llb_Grp_t * pGroup, int iG
     Aig_Obj_t * pObj;
     DdNode * bRes, * bTemp, * bVar;
     int i, iGroupLast;
-    clock_t TimeStop;
+    abctime TimeStop;
     TimeStop = p->dd->TimeStop; p->dd->TimeStop = 0;
     bRes = Cudd_ReadOne( p->dd );   Cudd_Ref( bRes );
     Vec_PtrForEachEntry( Aig_Obj_t *, pGroup->vIns, pObj, i )
@@ -251,7 +251,7 @@ DdNode * Llb_ManConstructQuantCubeBwd( Llb_Man_t * p, Llb_Grp_t * pGroup, int iG
     Aig_Obj_t * pObj;
     DdNode * bRes, * bTemp, * bVar;
     int i, iGroupFirst;
-    clock_t TimeStop;
+    abctime TimeStop;
     TimeStop = p->dd->TimeStop; p->dd->TimeStop = 0;
     bRes = Cudd_ReadOne( p->dd );   Cudd_Ref( bRes );
     Vec_PtrForEachEntry( Aig_Obj_t *, pGroup->vIns, pObj, i )
@@ -299,7 +299,7 @@ DdNode * Llb_ManComputeInitState( Llb_Man_t * p, DdManager * dd )
     Aig_Obj_t * pObj;
     DdNode * bRes, * bVar, * bTemp;
     int i, iVar;
-    clock_t TimeStop;
+    abctime TimeStop;
     TimeStop = dd->TimeStop; dd->TimeStop = 0;
     bRes = Cudd_ReadOne( dd );   Cudd_Ref( bRes );
     Saig_ManForEachLo( p->pAig, pObj, i )
@@ -414,7 +414,7 @@ DdNode * Llb_ManCreateConstraints( Llb_Man_t * p, Vec_Int_t * vHints, int fUseNs
     DdNode * bConstr, * bFunc, * bTemp;
     Aig_Obj_t * pObj;
     int i, Entry;
-    clock_t TimeStop;
+    abctime TimeStop;
     if ( vHints == NULL )
         return Cudd_ReadOne( p->dd );
     TimeStop = p->dd->TimeStop; p->dd->TimeStop = 0;
@@ -586,12 +586,12 @@ int Llb_ManReachability( Llb_Man_t * p, Vec_Int_t * vHints, DdManager ** pddGlo
     int * pGlo2Cs = Vec_IntArray( p->vGlo2Cs );
     DdNode * bCurrent, * bReached, * bNext, * bTemp, * bCube;
     DdNode * bConstrCs, * bConstrNs;
-    clock_t clk2, clk = clock();
+    abctime clk2, clk = Abc_Clock();
     int nIters, nBddSize = 0;
 //    int nThreshold = 10000;
 
     // compute time to stop
-    p->pPars->TimeTarget = p->pPars->TimeLimit ? p->pPars->TimeLimit * CLOCKS_PER_SEC + clock(): 0;
+    p->pPars->TimeTarget = p->pPars->TimeLimit ? p->pPars->TimeLimit * CLOCKS_PER_SEC + Abc_Clock(): 0;
 
     // define variable limits
     Llb_ManPrepareVarLimits( p );
@@ -660,9 +660,9 @@ int Llb_ManReachability( Llb_Man_t * p, Vec_Int_t * vHints, DdManager ** pddGlo
 //Extra_bddPrintSupport( p->dd, bCurrent ); printf( "\n" );
     for ( nIters = 0; nIters < p->pPars->nIterMax; nIters++ )
     { 
-        clk2 = clock();
+        clk2 = Abc_Clock();
         // check the runtime limit
-        if ( p->pPars->TimeLimit && clock() > p->pPars->TimeTarget )
+        if ( p->pPars->TimeLimit && Abc_Clock() > p->pPars->TimeTarget )
         {
             if ( !p->pPars->fSilent )
                 printf( "Reached timeout during image computation (%d seconds).\n",  p->pPars->TimeLimit );
@@ -702,7 +702,7 @@ int Llb_ManReachability( Llb_Man_t * p, Vec_Int_t * vHints, DdManager ** pddGlo
                     Abc_Print( 1, "Output %d of miter \"%s\" was asserted in frame %d.  ", p->pAigGlo->pSeqModel->iPo, p->pAigGlo->pName, p->pAigGlo->pName, nIters );
                 else
                     Abc_Print( 1, "Output ??? of miter \"%s\" was asserted in frame %d (counter-example is not produced).  ", p->pAigGlo->pName, nIters );
-                Abc_PrintTime( 1, "Time", clock() - clk );
+                Abc_PrintTime( 1, "Time", Abc_Clock() - clk );
             }
             p->pPars->iFrame = nIters - 1;
             Cudd_RecursiveDeref( p->dd,  bCurrent );  bCurrent = NULL;
@@ -839,7 +839,7 @@ int Llb_ManReachability( Llb_Man_t * p, Vec_Int_t * vHints, DdManager ** pddGlo
             fprintf( stdout, "(%4d %3d)   ", Cudd_ReadReorderings(p->dd),  Cudd_ReadGarbageCollections(p->dd) );
             fprintf( stdout, "Rea =%6d  ",   Cudd_DagSize(bReached) );
             fprintf( stdout, "(%4d%4d)   ",  Cudd_ReadReorderings(p->ddG), Cudd_ReadGarbageCollections(p->ddG) );
-            Abc_PrintTime( 1, "Time", clock() - clk2 );
+            Abc_PrintTime( 1, "Time", Abc_Clock() - clk2 );
         }
 /*
         if ( p->pPars->fVerbose )
diff --git a/src/proof/llb/llb2Bad.c b/src/proof/llb/llb2Bad.c
index 57745c1d..ac04b563 100644
--- a/src/proof/llb/llb2Bad.c
+++ b/src/proof/llb/llb2Bad.c
@@ -42,7 +42,7 @@ ABC_NAMESPACE_IMPL_START
   SeeAlso     []
 
 ***********************************************************************/
-DdNode * Llb_BddComputeBad( Aig_Man_t * pInit, DdManager * dd, clock_t TimeOut )
+DdNode * Llb_BddComputeBad( Aig_Man_t * pInit, DdManager * dd, abctime TimeOut )
 {
     Vec_Ptr_t * vNodes;
     DdNode * bBdd0, * bBdd1, * bTemp, * bResult;
@@ -111,7 +111,7 @@ DdNode * Llb_BddQuantifyPis( Aig_Man_t * pInit, DdManager * dd, DdNode * bFunc )
     DdNode * bVar, * bCube, * bTemp;
     Aig_Obj_t * pObj;
     int i;
-    clock_t TimeStop;
+    abctime TimeStop;
     assert( Cudd_ReadSize(dd) == Aig_ManCiNum(pInit) );
     TimeStop = dd->TimeStop; dd->TimeStop = 0;
     // create PI cube
diff --git a/src/proof/llb/llb2Core.c b/src/proof/llb/llb2Core.c
index a6f16aeb..3d62b322 100644
--- a/src/proof/llb/llb2Core.c
+++ b/src/proof/llb/llb2Core.c
@@ -69,7 +69,7 @@ DdNode * Llb_CoreComputeCube( DdManager * dd, Vec_Int_t * vVars, int fUseVarInde
 {
     DdNode * bRes, * bVar, * bTemp;
     int i, iVar, Index;
-    clock_t TimeStop;
+    abctime TimeStop;
     TimeStop = dd->TimeStop; dd->TimeStop = 0;
     bRes = Cudd_ReadOne( dd );   Cudd_Ref( bRes );
     Vec_IntForEachEntry( vVars, Index, i )
@@ -210,17 +210,17 @@ int Llb_CoreReachability_int( Llb_Img_t * p, Vec_Ptr_t * vQuant0, Vec_Ptr_t * vQ
     int * pLoc2GloR = p->pPars->fBackward? Vec_IntArray( p->vNs2Glo ) : Vec_IntArray( p->vCs2Glo );
     int * pGlo2Loc  = p->pPars->fBackward? Vec_IntArray( p->vGlo2Ns ) : Vec_IntArray( p->vGlo2Cs );
     DdNode * bCurrent, * bReached, * bNext, * bTemp;
-    clock_t clk2, clk = clock();
+    abctime clk2, clk = Abc_Clock();
     int nIters, nBddSize;//, iOutFail = -1;
 /*
     // compute time to stop
     if ( p->pPars->TimeLimit )
-        p->pPars->TimeTarget = clock() + p->pPars->TimeLimit * CLOCKS_PER_SEC;
+        p->pPars->TimeTarget = Abc_Clock() + p->pPars->TimeLimit * CLOCKS_PER_SEC;
     else
         p->pPars->TimeTarget = 0;
 */
 
-    if ( clock() > p->pPars->TimeTarget )
+    if ( Abc_Clock() > p->pPars->TimeTarget )
     {
         if ( !p->pPars->fSilent )
             printf( "Reached timeout (%d seconds) before image computation.\n", p->pPars->TimeLimit );
@@ -286,9 +286,9 @@ int Llb_CoreReachability_int( Llb_Img_t * p, Vec_Ptr_t * vQuant0, Vec_Ptr_t * vQ
     // compute onion rings
     for ( nIters = 0; nIters < p->pPars->nIterMax; nIters++ )
     { 
-        clk2 = clock();
+        clk2 = Abc_Clock();
         // check the runtime limit
-        if ( p->pPars->TimeLimit && clock() > p->pPars->TimeTarget )
+        if ( p->pPars->TimeLimit && Abc_Clock() > p->pPars->TimeTarget )
         {
             if ( !p->pPars->fSilent )
                 printf( "Reached timeout (%d seconds) during image computation.\n",  p->pPars->TimeLimit );
@@ -326,7 +326,7 @@ int Llb_CoreReachability_int( Llb_Img_t * p, Vec_Ptr_t * vQuant0, Vec_Ptr_t * vQ
                     Abc_Print( 1, "Output %d of miter \"%s\" was asserted in frame %d.  ", p->pInit->pSeqModel->iPo, p->pInit->pName, nIters );
                 else
                     Abc_Print( 1, "Output ??? was asserted in frame %d (counter-example is not produced).  ", nIters );
-                Abc_PrintTime( 1, "Time", clock() - clk );
+                Abc_PrintTime( 1, "Time", Abc_Clock() - clk );
             }
             p->pPars->iFrame = nIters - 1;
             return 0;
@@ -428,7 +428,7 @@ int Llb_CoreReachability_int( Llb_Img_t * p, Vec_Ptr_t * vQuant0, Vec_Ptr_t * vQ
             fprintf( stdout, "Reach =%6d  ", Cudd_DagSize(bReached) );
             fprintf( stdout, "(%4d%4d)  ", 
                 Cudd_ReadReorderings(p->ddG), Cudd_ReadGarbageCollections(p->ddG) );
-            Abc_PrintTime( 1, "Time", clock() - clk2 );
+            Abc_PrintTime( 1, "Time", Abc_Clock() - clk2 );
         }
 
         // check timeframe limit
@@ -471,7 +471,7 @@ int Llb_CoreReachability_int( Llb_Img_t * p, Vec_Ptr_t * vQuant0, Vec_Ptr_t * vQ
         if ( !p->pPars->fSilent )
         {
             printf( "Verified only for states reachable in %d frames.  ", nIters );
-            Abc_PrintTime( 1, "Time", clock() - clk );
+            Abc_PrintTime( 1, "Time", Abc_Clock() - clk );
         }
         p->pPars->iFrame = p->pPars->nIterMax;
         return -1; // undecided
@@ -479,7 +479,7 @@ int Llb_CoreReachability_int( Llb_Img_t * p, Vec_Ptr_t * vQuant0, Vec_Ptr_t * vQ
     if ( !p->pPars->fSilent )
     {
         printf( "The miter is proved unreachable after %d iterations.  ", nIters );
-        Abc_PrintTime( 1, "Time", clock() - clk );
+        Abc_PrintTime( 1, "Time", Abc_Clock() - clk );
     }
     p->pPars->iFrame = nIters - 1;
     return 1; // unreachable
@@ -531,7 +531,7 @@ int Llb_CoreReachability( Llb_Img_t * p )
   SeeAlso     []
 
 ***********************************************************************/
-Vec_Ptr_t * Llb_CoreConstructAll( Aig_Man_t * p, Vec_Ptr_t * vResult, Vec_Int_t * vVarsNs, clock_t TimeTarget )
+Vec_Ptr_t * Llb_CoreConstructAll( Aig_Man_t * p, Vec_Ptr_t * vResult, Vec_Int_t * vVarsNs, abctime TimeTarget )
 {
     DdManager * dd;
     Vec_Ptr_t * vDdMans;
@@ -691,7 +691,7 @@ void Llb_CoreStop( Llb_Img_t * p )
   SeeAlso     []
 
 ***********************************************************************/
-int Llb_CoreExperiment( Aig_Man_t * pInit, Aig_Man_t * pAig, Gia_ParLlb_t * pPars, Vec_Ptr_t * vResult, clock_t TimeTarget )
+int Llb_CoreExperiment( Aig_Man_t * pInit, Aig_Man_t * pAig, Gia_ParLlb_t * pPars, Vec_Ptr_t * vResult, abctime TimeTarget )
 {
     int RetValue;
     Llb_Img_t * p;
@@ -728,10 +728,10 @@ int Llb_ManReachMinCut( Aig_Man_t * pAig, Gia_ParLlb_t * pPars )
     Vec_Ptr_t * vResult;
     Aig_Man_t * p;
     int RetValue = -1;
-    clock_t clk = clock();
+    abctime clk = Abc_Clock();
 
     // compute time to stop
-    pPars->TimeTarget = pPars->TimeLimit ? pPars->TimeLimit * CLOCKS_PER_SEC + clock(): 0;
+    pPars->TimeTarget = pPars->TimeLimit ? pPars->TimeLimit * CLOCKS_PER_SEC + Abc_Clock(): 0;
 
     p = Aig_ManDupFlopsOnly( pAig );
 //Aig_ManShow( p, 0, NULL );
@@ -743,7 +743,7 @@ int Llb_ManReachMinCut( Aig_Man_t * pAig, Gia_ParLlb_t * pPars )
 
     vResult = Llb_ManComputeCuts( p, pPars->nPartValue, pPars->fVerbose, pPars->fVeryVerbose );
 
-    if ( pPars->TimeLimit && clock() > pPars->TimeTarget )
+    if ( pPars->TimeLimit && Abc_Clock() > pPars->TimeTarget )
     {
         if ( !pPars->fSilent )
             printf( "Reached timeout (%d seconds) after partitioning.\n", pPars->TimeLimit );
@@ -764,7 +764,7 @@ int Llb_ManReachMinCut( Aig_Man_t * pAig, Gia_ParLlb_t * pPars )
     Aig_ManStop( p );
 
     if ( RetValue == -1 )
-        Abc_PrintTime( 1, "Total runtime of the min-cut-based reachability engine", clock() - clk );
+        Abc_PrintTime( 1, "Total runtime of the min-cut-based reachability engine", Abc_Clock() - clk );
     return RetValue;
 }
 
diff --git a/src/proof/llb/llb2Driver.c b/src/proof/llb/llb2Driver.c
index 40d7a116..1471f377 100644
--- a/src/proof/llb/llb2Driver.c
+++ b/src/proof/llb/llb2Driver.c
@@ -130,7 +130,7 @@ DdNode * Llb_DriverPhaseCube( Aig_Man_t * pAig, Vec_Int_t * vDriRefs, DdManager
     DdNode * bCube, * bVar, * bTemp;
     Aig_Obj_t * pObj;
     int i;
-    clock_t TimeStop;
+    abctime TimeStop;
     TimeStop = dd->TimeStop; dd->TimeStop = 0;
     bCube = Cudd_ReadOne( dd );  Cudd_Ref( bCube );
     Saig_ManForEachLi( pAig, pObj, i )
@@ -160,7 +160,7 @@ DdNode * Llb_DriverPhaseCube( Aig_Man_t * pAig, Vec_Int_t * vDriRefs, DdManager
   SeeAlso     []
 
 ***********************************************************************/
-DdManager * Llb_DriverLastPartition( Aig_Man_t * p, Vec_Int_t * vVarsNs, clock_t TimeTarget )
+DdManager * Llb_DriverLastPartition( Aig_Man_t * p, Vec_Int_t * vVarsNs, abctime TimeTarget )
 {
 //    int fVerbose = 1;
     DdManager * dd;
diff --git a/src/proof/llb/llb2Flow.c b/src/proof/llb/llb2Flow.c
index a04998fc..9fa40b9e 100644
--- a/src/proof/llb/llb2Flow.c
+++ b/src/proof/llb/llb2Flow.c
@@ -1227,7 +1227,7 @@ Vec_Ptr_t * Llb_ManComputeCuts( Aig_Man_t * p, int Num, int fVerbose, int fVeryV
     int nVolMax = Aig_ManNodeNum(p) / Num;
     Vec_Ptr_t * vResult, * vMinCut = NULL, * vLower, * vUpper;
     int i, k, nVol;
-    clock_t clk = clock();
+    abctime clk = Abc_Clock();
     vResult = Vec_PtrAlloc( 100 );
     Vec_PtrPush( vResult, Llb_ManComputeCutLo(p) );
     Vec_PtrPush( vResult, Llb_ManComputeCutLi(p) );
@@ -1277,7 +1277,7 @@ Vec_Ptr_t * Llb_ManComputeCuts( Aig_Man_t * p, int Num, int fVerbose, int fVeryV
     if ( fVerbose )
     {
         printf( "Finished computing %d partitions.  ", Vec_PtrSize(vResult) - 1 );
-        Abc_PrintTime( 1, "Time", clock() - clk );
+        Abc_PrintTime( 1, "Time", Abc_Clock() - clk );
         Llb_ManResultPrint( p, vResult );
     }
     return vResult;
diff --git a/src/proof/llb/llb2Image.c b/src/proof/llb/llb2Image.c
index cfaef13c..36ff2df5 100644
--- a/src/proof/llb/llb2Image.c
+++ b/src/proof/llb/llb2Image.c
@@ -179,7 +179,7 @@ void Llb_ImgSchedule( Vec_Ptr_t * vSupps, Vec_Ptr_t ** pvQuant0, Vec_Ptr_t ** pv
   SeeAlso     []
 
 ***********************************************************************/
-DdManager * Llb_ImgPartition( Aig_Man_t * p, Vec_Ptr_t * vLower, Vec_Ptr_t * vUpper, clock_t TimeTarget )
+DdManager * Llb_ImgPartition( Aig_Man_t * p, Vec_Ptr_t * vLower, Vec_Ptr_t * vUpper, abctime TimeTarget )
 {
     Vec_Ptr_t * vNodes, * vRange;
     Aig_Obj_t * pObj;
@@ -260,7 +260,7 @@ DdNode * Llb_ImgComputeCube( Aig_Man_t * pAig, Vec_Int_t * vNodeIds, DdManager *
     DdNode * bProd, * bTemp;
     Aig_Obj_t * pObj;
     int i;
-    clock_t TimeStop;
+    abctime TimeStop;
     TimeStop = dd->TimeStop; dd->TimeStop = 0;
     bProd = Cudd_ReadOne(dd);   Cudd_Ref( bProd );
     Aig_ManForEachObjVec( vNodeIds, pAig, pObj, i )
@@ -289,7 +289,7 @@ void Llb_ImgQuantifyFirst( Aig_Man_t * pAig, Vec_Ptr_t * vDdMans, Vec_Ptr_t * vQ
     DdManager * dd;
     DdNode * bProd, * bRes, * bTemp;
     int i;
-    clock_t clk = clock();
+    abctime clk = Abc_Clock();
     Vec_PtrForEachEntry( DdManager *, vDdMans, dd, i )
     {
         // remember unquantified ones
@@ -320,7 +320,7 @@ void Llb_ImgQuantifyFirst( Aig_Man_t * pAig, Vec_Ptr_t * vDdMans, Vec_Ptr_t * vQ
         if ( fVerbose ) 
             Abc_Print( 1, "Supp = %3d.  ", Cudd_SupportSize(dd, bRes) );
         if ( fVerbose ) 
-            Abc_PrintTime( 1, "Time", clock() - clk );
+            Abc_PrintTime( 1, "Time", Abc_Clock() - clk );
 
     }
 }
@@ -362,13 +362,13 @@ void Llb_ImgQuantifyReset( Vec_Ptr_t * vDdMans )
 ***********************************************************************/
 DdNode * Llb_ImgComputeImage( Aig_Man_t * pAig, Vec_Ptr_t * vDdMans, DdManager * dd, DdNode * bInit, 
     Vec_Ptr_t * vQuant0, Vec_Ptr_t * vQuant1, Vec_Int_t * vDriRefs, 
-    clock_t TimeTarget, int fBackward, int fReorder, int fVerbose )
+    abctime TimeTarget, int fBackward, int fReorder, int fVerbose )
 {
 //    int fCheckSupport = 0;
     DdManager * ddPart;
     DdNode * bImage, * bGroup, * bCube, * bTemp;
     int i;
-    clock_t clk, clk0 = clock();
+    abctime clk, clk0 = Abc_Clock();
 
     bImage = bInit;  Cudd_Ref( bImage );
     if ( fBackward )
@@ -397,7 +397,7 @@ DdNode * Llb_ImgComputeImage( Aig_Man_t * pAig, Vec_Ptr_t * vDdMans, DdManager *
     // perform image computation
     Vec_PtrForEachEntry( DdManager *, vDdMans, ddPart, i )
     {
-        clk = clock();
+        clk = Abc_Clock();
 if ( fVerbose )
 printf( "   %2d : ", i );
         // transfer the BDD from the group manager to the main manager
@@ -434,7 +434,7 @@ printf( "Im0 =%6d. Im1 =%6d. ", Cudd_DagSize(bTemp), Cudd_DagSize(bImage) );
 if ( fVerbose )
 printf( "Supp =%3d. ", Cudd_SupportSize(dd, bImage) );
 if ( fVerbose )
-Abc_PrintTime( 1, "T", clock() - clk );
+Abc_PrintTime( 1, "T", Abc_Clock() - clk );
     }
 
     if ( !fBackward )
@@ -464,7 +464,7 @@ Abc_PrintTime( 1, "T", clock() - clk );
 //    Cudd_ReduceHeap( dd, CUDD_REORDER_SYMM_SIFT, 100 );
 //    Abc_Print( 1, "After =%5d.  ", Cudd_DagSize(bImage) );
     if ( fVerbose )
-    Abc_PrintTime( 1, "Time", clock() - clk0 );
+    Abc_PrintTime( 1, "Time", Abc_Clock() - clk0 );
 //    Abc_Print( 1, "\n" );
     }
 
diff --git a/src/proof/llb/llb3Image.c b/src/proof/llb/llb3Image.c
index dcce8441..72c6120a 100644
--- a/src/proof/llb/llb3Image.c
+++ b/src/proof/llb/llb3Image.c
@@ -79,7 +79,7 @@ static inline Llb_Prt_t * Llb_MgrPart( Llb_Mgr_t * p, int i )  { return p->pPart
     for ( i = 0; (i < Vec_IntSize(pVar->vParts)) && (((pPart) = Llb_MgrPart(p, Vec_IntEntry(pVar->vParts,i))), 1); i++ )
 
 // statistics
-clock_t timeBuild, timeAndEx, timeOther;
+abctime timeBuild, timeAndEx, timeOther;
 int nSuppMax;
 
 ////////////////////////////////////////////////////////////////////////
@@ -141,7 +141,7 @@ DdNode * Llb_NonlinCreateCube1( Llb_Mgr_t * p, Llb_Prt_t * pPart )
     DdNode * bCube, * bTemp;
     Llb_Var_t * pVar;
     int i;
-    clock_t TimeStop;
+    abctime TimeStop;
     TimeStop = p->dd->TimeStop; p->dd->TimeStop = 0;
     bCube = Cudd_ReadOne(p->dd);   Cudd_Ref( bCube );
     Llb_PartForEachVar( p, pPart, pVar, i )
@@ -174,7 +174,7 @@ DdNode * Llb_NonlinCreateCube2( Llb_Mgr_t * p, Llb_Prt_t * pPart1, Llb_Prt_t * p
     DdNode * bCube, * bTemp;
     Llb_Var_t * pVar;
     int i;
-    clock_t TimeStop;
+    abctime TimeStop;
     TimeStop = p->dd->TimeStop; p->dd->TimeStop = 0;
     bCube = Cudd_ReadOne(p->dd);   Cudd_Ref( bCube );
     Llb_PartForEachVar( p, pPart1, pVar, i )
@@ -747,7 +747,7 @@ int Llb_NonlinNextPartitions( Llb_Mgr_t * p, Llb_Prt_t ** ppPart1, Llb_Prt_t **
 ***********************************************************************/
 void Llb_NonlinReorder( DdManager * dd, int fTwice, int fVerbose )
 {
-    clock_t clk = clock();
+    abctime clk = Abc_Clock();
     if ( fVerbose )
         Abc_Print( 1, "Reordering... Before =%5d. ", Cudd_ReadKeys(dd) - Cudd_ReadDead(dd) );
     Cudd_ReduceHeap( dd, CUDD_REORDER_SYMM_SIFT, 100 );
@@ -760,7 +760,7 @@ void Llb_NonlinReorder( DdManager * dd, int fTwice, int fVerbose )
             Abc_Print( 1, "After =%5d. ", Cudd_ReadKeys(dd) - Cudd_ReadDead(dd) );
     }
     if ( fVerbose )
-        Abc_PrintTime( 1, "Time", clock() - clk );
+        Abc_PrintTime( 1, "Time", Abc_Clock() - clk );
 }
 
 /**Function*************************************************************
@@ -888,9 +888,9 @@ DdNode * Llb_NonlinImage( Aig_Man_t * pAig, Vec_Ptr_t * vLeaves, Vec_Ptr_t * vRo
     Llb_Mgr_t * p;
     DdNode * bFunc, * bTemp;
     int i, nReorders, timeInside;
-    clock_t clk = clock(), clk2;
+    abctime clk = Abc_Clock(), clk2;
     // start the manager
-    clk2 = clock();
+    clk2 = Abc_Clock();
     p = Llb_NonlinAlloc( pAig, vLeaves, vRoots, pVars2Q, dd );
     if ( !Llb_NonlinStart( p ) )
     {
@@ -903,8 +903,8 @@ DdNode * Llb_NonlinImage( Aig_Man_t * pAig, Vec_Ptr_t * vLeaves, Vec_Ptr_t * vRo
     Llb_MgrForEachPart( p, pPart, i )
         if ( Llb_NonlinHasSingletonVars(p, pPart) )
             Llb_NonlinQuantify1( p, pPart, 0 );
-    timeBuild += clock() - clk2;
-    timeInside = clock() - clk2;
+    timeBuild += Abc_Clock() - clk2;
+    timeInside = Abc_Clock() - clk2;
     // compute scores
     Llb_NonlinRecomputeScores( p );
     // save permutation
@@ -913,15 +913,15 @@ DdNode * Llb_NonlinImage( Aig_Man_t * pAig, Vec_Ptr_t * vLeaves, Vec_Ptr_t * vRo
     // iteratively quantify variables
     while ( Llb_NonlinNextPartitions(p, &pPart1, &pPart2) )
     {
-        clk2 = clock();
+        clk2 = Abc_Clock();
         nReorders = Cudd_ReadReorderings(dd);
         if ( !Llb_NonlinQuantify2( p, pPart1, pPart2 ) )
         {
             Llb_NonlinFree( p );
             return NULL;
         }
-        timeAndEx  += clock() - clk2;
-        timeInside += clock() - clk2;
+        timeAndEx  += Abc_Clock() - clk2;
+        timeInside += Abc_Clock() - clk2;
         if ( nReorders < Cudd_ReadReorderings(dd) )
             Llb_NonlinRecomputeScores( p );
 //        else
@@ -939,7 +939,7 @@ DdNode * Llb_NonlinImage( Aig_Man_t * pAig, Vec_Ptr_t * vLeaves, Vec_Ptr_t * vRo
     // reorder variables
     if ( fReorder )
         Llb_NonlinReorder( dd, 0, fVerbose );
-    timeOther += clock() - clk - timeInside;
+    timeOther += Abc_Clock() - clk - timeInside;
     // return
     Cudd_Deref( bFunc );
     return bFunc;
@@ -960,10 +960,10 @@ static Llb_Mgr_t * p = NULL;
   SeeAlso     []
 
 ***********************************************************************/
-DdManager * Llb_NonlinImageStart( Aig_Man_t * pAig, Vec_Ptr_t * vLeaves, Vec_Ptr_t * vRoots, int * pVars2Q, int * pOrder, int fFirst, clock_t TimeTarget )
+DdManager * Llb_NonlinImageStart( Aig_Man_t * pAig, Vec_Ptr_t * vLeaves, Vec_Ptr_t * vRoots, int * pVars2Q, int * pOrder, int fFirst, abctime TimeTarget )
 {
     DdManager * dd;
-    clock_t clk = clock();
+    abctime clk = Abc_Clock();
     assert( p == NULL );
     // start a new manager (disable reordering)
     dd = Cudd_Init( Aig_ManObjNumMax(pAig), 0, CUDD_UNIQUE_SLOTS, CUDD_CACHE_SLOTS, 0 );
@@ -979,7 +979,7 @@ DdManager * Llb_NonlinImageStart( Aig_Man_t * pAig, Vec_Ptr_t * vLeaves, Vec_Ptr
         p = NULL;
         return NULL;
     }
-    timeBuild += clock() - clk;
+    timeBuild += Abc_Clock() - clk;
 //    if ( !fFirst )
 //        Cudd_AutodynEnable( dd,  CUDD_REORDER_SYMM_SIFT );
     return dd;
@@ -1001,7 +1001,7 @@ DdNode * Llb_NonlinImageCompute( DdNode * bCurrent, int fReorder, int fDrop, int
     Llb_Prt_t * pPart, * pPart1, * pPart2;
     DdNode * bFunc, * bTemp;
     int i, nReorders, timeInside = 0;
-    clock_t clk = clock(), clk2;
+    abctime clk = Abc_Clock(), clk2;
 
     // add partition
     Llb_NonlinAddPartition( p, p->iPartFree++, bCurrent );
@@ -1020,15 +1020,15 @@ DdNode * Llb_NonlinImageCompute( DdNode * bCurrent, int fReorder, int fDrop, int
     // iteratively quantify variables
     while ( Llb_NonlinNextPartitions(p, &pPart1, &pPart2) )
     {
-        clk2 = clock();
+        clk2 = Abc_Clock();
         nReorders = Cudd_ReadReorderings(p->dd);
         if ( !Llb_NonlinQuantify2( p, pPart1, pPart2 ) )
         {
             Llb_NonlinFree( p );
             return NULL;
         }
-        timeAndEx  += clock() - clk2;
-        timeInside += clock() - clk2;
+        timeAndEx  += Abc_Clock() - clk2;
+        timeInside += Abc_Clock() - clk2;
         if ( nReorders < Cudd_ReadReorderings(p->dd) )
             Llb_NonlinRecomputeScores( p );
 //        else
@@ -1055,7 +1055,7 @@ DdNode * Llb_NonlinImageCompute( DdNode * bCurrent, int fReorder, int fDrop, int
     // save permutation
 //    memcpy( pOrder, p->dd->invperm, sizeof(int) * Cudd_ReadSize(p->dd) );
 
-    timeOther += clock() - clk - timeInside;
+    timeOther += Abc_Clock() - clk - timeInside;
     // return
     Cudd_Deref( bFunc );
     return bFunc;
diff --git a/src/proof/llb/llb3Nonlin.c b/src/proof/llb/llb3Nonlin.c
index 22e23337..94a48bbf 100644
--- a/src/proof/llb/llb3Nonlin.c
+++ b/src/proof/llb/llb3Nonlin.c
@@ -54,18 +54,18 @@ struct Llb_Mnn_t_
     int             ddLocReos;
     int             ddLocGrbs;
 
-    clock_t         timeImage;
-    clock_t         timeTran1;
-    clock_t         timeTran2;
-    clock_t         timeGloba;
-    clock_t         timeOther;
-    clock_t         timeTotal;
-    clock_t         timeReo;
-    clock_t         timeReoG;
+    abctime         timeImage;
+    abctime         timeTran1;
+    abctime         timeTran2;
+    abctime         timeGloba;
+    abctime         timeOther;
+    abctime         timeTotal;
+    abctime         timeReo;
+    abctime         timeReoG;
 
 };
 
-extern clock_t timeBuild, timeAndEx, timeOther;
+extern abctime timeBuild, timeAndEx, timeOther;
 extern int nSuppMax;
 
 ////////////////////////////////////////////////////////////////////////
@@ -90,7 +90,7 @@ int Llb_NonlinFindBestVar( DdManager * dd, DdNode * bFunc, Aig_Man_t * pAig )
     DdNode * bCof, * bVar;
     int i, iVar, iVarBest = -1, iValue, iValueBest = ABC_INFINITY, Size0Best = -1;
     int Size, Size0, Size1;
-    clock_t clk = clock();
+    abctime clk = Abc_Clock();
     Size = Cudd_DagSize(bFunc);
 //    printf( "Original = %6d.  SuppSize = %3d. Vars = %3d.\n", 
 //        Size = Cudd_DagSize(bFunc), Cudd_SupportSize(dd, bFunc), Aig_ManRegNum(pAig) );
@@ -134,7 +134,7 @@ printf( "S =%6d\n", iValue );
     }
     printf( "BestVar = %4d/%4d.  Value =%6d.  Orig =%6d. Size0 =%6d. ", 
         iVarBest, Aig_ObjId(Saig_ManLo(pAig,iVarBest)), iValueBest, Size, Size0Best );
-    Abc_PrintTime( 1, "Time", clock() - clk );
+    Abc_PrintTime( 1, "Time", Abc_Clock() - clk );
     return iVarBest;
 }
 
@@ -216,7 +216,7 @@ DdNode * Llb_NonlinComputeInitState( Aig_Man_t * pAig, DdManager * dd )
     Aig_Obj_t * pObj;
     DdNode * bRes, * bVar, * bTemp;
     int i, iVar;
-    clock_t TimeStop;
+    abctime TimeStop;
     TimeStop = dd->TimeStop;  dd->TimeStop = 0;
     bRes = Cudd_ReadOne( dd );   Cudd_Ref( bRes );
     Saig_ManForEachLo( pAig, pObj, i )
@@ -430,11 +430,11 @@ int Llb_NonlinReachability( Llb_Mnn_t * p )
 { 
     DdNode * bTemp, * bNext;
     int nIters, nBddSize0, nBddSize = -1, NumCmp;//, Limit = p->pPars->nBddMax;
-    clock_t clk2, clk3, clk = clock();
+    abctime clk2, clk3, clk = Abc_Clock();
     assert( Aig_ManRegNum(p->pAig) > 0 );
 
     // compute time to stop
-    p->pPars->TimeTarget = p->pPars->TimeLimit ? p->pPars->TimeLimit * CLOCKS_PER_SEC + clock(): 0;
+    p->pPars->TimeTarget = p->pPars->TimeLimit ? p->pPars->TimeLimit * CLOCKS_PER_SEC + Abc_Clock(): 0;
 
     // set the stop time parameter
     p->dd->TimeStop  = p->pPars->TimeTarget;
@@ -472,8 +472,8 @@ int Llb_NonlinReachability( Llb_Mnn_t * p )
     for ( nIters = 0; nIters < p->pPars->nIterMax; nIters++ )
     { 
         // check the runtime limit
-        clk2 = clock();
-        if ( p->pPars->TimeLimit && clock() > p->pPars->TimeTarget )
+        clk2 = Abc_Clock();
+        if ( p->pPars->TimeLimit && Abc_Clock() > p->pPars->TimeTarget )
         {
             if ( !p->pPars->fSilent )
                 printf( "Reached timeout (%d seconds) during image computation.\n",  p->pPars->TimeLimit );
@@ -507,7 +507,7 @@ int Llb_NonlinReachability( Llb_Mnn_t * p )
                     Abc_Print( 1, "Output %d of miter \"%s\" was asserted in frame %d.  ", p->pInit->pSeqModel->iPo, nIters );
                 else
                     Abc_Print( 1, "Output ??? was asserted in frame %d (counter-example is not produced).  ", nIters );
-                Abc_PrintTime( 1, "Time", clock() - clk );
+                Abc_PrintTime( 1, "Time", Abc_Clock() - clk );
             }
             p->pPars->iFrame = nIters - 1;
             Llb_NonlinImageQuit();
@@ -515,7 +515,7 @@ int Llb_NonlinReachability( Llb_Mnn_t * p )
         }
 
         // compute the next states
-        clk3 = clock();
+        clk3 = Abc_Clock();
         nBddSize0 = Cudd_DagSize( p->dd->bFunc );
         bNext = Llb_NonlinImageCompute( p->dd->bFunc, p->pPars->fReorder, 0, 1, p->pOrderL ); // consumes ref   
 //        bNext = Llb_NonlinImage( p->pAig, p->vLeaves, p->vRoots, p->pVars2Q, p->dd, bCurrent, 
@@ -530,11 +530,11 @@ int Llb_NonlinReachability( Llb_Mnn_t * p )
         }
         Cudd_Ref( bNext );
         nBddSize = Cudd_DagSize( bNext );
-        p->timeImage += clock() - clk3;
+        p->timeImage += Abc_Clock() - clk3;
 
 
         // transfer to the state manager
-        clk3 = clock();
+        clk3 = Abc_Clock();
         Cudd_RecursiveDeref( p->ddG, p->ddG->bFunc2 );
         p->ddG->bFunc2 = Extra_TransferPermute( p->dd, p->ddG, bNext, Vec_IntArray(p->vNs2Glo) );    
 //        p->ddG->bFunc2 = Extra_bddAndPermute( p->ddG, Cudd_Not(p->ddG->bFunc), p->dd, bNext, Vec_IntArray(p->vNs2Glo) );    
@@ -549,7 +549,7 @@ int Llb_NonlinReachability( Llb_Mnn_t * p )
         }
         Cudd_Ref( p->ddG->bFunc2 );
         Cudd_RecursiveDeref( p->dd, bNext );
-        p->timeTran1 += clock() - clk3;
+        p->timeTran1 += Abc_Clock() - clk3;
 
         // save permutation
         NumCmp = Llb_NonlinCompPerms( p->dd, p->pOrderL2 );
@@ -571,7 +571,7 @@ int Llb_NonlinReachability( Llb_Mnn_t * p )
         //Extra_TestAndPerm( p->ddG, Cudd_Not(p->ddG->bFunc), p->ddG->bFunc2 );    
 
         // derive new states
-        clk3 = clock();
+        clk3 = Abc_Clock();
         p->ddG->bFunc2 = Cudd_bddAnd( p->ddG, bTemp = p->ddG->bFunc2, Cudd_Not(p->ddG->bFunc) );     
         if ( p->ddG->bFunc2 == NULL )
         {
@@ -584,12 +584,12 @@ int Llb_NonlinReachability( Llb_Mnn_t * p )
         }
         Cudd_Ref( p->ddG->bFunc2 );
         Cudd_RecursiveDeref( p->ddG, bTemp );
-        p->timeGloba += clock() - clk3;
+        p->timeGloba += Abc_Clock() - clk3;
 
         if ( Cudd_IsConstant(p->ddG->bFunc2) )
             break;
         // add to the reached set
-        clk3 = clock();
+        clk3 = Abc_Clock();
         p->ddG->bFunc = Cudd_bddOr( p->ddG, bTemp = p->ddG->bFunc, p->ddG->bFunc2 );                 
         if ( p->ddG->bFunc == NULL )
         {
@@ -602,7 +602,7 @@ int Llb_NonlinReachability( Llb_Mnn_t * p )
         }
         Cudd_Ref( p->ddG->bFunc );
         Cudd_RecursiveDeref( p->ddG, bTemp );
-        p->timeGloba += clock() - clk3;
+        p->timeGloba += Abc_Clock() - clk3;
 
         // reset permutation
 //        RetValue = Cudd_CheckZeroRef( dd );
@@ -610,7 +610,7 @@ int Llb_NonlinReachability( Llb_Mnn_t * p )
 //        Cudd_ShuffleHeap( dd, pOrderG );
 
         // move new states to the working manager
-        clk3 = clock();
+        clk3 = Abc_Clock();
         p->dd->bFunc = Extra_TransferPermute( p->ddG, p->dd, p->ddG->bFunc2, Vec_IntArray(p->vGlo2Cs) ); 
         if ( p->dd->bFunc == NULL )
         {
@@ -621,7 +621,7 @@ int Llb_NonlinReachability( Llb_Mnn_t * p )
             return -1;
         }
         Cudd_Ref( p->dd->bFunc );
-        p->timeTran2 += clock() - clk3;
+        p->timeTran2 += Abc_Clock() - clk3;
 
         // report the results
         if ( p->pPars->fVerbose )
@@ -635,7 +635,7 @@ int Llb_NonlinReachability( Llb_Mnn_t * p )
             printf( "S =%4d ",     nSuppMax );
             printf( "cL =%5d ",    NumCmp );
             printf( "cG =%5d ",    Llb_NonlinCompPerms( p->ddG, p->pOrderG ) );
-            Abc_PrintTime( 1, "T", clock() - clk2 );
+            Abc_PrintTime( 1, "T", Abc_Clock() - clk2 );
             memcpy( p->pOrderG, p->ddG->perm, sizeof(int) * p->ddG->size );
         }
 /*
@@ -680,7 +680,7 @@ int Llb_NonlinReachability( Llb_Mnn_t * p )
     if ( !p->pPars->fSilent )
         printf( "The miter is proved unreachable after %d iterations.  ", nIters );
     p->pPars->iFrame = nIters - 1;
-    Abc_PrintTime( 1, "Time", clock() - clk );
+    Abc_PrintTime( 1, "Time", Abc_Clock() - clk );
     return 1; // unreachable
 }
 
@@ -808,7 +808,7 @@ void Llb_NonlinExperiment( Aig_Man_t * pAig, int Num )
     Llb_Mnn_t * pMnn;
     Gia_ParLlb_t Pars, * pPars = &Pars;
     Aig_Man_t * p;
-    clock_t clk = clock();
+    abctime clk = Abc_Clock();
 
     Llb_ManSetDefaultParams( pPars );
     pPars->fVerbose = 1;
@@ -820,7 +820,7 @@ void Llb_NonlinExperiment( Aig_Man_t * pAig, int Num )
 
     pMnn = Llb_MnnStart( pAig, p, pPars );
     Llb_NonlinReachability( pMnn );
-    pMnn->timeTotal = clock() - clk;
+    pMnn->timeTotal = Abc_Clock() - clk;
     Llb_MnnStop( pMnn );
 
     Aig_ManStop( p );
@@ -852,10 +852,10 @@ int Llb_NonlinCoreReach( Aig_Man_t * pAig, Gia_ParLlb_t * pPars )
 
     if ( !pPars->fSkipReach )
     {
-        clock_t clk = clock();
+        abctime clk = Abc_Clock();
         pMnn = Llb_MnnStart( pAig, p, pPars );
         RetValue = Llb_NonlinReachability( pMnn );
-        pMnn->timeTotal = clock() - clk;
+        pMnn->timeTotal = Abc_Clock() - clk;
         Llb_MnnStop( pMnn );
     }
 
diff --git a/src/proof/llb/llb4Cex.c b/src/proof/llb/llb4Cex.c
index c676b76e..18aeaf04 100644
--- a/src/proof/llb/llb4Cex.c
+++ b/src/proof/llb/llb4Cex.c
@@ -52,7 +52,7 @@ Abc_Cex_t * Llb4_Nonlin4TransformCex( Aig_Man_t * pAig, Vec_Ptr_t * vStates, int
     sat_solver * pSat;
     Aig_Obj_t * pObj;
     unsigned * pNext, * pThis;
-    int i, k, iBit, status, nRegs;//, clk = clock();
+    int i, k, iBit, status, nRegs;//, clk = Abc_Clock();
 /*
     Vec_PtrForEachEntry( unsigned *, vStates, pNext, i )
     {
@@ -187,7 +187,7 @@ Abc_Cex_t * Llb4_Nonlin4TransformCex( Aig_Man_t * pAig, Vec_Ptr_t * vStates, int
     }
     // report the results
 //    if ( fVerbose )
-//       Abc_PrintTime( 1, "SAT-based cex generation time", clock() - clk );
+//       Abc_PrintTime( 1, "SAT-based cex generation time", Abc_Clock() - clk );
     return pCex;
 }
 
diff --git a/src/proof/llb/llb4Image.c b/src/proof/llb/llb4Image.c
index 4ae087b5..2ba4fcfd 100644
--- a/src/proof/llb/llb4Image.c
+++ b/src/proof/llb/llb4Image.c
@@ -77,7 +77,7 @@ static inline Llb_Prt_t * Llb_MgrPart( Llb_Mgr_t * p, int i )  { return p->pPart
     for ( i = 0; (i < Vec_IntSize(pVar->vParts)) && (((pPart) = Llb_MgrPart(p, Vec_IntEntry(pVar->vParts,i))), 1); i++ )
 
 // statistics
-//clock_t timeBuild, timeAndEx, timeOther;
+//abctime timeBuild, timeAndEx, timeOther;
 //int nSuppMax;
 
 ////////////////////////////////////////////////////////////////////////
@@ -140,7 +140,7 @@ DdNode * Llb_Nonlin4CreateCube1( Llb_Mgr_t * p, Llb_Prt_t * pPart )
     DdNode * bCube, * bTemp;
     Llb_Var_t * pVar;
     int i;
-    clock_t TimeStop;
+    abctime TimeStop;
     TimeStop = p->dd->TimeStop; p->dd->TimeStop = 0;
     bCube = Cudd_ReadOne(p->dd);   Cudd_Ref( bCube );
     Llb_PartForEachVar( p, pPart, pVar, i )
@@ -173,7 +173,7 @@ DdNode * Llb_Nonlin4CreateCube2( Llb_Mgr_t * p, Llb_Prt_t * pPart1, Llb_Prt_t *
     DdNode * bCube, * bTemp;
     Llb_Var_t * pVar;
     int i;
-    clock_t TimeStop;
+    abctime TimeStop;
     TimeStop = p->dd->TimeStop; p->dd->TimeStop = 0;
     bCube = Cudd_ReadOne(p->dd);   Cudd_Ref( bCube );
     Llb_PartForEachVar( p, pPart1, pVar, i )
@@ -808,7 +808,7 @@ Vec_Ptr_t * Llb_Nonlin4Group( DdManager * dd, Vec_Ptr_t * vParts, Vec_Int_t * vV
     Vec_Ptr_t * vGroups;
     Llb_Prt_t * pPart, * pPart1, * pPart2;
     Llb_Mgr_t * p;
-    int i, nReorders;//, clk = clock();
+    int i, nReorders;//, clk = Abc_Clock();
     // start the manager
     p = Llb_Nonlin4Alloc( dd, vParts, NULL, vVars2Q, nSizeMax );
     // remove singles
@@ -849,7 +849,7 @@ Vec_Ptr_t * Llb_Nonlin4Group( DdManager * dd, Vec_Ptr_t * vParts, Vec_Int_t * vV
 //Extra_bddPrintSupport( p->dd, pPart->bFunc ); printf( "\n" );
     }
     Llb_Nonlin4Free( p );
-//Abc_PrintTime( 1, "Reparametrization time", clock() - clk );
+//Abc_PrintTime( 1, "Reparametrization time", Abc_Clock() - clk );
     return vGroups;
 }
 
diff --git a/src/proof/llb/llb4Nonlin.c b/src/proof/llb/llb4Nonlin.c
index 51f9d602..6d5826a0 100644
--- a/src/proof/llb/llb4Nonlin.c
+++ b/src/proof/llb/llb4Nonlin.c
@@ -47,11 +47,11 @@ struct Llb_Mnx_t_
     Vec_Int_t *     vOrder;         // for each object ID, its BDD variable number or -1
     Vec_Int_t *     vVars2Q;        // 1 if variable is quantifiable; 0 othervise
 
-    clock_t         timeImage;
-    clock_t         timeRemap;
-    clock_t         timeReo;
-    clock_t         timeOther;
-    clock_t         timeTotal;
+    abctime         timeImage;
+    abctime         timeRemap;
+    abctime         timeReo;
+    abctime         timeOther;
+    abctime         timeTotal;
 };
 
 //extern int timeBuild, timeAndEx, timeOther;
@@ -447,7 +447,7 @@ DdNode * Llb_Nonlin4ComputeInitState( DdManager * dd, Aig_Man_t * pAig, Vec_Int_
     Aig_Obj_t * pObjLi, * pObjLo;
     DdNode * bRes, * bVar, * bTemp;
     int i;
-    clock_t TimeStop;
+    abctime TimeStop;
     TimeStop = dd->TimeStop;  dd->TimeStop = 0;
     bRes = Cudd_ReadOne( dd );   Cudd_Ref( bRes );
     Saig_ManForEachLiLo( pAig, pObjLi, pObjLo, i )
@@ -477,7 +477,7 @@ DdNode * Llb_Nonlin4ComputeCube( DdManager * dd, Aig_Man_t * pAig, Vec_Int_t * v
     Aig_Obj_t * pObjLo, * pObjLi, * pObjTemp;
     DdNode * bRes, * bVar, * bTemp;
     int i;
-    clock_t TimeStop;
+    abctime TimeStop;
     TimeStop = dd->TimeStop;  dd->TimeStop = 0;
     bRes = Cudd_ReadOne( dd );   Cudd_Ref( bRes );
     Saig_ManForEachLiLo( pAig, pObjLi, pObjLo, i )
@@ -579,7 +579,7 @@ Vec_Ptr_t * Llb_Nonlin4DeriveCex( Llb_Mnx_t * p, int fBackward, int fVerbose )
     Vec_Ptr_t * vStates, * vRootsNew;
     Aig_Obj_t * pObj;
     DdNode * bState = NULL, * bImage, * bOneCube, * bRing;
-    int i, v, RetValue;//, clk = clock();
+    int i, v, RetValue;//, clk = Abc_Clock();
     char * pValues;
     assert( Vec_PtrSize(p->vRings) > 0 );
     // disable the timeout
@@ -649,7 +649,7 @@ Vec_Ptr_t * Llb_Nonlin4DeriveCex( Llb_Mnx_t * p, int fBackward, int fVerbose )
     if ( fBackward )
         Vec_PtrReverseOrder( vStates );
 //    if ( fVerbose )
-//        Abc_PrintTime( 1, "BDD-based cex generation time", clock() - clk );
+//        Abc_PrintTime( 1, "BDD-based cex generation time", Abc_Clock() - clk );
     return vStates;
 }
 
@@ -669,7 +669,7 @@ int Llb_Nonlin4Reachability( Llb_Mnx_t * p )
 { 
     DdNode * bAux;
     int nIters, nBddSizeFr = 0, nBddSizeTo = 0, nBddSizeTo2 = 0;
-    clock_t clkTemp, clkIter, clk = clock();
+    abctime clkTemp, clkIter, clk = Abc_Clock();
     assert( Aig_ManRegNum(p->pAig) > 0 );
 
     if ( p->pPars->fBackward )
@@ -736,9 +736,9 @@ int Llb_Nonlin4Reachability( Llb_Mnx_t * p )
     p->bReached = p->bCurrent; Cudd_Ref( p->bReached );
     for ( nIters = 0; nIters < p->pPars->nIterMax; nIters++ )
     { 
-        clkIter = clock();
+        clkIter = Abc_Clock();
         // check the runtime limit
-        if ( p->pPars->TimeLimit && clock() > p->pPars->TimeTarget )
+        if ( p->pPars->TimeLimit && Abc_Clock() > p->pPars->TimeTarget )
         {
             if ( !p->pPars->fSilent )
                 printf( "Reached timeout (%d seconds) during image computation.\n",  p->pPars->TimeLimit );
@@ -760,14 +760,14 @@ int Llb_Nonlin4Reachability( Llb_Mnx_t * p )
             if ( !p->pPars->fSilent )
             {
                 Abc_Print( 1, "Output %d of miter \"%s\" was asserted in frame %d.  ", p->pAig->pSeqModel->iPo, p->pAig->pName, nIters );
-                Abc_PrintTime( 1, "Time", clock() - clk );
+                Abc_PrintTime( 1, "Time", Abc_Clock() - clk );
             }
             p->pPars->iFrame = nIters - 1;
             return 0;
         }
 
         // compute the next states
-        clkTemp = clock();
+        clkTemp = Abc_Clock();
         p->bNext = Llb_Nonlin4Image( p->dd, p->vRoots, p->bCurrent, p->vVars2Q );
         if ( p->bNext == NULL )
         {
@@ -777,10 +777,10 @@ int Llb_Nonlin4Reachability( Llb_Mnx_t * p )
             return -1;
         }
         Cudd_Ref( p->bNext );
-        p->timeImage += clock() - clkTemp;
+        p->timeImage += Abc_Clock() - clkTemp;
 
         // remap into current states
-        clkTemp = clock();
+        clkTemp = Abc_Clock();
         p->bNext = Cudd_bddVarMap( p->dd, bAux = p->bNext );
         if ( p->bNext == NULL )
         {
@@ -792,7 +792,7 @@ int Llb_Nonlin4Reachability( Llb_Mnx_t * p )
         }
         Cudd_Ref( p->bNext );
         Cudd_RecursiveDeref( p->dd, bAux );
-        p->timeRemap += clock() - clkTemp;
+        p->timeRemap += Abc_Clock() - clkTemp;
 
         // collect statistics
         if ( p->pPars->fVerbose )
@@ -847,7 +847,7 @@ printf( "Before = %d.  After = %d.\n", Cudd_DagSize(bAux), Cudd_DagSize(p->bCurr
             printf( "ImCs =%7d  ", nBddSizeTo2 );
             printf( "Rea =%7d   ", Cudd_DagSize(p->bReached) );
             printf( "(%4d %4d)  ", Cudd_ReadReorderings(p->dd), Cudd_ReadGarbageCollections(p->dd) );
-            Abc_PrintTime( 1, "T", clock() - clkIter );
+            Abc_PrintTime( 1, "T", Abc_Clock() - clkIter );
         }
 /*
         if ( pPars->fVerbose )
@@ -889,7 +889,7 @@ printf( "Before = %d.  After = %d.\n", Cudd_DagSize(bAux), Cudd_DagSize(p->bCurr
     if ( !p->pPars->fSilent )
         printf( "The miter is proved unreachable after %d iterations.  ", nIters );
     p->pPars->iFrame = nIters - 1;
-    Abc_PrintTime( 1, "Time", clock() - clk );
+    Abc_PrintTime( 1, "Time", Abc_Clock() - clk );
     return 1; // unreachable
 }
 
@@ -906,7 +906,7 @@ printf( "Before = %d.  After = %d.\n", Cudd_DagSize(bAux), Cudd_DagSize(p->bCurr
 ***********************************************************************/
 void Llb_Nonlin4Reorder( DdManager * dd, int fTwice, int fVerbose )
 {
-    clock_t clk = clock();
+    abctime clk = Abc_Clock();
     if ( fVerbose )
         Abc_Print( 1, "Reordering... Before =%5d. ", Cudd_ReadKeys(dd) - Cudd_ReadDead(dd) );
     Cudd_ReduceHeap( dd, CUDD_REORDER_SYMM_SIFT, 100 );
@@ -919,7 +919,7 @@ void Llb_Nonlin4Reorder( DdManager * dd, int fTwice, int fVerbose )
             Abc_Print( 1, "After =%5d. ", Cudd_ReadKeys(dd) - Cudd_ReadDead(dd) );
     }
     if ( fVerbose )
-        Abc_PrintTime( 1, "Time", clock() - clk );
+        Abc_PrintTime( 1, "Time", Abc_Clock() - clk );
 }
  
 /**Function*************************************************************
@@ -942,7 +942,7 @@ Llb_Mnx_t * Llb_MnxStart( Aig_Man_t * pAig, Gia_ParLlb_t * pPars )
     p->pPars   = pPars;
 
     // compute time to stop
-    p->pPars->TimeTarget = p->pPars->TimeLimit ? p->pPars->TimeLimit * CLOCKS_PER_SEC + clock(): 0;
+    p->pPars->TimeTarget = p->pPars->TimeLimit ? p->pPars->TimeLimit * CLOCKS_PER_SEC + Abc_Clock(): 0;
 
     if ( pPars->fCluster )
     {
@@ -1073,12 +1073,12 @@ int Llb_Nonlin4CoreReach( Aig_Man_t * pAig, Gia_ParLlb_t * pPars )
         return RetValue;
     }
     {
-        clock_t clk = clock();
+        abctime clk = Abc_Clock();
         pMnn = Llb_MnxStart( pAig, pPars );
 //Llb_MnxCheckNextStateVars( pMnn );
         if ( !pPars->fSkipReach )
             RetValue = Llb_Nonlin4Reachability( pMnn );
-        pMnn->timeTotal = clock() - clk;
+        pMnn->timeTotal = Abc_Clock() - clk;
         Llb_MnxStop( pMnn );
     }
     return RetValue;
diff --git a/src/proof/llb/llb4Sweep.c b/src/proof/llb/llb4Sweep.c
index 709bd61a..6b318572 100644
--- a/src/proof/llb/llb4Sweep.c
+++ b/src/proof/llb/llb4Sweep.c
@@ -287,7 +287,7 @@ DdNode * Llb4_Nonlin4SweepBadMonitor( Aig_Man_t * pAig, Vec_Int_t * vOrder, DdMa
     Aig_Obj_t * pObj;
     DdNode * bRes, * bVar, * bTemp;
     int i;
-    clock_t TimeStop;
+    abctime TimeStop;
     TimeStop = dd->TimeStop;  dd->TimeStop = 0;
     bRes = Cudd_ReadOne( dd );   Cudd_Ref( bRes );
     Saig_ManForEachPo( pAig, pObj, i )
diff --git a/src/proof/llb/llbInt.h b/src/proof/llb/llbInt.h
index 208d291c..0c53c01f 100644
--- a/src/proof/llb/llbInt.h
+++ b/src/proof/llb/llbInt.h
@@ -152,28 +152,28 @@ extern int             Llb_ManReachability( Llb_Man_t * p, Vec_Int_t * vHints, D
 extern void            Llb_MtrSchedule( Llb_Mtr_t * p );
 
 /*=== llb2Bad.c ======================================================*/
-extern DdNode *        Llb_BddComputeBad( Aig_Man_t * pInit, DdManager * dd, clock_t TimeOut );
+extern DdNode *        Llb_BddComputeBad( Aig_Man_t * pInit, DdManager * dd, abctime TimeOut );
 extern DdNode *        Llb_BddQuantifyPis( Aig_Man_t * pInit, DdManager * dd, DdNode * bFunc );
 /*=== llb2Core.c ======================================================*/
 extern DdNode *        Llb_CoreComputeCube( DdManager * dd, Vec_Int_t * vVars, int fUseVarIndex, char * pValues );
-extern int             Llb_CoreExperiment( Aig_Man_t * pInit, Aig_Man_t * pAig, Gia_ParLlb_t * pPars, Vec_Ptr_t * vResult, clock_t TimeTarget ); 
+extern int             Llb_CoreExperiment( Aig_Man_t * pInit, Aig_Man_t * pAig, Gia_ParLlb_t * pPars, Vec_Ptr_t * vResult, abctime TimeTarget ); 
 /*=== llb2Driver.c ======================================================*/
 extern Vec_Int_t *     Llb_DriverCountRefs( Aig_Man_t * p );
 extern Vec_Int_t *     Llb_DriverCollectNs( Aig_Man_t * pAig, Vec_Int_t * vDriRefs );
 extern Vec_Int_t *     Llb_DriverCollectCs( Aig_Man_t * pAig );
 extern DdNode *        Llb_DriverPhaseCube( Aig_Man_t * pAig, Vec_Int_t * vDriRefs, DdManager * dd );
-extern DdManager *     Llb_DriverLastPartition( Aig_Man_t * p, Vec_Int_t * vVarsNs, clock_t TimeTarget );
+extern DdManager *     Llb_DriverLastPartition( Aig_Man_t * p, Vec_Int_t * vVarsNs, abctime TimeTarget );
 /*=== llb2Image.c ======================================================*/
 extern Vec_Ptr_t *     Llb_ImgSupports( Aig_Man_t * p, Vec_Ptr_t * vDdMans, Vec_Int_t * vStart, Vec_Int_t * vStop, int fAddPis, int fVerbose );
 extern void            Llb_ImgSchedule( Vec_Ptr_t * vSupps, Vec_Ptr_t ** pvQuant0, Vec_Ptr_t ** pvQuant1, int fVerbose );
-extern DdManager *     Llb_ImgPartition( Aig_Man_t * p, Vec_Ptr_t * vLower, Vec_Ptr_t * vUpper, clock_t TimeTarget );
+extern DdManager *     Llb_ImgPartition( Aig_Man_t * p, Vec_Ptr_t * vLower, Vec_Ptr_t * vUpper, abctime TimeTarget );
 extern void            Llb_ImgQuantifyFirst( Aig_Man_t * pAig, Vec_Ptr_t * vDdMans, Vec_Ptr_t * vQuant0, int fVerbose );
 extern void            Llb_ImgQuantifyReset( Vec_Ptr_t * vDdMans );
 extern DdNode *        Llb_ImgComputeImage( Aig_Man_t * pAig, Vec_Ptr_t * vDdMans, DdManager * dd, DdNode * bInit, 
                            Vec_Ptr_t * vQuant0, Vec_Ptr_t * vQuant1, Vec_Int_t * vDriRefs, 
-                           clock_t TimeTarget, int fBackward, int fReorder, int fVerbose );
+                           abctime TimeTarget, int fBackward, int fReorder, int fVerbose );
 
-extern DdManager *     Llb_NonlinImageStart( Aig_Man_t * pAig, Vec_Ptr_t * vLeaves, Vec_Ptr_t * vRoots, int * pVars2Q, int * pOrder, int fFirst, clock_t TimeTarget );
+extern DdManager *     Llb_NonlinImageStart( Aig_Man_t * pAig, Vec_Ptr_t * vLeaves, Vec_Ptr_t * vRoots, int * pVars2Q, int * pOrder, int fFirst, abctime TimeTarget );
 extern DdNode *        Llb_NonlinImageCompute( DdNode * bCurrent, int fReorder, int fDrop, int fVerbose, int * pOrder );
 extern void            Llb_NonlinImageQuit();
 
diff --git a/src/proof/pdr/pdr.h b/src/proof/pdr/pdr.h
index 10d2af3b..f32fe0b3 100644
--- a/src/proof/pdr/pdr.h
+++ b/src/proof/pdr/pdr.h
@@ -66,7 +66,7 @@ struct Pdr_Par_t_
     int RunId;            // PDR id in this run 
     int(*pFuncStop)(int); // callback to terminate
     int(*pFuncOnFail)(int,Abc_Cex_t*); // called for a failed output in MO mode
-    clock_t timeLastSolved; // the time when the last output was solved
+    abctime timeLastSolved; // the time when the last output was solved
     Vec_Int_t * vOutMap;  // in the multi-output mode, contains status for each PO (0 = sat; 1 = unsat; negative = undecided)
 };
 
diff --git a/src/proof/pdr/pdrCore.c b/src/proof/pdr/pdrCore.c
index 987a1a3e..7cd60d9e 100644
--- a/src/proof/pdr/pdrCore.c
+++ b/src/proof/pdr/pdrCore.c
@@ -135,7 +135,7 @@ int Pdr_ManPushClauses( Pdr_Man_t * p )
     Vec_Ptr_t * vArrayK, * vArrayK1;
     int i, j, k, m, RetValue = 0, RetValue2, kMax = Vec_PtrSize(p->vSolvers)-1;
     int Counter = 0;
-    clock_t clk = clock();
+    abctime clk = Abc_Clock();
     Vec_VecForEachLevelStartStop( p->vClauses, vArrayK, k, 1, kMax )
     {
         Vec_PtrSort( vArrayK, (int (*)(void))Pdr_SetCompare );
@@ -218,7 +218,7 @@ int Pdr_ManPushClauses( Pdr_Man_t * p )
             m--;
         }
     }
-    p->tPush += clock() - clk;
+    p->tPush += Abc_Clock() - clk;
     return RetValue;
 }
 
@@ -300,7 +300,7 @@ int Pdr_ManGeneralize( Pdr_Man_t * p, int k, Pdr_Set_t * pCube, Pdr_Set_t ** ppP
 {
     Pdr_Set_t * pCubeMin, * pCubeTmp = NULL;
     int i, j, n, Lit, RetValue;
-    clock_t clk = clock();
+    abctime clk = Abc_Clock();
     int * pOrder;
     // if there is no induction, return
     *ppCubeMin = NULL;
@@ -309,7 +309,7 @@ int Pdr_ManGeneralize( Pdr_Man_t * p, int k, Pdr_Set_t * pCube, Pdr_Set_t ** ppP
         return -1;
     if ( RetValue == 0 )
     {
-        p->tGeneral += clock() - clk;
+        p->tGeneral += Abc_Clock() - clk;
         return 0;
     }
 
@@ -403,7 +403,7 @@ int Pdr_ManGeneralize( Pdr_Man_t * p, int k, Pdr_Set_t * pCube, Pdr_Set_t ** ppP
 
     assert( ppCubeMin != NULL );
     *ppCubeMin = pCubeMin;
-    p->tGeneral += clock() - clk;
+    p->tGeneral += Abc_Clock() - clk;
     return 1;
 }
 
@@ -424,7 +424,7 @@ int Pdr_ManBlockCube( Pdr_Man_t * p, Pdr_Set_t * pCube )
     Pdr_Set_t * pPred, * pCubeMin;
     int i, k, RetValue, Prio = ABC_INFINITY, Counter = 0;
     int kMax = Vec_PtrSize(p->vSolvers)-1;
-    clock_t clk;
+    abctime clk;
     p->nBlocks++;
     // create first proof obligation
     assert( p->pQueue == NULL );
@@ -447,14 +447,14 @@ int Pdr_ManBlockCube( Pdr_Man_t * p, Pdr_Set_t * pCube )
         assert( pThis->iFrame > 0 );
         assert( !Pdr_SetIsInit(pThis->pState, -1) );
 
-        clk = clock();
+        clk = Abc_Clock();
         if ( Pdr_ManCheckContainment( p, pThis->iFrame, pThis->pState ) )
         {
-            p->tContain += clock() - clk;
+            p->tContain += Abc_Clock() - clk;
             Pdr_OblDeref( pThis );
             continue;
         }
-        p->tContain += clock() - clk;
+        p->tContain += Abc_Clock() - clk;
 
         // check if the cube is already contained
         RetValue = Pdr_ManCheckCubeCs( p, pThis->iFrame, pThis->pState );
@@ -536,11 +536,11 @@ int Pdr_ManBlockCube( Pdr_Man_t * p, Pdr_Set_t * pCube )
         // check termination
         if ( p->pPars->pFuncStop && p->pPars->pFuncStop(p->pPars->RunId) )
             return -1;
-        if ( p->timeToStop && clock() > p->timeToStop )
+        if ( p->timeToStop && Abc_Clock() > p->timeToStop )
             return -1;
-        if ( p->timeToStopOne && clock() > p->timeToStopOne )
+        if ( p->timeToStopOne && Abc_Clock() > p->timeToStopOne )
             return -1;
-        if ( p->pPars->nTimeOutGap && p->pPars->timeLastSolved && clock() > p->pPars->timeLastSolved + p->pPars->nTimeOutGap * CLOCKS_PER_SEC )
+        if ( p->pPars->nTimeOutGap && p->pPars->timeLastSolved && Abc_Clock() > p->pPars->timeLastSolved + p->pPars->nTimeOutGap * CLOCKS_PER_SEC )
             return -1;
     }
     return 1;
@@ -564,11 +564,11 @@ int Pdr_ManSolveInt( Pdr_Man_t * p )
     Aig_Obj_t * pObj;
     int k, RetValue = -1;
     int nOutDigits = Abc_Base10Log( Saig_ManPoNum(p->pAig) );
-    clock_t clkStart = clock(), clkOne = 0;
-    p->timeToStop = p->pPars->nTimeOut ? p->pPars->nTimeOut * CLOCKS_PER_SEC + clock(): 0;
+    abctime clkStart = Abc_Clock(), clkOne = 0;
+    p->timeToStop = p->pPars->nTimeOut ? p->pPars->nTimeOut * CLOCKS_PER_SEC + Abc_Clock(): 0;
     assert( Vec_PtrSize(p->vSolvers) == 0 );
     // create the first timeframe
-    p->pPars->timeLastSolved = clock();
+    p->pPars->timeLastSolved = Abc_Clock();
     Pdr_ManCreateSolver( p, (k = 0) );
     while ( 1 )
     {
@@ -604,7 +604,7 @@ int Pdr_ManSolveInt( Pdr_Man_t * p )
                 if ( p->pPars->pFuncOnFail && p->pPars->pFuncOnFail(p->iOutCur, p->pPars->fStoreCex ? (Abc_Cex_t *)Vec_PtrEntry(p->vCexes, p->iOutCur) : NULL) )
                 {
                     if ( p->pPars->fVerbose ) 
-                        Pdr_ManPrintProgress( p, 1, clock() - clkStart );
+                        Pdr_ManPrintProgress( p, 1, Abc_Clock() - clkStart );
                     if ( !p->pPars->fSilent )
                         Abc_Print( 1, "Quitting due to callback on fail.\n" );
                     p->pPars->iFrame = k;
@@ -612,22 +612,22 @@ int Pdr_ManSolveInt( Pdr_Man_t * p )
                 }
                 if ( p->pPars->nFailOuts + p->pPars->nDropOuts == Saig_ManPoNum(p->pAig) )
                     return p->pPars->nFailOuts ? 0 : -1; // SAT or UNDEC
-                p->pPars->timeLastSolved = clock();
+                p->pPars->timeLastSolved = Abc_Clock();
                 continue;
             } 
             // try to solve this output
             if ( p->pTime4Outs )
             {
                 assert( p->pTime4Outs[p->iOutCur] > 0 );
-                clkOne = clock();
-                p->timeToStopOne = p->pTime4Outs[p->iOutCur] + clock();
+                clkOne = Abc_Clock();
+                p->timeToStopOne = p->pTime4Outs[p->iOutCur] + Abc_Clock();
             }
             while ( 1 )
             {
-                if ( p->pPars->nTimeOutGap && p->pPars->timeLastSolved && clock() > p->pPars->timeLastSolved + p->pPars->nTimeOutGap * CLOCKS_PER_SEC )
+                if ( p->pPars->nTimeOutGap && p->pPars->timeLastSolved && Abc_Clock() > p->pPars->timeLastSolved + p->pPars->nTimeOutGap * CLOCKS_PER_SEC )
                 {
                     if ( p->pPars->fVerbose ) 
-                        Pdr_ManPrintProgress( p, 1, clock() - clkStart );
+                        Pdr_ManPrintProgress( p, 1, Abc_Clock() - clkStart );
                     if ( !p->pPars->fSilent )
                         Abc_Print( 1, "Reached gap timeout (%d seconds).\n",  p->pPars->nTimeOutGap );
                     p->pPars->iFrame = k;
@@ -639,7 +639,7 @@ int Pdr_ManSolveInt( Pdr_Man_t * p )
                 if ( RetValue == -1 )
                 {
                     if ( p->pPars->fVerbose ) 
-                        Pdr_ManPrintProgress( p, 1, clock() - clkStart );
+                        Pdr_ManPrintProgress( p, 1, Abc_Clock() - clkStart );
                     if ( p->pPars->nConfLimit )
                         Abc_Print( 1, "Reached conflict limit (%d).\n",  p->pPars->nConfLimit );
                     else if ( p->pPars->fVerbose ) 
@@ -653,14 +653,14 @@ int Pdr_ManSolveInt( Pdr_Man_t * p )
                     if ( RetValue == -1 )
                     {
                         if ( p->pPars->fVerbose ) 
-                            Pdr_ManPrintProgress( p, 1, clock() - clkStart );
+                            Pdr_ManPrintProgress( p, 1, Abc_Clock() - clkStart );
                         if ( p->pPars->nConfLimit )
                             Abc_Print( 1, "Reached conflict limit (%d).\n",  p->pPars->nConfLimit );
-                        else if ( p->timeToStop && clock() > p->timeToStop )
+                        else if ( p->timeToStop && Abc_Clock() > p->timeToStop )
                             Abc_Print( 1, "Reached timeout (%d seconds).\n",  p->pPars->nTimeOut );
-                        else if ( p->pPars->nTimeOutGap && p->pPars->timeLastSolved && clock() > p->pPars->timeLastSolved + p->pPars->nTimeOutGap * CLOCKS_PER_SEC )
+                        else if ( p->pPars->nTimeOutGap && p->pPars->timeLastSolved && Abc_Clock() > p->pPars->timeLastSolved + p->pPars->nTimeOutGap * CLOCKS_PER_SEC )
                             Abc_Print( 1, "Reached gap timeout (%d seconds).\n",  p->pPars->nTimeOutGap );
-                        else if ( p->timeToStopOne && clock() > p->timeToStopOne )
+                        else if ( p->timeToStopOne && Abc_Clock() > p->timeToStopOne )
                         {
                             Pdr_QueueClean( p );
                             pCube = NULL;
@@ -679,7 +679,7 @@ int Pdr_ManSolveInt( Pdr_Man_t * p )
                             Pdr_ManPrintClauses( p, 0 );
                         }
                         if ( p->pPars->fVerbose ) 
-                            Pdr_ManPrintProgress( p, !p->pPars->fSolveAll, clock() - clkStart );
+                            Pdr_ManPrintProgress( p, !p->pPars->fSolveAll, Abc_Clock() - clkStart );
                         p->pPars->iFrame = k;
 
                         if ( !p->pPars->fSolveAll )
@@ -696,7 +696,7 @@ int Pdr_ManSolveInt( Pdr_Man_t * p )
                         if ( p->pPars->pFuncOnFail && p->pPars->pFuncOnFail(p->iOutCur, p->pPars->fStoreCex ? (Abc_Cex_t *)Vec_PtrEntry(p->vCexes, p->iOutCur) : NULL) )
                         {
                             if ( p->pPars->fVerbose ) 
-                                Pdr_ManPrintProgress( p, 1, clock() - clkStart );
+                                Pdr_ManPrintProgress( p, 1, Abc_Clock() - clkStart );
                             if ( !p->pPars->fSilent )
                                 Abc_Print( 1, "Quitting due to callback on fail.\n" );
                             p->pPars->iFrame = k;
@@ -712,12 +712,12 @@ int Pdr_ManSolveInt( Pdr_Man_t * p )
                         break; // keep solving
                     }
                     if ( p->pPars->fVerbose ) 
-                        Pdr_ManPrintProgress( p, 0, clock() - clkStart );
+                        Pdr_ManPrintProgress( p, 0, Abc_Clock() - clkStart );
                 }
             } 
             if ( p->pTime4Outs )
             {
-                clock_t timeSince = clock() - clkOne;
+                abctime timeSince = Abc_Clock() - clkOne;
                 assert( p->pTime4Outs[p->iOutCur] > 0 );
                 p->pTime4Outs[p->iOutCur] = (p->pTime4Outs[p->iOutCur] > timeSince) ? p->pTime4Outs[p->iOutCur] - timeSince : 0;
                 if ( p->pTime4Outs[p->iOutCur] == 0 && p->vCexes && Vec_PtrEntry(p->vCexes, p->iOutCur) == NULL )
@@ -730,7 +730,7 @@ int Pdr_ManSolveInt( Pdr_Man_t * p )
         }
 
         if ( p->pPars->fVerbose ) 
-            Pdr_ManPrintProgress( p, 1, clock() - clkStart );
+            Pdr_ManPrintProgress( p, 1, Abc_Clock() - clkStart );
         // open a new timeframe
         p->nQueLim = p->pPars->nRestLimit;
         assert( pCube == NULL );
@@ -746,10 +746,10 @@ int Pdr_ManSolveInt( Pdr_Man_t * p )
         if ( RetValue == -1 )
         {
             if ( p->pPars->fVerbose ) 
-                Pdr_ManPrintProgress( p, 1, clock() - clkStart );
+                Pdr_ManPrintProgress( p, 1, Abc_Clock() - clkStart );
             if ( !p->pPars->fSilent )
             {
-                if ( p->timeToStop && clock() > p->timeToStop )
+                if ( p->timeToStop && Abc_Clock() > p->timeToStop )
                     Abc_Print( 1, "Reached timeout (%d seconds).\n",  p->pPars->nTimeOut );
                 else
                     Abc_Print( 1, "Reached conflict limit (%d).\n",  p->pPars->nConfLimit );
@@ -760,7 +760,7 @@ int Pdr_ManSolveInt( Pdr_Man_t * p )
         if ( RetValue )
         {
             if ( p->pPars->fVerbose ) 
-                Pdr_ManPrintProgress( p, 1, clock() - clkStart );
+                Pdr_ManPrintProgress( p, 1, Abc_Clock() - clkStart );
             if ( !p->pPars->fSilent )
                 Pdr_ManReportInvariant( p );
             if ( !p->pPars->fSilent )
@@ -776,7 +776,7 @@ int Pdr_ManSolveInt( Pdr_Man_t * p )
             return p->vCexes ? 0 : 1; // UNSAT
         }
         if ( p->pPars->fVerbose ) 
-            Pdr_ManPrintProgress( p, 0, clock() - clkStart );
+            Pdr_ManPrintProgress( p, 0, Abc_Clock() - clkStart );
 
         // check termination
         if ( p->pPars->pFuncStop && p->pPars->pFuncStop(p->pPars->RunId) )
@@ -784,7 +784,7 @@ int Pdr_ManSolveInt( Pdr_Man_t * p )
             p->pPars->iFrame = k;
             return -1;
         }
-        if ( p->timeToStop && clock() > p->timeToStop )
+        if ( p->timeToStop && Abc_Clock() > p->timeToStop )
         {
             if ( fPrintClauses )
             {
@@ -792,13 +792,13 @@ int Pdr_ManSolveInt( Pdr_Man_t * p )
                 Pdr_ManPrintClauses( p, 0 );
             }
             if ( p->pPars->fVerbose ) 
-                Pdr_ManPrintProgress( p, 1, clock() - clkStart );
+                Pdr_ManPrintProgress( p, 1, Abc_Clock() - clkStart );
             if ( !p->pPars->fSilent )
                 Abc_Print( 1, "Reached timeout (%d seconds).\n",  p->pPars->nTimeOut );
             p->pPars->iFrame = k;
             return -1;
         }
-        if ( p->pPars->nTimeOutGap && p->pPars->timeLastSolved && clock() > p->pPars->timeLastSolved + p->pPars->nTimeOutGap * CLOCKS_PER_SEC )
+        if ( p->pPars->nTimeOutGap && p->pPars->timeLastSolved && Abc_Clock() > p->pPars->timeLastSolved + p->pPars->nTimeOutGap * CLOCKS_PER_SEC )
         {
             if ( fPrintClauses )
             {
@@ -806,7 +806,7 @@ int Pdr_ManSolveInt( Pdr_Man_t * p )
                 Pdr_ManPrintClauses( p, 0 );
             }
             if ( p->pPars->fVerbose ) 
-                Pdr_ManPrintProgress( p, 1, clock() - clkStart );
+                Pdr_ManPrintProgress( p, 1, Abc_Clock() - clkStart );
             if ( !p->pPars->fSilent )
                 Abc_Print( 1, "Reached gap timeout (%d seconds).\n",  p->pPars->nTimeOutGap );
             p->pPars->iFrame = k;
@@ -815,7 +815,7 @@ int Pdr_ManSolveInt( Pdr_Man_t * p )
         if ( p->pPars->nFrameMax && k >= p->pPars->nFrameMax )
         {
             if ( p->pPars->fVerbose ) 
-                Pdr_ManPrintProgress( p, 1, clock() - clkStart );
+                Pdr_ManPrintProgress( p, 1, Abc_Clock() - clkStart );
             if ( !p->pPars->fSilent )
                 Abc_Print( 1, "Reached limit on the number of timeframes (%d).\n", p->pPars->nFrameMax );
             p->pPars->iFrame = k;
@@ -841,7 +841,7 @@ int Pdr_ManSolve( Aig_Man_t * pAig, Pdr_Par_t * pPars )
 {
     Pdr_Man_t * p;
     int k, RetValue;
-    clock_t clk = clock();
+    abctime clk = Abc_Clock();
     if ( pPars->nTimeOutOne )
         pPars->nTimeOut = pPars->nTimeOutOne * Saig_ManPoNum(pAig) / 1000 + 1;
     if ( pPars->nTimeOutOne && !pPars->fSolveAll )
@@ -872,7 +872,7 @@ int Pdr_ManSolve( Aig_Man_t * pAig, Pdr_Par_t * pPars )
     }
     if ( p->pPars->fDumpInv )
         Pdr_ManDumpClauses( p, (char *)"inv.pla", RetValue==1 );
-    p->tTotal += clock() - clk;
+    p->tTotal += Abc_Clock() - clk;
     Pdr_ManStop( p );
     pPars->iFrame--;
     // convert all -2 (unknown) entries into -1 (undec)
diff --git a/src/proof/pdr/pdrInt.h b/src/proof/pdr/pdrInt.h
index 3f74dd5f..72393077 100644
--- a/src/proof/pdr/pdrInt.h
+++ b/src/proof/pdr/pdrInt.h
@@ -97,7 +97,7 @@ struct Pdr_Man_t_
     Vec_Int_t * vRes;      // final result
     Vec_Int_t * vSuppLits; // support literals
     Pdr_Set_t * pCubeJust; // justification
-    clock_t *   pTime4Outs;// timeout per output
+    abctime *   pTime4Outs;// timeout per output
     // statistics
     int         nBlocks;   // the number of times blockState was called
     int         nObligs;   // the number of proof obligations derived
@@ -115,18 +115,18 @@ struct Pdr_Man_t_
     int         nQueMax;
     int         nQueLim;
     // runtime
-    time_t      timeToStop;
-    time_t      timeToStopOne;
+    abctime     timeToStop;
+    abctime     timeToStopOne;
     // time stats
-    clock_t     tSat;
-    clock_t     tSatSat;
-    clock_t     tSatUnsat;
-    clock_t     tGeneral;
-    clock_t     tPush;
-    clock_t     tTsim;
-    clock_t     tContain;
-    clock_t     tCnf;
-    clock_t     tTotal;
+    abctime     tSat;
+    abctime     tSatSat;
+    abctime     tSatUnsat;
+    abctime     tGeneral;
+    abctime     tPush;
+    abctime     tTsim;
+    abctime     tContain;
+    abctime     tCnf;
+    abctime     tTotal;
 };
 
 ////////////////////////////////////////////////////////////////////////
@@ -135,7 +135,7 @@ struct Pdr_Man_t_
 
 static inline sat_solver * Pdr_ManSolver( Pdr_Man_t * p, int k )  { return (sat_solver *)Vec_PtrEntry(p->vSolvers, k); }
 
-static inline clock_t      Pdr_ManTimeLimit( Pdr_Man_t * p )
+static inline abctime      Pdr_ManTimeLimit( Pdr_Man_t * p )
 {
     if ( p->timeToStop == 0 )
         return p->timeToStopOne;
@@ -160,7 +160,7 @@ extern sat_solver *    Pdr_ManNewSolver( sat_solver * pSat, Pdr_Man_t * p, int k
 /*=== pdrCore.c ==========================================================*/
 extern int             Pdr_ManCheckContainment( Pdr_Man_t * p, int k, Pdr_Set_t * pSet );
 /*=== pdrInv.c ==========================================================*/
-extern void            Pdr_ManPrintProgress( Pdr_Man_t * p, int fClose, clock_t Time );
+extern void            Pdr_ManPrintProgress( Pdr_Man_t * p, int fClose, abctime Time );
 extern void            Pdr_ManPrintClauses( Pdr_Man_t * p, int kStart );
 extern void            Pdr_ManDumpClauses( Pdr_Man_t * p, char * pFileName, int fProved );
 extern void            Pdr_ManReportInvariant( Pdr_Man_t * p );
diff --git a/src/proof/pdr/pdrInv.c b/src/proof/pdr/pdrInv.c
index bb8d110d..b1bff676 100644
--- a/src/proof/pdr/pdrInv.c
+++ b/src/proof/pdr/pdrInv.c
@@ -44,7 +44,7 @@ ABC_NAMESPACE_IMPL_START
   SeeAlso     []
 
 ***********************************************************************/
-void Pdr_ManPrintProgress( Pdr_Man_t * p, int fClose, clock_t Time )
+void Pdr_ManPrintProgress( Pdr_Man_t * p, int fClose, abctime Time )
 {
     Vec_Ptr_t * vVec;
     int i, ThisSize, Length, LengthStart;
@@ -328,7 +328,7 @@ void Pdr_ManVerifyInvariant( Pdr_Man_t * p )
     Vec_Ptr_t * vCubes;
     Pdr_Set_t * pCube;
     int i, kStart, kThis, RetValue, Counter = 0;
-    clock_t clk = clock();
+    abctime clk = Abc_Clock();
     // collect cubes used in the inductive invariant
     kStart = Pdr_ManFindInvariantStart( p );
     vCubes = Pdr_ManCollectCubes( p, kStart );
@@ -361,7 +361,7 @@ void Pdr_ManVerifyInvariant( Pdr_Man_t * p )
     else
     {
         Abc_Print( 1, "Verification of invariant with %d clauses was successful.  ", Vec_PtrSize(vCubes) );
-        Abc_PrintTime( 1, "Time", clock() - clk );
+        Abc_PrintTime( 1, "Time", Abc_Clock() - clk );
     }
 //    sat_solver_delete( pSat );
     Vec_PtrFree( vCubes );
diff --git a/src/proof/pdr/pdrMan.c b/src/proof/pdr/pdrMan.c
index 36a62029..c5380147 100644
--- a/src/proof/pdr/pdrMan.c
+++ b/src/proof/pdr/pdrMan.c
@@ -77,7 +77,7 @@ Pdr_Man_t * Pdr_ManStart( Aig_Man_t * pAig, Pdr_Par_t * pPars, Vec_Int_t * vPrio
     if ( pPars->nTimeOutOne )
     {
         int i;
-        p->pTime4Outs = ABC_ALLOC( clock_t, Saig_ManPoNum(pAig) );
+        p->pTime4Outs = ABC_ALLOC( abctime, Saig_ManPoNum(pAig) );
         for ( i = 0; i < Saig_ManPoNum(pAig); i++ )
             p->pTime4Outs[i] = pPars->nTimeOutOne * CLOCKS_PER_SEC / 1000 + 1;
     }
diff --git a/src/proof/pdr/pdrSat.c b/src/proof/pdr/pdrSat.c
index c9028c24..663a0e2f 100644
--- a/src/proof/pdr/pdrSat.c
+++ b/src/proof/pdr/pdrSat.c
@@ -144,7 +144,7 @@ Vec_Int_t * Pdr_ManCubeToLits( Pdr_Man_t * p, int k, Pdr_Set_t * pCube, int fCom
 {
     Aig_Obj_t * pObj;
     int i, iVar, iVarMax = 0;
-    clock_t clk = clock();
+    abctime clk = Abc_Clock();
     Vec_IntClear( p->vLits );
     for ( i = 0; i < pCube->nLits; i++ )
     {
@@ -159,7 +159,7 @@ Vec_Int_t * Pdr_ManCubeToLits( Pdr_Man_t * p, int k, Pdr_Set_t * pCube, int fCom
         Vec_IntPush( p->vLits, toLitCond( iVar, fCompl ^ lit_sign(pCube->Lits[i]) ) );
     }
 //    sat_solver_setnvars( Pdr_ManSolver(p, k), iVarMax + 1 );
-    p->tCnf += clock() - clk;
+    p->tCnf += Abc_Clock() - clk;
     return p->vLits;
 }
 
@@ -256,7 +256,7 @@ int Pdr_ManCheckCubeCs( Pdr_Man_t * p, int k, Pdr_Set_t * pCube )
 { 
     sat_solver * pSat;
     Vec_Int_t * vLits;
-    clock_t Limit;
+    abctime Limit;
     int RetValue;
     pSat = Pdr_ManFetchSolver( p, k );
     vLits = Pdr_ManCubeToLits( p, k, pCube, 0, 0 );
@@ -287,12 +287,12 @@ int Pdr_ManCheckCube( Pdr_Man_t * p, int k, Pdr_Set_t * pCube, Pdr_Set_t ** ppPr
     sat_solver * pSat;
     Vec_Int_t * vLits;
     int Lit, RetValue;
-    clock_t clk, Limit;
+    abctime clk, Limit;
     p->nCalls++;
     pSat = Pdr_ManFetchSolver( p, k );
     if ( pCube == NULL ) // solve the property
     {
-        clk = clock();
+        clk = Abc_Clock();
         Lit = toLit( Pdr_ObjSatVar(p, k, Aig_ManCo(p->pAig, p->iOutCur)) ); // pos literal (property fails)
         Limit = sat_solver_set_runtime_limit( pSat, Pdr_ManTimeLimit(p) );
         RetValue = sat_solver_solve( pSat, &Lit, &Lit + 1, nConfLimit, 0, 0, 0 );
@@ -324,7 +324,7 @@ int Pdr_ManCheckCube( Pdr_Man_t * p, int k, Pdr_Set_t * pCube, Pdr_Set_t ** ppPr
             vLits = Pdr_ManCubeToLits( p, k, pCube, 0, 1 );
 
         // solve 
-        clk = clock();
+        clk = Abc_Clock();
         Limit = sat_solver_set_runtime_limit( pSat, Pdr_ManTimeLimit(p) );
         RetValue = sat_solver_solve( pSat, Vec_IntArray(vLits), Vec_IntArray(vLits) + Vec_IntSize(vLits), nConfLimit, 0, 0, 0 );
         sat_solver_set_runtime_limit( pSat, Limit );
@@ -349,7 +349,7 @@ int Pdr_ManCheckCube( Pdr_Man_t * p, int k, Pdr_Set_t * pCube, Pdr_Set_t ** ppPr
         }
 */
     }
-    clk = clock() - clk;
+    clk = Abc_Clock() - clk;
     p->tSat += clk;
     assert( RetValue != l_Undef );
     if ( RetValue == l_False )
diff --git a/src/proof/pdr/pdrTsim.c b/src/proof/pdr/pdrTsim.c
index 1865e14b..32d1c857 100644
--- a/src/proof/pdr/pdrTsim.c
+++ b/src/proof/pdr/pdrTsim.c
@@ -364,7 +364,7 @@ Pdr_Set_t * Pdr_ManTernarySim( Pdr_Man_t * p, int k, Pdr_Set_t * pCube )
     Vec_Int_t * vRes    = p->vRes;     // final result (flop literals)
     Aig_Obj_t * pObj;
     int i, Entry, RetValue;
-    clock_t clk = clock();
+    abctime clk = Abc_Clock();
 
     // collect CO objects
     Vec_IntClear( vCoObjs );
@@ -474,7 +474,7 @@ Pdr_ManPrintCex( p->pAig, vCiObjs, vCiVals, vCi2Rem );
     // derive the set of resulting registers
     Pdr_ManDeriveResult( p->pAig, vCiObjs, vCiVals, vCi2Rem, vRes, vPiLits );
     assert( Vec_IntSize(vRes) > 0 );
-    p->tTsim += clock() - clk;
+    p->tTsim += Abc_Clock() - clk;
     pRes = Pdr_SetCreate( vRes, vPiLits );
     assert( k == 0 || !Pdr_SetIsInit(pRes, -1) );
     return pRes;
diff --git a/src/proof/ssc/sscCore.c b/src/proof/ssc/sscCore.c
index 411df1e5..4c3f98da 100644
--- a/src/proof/ssc/sscCore.c
+++ b/src/proof/ssc/sscCore.c
@@ -218,9 +218,9 @@ Gia_Man_t * Ssc_PerformSweeping( Gia_Man_t * pAig, Gia_Man_t * pCare, Ssc_Pars_t
     Ssc_Man_t * p;
     Gia_Man_t * pResult, * pTemp;
     Gia_Obj_t * pObj, * pRepr;
-    clock_t clk, clkTotal = clock();
+    abctime clk, clkTotal = Abc_Clock();
     int i, fCompl, nRefined, status;
-clk = clock();
+clk = Abc_Clock();
     assert( Gia_ManRegNum(pCare) == 0 );
     assert( Gia_ManCiNum(pAig) == Gia_ManCiNum(pCare) );
     assert( Gia_ManIsNormalized(pAig) );
@@ -250,7 +250,7 @@ clk = clock();
         if ( nRefined <= Gia_ManCandNum(pAig) / 100 )
             break;
     }
-p->timeSimInit += clock() - clk;
+p->timeSimInit += Abc_Clock() - clk;
 
     // prepare user's AIG
     Gia_ManFillValue(pAig);
@@ -267,7 +267,7 @@ p->timeSimInit += clock() - clk;
     {
         if ( pAig->iPatsPi == 64 * pPars->nWords )
         {
-clk = clock();
+clk = Abc_Clock();
             Ssc_GiaSimRound( pAig );
             Ssc_GiaClassesRefine( pAig );
             if ( pPars->fVerbose ) 
@@ -277,7 +277,7 @@ clk = clock();
             // prepare next patterns
             Ssc_GiaResetPiPattern( pAig, pPars->nWords );
             Ssc_GiaSavePiPattern( pAig, p->vPivot );
-p->timeSimSat += clock() - clk;
+p->timeSimSat += Abc_Clock() - clk;
 //printf( "\n" );
         }
         if ( Gia_ObjIsAnd(pObj) )
@@ -294,7 +294,7 @@ p->timeSimSat += clock() - clk;
         fCompl = pRepr->fPhase ^ pObj->fPhase ^ Abc_LitIsCompl(pRepr->Value) ^ Abc_LitIsCompl(pObj->Value);
 
         // perform SAT call
-clk = clock();
+clk = Abc_Clock();
         p->nSatCalls++;
         status = Ssc_ManCheckEquivalence( p, Abc_Lit2Var(pRepr->Value), Abc_Lit2Var(pObj->Value), fCompl );
         if ( status == l_False )
@@ -317,11 +317,11 @@ clk = clock();
         else if ( status == l_Undef )
             p->nSatCallsUndec++;
         else assert( 0 );
-p->timeSat += clock() - clk;
+p->timeSat += Abc_Clock() - clk;
     }
     if ( pAig->iPatsPi > 1 )
     {
-clk = clock();
+clk = Abc_Clock();
         while ( pAig->iPatsPi < 64 * pPars->nWords )
             Ssc_GiaSavePiPattern( pAig, p->vPivot );
         Ssc_GiaSimRound( pAig );
@@ -330,7 +330,7 @@ clk = clock();
             Gia_ManEquivPrintClasses( pAig, 0, 0 );
         Ssc_GiaClassesCheckPairs( pAig, p->vDisPairs );
         Vec_IntClear( p->vDisPairs );
-p->timeSimSat += clock() - clk;
+p->timeSimSat += Abc_Clock() - clk;
     }
 //    Gia_ManEquivPrintClasses( pAig, 1, 0 );
 //    Gia_ManPrint( pAig );
@@ -346,7 +346,7 @@ p->timeSimSat += clock() - clk;
     }
     pResult = Gia_ManCleanup( pTemp = pResult );
     Gia_ManStop( pTemp );
-    p->timeTotal = clock() - clkTotal;
+    p->timeTotal = Abc_Clock() - clkTotal;
     if ( pPars->fVerbose )
         Ssc_ManPrintStats( p );
     Ssc_ManStop( p );
@@ -356,7 +356,7 @@ p->timeSimSat += clock() - clk;
         Abc_Print( 1, "Reduction in AIG nodes:%8d  ->%8d (%6.2f %%).  ", 
             Gia_ManAndNum(pAig), Gia_ManAndNum(pResult), 
             100.0 - 100.0 * Gia_ManAndNum(pResult) / Gia_ManAndNum(pAig) );
-        Abc_PrintTime( 1, "Time", clock() - clkTotal );
+        Abc_PrintTime( 1, "Time", Abc_Clock() - clkTotal );
     }
     return pResult;
 }
diff --git a/src/proof/ssc/sscInt.h b/src/proof/ssc/sscInt.h
index 0be25174..4e785bce 100644
--- a/src/proof/ssc/sscInt.h
+++ b/src/proof/ssc/sscInt.h
@@ -72,15 +72,15 @@ struct Ssc_Man_t_
     int              nSatCallsSat;   // the number of sat SAT calls
     int              nSatCallsUndec; // the number of undec SAT calls
     // runtime stats
-    clock_t          timeSimInit;    // simulation and class computation
-    clock_t          timeSimSat;     // simulation of the counter-examples
-    clock_t          timeCnfGen;     // generation of CNF
-    clock_t          timeSat;        // total SAT time
-    clock_t          timeSatSat;     // sat
-    clock_t          timeSatUnsat;   // unsat
-    clock_t          timeSatUndec;   // undecided
-    clock_t          timeOther;      // other runtime
-    clock_t          timeTotal;      // total runtime
+    abctime          timeSimInit;    // simulation and class computation
+    abctime          timeSimSat;     // simulation of the counter-examples
+    abctime          timeCnfGen;     // generation of CNF
+    abctime          timeSat;        // total SAT time
+    abctime          timeSatSat;     // sat
+    abctime          timeSatUnsat;   // unsat
+    abctime          timeSatUndec;   // undecided
+    abctime          timeOther;      // other runtime
+    abctime          timeTotal;      // total runtime
 };
 
 ////////////////////////////////////////////////////////////////////////
diff --git a/src/proof/ssc/sscSat.c b/src/proof/ssc/sscSat.c
index 1de99c2e..9992f18e 100644
--- a/src/proof/ssc/sscSat.c
+++ b/src/proof/ssc/sscSat.c
@@ -209,12 +209,12 @@ static void Ssc_ManCnfNodeAddToSolver( Ssc_Man_t * p, int NodeId )
 {
     Gia_Obj_t * pNode;
     int i, k, Id, Lit;
-    clock_t clk;
+    abctime clk;
     assert( NodeId > 0 );
     // quit if CNF is ready
     if ( Ssc_ObjSatVar(p, NodeId) )
         return;
-clk = clock();
+clk = Abc_Clock();
     // start the frontier
     Vec_IntClear( p->vFront );
     Ssc_ManCnfAddToFrontier( p, NodeId, p->vFront );
@@ -243,7 +243,7 @@ clk = clock();
         }
         assert( Vec_IntSize(p->vFanins) > 1 );
     }
-p->timeCnfGen += clock() - clk;
+p->timeCnfGen += Abc_Clock() - clk;
 }
 
 
@@ -346,10 +346,10 @@ Vec_Int_t * Ssc_ManFindPivotSat( Ssc_Man_t * p )
 int Ssc_ManCheckEquivalence( Ssc_Man_t * p, int iRepr, int iNode, int fCompl )
 {
     int pLitsSat[2], RetValue;
-    clock_t clk;
+    abctime clk;
     assert( iRepr < iNode );
 //    if ( p->nTimeOut )
-//        sat_solver_set_runtime_limit( p->pSat, p->nTimeOut * CLOCKS_PER_SEC + clock() );
+//        sat_solver_set_runtime_limit( p->pSat, p->nTimeOut * CLOCKS_PER_SEC + Abc_Clock() );
 
     // create CNF
     if ( iRepr )
@@ -363,7 +363,7 @@ int Ssc_ManCheckEquivalence( Ssc_Man_t * p, int iRepr, int iNode, int fCompl )
 
     // solve under assumptions
     // A = 1; B = 0
-    clk = clock();
+    clk = Abc_Clock();
     RetValue = sat_solver_solve( p->pSat, pLitsSat, pLitsSat + 2, (ABC_INT64_T)p->pPars->nBTLimit, (ABC_INT64_T)0, (ABC_INT64_T)0, (ABC_INT64_T)0 );
     if ( RetValue == l_False )
     {
@@ -371,17 +371,17 @@ int Ssc_ManCheckEquivalence( Ssc_Man_t * p, int iRepr, int iNode, int fCompl )
         pLitsSat[1] = Abc_LitNot( pLitsSat[1] ); // compl
         RetValue = sat_solver_addclause( p->pSat, pLitsSat, pLitsSat + 2 );
         assert( RetValue );
-        p->timeSatUnsat += clock() - clk;
+        p->timeSatUnsat += Abc_Clock() - clk;
     }
     else if ( RetValue == l_True )
     {
         Ssc_ManCollectSatPattern( p, p->vPattern );
-        p->timeSatSat += clock() - clk;
+        p->timeSatSat += Abc_Clock() - clk;
         return l_True;
     }
     else // if ( RetValue1 == l_Undef )
     {
-        p->timeSatUndec += clock() - clk;
+        p->timeSatUndec += Abc_Clock() - clk;
         return l_Undef;
     }
 
@@ -391,7 +391,7 @@ int Ssc_ManCheckEquivalence( Ssc_Man_t * p, int iRepr, int iNode, int fCompl )
 
     // solve under assumptions
     // A = 0; B = 1
-    clk = clock();
+    clk = Abc_Clock();
     RetValue = sat_solver_solve( p->pSat, pLitsSat, pLitsSat + 2, (ABC_INT64_T)p->pPars->nBTLimit, (ABC_INT64_T)0, (ABC_INT64_T)0, (ABC_INT64_T)0 );
     if ( RetValue == l_False )
     {
@@ -399,17 +399,17 @@ int Ssc_ManCheckEquivalence( Ssc_Man_t * p, int iRepr, int iNode, int fCompl )
         pLitsSat[1] = Abc_LitNot( pLitsSat[1] );
         RetValue = sat_solver_addclause( p->pSat, pLitsSat, pLitsSat + 2 );
         assert( RetValue );
-        p->timeSatUnsat += clock() - clk;
+        p->timeSatUnsat += Abc_Clock() - clk;
     }
     else if ( RetValue == l_True )
     {
         Ssc_ManCollectSatPattern( p, p->vPattern );
-        p->timeSatSat += clock() - clk;
+        p->timeSatSat += Abc_Clock() - clk;
         return l_True;
     }
     else // if ( RetValue1 == l_Undef )
     {
-        p->timeSatUndec += clock() - clk;
+        p->timeSatUndec += Abc_Clock() - clk;
         return l_Undef;
     }
     return l_False;
diff --git a/src/proof/ssw/sswBmc.c b/src/proof/ssw/sswBmc.c
index c88b2dcc..61c1c2a7 100644
--- a/src/proof/ssw/sswBmc.c
+++ b/src/proof/ssw/sswBmc.c
@@ -129,7 +129,7 @@ int Ssw_BmcDynamic( Aig_Man_t * pAig, int nFramesMax, int nConfLimit, int fVerbo
     Ssw_Sat_t * pSat;
     Aig_Obj_t * pObj, * pObjFrame;
     int status, Lit, i, f, RetValue;
-    clock_t clkPart;
+    abctime clkPart;
 
     // start managers
     assert( Saig_ManRegNum(pAig) > 0 );
@@ -149,7 +149,7 @@ int Ssw_BmcDynamic( Aig_Man_t * pAig, int nFramesMax, int nConfLimit, int fVerbo
     RetValue = -1;
     for ( f = 0; f < nFramesMax; f++ )
     {
-        clkPart = clock();
+        clkPart = Abc_Clock();
         Saig_ManForEachPo( pAig, pObj, i )
         {
             // unroll the circuit for this output
@@ -203,8 +203,8 @@ int Ssw_BmcDynamic( Aig_Man_t * pAig, int nFramesMax, int nConfLimit, int fVerbo
             Abc_Print( 1, "Conf =%8.0f. Var =%8d. AIG=%9d. ",
                 (double)pSat->pSat->stats.conflicts,
                 pSat->nSatVars, Aig_ManNodeNum(pFrm->pFrames) );
-            ABC_PRT( "T", clock() - clkPart );
-            clkPart = clock();
+            ABC_PRT( "T", Abc_Clock() - clkPart );
+            clkPart = Abc_Clock();
             fflush( stdout );
         }
         if ( RetValue != 1 )
diff --git a/src/proof/ssw/sswClass.c b/src/proof/ssw/sswClass.c
index 9cf8871b..0613302e 100644
--- a/src/proof/ssw/sswClass.c
+++ b/src/proof/ssw/sswClass.c
@@ -611,25 +611,25 @@ Ssw_Cla_t * Ssw_ClassesPrepare( Aig_Man_t * pAig, int nFramesK, int fLatchCorr,
     Vec_Ptr_t * vCands;
     Aig_Obj_t * pObj;
     int i, k, RetValue;
-    clock_t clk;
+    abctime clk;
 
     // start the classes
     p = Ssw_ClassesStart( pAig );
     p->fConstCorr = fConstCorr;
 
     // perform sequential simulation
-clk = clock();
+clk = Abc_Clock();
     pSml = Ssw_SmlSimulateSeq( pAig, 0, nFrames, nWords );
 if ( fVerbose )
 {
     Abc_Print( 1, "Allocated %.2f MB to store simulation information.\n",
         1.0*(sizeof(unsigned) * Aig_ManObjNumMax(pAig) * nFrames * nWords)/(1<<20) );
     Abc_Print( 1, "Initial simulation of %d frames with %d words.     ", nFrames, nWords );
-    ABC_PRT( "Time", clock() - clk );
+    ABC_PRT( "Time", Abc_Clock() - clk );
 }
 
     // set comparison procedures
-clk = clock();
+clk = Abc_Clock();
     Ssw_ClassesSetData( p, pSml, (unsigned(*)(void *,Aig_Obj_t *))Ssw_SmlObjHashWord, (int(*)(void *,Aig_Obj_t *))Ssw_SmlObjIsConstWord, (int(*)(void *,Aig_Obj_t *,Aig_Obj_t *))Ssw_SmlObjsAreEqualWord );
 
     // collect nodes to be considered as candidates
@@ -677,10 +677,10 @@ clk = clock();
 if ( fVerbose )
 {
     Abc_Print( 1, "Collecting candidate equivalence classes.        " );
-ABC_PRT( "Time", clock() - clk );
+ABC_PRT( "Time", Abc_Clock() - clk );
 }
 
-clk = clock();
+clk = Abc_Clock();
     // perform iterative refinement using simulation
     for ( i = 1; i < nIters; i++ )
     {
@@ -703,7 +703,7 @@ if ( fVerbose )
 {
     Abc_Print( 1, "Simulation of %d frames with %d words (%2d rounds). ",
         nFrames, nWords, i-1 );
-    ABC_PRT( "Time", clock() - clk );
+    ABC_PRT( "Time", Abc_Clock() - clk );
 }
     Ssw_ClassesCheck( p );
 //    Ssw_ClassesPrint( p, 0 );
diff --git a/src/proof/ssw/sswConstr.c b/src/proof/ssw/sswConstr.c
index 3dcf0a34..a9ed17fc 100644
--- a/src/proof/ssw/sswConstr.c
+++ b/src/proof/ssw/sswConstr.c
@@ -409,8 +409,8 @@ int Ssw_ManSweepBmcConstr_old( Ssw_Man_t * p )
     Bar_Progress_t * pProgress = NULL;
     Aig_Obj_t * pObj, * pObjNew, * pObjLi, * pObjLo;
     int i, f, iLits;
-    clock_t clk;
-clk = clock();
+    abctime clk;
+clk = Abc_Clock();
 
     // start initialized timeframes
     p->pFrames = Aig_ManStart( Aig_ManObjNumMax(p->pAig) * p->pPars->nFramesK );
@@ -480,7 +480,7 @@ clk = clock();
 
     // cleanup
 //    Ssw_ClassesCheck( p->ppClasses );
-p->timeBmc += clock() - clk;
+p->timeBmc += Abc_Clock() - clk;
     return p->fRefined;
 }
 
@@ -499,8 +499,8 @@ int Ssw_ManSweepBmcConstr( Ssw_Man_t * p )
 {
     Aig_Obj_t * pObj, * pObjNew, * pObjLi, * pObjLo;
     int i, f, iLits;
-    clock_t clk;
-clk = clock();
+    abctime clk;
+clk = Abc_Clock();
 
     // start initialized timeframes
     p->pFrames = Aig_ManStart( Aig_ManObjNumMax(p->pAig) * p->pPars->nFramesK );
@@ -560,7 +560,7 @@ clk = clock();
 
     // cleanup
 //    Ssw_ClassesCheck( p->ppClasses );
-p->timeBmc += clock() - clk;
+p->timeBmc += Abc_Clock() - clk;
     return p->fRefined;
 }
 
@@ -621,11 +621,11 @@ int Ssw_ManSweepConstr( Ssw_Man_t * p )
     Bar_Progress_t * pProgress = NULL;
     Aig_Obj_t * pObj, * pObj2, * pObjNew;
     int nConstrPairs, i, f, iLits;
-    clock_t clk;
+    abctime clk;
 //Ssw_ManPrintPolarity( p->pAig );
 
     // perform speculative reduction
-clk = clock();
+clk = Abc_Clock();
     // create timeframes
     p->pFrames = Ssw_FramesWithClasses( p );
     // add constants
@@ -656,7 +656,7 @@ clk = clock();
         Ssw_ObjSetFrame( p, pObj, f, pObjNew );
     }
     assert( Vec_IntSize(p->vInits) == iLits );
-p->timeReduce += clock() - clk;
+p->timeReduce += Abc_Clock() - clk;
 
     // add constraints to all timeframes
     for ( f = 0; f <= p->pPars->nFramesK; f++ )
diff --git a/src/proof/ssw/sswCore.c b/src/proof/ssw/sswCore.c
index 7a9d4b9f..f944eddc 100644
--- a/src/proof/ssw/sswCore.c
+++ b/src/proof/ssw/sswCore.c
@@ -236,7 +236,7 @@ Aig_Man_t * Ssw_SignalCorrespondenceRefine( Ssw_Man_t * p )
     int nSatProof, nSatCallsSat, nRecycles, nSatFailsReal, nUniques;
     Aig_Man_t * pAigNew;
     int RetValue, nIter = -1;
-    clock_t clk, clkTotal = clock();
+    abctime clk, clkTotal = Abc_Clock();
     // get the starting stats
     p->nLitsBeg  = Ssw_ClassesLitNum( p->ppClasses );
     p->nNodesBeg = Aig_ManNodeNum(p->pAig);
@@ -306,7 +306,7 @@ Aig_Man_t * Ssw_SignalCorrespondenceRefine( Ssw_Man_t * p )
             break;
         }
 
-clk = clock();
+clk = Abc_Clock();
         p->pMSat = Ssw_SatStart( 0 );
         if ( p->pPars->fLatchCorrOpt )
         {
@@ -317,7 +317,7 @@ clk = clock();
                     nIter, Ssw_ClassesCand1Num(p->ppClasses), Ssw_ClassesClassNum(p->ppClasses),
                     p->nSatProof-nSatProof, p->nSatCallsSat-nSatCallsSat,
                     p->nRecycles-nRecycles, p->nSatFailsReal-nSatFailsReal );
-                ABC_PRT( "T", clock() - clk );
+                ABC_PRT( "T", Abc_Clock() - clk );
             }
         }
         else
@@ -342,7 +342,7 @@ clk = clock();
                 }
                 Abc_Print( 1, "F =%5d. %s ", p->nSatFailsReal-nSatFailsReal,
                     (Saig_ManPoNum(p->pAig)==1 && Ssw_ObjIsConst1Cand(p->pAig,Aig_ObjFanin0(Aig_ManCo(p->pAig,0))))? "+" : "-" );
-                ABC_PRT( "T", clock() - clk );
+                ABC_PRT( "T", Abc_Clock() - clk );
             }
 //            if ( p->pPars->fDynamic && p->nSatCallsSat-nSatCallsSat < 100 )
 //                p->pPars->nBTLimit = 10000;
@@ -384,7 +384,7 @@ clk = clock();
 
 finalize:
     p->pPars->nIters = nIter + 1;
-p->timeTotal = clock() - clkTotal;
+p->timeTotal = Abc_Clock() - clkTotal;
 
     Ssw_ManUpdateEquivs( p, p->pAig, p->pPars->fVerbose );
     pAigNew = Aig_ManDupRepr( p->pAig, 0 );
diff --git a/src/proof/ssw/sswDyn.c b/src/proof/ssw/sswDyn.c
index 5fc22fdf..316b2e4d 100644
--- a/src/proof/ssw/sswDyn.c
+++ b/src/proof/ssw/sswDyn.c
@@ -263,7 +263,7 @@ void Ssw_ManSweepTransferDyn( Ssw_Man_t * p )
 int Ssw_ManSweepResimulateDyn( Ssw_Man_t * p, int f )
 {
     int RetValue1, RetValue2;
-    clock_t clk = clock();
+    abctime clk = Abc_Clock();
     // transfer PI simulation information from storage
 //    Ssw_SmlAssignDist1Plus( p->pSml, p->pPatWords );
     Ssw_ManSweepTransferDyn( p );
@@ -277,7 +277,7 @@ int Ssw_ManSweepResimulateDyn( Ssw_Man_t * p, int f )
     Vec_PtrCleanSimInfo( p->vSimInfo, 0, 1 );
     p->nPatterns = 0;
     p->nSimRounds++;
-p->timeSimSat += clock() - clk;
+p->timeSimSat += Abc_Clock() - clk;
     return RetValue1 > 0 || RetValue2 > 0;
 }
 
@@ -296,7 +296,7 @@ int Ssw_ManSweepResimulateDynLocal( Ssw_Man_t * p, int f )
 {
     Aig_Obj_t * pObj, * pRepr, ** ppClass;
     int i, k, nSize, RetValue1, RetValue2;
-    clock_t clk = clock();
+    abctime clk = Abc_Clock();
     p->nSimRounds++;
     // transfer PI simulation information from storage
 //    Ssw_SmlAssignDist1Plus( p->pSml, p->pPatWords );
@@ -355,7 +355,7 @@ int Ssw_ManSweepResimulateDynLocal( Ssw_Man_t * p, int f )
     Vec_PtrCleanSimInfo( p->vSimInfo, 0, 1 );
     p->nPatterns = 0;
     p->nSimRounds++;
-p->timeSimSat += clock() - clk;
+p->timeSimSat += Abc_Clock() - clk;
     return RetValue1 > 0 || RetValue2 > 0;
 }
 
@@ -375,10 +375,10 @@ int Ssw_ManSweepDyn( Ssw_Man_t * p )
     Bar_Progress_t * pProgress = NULL;
     Aig_Obj_t * pObj, * pObjNew;
     int i, f;
-    clock_t clk;
+    abctime clk;
 
     // perform speculative reduction
-clk = clock();
+clk = Abc_Clock();
     // create timeframes
     p->pFrames = Ssw_FramesWithClasses( p );
     Aig_ManFanoutStart( p->pFrames );
@@ -392,7 +392,7 @@ clk = clock();
     Aig_ManSetCioIds( p->pFrames );
     // label nodes corresponding to primary inputs
     Ssw_ManLabelPiNodes( p );
-p->timeReduce += clock() - clk;
+p->timeReduce += Abc_Clock() - clk;
 
     // prepare simulation info
     assert( p->vSimInfo == NULL );
diff --git a/src/proof/ssw/sswFilter.c b/src/proof/ssw/sswFilter.c
index 534fc275..9027d773 100644
--- a/src/proof/ssw/sswFilter.c
+++ b/src/proof/ssw/sswFilter.c
@@ -279,7 +279,7 @@ int Ssw_ManSweepBmcFilter( Ssw_Man_t * p, int TimeLimit )
 {
     Aig_Obj_t * pObj, * pObjNew, * pObjLi, * pObjLo;
     int f, f1, i;
-    clock_t clkTotal = clock();
+    abctime clkTotal = Abc_Clock();
     // start initialized timeframes
     p->pFrames = Aig_ManStart( Aig_ManObjNumMax(p->pAig) * p->pPars->nFramesK );
     Saig_ManForEachLo( p->pAig, pObj, i )
@@ -349,7 +349,7 @@ int Ssw_ManSweepBmcFilter( Ssw_Man_t * p, int TimeLimit )
             break;
         }
         // check timeout
-        if ( TimeLimit && ((float)TimeLimit <= (float)(clock()-clkTotal)/(float)(CLOCKS_PER_SEC)) )
+        if ( TimeLimit && ((float)TimeLimit <= (float)(Abc_Clock()-clkTotal)/(float)(CLOCKS_PER_SEC)) )
             break;
         // transfer latch input to the latch outputs 
         Aig_ManForEachCo( p->pAig, pObj, i )
@@ -383,8 +383,8 @@ void Ssw_SignalFilter( Aig_Man_t * pAig, int nFramesMax, int nConfMax, int nRoun
 {
     Ssw_Pars_t Pars, * pPars = &Pars;
     Ssw_Man_t * p;
-    int r, TimeLimitPart;//, clkTotal = clock();
-    clock_t nTimeToStop = TimeLimit ? TimeLimit * CLOCKS_PER_SEC + clock(): 0;
+    int r, TimeLimitPart;//, clkTotal = Abc_Clock();
+    abctime nTimeToStop = TimeLimit ? TimeLimit * CLOCKS_PER_SEC + Abc_Clock(): 0;
     assert( Aig_ManRegNum(pAig) > 0 );
     assert( Aig_ManConstrNum(pAig) == 0 );
     // consider the case of empty AIG
@@ -430,7 +430,7 @@ void Ssw_SignalFilter( Aig_Man_t * pAig, int nFramesMax, int nConfMax, int nRoun
             Ssw_ClassesPrint( p->ppClasses, 0 );
         }
         p->pMSat = Ssw_SatStart( 0 );
-        TimeLimitPart = TimeLimit ? (nTimeToStop - clock()) / CLOCKS_PER_SEC : 0;
+        TimeLimitPart = TimeLimit ? (nTimeToStop - Abc_Clock()) / CLOCKS_PER_SEC : 0;
         if ( TimeLimit2 )
         {
             if ( TimeLimitPart )
@@ -445,7 +445,7 @@ void Ssw_SignalFilter( Aig_Man_t * pAig, int nFramesMax, int nConfMax, int nRoun
         // simulate pattern forward
         Ssw_ManRollForward( p, p->pPars->nFramesK );
         // check timeout
-        if ( TimeLimit && clock() > nTimeToStop )
+        if ( TimeLimit && Abc_Clock() > nTimeToStop )
         {
             Abc_Print( 1, "Reached timeout (%d seconds).\n",  TimeLimit );
             break;
diff --git a/src/proof/ssw/sswInt.h b/src/proof/ssw/sswInt.h
index 1edf2087..00681923 100644
--- a/src/proof/ssw/sswInt.h
+++ b/src/proof/ssw/sswInt.h
@@ -127,16 +127,16 @@ struct Ssw_Man_t_
     int              nRegsBegC;
     int              nRegsEndC;
     // runtime stats
-    clock_t          timeBmc;        // bounded model checking
-    clock_t          timeReduce;     // speculative reduction
-    clock_t          timeMarkCones;  // marking the cones not to be refined
-    clock_t          timeSimSat;     // simulation of the counter-examples
-    clock_t          timeSat;        // solving SAT
-    clock_t          timeSatSat;     // sat
-    clock_t          timeSatUnsat;   // unsat
-    clock_t          timeSatUndec;   // undecided
-    clock_t          timeOther;      // other runtime
-    clock_t          timeTotal;      // total runtime
+    abctime          timeBmc;        // bounded model checking
+    abctime          timeReduce;     // speculative reduction
+    abctime          timeMarkCones;  // marking the cones not to be refined
+    abctime          timeSimSat;     // simulation of the counter-examples
+    abctime          timeSat;        // solving SAT
+    abctime          timeSatSat;     // sat
+    abctime          timeSatUnsat;   // unsat
+    abctime          timeSatUndec;   // undecided
+    abctime          timeOther;      // other runtime
+    abctime          timeTotal;      // total runtime
 };
 
 // internal SAT manager
diff --git a/src/proof/ssw/sswIslands.c b/src/proof/ssw/sswIslands.c
index d1758b75..87df4ebf 100644
--- a/src/proof/ssw/sswIslands.c
+++ b/src/proof/ssw/sswIslands.c
@@ -480,7 +480,7 @@ int Ssw_SecWithSimilarityPairs( Aig_Man_t * p0, Aig_Man_t * p1, Vec_Int_t * vPai
     Ssw_Pars_t Pars;
     Aig_Man_t * pAigRes;
     int RetValue;
-    clock_t clk = clock();
+    abctime clk = Abc_Clock();
     // derive parameters if not given
     if ( pPars == NULL )
         Ssw_ManSetDefaultParams( pPars = &Pars );
@@ -495,7 +495,7 @@ int Ssw_SecWithSimilarityPairs( Aig_Man_t * p0, Aig_Man_t * p1, Vec_Int_t * vPai
     else
         Abc_Print( 1, "Verification UNDECIDED. The number of remaining regs = %d (total = %d).  ",
             Aig_ManRegNum(pAigRes), Aig_ManRegNum(p0)+Aig_ManRegNum(p1) );
-    ABC_PRT( "Time", clock() - clk );
+    ABC_PRT( "Time", Abc_Clock() - clk );
     Aig_ManStop( pAigRes );
     return RetValue;
 }
diff --git a/src/proof/ssw/sswLcorr.c b/src/proof/ssw/sswLcorr.c
index cd212e0b..d020ef00 100644
--- a/src/proof/ssw/sswLcorr.c
+++ b/src/proof/ssw/sswLcorr.c
@@ -78,7 +78,7 @@ void Ssw_ManSweepTransfer( Ssw_Man_t * p )
 int Ssw_ManSweepResimulate( Ssw_Man_t * p )
 {
     int RetValue1, RetValue2;
-    clock_t clk = clock();
+    abctime clk = Abc_Clock();
     // transfer PI simulation information from storage
     Ssw_ManSweepTransfer( p );
     // simulate internal nodes
@@ -90,7 +90,7 @@ int Ssw_ManSweepResimulate( Ssw_Man_t * p )
     Vec_PtrCleanSimInfo( p->vSimInfo, 0, 1 );
     p->nPatterns = 0;
     p->nSimRounds++;
-p->timeSimSat += clock() - clk;
+p->timeSimSat += Abc_Clock() - clk;
     return RetValue1 > 0 || RetValue2 > 0;
 }
 
@@ -161,7 +161,7 @@ void Ssw_ManSweepLatchOne( Ssw_Man_t * p, Aig_Obj_t * pObjRepr, Aig_Obj_t * pObj
 {
     Aig_Obj_t * pObjFraig, * pObjReprFraig, * pObjLi;
     int RetValue;
-    clock_t clk;
+    abctime clk;
     assert( Aig_ObjIsCi(pObj) );
     assert( Aig_ObjIsCi(pObjRepr) || Aig_ObjIsConst1(pObjRepr) );
     // check if it makes sense to skip some calls
@@ -171,7 +171,7 @@ void Ssw_ManSweepLatchOne( Ssw_Man_t * p, Aig_Obj_t * pObjRepr, Aig_Obj_t * pObj
             return;
     }
     p->nCallsDelta = 0;
-clk = clock();
+clk = Abc_Clock();
     // get the fraiged node
     pObjLi = Saig_ObjLoToLi( p->pAig, pObj );
     Ssw_ManBuildCone_rec( p, Aig_ObjFanin0(pObjLi) );
@@ -185,7 +185,7 @@ clk = clock();
     }
     else
         pObjReprFraig = Ssw_ObjFrame( p, pObjRepr, 0 );
-p->timeReduce += clock() - clk;
+p->timeReduce += Abc_Clock() - clk;
     // if the fraiged nodes are the same, return
     if ( Aig_Regular(pObjFraig) == Aig_Regular(pObjReprFraig) )
         return;
diff --git a/src/proof/ssw/sswPairs.c b/src/proof/ssw/sswPairs.c
index 3068adc4..fe389191 100644
--- a/src/proof/ssw/sswPairs.c
+++ b/src/proof/ssw/sswPairs.c
@@ -321,7 +321,7 @@ Aig_Man_t * Ssw_SignalCorrespondeceTestPairs( Aig_Man_t * pAig )
     Vec_Int_t * vIds1, * vIds2;
     Aig_Obj_t * pObj, * pRepr;
     int RetValue, i;
-    clock_t clk = clock();
+    abctime clk = Abc_Clock();
     Ssw_ManSetDefaultParams( pPars );
     pPars->fVerbose = 1;
     pAigNew = Ssw_SignalCorrespondence( pAig, pPars );
@@ -360,7 +360,7 @@ Aig_Man_t * Ssw_SignalCorrespondeceTestPairs( Aig_Man_t * pAig )
     else
         Abc_Print( 1, "Verification UNDECIDED. Remaining registers %d (total %d).  ",
             Aig_ManRegNum(pAigRes), Aig_ManRegNum(pAig) + Aig_ManRegNum(pAigNew) );
-    ABC_PRT( "Time", clock() - clk );
+    ABC_PRT( "Time", Abc_Clock() - clk );
     // cleanup
     Aig_ManStop( pAigNew );
     return pAigRes;
@@ -381,7 +381,7 @@ int Ssw_SecWithPairs( Aig_Man_t * pAig1, Aig_Man_t * pAig2, Vec_Int_t * vIds1, V
 {
     Aig_Man_t * pAigRes;
     int RetValue;
-    clock_t clk = clock();
+    abctime clk = Abc_Clock();
     assert( vIds1 != NULL && vIds2 != NULL );
     // try the new AIGs
     Abc_Print( 1, "Performing specialized verification with node pairs.\n" );
@@ -395,7 +395,7 @@ int Ssw_SecWithPairs( Aig_Man_t * pAig1, Aig_Man_t * pAig2, Vec_Int_t * vIds1, V
     else
         Abc_Print( 1, "Verification UNDECIDED. The number of remaining regs = %d (total = %d).  ",
             Aig_ManRegNum(pAigRes), Aig_ManRegNum(pAig1) + Aig_ManRegNum(pAig2) );
-    ABC_PRT( "Time", clock() - clk );
+    ABC_PRT( "Time", Abc_Clock() - clk );
     // cleanup
     Aig_ManStop( pAigRes );
     return RetValue;
@@ -416,7 +416,7 @@ int Ssw_SecGeneral( Aig_Man_t * pAig1, Aig_Man_t * pAig2, Ssw_Pars_t * pPars )
 {
     Aig_Man_t * pAigRes, * pMiter;
     int RetValue;
-    clock_t clk = clock();
+    abctime clk = Abc_Clock();
     // try the new AIGs
     Abc_Print( 1, "Performing general verification without node pairs.\n" );
     pMiter = Saig_ManCreateMiter( pAig1, pAig2, 0 );
@@ -432,7 +432,7 @@ int Ssw_SecGeneral( Aig_Man_t * pAig1, Aig_Man_t * pAig2, Ssw_Pars_t * pPars )
     else
         Abc_Print( 1, "Verification UNDECIDED. The number of remaining regs = %d (total = %d).  ",
             Aig_ManRegNum(pAigRes), Aig_ManRegNum(pAig1) + Aig_ManRegNum(pAig2) );
-    ABC_PRT( "Time", clock() - clk );
+    ABC_PRT( "Time", Abc_Clock() - clk );
     // cleanup
     Aig_ManStop( pAigRes );
     return RetValue;
@@ -453,7 +453,7 @@ int Ssw_SecGeneralMiter( Aig_Man_t * pMiter, Ssw_Pars_t * pPars )
 {
     Aig_Man_t * pAigRes;
     int RetValue;
-    clock_t clk = clock();
+    abctime clk = Abc_Clock();
     // try the new AIGs
 //    Abc_Print( 1, "Performing general verification without node pairs.\n" );
     pAigRes = Ssw_SignalCorrespondence( pMiter, pPars );
@@ -466,7 +466,7 @@ int Ssw_SecGeneralMiter( Aig_Man_t * pMiter, Ssw_Pars_t * pPars )
     else
         Abc_Print( 1, "Verification UNDECIDED. The number of remaining regs = %d (total = %d).  ",
             Aig_ManRegNum(pAigRes), Aig_ManRegNum(pMiter) );
-    ABC_PRT( "Time", clock() - clk );
+    ABC_PRT( "Time", Abc_Clock() - clk );
     // cleanup
     Aig_ManStop( pAigRes );
     return RetValue;
diff --git a/src/proof/ssw/sswPart.c b/src/proof/ssw/sswPart.c
index dbe8a877..30afddca 100644
--- a/src/proof/ssw/sswPart.c
+++ b/src/proof/ssw/sswPart.c
@@ -53,7 +53,7 @@ Aig_Man_t * Ssw_SignalCorrespondencePart( Aig_Man_t * pAig, Ssw_Pars_t * pPars )
     int * pMapBack;
     int i, nCountPis, nCountRegs;
     int nClasses, nPartSize, fVerbose;
-    clock_t clk = clock();
+    abctime clk = Abc_Clock();
     if ( pPars->fConstrs )
     {
         Abc_Print( 1, "Cannot use partitioned computation with constraints.\n" );
@@ -126,7 +126,7 @@ Aig_Man_t * Ssw_SignalCorrespondencePart( Aig_Man_t * pAig, Ssw_Pars_t * pPars )
     pPars->fVerbose = fVerbose;
     if ( fVerbose )
     {
-        ABC_PRT( "Total time", clock() - clk );
+        ABC_PRT( "Total time", Abc_Clock() - clk );
     }
     return pNew;
 }
diff --git a/src/proof/ssw/sswRarity.c b/src/proof/ssw/sswRarity.c
index d780b915..10e19b5a 100644
--- a/src/proof/ssw/sswRarity.c
+++ b/src/proof/ssw/sswRarity.c
@@ -314,7 +314,7 @@ void TransposeTest()
 {
     word M[64], N[64];
     int i;
-    clock_t clk;
+    abctime clk;
     Aig_ManRandom64( 1 );
 //    for ( i = 0; i < 64; i++ )
 //        M[i] = Aig_ManRandom64( 0 );
@@ -323,15 +323,15 @@ void TransposeTest()
 //    for ( i = 0; i < 64; i++ )
 //        Extra_PrintBinary( stdout, (unsigned *)&M[i], 64 ), Abc_Print( 1, "\n" );
 
-    clk = clock();
+    clk = Abc_Clock();
     for ( i = 0; i < 100001; i++ )
         transpose64Simple( M, N );
-    Abc_PrintTime( 1, "Time", clock() - clk );
+    Abc_PrintTime( 1, "Time", Abc_Clock() - clk );
 
-    clk = clock();
+    clk = Abc_Clock();
     for ( i = 0; i < 100001; i++ )
         transpose64( M );
-    Abc_PrintTime( 1, "Time", clock() - clk );
+    Abc_PrintTime( 1, "Time", Abc_Clock() - clk );
 
     for ( i = 0; i < 64; i++ )
         if ( M[i] != N[i] )
@@ -594,7 +594,7 @@ int Ssw_RarManObjWhichOne( Ssw_RarMan_t * p, Aig_Obj_t * pObj )
   SeeAlso     []
 
 ***********************************************************************/
-int Ssw_RarManCheckNonConstOutputs( Ssw_RarMan_t * p, int iFrame, clock_t Time )
+int Ssw_RarManCheckNonConstOutputs( Ssw_RarMan_t * p, int iFrame, abctime Time )
 {
     Aig_Obj_t * pObj;
     int i;
@@ -976,9 +976,9 @@ int Ssw_RarSimulate( Aig_Man_t * pAig, Ssw_RarPars_t * pPars )
     int fMiter = 1;
     Ssw_RarMan_t * p;
     int r, f = -1;
-    clock_t clk, clkTotal = clock();
-    clock_t nTimeToStop = pPars->TimeOut ? pPars->TimeOut * CLOCKS_PER_SEC + clock(): 0;
-    clock_t timeLastSolved = 0;
+    abctime clk, clkTotal = Abc_Clock();
+    abctime nTimeToStop = pPars->TimeOut ? pPars->TimeOut * CLOCKS_PER_SEC + Abc_Clock(): 0;
+    abctime timeLastSolved = 0;
     int nNumRestart = 0;
     int nSavedSeed = pPars->nRandSeed;
     int RetValue = -1;
@@ -1004,10 +1004,10 @@ int Ssw_RarSimulate( Aig_Man_t * pAig, Ssw_RarPars_t * pPars )
 
     // perform simulation rounds
     pPars->nSolved = 0;
-    timeLastSolved = clock();
+    timeLastSolved = Abc_Clock();
     for ( r = 0; !pPars->nRounds || (nNumRestart * pPars->nRestart + r < pPars->nRounds); r++ )
     {
-        clk = clock();
+        clk = Abc_Clock();
         if ( fTryBmc )
         {
             Aig_Man_t * pNewAig = Saig_ManDupWithPhase( pAig, p->vInits );
@@ -1022,7 +1022,7 @@ int Ssw_RarSimulate( Aig_Man_t * pAig, Ssw_RarPars_t * pPars )
             Ssw_RarManSimulate( p, f ? NULL : p->vInits, 0, 0 );
             if ( fMiter )
             {
-                int Status = Ssw_RarManCheckNonConstOutputs(p, r * p->pPars->nFrames + f, clock() - clkTotal);
+                int Status = Ssw_RarManCheckNonConstOutputs(p, r * p->pPars->nFrames + f, Abc_Clock() - clkTotal);
                 if ( Status == 2 )
                 {
                     Abc_Print( 1, "Quitting due to callback on fail.\n" );
@@ -1041,22 +1041,22 @@ int Ssw_RarSimulate( Aig_Man_t * pAig, Ssw_RarPars_t * pPars )
                         pAig->pSeqModel = Ssw_RarDeriveCex( p, r * p->pPars->nFrames + f, p->iFailPo, p->iFailPat, pPars->fVerbose );
                         // print final report
                         Abc_Print( 1, "Output %d of miter \"%s\" was asserted in frame %d.  ", pAig->pSeqModel->iPo, pAig->pName, pAig->pSeqModel->iFrame );
-                        Abc_PrintTime( 1, "Time", clock() - clkTotal );
+                        Abc_PrintTime( 1, "Time", Abc_Clock() - clkTotal );
                         goto finish;
                     }
-                    timeLastSolved = clock();
+                    timeLastSolved = Abc_Clock();
                 }
                 // else - did not find a counter example
             }
             // check timeout
-            if ( pPars->TimeOut && clock() > nTimeToStop )
+            if ( pPars->TimeOut && Abc_Clock() > nTimeToStop )
             {
                 if ( pPars->fVerbose && !pPars->fSolveAll ) Abc_Print( 1, "\n" );
                 Abc_Print( 1, "Simulated %d frames for %d rounds with %d restarts.  ", pPars->nFrames, nNumRestart * pPars->nRestart + r, nNumRestart );
                 Abc_Print( 1, "Reached timeout (%d sec).\n",  pPars->TimeOut );
                 goto finish;
             }
-            if ( pPars->TimeOutGap && timeLastSolved && clock() > timeLastSolved + pPars->TimeOutGap * CLOCKS_PER_SEC )
+            if ( pPars->TimeOutGap && timeLastSolved && Abc_Clock() > timeLastSolved + pPars->TimeOutGap * CLOCKS_PER_SEC )
             {
                 if ( pPars->fVerbose && !pPars->fSolveAll ) Abc_Print( 1, "\n" );
                 Abc_Print( 1, "Simulated %d frames for %d rounds with %d restarts.  ", pPars->nFrames, nNumRestart * pPars->nRestart + r, nNumRestart );
@@ -1090,7 +1090,7 @@ int Ssw_RarSimulate( Aig_Man_t * pAig, Ssw_RarPars_t * pPars )
                 Abc_Print( 1, "Rounds =%6d   ",  nNumRestart * pPars->nRestart + ((r==-1)?0:r) );
                 Abc_Print( 1, "Frames =%6d   ", (nNumRestart * pPars->nRestart + r) * pPars->nFrames );
                 Abc_Print( 1, "CEX =%6d (%6.2f %%)   ", pPars->nSolved, 100.0*pPars->nSolved/Saig_ManPoNum(p->pAig) );
-                Abc_PrintTime( 1, "Time", clock() - clkTotal );
+                Abc_PrintTime( 1, "Time", Abc_Clock() - clkTotal );
             }
             else
                 Abc_Print( 1, "." );
@@ -1108,13 +1108,13 @@ finish:
     {
         if ( pPars->fVerbose && !pPars->fSolveAll ) Abc_Print( 1, "\n" );
         Abc_Print( 1, "Simulation of %d frames for %d rounds with %d restarts asserted %d (out of %d) POs.    ", pPars->nFrames, nNumRestart * pPars->nRestart + r, nNumRestart, pPars->nSolved, Saig_ManPoNum(p->pAig) );
-        Abc_PrintTime( 1, "Time", clock() - clkTotal );
+        Abc_PrintTime( 1, "Time", Abc_Clock() - clkTotal );
     }
     else if ( r == pPars->nRounds && f == pPars->nFrames )
     {
         if ( pPars->fVerbose ) Abc_Print( 1, "\n" );
         Abc_Print( 1, "Simulation of %d frames for %d rounds with %d restarts did not assert POs.    ", pPars->nFrames, nNumRestart * pPars->nRestart + r, nNumRestart );
-        Abc_PrintTime( 1, "Time", clock() - clkTotal );
+        Abc_PrintTime( 1, "Time", Abc_Clock() - clkTotal );
     }
     // cleanup
     Ssw_RarManStop( p );
@@ -1161,8 +1161,8 @@ int Ssw_RarSignalFilter( Aig_Man_t * pAig, Ssw_RarPars_t * pPars )
 {
     Ssw_RarMan_t * p;
     int r, f = -1, i, k;
-    clock_t clkTotal = clock();
-    clock_t nTimeToStop = pPars->TimeOut ? pPars->TimeOut * CLOCKS_PER_SEC + clock(): 0;
+    abctime clkTotal = Abc_Clock();
+    abctime nTimeToStop = pPars->TimeOut ? pPars->TimeOut * CLOCKS_PER_SEC + Abc_Clock(): 0;
     int nNumRestart = 0;
     int nSavedSeed = pPars->nRandSeed;
     int RetValue = -1;
@@ -1234,12 +1234,12 @@ int Ssw_RarSignalFilter( Aig_Man_t * pAig, Ssw_RarPars_t * pPars )
                 pAig->pSeqModel = Ssw_RarDeriveCex( p, r * p->pPars->nFrames + f, p->iFailPo, p->iFailPat, 1 );
                 // print final report
                 Abc_Print( 1, "Output %d of miter \"%s\" was asserted in frame %d.  ", pAig->pSeqModel->iPo, pAig->pName, pAig->pSeqModel->iFrame );
-                Abc_PrintTime( 1, "Time", clock() - clkTotal );
+                Abc_PrintTime( 1, "Time", Abc_Clock() - clkTotal );
                 RetValue = 0;
                 goto finish;
             }
             // check timeout
-            if ( pPars->TimeOut && clock() > nTimeToStop )
+            if ( pPars->TimeOut && Abc_Clock() > nTimeToStop )
             {
                 if ( pPars->fVerbose ) Abc_Print( 1, "\n" );
                 Abc_Print( 1, "Simulated %d frames for %d rounds with %d restarts.  ", pPars->nFrames, nNumRestart * pPars->nRestart + r, nNumRestart );
@@ -1279,7 +1279,7 @@ finish:
         if ( !pPars->fVerbose )
             Abc_Print( 1, "%s", Abc_FrameIsBatchMode() ? "\n" : "\r" );
         Abc_Print( 1, "Simulation of %d frames for %d rounds with %d restarts did not assert POs.    ", pPars->nFrames, nNumRestart * pPars->nRestart + r, nNumRestart );
-        Abc_PrintTime( 1, "Time", clock() - clkTotal );
+        Abc_PrintTime( 1, "Time", Abc_Clock() - clkTotal );
     }
     // cleanup
     Ssw_RarManStop( p );
diff --git a/src/proof/ssw/sswRarity2.c b/src/proof/ssw/sswRarity2.c
index f6b2c319..01f288c1 100644
--- a/src/proof/ssw/sswRarity2.c
+++ b/src/proof/ssw/sswRarity2.c
@@ -309,8 +309,8 @@ int Ssw_RarSimulate2( Aig_Man_t * pAig, int nFrames, int nWords, int nBinSize, i
     int fMiter = 1;
     Ssw_RarMan_t * p;
     int r;
-    clock_t clk, clkTotal = clock();
-    clock_t nTimeToStop = TimeOut ? TimeOut * CLOCKS_PER_SEC + clock(): 0;
+    abctime clk, clkTotal = Abc_Clock();
+    abctime nTimeToStop = TimeOut ? TimeOut * CLOCKS_PER_SEC + Abc_Clock(): 0;
     int RetValue = -1;
     assert( Aig_ManRegNum(pAig) > 0 );
     assert( Aig_ManConstrNum(pAig) == 0 );
@@ -331,7 +331,7 @@ int Ssw_RarSimulate2( Aig_Man_t * pAig, int nFrames, int nWords, int nBinSize, i
     // perform simulation rounds
     for ( r = 0; r < nRounds; r++ )
     {
-        clk = clock();
+        clk = Abc_Clock();
         // simulate
         Ssw_SmlSimulateOne( p->pSml );
         if ( fMiter && Ssw_SmlCheckNonConstOutputs(p->pSml) )
@@ -349,11 +349,11 @@ int Ssw_RarSimulate2( Aig_Man_t * pAig, int nFrames, int nWords, int nBinSize, i
         if ( fVerbose )
         {
 //            Abc_Print( 1, "Round %3d:  ", r );
-//            Abc_PrintTime( 1, "Time", clock() - clk );
+//            Abc_PrintTime( 1, "Time", Abc_Clock() - clk );
             Abc_Print( 1, "." );
         }
         // check timeout
-        if ( TimeOut && clock() > nTimeToStop )
+        if ( TimeOut && Abc_Clock() > nTimeToStop )
         {
             if ( fVerbose ) Abc_Print( 1, "\n" );
             Abc_Print( 1, "Reached timeout (%d seconds).\n",  TimeOut );
@@ -364,7 +364,7 @@ int Ssw_RarSimulate2( Aig_Man_t * pAig, int nFrames, int nWords, int nBinSize, i
     {
         if ( fVerbose ) Abc_Print( 1, "\n" );
         Abc_Print( 1, "Simulation did not assert POs in the first %d frames.  ", nRounds * nFrames );
-        Abc_PrintTime( 1, "Time", clock() - clkTotal );
+        Abc_PrintTime( 1, "Time", Abc_Clock() - clkTotal );
     }
     // cleanup
     Ssw_RarManStop( p );
@@ -388,8 +388,8 @@ int Ssw_RarSignalFilter2( Aig_Man_t * pAig, int nFrames, int nWords, int nBinSiz
     int fMiter = 0;
     Ssw_RarMan_t * p;
     int r, i, k;
-    clock_t clkTotal = clock();
-    clock_t nTimeToStop = TimeOut ? TimeOut * CLOCKS_PER_SEC + clock(): 0;
+    abctime clkTotal = Abc_Clock();
+    abctime nTimeToStop = TimeOut ? TimeOut * CLOCKS_PER_SEC + Abc_Clock(): 0;
     int RetValue = -1;
     assert( Aig_ManRegNum(pAig) > 0 );
     assert( Aig_ManConstrNum(pAig) == 0 );
@@ -462,7 +462,7 @@ int Ssw_RarSignalFilter2( Aig_Man_t * pAig, int nFrames, int nWords, int nBinSiz
         Ssw_RarTransferPatterns( p, p->vInits );
         Ssw_SmlInitializeSpecial( p->pSml, p->vInits );
         // check timeout
-        if ( TimeOut && clock() > nTimeToStop )
+        if ( TimeOut && Abc_Clock() > nTimeToStop )
         {
             if ( fVerbose ) Abc_Print( 1, "\n" );
             Abc_Print( 1, "Reached timeout (%d seconds).\n",  TimeOut );
@@ -472,7 +472,7 @@ int Ssw_RarSignalFilter2( Aig_Man_t * pAig, int nFrames, int nWords, int nBinSiz
     if ( r == nRounds )
     {
         Abc_Print( 1, "Simulation did not assert POs in the first %d frames.  ", nRounds * nFrames );
-        Abc_PrintTime( 1, "Time", clock() - clkTotal );
+        Abc_PrintTime( 1, "Time", Abc_Clock() - clkTotal );
     }
     // cleanup
     Ssw_RarManStop( p );
diff --git a/src/proof/ssw/sswSat.c b/src/proof/ssw/sswSat.c
index e5971a64..59ed6945 100644
--- a/src/proof/ssw/sswSat.c
+++ b/src/proof/ssw/sswSat.c
@@ -46,7 +46,7 @@ int Ssw_NodesAreEquiv( Ssw_Man_t * p, Aig_Obj_t * pOld, Aig_Obj_t * pNew )
 {
     int nBTLimit = p->pPars->nBTLimit;
     int pLits[3], nLits, RetValue, RetValue1;
-    clock_t clk;//, status;
+    abctime clk;//, status;
     p->nSatCalls++;
     p->pMSat->nSolverCalls++;
 
@@ -80,13 +80,13 @@ int Ssw_NodesAreEquiv( Ssw_Man_t * p, Aig_Obj_t * pOld, Aig_Obj_t * pNew )
         assert( RetValue != 0 );
     }
 
-clk = clock();
+clk = Abc_Clock();
     RetValue1 = sat_solver_solve( p->pMSat->pSat, pLits, pLits + nLits, 
         (ABC_INT64_T)nBTLimit, (ABC_INT64_T)0, (ABC_INT64_T)0, (ABC_INT64_T)0 );
-p->timeSat += clock() - clk;
+p->timeSat += Abc_Clock() - clk;
     if ( RetValue1 == l_False )
     {
-p->timeSatUnsat += clock() - clk;
+p->timeSatUnsat += Abc_Clock() - clk;
         if ( nLits == 2 )
         {
             pLits[0] = lit_neg( pLits[0] );
@@ -105,13 +105,13 @@ p->timeSatUnsat += clock() - clk;
     }
     else if ( RetValue1 == l_True )
     {
-p->timeSatSat += clock() - clk;
+p->timeSatSat += Abc_Clock() - clk;
         p->nSatCallsSat++;
         return 0;
     }
     else // if ( RetValue1 == l_Undef )
     {
-p->timeSatUndec += clock() - clk;
+p->timeSatUndec += Abc_Clock() - clk;
         p->nSatFailsReal++;
         return -1;
     }
@@ -142,13 +142,13 @@ p->timeSatUndec += clock() - clk;
         assert( RetValue != 0 );
     }
 
-clk = clock();
+clk = Abc_Clock();
     RetValue1 = sat_solver_solve( p->pMSat->pSat, pLits, pLits + nLits, 
         (ABC_INT64_T)nBTLimit, (ABC_INT64_T)0, (ABC_INT64_T)0, (ABC_INT64_T)0 );
-p->timeSat += clock() - clk;
+p->timeSat += Abc_Clock() - clk;
     if ( RetValue1 == l_False )
     {
-p->timeSatUnsat += clock() - clk;
+p->timeSatUnsat += Abc_Clock() - clk;
         if ( nLits == 2 )
         {
             pLits[0] = lit_neg( pLits[0] );
@@ -167,13 +167,13 @@ p->timeSatUnsat += clock() - clk;
     }
     else if ( RetValue1 == l_True )
     {
-p->timeSatSat += clock() - clk;
+p->timeSatSat += Abc_Clock() - clk;
         p->nSatCallsSat++;
         return 0;
     }
     else // if ( RetValue1 == l_Undef )
     {
-p->timeSatUndec += clock() - clk;
+p->timeSatUndec += Abc_Clock() - clk;
         p->nSatFailsReal++;
         return -1;
     }
diff --git a/src/proof/ssw/sswSemi.c b/src/proof/ssw/sswSemi.c
index 822f63f5..d5af1394 100644
--- a/src/proof/ssw/sswSemi.c
+++ b/src/proof/ssw/sswSemi.c
@@ -180,8 +180,8 @@ int Ssw_ManFilterBmc( Ssw_Sem_t * pBmc, int iPat, int fCheckTargets )
     Aig_Obj_t * pObj, * pObjNew, * pObjLi, * pObjLo;
     unsigned * pInfo;
     int i, f, RetValue, fFirst = 0;
-    clock_t clk;
-clk = clock();
+    abctime clk;
+clk = Abc_Clock();
 
     // start initialized timeframes
     p->pFrames = Aig_ManStart( Aig_ManObjNumMax(p->pAig) * 3 );
@@ -243,7 +243,7 @@ clk = clock();
 
     // cleanup
     Ssw_ClassesCheck( p->ppClasses );
-p->timeBmc += clock() - clk;
+p->timeBmc += Abc_Clock() - clk;
     return RetValue;
 }
 
@@ -262,7 +262,7 @@ int Ssw_FilterUsingSemi( Ssw_Man_t * pMan, int fCheckTargets, int nConfMax, int
 {
     Ssw_Sem_t * p;
     int RetValue, Frames, Iter;
-    clock_t clk = clock();
+    abctime clk = Abc_Clock();
     p = Ssw_SemManStart( pMan, nConfMax, fVerbose );
     if ( fCheckTargets && Ssw_SemCheckTargets( p ) )
     {
@@ -279,7 +279,7 @@ int Ssw_FilterUsingSemi( Ssw_Man_t * pMan, int fCheckTargets, int nConfMax, int
     RetValue = 0;
     for ( Iter = 0; Iter < p->nPatterns; Iter++ )
     {
-clk = clock();
+clk = Abc_Clock();
         pMan->pMSat = Ssw_SatStart( 0 );
         Frames = Ssw_ManFilterBmc( p, Iter, fCheckTargets );
         if ( fVerbose )
@@ -288,7 +288,7 @@ clk = clock();
                 Iter, Ssw_ClassesCand1Num(p->pMan->ppClasses), Ssw_ClassesClassNum(p->pMan->ppClasses),
                 Aig_ManNodeNum(p->pMan->pFrames), Frames, (int)p->pMan->pMSat->pSat->stats.conflicts, p->nPatterns,
                 p->pMan->nSatFailsReal? "f" : " " );
-            ABC_PRT( "T", clock() - clk );
+            ABC_PRT( "T", Abc_Clock() - clk );
         }
         Ssw_ManCleanup( p->pMan );
         if ( fCheckTargets && Ssw_SemCheckTargets( p ) )
diff --git a/src/proof/ssw/sswSim.c b/src/proof/ssw/sswSim.c
index 469af654..c458855d 100644
--- a/src/proof/ssw/sswSim.c
+++ b/src/proof/ssw/sswSim.c
@@ -38,7 +38,7 @@ struct Ssw_Sml_t_
     int              nWordsPref;        // the number of word in the prefix
     int              fNonConstOut;      // have seen a non-const-0 output during simulation
     int              nSimRounds;        // statistics
-    clock_t          timeSim;           // statistics
+    abctime          timeSim;           // statistics
     unsigned         pData[0];          // simulation data for the nodes
 };
 
@@ -1006,8 +1006,8 @@ void Ssw_SmlSimulateOne( Ssw_Sml_t * p )
 {
     Aig_Obj_t * pObj, * pObjLi, * pObjLo;
     int f, i;
-    clock_t clk;
-clk = clock();
+    abctime clk;
+clk = Abc_Clock();
     for ( f = 0; f < p->nFrames; f++ )
     {
         // simulate the nodes
@@ -1026,7 +1026,7 @@ clk = clock();
         Saig_ManForEachLiLo( p->pAig, pObjLi, pObjLo, i )
             Ssw_SmlNodeTransferNext( p, pObjLi, pObjLo, f );
     }
-p->timeSim += clock() - clk;
+p->timeSim += Abc_Clock() - clk;
 p->nSimRounds++;
 }
 
@@ -1118,8 +1118,8 @@ void Ssw_SmlSimulateOneFrame( Ssw_Sml_t * p )
 {
     Aig_Obj_t * pObj, * pObjLi, * pObjLo;
     int i;
-    clock_t clk;
-clk = clock();
+    abctime clk;
+clk = Abc_Clock();
     // simulate the nodes
     Aig_ManForEachNode( p->pAig, pObj, i )
         Ssw_SmlNodeSimulate( p, pObj, 0 );
@@ -1129,7 +1129,7 @@ clk = clock();
     // copy simulation info into the inputs
     Saig_ManForEachLiLo( p->pAig, pObjLi, pObjLo, i )
         Ssw_SmlNodeTransferNext( p, pObjLi, pObjLo, 0 );
-p->timeSim += clock() - clk;
+p->timeSim += Abc_Clock() - clk;
 p->nSimRounds++;
 }
 
diff --git a/src/proof/ssw/sswSimSat.c b/src/proof/ssw/sswSimSat.c
index 6e5944d1..74c65c00 100644
--- a/src/proof/ssw/sswSimSat.c
+++ b/src/proof/ssw/sswSimSat.c
@@ -46,7 +46,7 @@ void Ssw_ManResimulateBit( Ssw_Man_t * p, Aig_Obj_t * pCand, Aig_Obj_t * pRepr )
 {
     Aig_Obj_t * pObj;
     int i, RetValue1, RetValue2;
-    clock_t clk = clock();
+    abctime clk = Abc_Clock();
     // set the PI simulation information
     Aig_ManConst1(p->pAig)->fMarkB = 1;
     Aig_ManForEachCi( p->pAig, pObj, i )
@@ -75,7 +75,7 @@ void Ssw_ManResimulateBit( Ssw_Man_t * p, Aig_Obj_t * pCand, Aig_Obj_t * pRepr )
                 Abc_Print( 1, "\nSsw_ManResimulateBit() Error: RetValue2 does not hold.\n" );
         }
     }
-p->timeSimSat += clock() - clk;
+p->timeSimSat += Abc_Clock() - clk;
 }
 
 /**Function*************************************************************
@@ -92,7 +92,7 @@ p->timeSimSat += clock() - clk;
 void Ssw_ManResimulateWord( Ssw_Man_t * p, Aig_Obj_t * pCand, Aig_Obj_t * pRepr, int f )
 {
     int RetValue1, RetValue2;
-    clock_t clk = clock();
+    abctime clk = Abc_Clock();
     // set the PI simulation information
     Ssw_SmlAssignDist1Plus( p->pSml, p->pPatWords );
     // simulate internal nodes
@@ -113,7 +113,7 @@ void Ssw_ManResimulateWord( Ssw_Man_t * p, Aig_Obj_t * pCand, Aig_Obj_t * pRepr,
         if ( RetValue2 == 0 )
             Abc_Print( 1, "\nSsw_ManResimulateWord() Error: RetValue2 does not hold.\n" );
     }
-p->timeSimSat += clock() - clk;
+p->timeSimSat += Abc_Clock() - clk;
 }
 
 ////////////////////////////////////////////////////////////////////////
diff --git a/src/proof/ssw/sswSweep.c b/src/proof/ssw/sswSweep.c
index bccc6aa4..6db673cc 100644
--- a/src/proof/ssw/sswSweep.c
+++ b/src/proof/ssw/sswSweep.c
@@ -188,7 +188,7 @@ int Ssw_ManSweepNode( Ssw_Man_t * p, Aig_Obj_t * pObj, int f, int fBmc, Vec_Int_
 {
     Aig_Obj_t * pObjRepr, * pObjFraig, * pObjFraig2, * pObjReprFraig;
     int RetValue;
-    clock_t clk;
+    abctime clk;
     // get representative of this class
     pObjRepr = Aig_ObjRepr( p->pAig, pObj );
     if ( pObjRepr == NULL )
@@ -206,10 +206,10 @@ int Ssw_ManSweepNode( Ssw_Man_t * p, Aig_Obj_t * pObj, int f, int fBmc, Vec_Int_
     // add constraints on demand
     if ( !fBmc && p->pPars->fDynamic )
     {
-clk = clock();
+clk = Abc_Clock();
         Ssw_ManLoadSolver( p, pObjRepr, pObj );
         p->nRecycleCalls++;
-p->timeMarkCones += clock() - clk;
+p->timeMarkCones += Abc_Clock() - clk;
     }
     // call equivalence checking
     if ( Aig_Regular(pObjFraig) != Aig_ManConst1(p->pFrames) )
@@ -269,8 +269,8 @@ int Ssw_ManSweepBmc( Ssw_Man_t * p )
     Bar_Progress_t * pProgress = NULL;
     Aig_Obj_t * pObj, * pObjNew, * pObjLi, * pObjLo;
     int i, f;
-    clock_t clk;
-clk = clock();
+    abctime clk;
+clk = Abc_Clock();
 
     // start initialized timeframes
     p->pFrames = Aig_ManStart( Aig_ManObjNumMax(p->pAig) * p->pPars->nFramesK );
@@ -315,7 +315,7 @@ clk = clock();
 
     // cleanup
 //    Ssw_ClassesCheck( p->ppClasses );
-p->timeBmc += clock() - clk;
+p->timeBmc += Abc_Clock() - clk;
     return p->fRefined;
 }
 
@@ -368,11 +368,11 @@ int Ssw_ManSweep( Ssw_Man_t * p )
     Bar_Progress_t * pProgress = NULL;
     Aig_Obj_t * pObj, * pObj2, * pObjNew;
     int nConstrPairs, i, f;
-    clock_t clk;
+    abctime clk;
     Vec_Int_t * vDisproved;
 
     // perform speculative reduction
-clk = clock();
+clk = Abc_Clock();
     // create timeframes
     p->pFrames = Ssw_FramesWithClasses( p );
     // add constants
@@ -397,7 +397,7 @@ clk = clock();
     Ssw_ObjSetFrame( p, Aig_ManConst1(p->pAig), f, Aig_ManConst1(p->pFrames) );
     Saig_ManForEachPi( p->pAig, pObj, i )
         Ssw_ObjSetFrame( p, pObj, f, Aig_ObjCreateCi(p->pFrames) );
-p->timeReduce += clock() - clk;
+p->timeReduce += Abc_Clock() - clk;
 
     // sweep internal nodes
     p->fRefined = 0;