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authorAlan Mishchenko <alanmi@berkeley.edu>2007-02-11 08:01:00 -0800
committerAlan Mishchenko <alanmi@berkeley.edu>2007-02-11 08:01:00 -0800
commit5f3e4c0fe21ba5e24db0c187a616a28afc0dabae (patch)
tree30a84432ebcd370992d24ffced01ac0034072f30 /src/base
parentb9e0c95b690cf363f99b182ba8e7688aef091d95 (diff)
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Version abc70211
Diffstat (limited to 'src/base')
-rw-r--r--src/base/abc/abcCheck.c45
-rw-r--r--src/base/abc/abcHie.c100
-rw-r--r--src/base/abc/abcObj.c10
-rw-r--r--src/base/abci/abcPrint.c3
-rw-r--r--src/base/io/io.c6
-rw-r--r--src/base/io/io.h8
-rw-r--r--src/base/io/ioReadVerilog.c720
-rw-r--r--src/base/io/ioUtil.c92
-rw-r--r--src/base/io/ioWriteBlif.c1
-rw-r--r--src/base/io/ioWriteVerAux.c444
-rw-r--r--src/base/io/ioWriteVerilog.c (renamed from src/base/io/ioWriteVer.c)434
-rw-r--r--src/base/io/module.make4
-rw-r--r--src/base/ver/ver.h1
-rw-r--r--src/base/ver/verCore.c263
-rw-r--r--src/base/ver/verFormula.c5
-rw-r--r--src/base/ver/verParse.c2
-rw-r--r--src/base/ver/verStream.c6
17 files changed, 554 insertions, 1590 deletions
diff --git a/src/base/abc/abcCheck.c b/src/base/abc/abcCheck.c
index 72597881..e159bcab 100644
--- a/src/base/abc/abcCheck.c
+++ b/src/base/abc/abcCheck.c
@@ -140,6 +140,9 @@ bool Abc_NtkDoCheck( Abc_Ntk_t * pNtk )
if ( !Abc_NtkCheckPos( pNtk ) )
return 0;
+ if ( Abc_NtkHasBlackbox(pNtk) )
+ return 1;
+
// check the connectivity of objects
Abc_NtkForEachObj( pNtk, pObj, i )
if ( !Abc_NtkCheckObj( pNtk, pObj ) )
@@ -236,41 +239,27 @@ bool Abc_NtkCheckNames( Abc_Ntk_t * pNtk )
Vec_Int_t * vNameIds;
char * pName;
int i, NameId;
-/*
+
if ( Abc_NtkIsNetlist(pNtk) )
- {
+ return 1;
- // check that each net has a name
- Abc_NtkForEachNet( pNtk, pObj, i )
+ // check that each CI/CO has a name
+ Abc_NtkForEachCi( pNtk, pObj, i )
+ {
+ pObj = Abc_ObjFanout0Ntk(pObj);
+ if ( Nm_ManFindNameById(pObj->pNtk->pManName, pObj->Id) == NULL )
{
- if ( Nm_ManFindNameById(pObj->pNtk->pManName, pObj->Id) )
- {
- fprintf( stdout, "NetworkCheck: Net \"%s\" has different name in the name table and at the data pointer.\n", pObj->pData );
- return 0;
- }
+ fprintf( stdout, "NetworkCheck: CI with ID %d is in the network but not in the name table.\n", pObj->Id );
+ return 0;
}
}
- else
-*/
+ Abc_NtkForEachCo( pNtk, pObj, i )
{
- // check that each CI/CO has a name
- Abc_NtkForEachCi( pNtk, pObj, i )
+ pObj = Abc_ObjFanin0Ntk(pObj);
+ if ( Nm_ManFindNameById(pObj->pNtk->pManName, pObj->Id) == NULL )
{
- pObj = Abc_ObjFanout0Ntk(pObj);
- if ( Nm_ManFindNameById(pObj->pNtk->pManName, pObj->Id) == NULL )
- {
- fprintf( stdout, "NetworkCheck: CI with ID %d is in the network but not in the name table.\n", pObj->Id );
- return 0;
- }
- }
- Abc_NtkForEachCo( pNtk, pObj, i )
- {
- pObj = Abc_ObjFanin0Ntk(pObj);
- if ( Nm_ManFindNameById(pObj->pNtk->pManName, pObj->Id) == NULL )
- {
- fprintf( stdout, "NetworkCheck: CO with ID %d is in the network but not in the name table.\n", pObj->Id );
- return 0;
- }
+ fprintf( stdout, "NetworkCheck: CO with ID %d is in the network but not in the name table.\n", pObj->Id );
+ return 0;
}
}
diff --git a/src/base/abc/abcHie.c b/src/base/abc/abcHie.c
index a804203f..1047650f 100644
--- a/src/base/abc/abcHie.c
+++ b/src/base/abc/abcHie.c
@@ -265,7 +265,7 @@ Abc_Ntk_t * Abc_NtkConvertBlackboxes( Abc_Ntk_t * pNtk )
Abc_ObjForEachFanin( pObj, pTerm, k )
{
pNet = Abc_ObjFanin0(pTerm);
- if ( pNet->pCopy )
+ if ( pNet->pCopy && !Abc_ObjIsCi(Abc_ObjFanin0(pNet)) )
{
Abc_NodeSetTravIdCurrent( pTerm );
continue;
@@ -315,13 +315,14 @@ Abc_Ntk_t * Abc_NtkConvertBlackboxes( Abc_Ntk_t * pNtk )
***********************************************************************/
Abc_Ntk_t * Abc_NtkInsertNewLogic( Abc_Ntk_t * pNtkH, Abc_Ntk_t * pNtkL )
{
+ Abc_Lib_t * pDesign;
Abc_Ntk_t * pNtkNew;
Abc_Obj_t * pObjH, * pObjL, * pNetH, * pNetL, * pTermH;
int i, k;
assert( Abc_NtkIsNetlist(pNtkH) );
assert( Abc_NtkWhiteboxNum(pNtkH) == 0 );
- assert( Abc_NtkBlackboxNum(pNtkL) > 0 );
+ assert( Abc_NtkBlackboxNum(pNtkH) > 0 );
assert( Abc_NtkIsNetlist(pNtkL) );
assert( Abc_NtkWhiteboxNum(pNtkL) == 0 );
@@ -343,38 +344,73 @@ Abc_Ntk_t * Abc_NtkInsertNewLogic( Abc_Ntk_t * pNtkH, Abc_Ntk_t * pNtkL )
pNetL = Abc_NtkFindNet( pNtkL, Abc_ObjName(pNetH) );
if ( pNetL == NULL || !Abc_ObjIsPi( Abc_ObjFanin0(pNetL) ) )
{
- printf( "There is no PI corresponding to the PI %s.\n", Abc_ObjName(pNetH) );
+ printf( "Error in Abc_NtkInsertNewLogic(): There is no PI corresponding to the PI %s.\n", Abc_ObjName(pNetH) );
+ Abc_NtkDelete( pNtkNew );
+ return NULL;
+ }
+ if ( pNetL->pCopy )
+ {
+ printf( "Error in Abc_NtkInsertNewLogic(): Primary input %s is repeated twice.\n", Abc_ObjName(pNetH) );
Abc_NtkDelete( pNtkNew );
return NULL;
}
- // duplicate
+ // create the new net
pNetL->pCopy = Abc_NtkFindOrCreateNet( pNtkNew, Abc_ObjName(pNetH) );
Abc_NtkDupObj( pNtkNew, Abc_ObjFanin0(pNetL), 0 );
}
+
+ // make sure every BB has a PI/PO in the processed network
+ Abc_NtkForEachBlackbox( pNtkH, pObjH, i )
+ {
+ // duplicate the box
+ Abc_NtkDupBox( pNtkNew, pObjH, 0 );
+ pObjH->pCopy->pData = pObjH->pData;
+ // create PIs
+ Abc_ObjForEachFanout( pObjH, pTermH, k )
+ {
+ pNetH = Abc_ObjFanout0( pTermH );
+ pNetL = Abc_NtkFindNet( pNtkL, Abc_ObjName(pNetH) );
+ if ( pNetL == NULL || !Abc_ObjIsPi( Abc_ObjFanin0(pNetL) ) )
+ {
+ printf( "Error in Abc_NtkInsertNewLogic(): There is no PI corresponding to the inpout %s of blackbox %s.\n", Abc_ObjName(pNetH), Abc_ObjName(pObjH) );
+ Abc_NtkDelete( pNtkNew );
+ return NULL;
+ }
+ if ( pNetL->pCopy )
+ {
+ printf( "Error in Abc_NtkInsertNewLogic(): Box output %s is repeated twice.\n", Abc_ObjName(pNetH) );
+ Abc_NtkDelete( pNtkNew );
+ return NULL;
+ }
+ // create net and map the PI
+ pNetL->pCopy = Abc_NtkFindOrCreateNet( pNtkNew, Abc_ObjName(pNetH) );
+ Abc_ObjFanin0(pNetL)->pCopy = pTermH->pCopy;
+ }
+ }
+
Abc_NtkForEachPo( pNtkH, pObjH, i )
{
pNetH = Abc_ObjFanin0(pObjH);
pNetL = Abc_NtkFindNet( pNtkL, Abc_ObjName(pNetH) );
if ( pNetL == NULL || !Abc_ObjIsPo( Abc_ObjFanout0(pNetL) ) )
{
- printf( "There is no PO corresponding to the PO %s.\n", Abc_ObjName(pNetH) );
+ printf( "Error in Abc_NtkInsertNewLogic(): There is no PO corresponding to the PO %s.\n", Abc_ObjName(pNetH) );
Abc_NtkDelete( pNtkNew );
return NULL;
}
- // duplicate
+ if ( pNetL->pCopy )
+ continue;
+ // create the new net
pNetL->pCopy = Abc_NtkFindOrCreateNet( pNtkNew, Abc_ObjName(pNetH) );
Abc_NtkDupObj( pNtkNew, Abc_ObjFanout0(pNetL), 0 );
}
-
- // make sure every BB has a PI/PO in the processed network
Abc_NtkForEachBlackbox( pNtkH, pObjH, i )
{
- // duplicate the box
- Abc_NtkDupObj( pNtkNew, pObjH, 1 );
- // look and fanins/fanouts of the box
Abc_ObjForEachFanin( pObjH, pTermH, k )
{
+ char * pName;
pNetH = Abc_ObjFanin0( pTermH );
+ pName = Abc_ObjName(pNetH);
pNetL = Abc_NtkFindNet( pNtkL, Abc_ObjName(pNetH) );
if ( pNetL == NULL || !Abc_ObjIsPo( Abc_ObjFanout0(pNetL) ) )
{
@@ -382,39 +418,39 @@ Abc_Ntk_t * Abc_NtkInsertNewLogic( Abc_Ntk_t * pNtkH, Abc_Ntk_t * pNtkL )
Abc_NtkDelete( pNtkNew );
return NULL;
}
- // duplicate
- pNetL->pCopy = Abc_NtkFindOrCreateNet( pNtkNew, Abc_ObjName(pNetH) );
- Abc_NtkDupObj( pNtkNew, Abc_ObjFanout0(pNetL), 0 );
- // connect
- Abc_ObjAddFanin( pObjH->pCopy, Abc_ObjFanout0(pNetL)->pCopy );
- }
- Abc_ObjForEachFanout( pObjH, pTermH, k )
- {
- pNetH = Abc_ObjFanout0( pTermH );
- pNetL = Abc_NtkFindNet( pNtkL, Abc_ObjName(pNetH) );
- if ( pNetL == NULL || !Abc_ObjIsPi( Abc_ObjFanin0(pNetL) ) )
+ // create net and map the PO
+ if ( pNetL->pCopy )
{
- printf( "There is no PI corresponding to the inpout %s of blackbox %s.\n", Abc_ObjName(pNetH), Abc_ObjName(pObjH) );
- Abc_NtkDelete( pNtkNew );
- return NULL;
+ if ( Abc_ObjFanout0(pNetL)->pCopy == NULL )
+ Abc_ObjFanout0(pNetL)->pCopy = pTermH->pCopy;
+ else
+ Abc_ObjAddFanin( pTermH->pCopy, pNetL->pCopy );
+ continue;
}
- // duplicate
pNetL->pCopy = Abc_NtkFindOrCreateNet( pNtkNew, Abc_ObjName(pNetH) );
- Abc_NtkDupObj( pNtkNew, Abc_ObjFanin0(pNetL), 0 );
- // connect
- Abc_ObjAddFanin( Abc_ObjFanin0(pNetL)->pCopy, pObjH->pCopy );
+ Abc_ObjFanout0(pNetL)->pCopy = pTermH->pCopy;
}
}
// duplicate other objects of the logic network
Abc_NtkForEachObj( pNtkL, pObjL, i )
- if ( pObjL->pCopy )
- Abc_NtkDupObj( pNtkNew, pObjL, 0 );
+ if ( pObjL->pCopy == NULL && !Abc_ObjIsPo(pObjL) ) // skip POs feeding into PIs
+ Abc_NtkDupObj( pNtkNew, pObjL, Abc_ObjIsNet(pObjL) );
// connect objects
Abc_NtkForEachObj( pNtkL, pObjL, i )
Abc_ObjForEachFanin( pObjL, pNetL, k )
- Abc_ObjAddFanin( pObjL->pCopy, pNetL->pCopy );
+ if ( pObjL->pCopy )
+ Abc_ObjAddFanin( pObjL->pCopy, pNetL->pCopy );
+
+ // transfer the design
+ pDesign = pNtkH->pDesign; pNtkH->pDesign = NULL;
+ assert( Vec_PtrEntry( pDesign->vModules, 0 ) == pNtkH );
+ Vec_PtrWriteEntry( pDesign->vModules, 0, pNtkNew );
+ pNtkNew->pDesign = pDesign;
+
+//Abc_NtkPrintStats( stdout, pNtkH, 0 );
+//Abc_NtkPrintStats( stdout, pNtkNew, 0 );
// check integrity
if ( !Abc_NtkCheck( pNtkNew ) )
diff --git a/src/base/abc/abcObj.c b/src/base/abc/abcObj.c
index d55ccfcf..4931f238 100644
--- a/src/base/abc/abcObj.c
+++ b/src/base/abc/abcObj.c
@@ -329,7 +329,15 @@ Abc_Obj_t * Abc_NtkDupObj( Abc_Ntk_t * pNtkNew, Abc_Obj_t * pObj, int fCopyName
else if ( Abc_ObjIsCo(pObj) )
{
if ( !Abc_NtkIsNetlist(pNtkNew) )
- Abc_ObjAssignName( pObjNew, Abc_ObjName(Abc_ObjFanin0Ntk(pObj)), NULL );
+ {
+ if ( Abc_ObjIsPo(pObj) )
+ Abc_ObjAssignName( pObjNew, Abc_ObjName(Abc_ObjFanin0Ntk(pObj)), NULL );
+ else
+ {
+ assert( Abc_ObjIsLatch(Abc_ObjFanout0(pObj)) );
+ Abc_ObjAssignName( pObjNew, Abc_ObjName(pObj), NULL );
+ }
+ }
}
else if ( Abc_ObjIsBox(pObj) || Abc_ObjIsNet(pObj) )
Abc_ObjAssignName( pObjNew, Abc_ObjName(pObj), NULL );
diff --git a/src/base/abci/abcPrint.c b/src/base/abci/abcPrint.c
index 59ce1674..0a917bbb 100644
--- a/src/base/abci/abcPrint.c
+++ b/src/base/abci/abcPrint.c
@@ -62,7 +62,8 @@ void Abc_NtkPrintStats( FILE * pFile, Abc_Ntk_t * pNtk, int fFactored )
{
fprintf( pFile, " net = %5d", Abc_NtkNetNum(pNtk) );
fprintf( pFile, " nd = %5d", Abc_NtkNodeNum(pNtk) );
- fprintf( pFile, " box = %5d", Abc_NtkBoxNum(pNtk) );
+ fprintf( pFile, " wbox = %3d", Abc_NtkWhiteboxNum(pNtk) );
+ fprintf( pFile, " bbox = %3d", Abc_NtkBlackboxNum(pNtk) );
}
else if ( Abc_NtkIsStrash(pNtk) )
{
diff --git a/src/base/io/io.c b/src/base/io/io.c
index 64451118..e79e1857 100644
--- a/src/base/io/io.c
+++ b/src/base/io/io.c
@@ -85,7 +85,7 @@ void Io_Init( Abc_Frame_t * pAbc )
Cmd_CommandAdd( pAbc, "I/O", "read_eqn", IoCommandReadEqn, 1 );
Cmd_CommandAdd( pAbc, "I/O", "read_pla", IoCommandReadPla, 1 );
Cmd_CommandAdd( pAbc, "I/O", "read_truth", IoCommandReadTruth, 1 );
-// Cmd_CommandAdd( pAbc, "I/O", "read_verilog", IoCommandReadVerilog, 1 );
+ Cmd_CommandAdd( pAbc, "I/O", "read_verilog", IoCommandReadVerilog, 1 );
// Cmd_CommandAdd( pAbc, "I/O", "read_ver", IoCommandReadVer, 1 );
// Cmd_CommandAdd( pAbc, "I/O", "read_verlib", IoCommandReadVerLib, 0 );
@@ -103,7 +103,7 @@ void Io_Init( Abc_Frame_t * pAbc )
Cmd_CommandAdd( pAbc, "I/O", "write_gml", IoCommandWriteGml, 0 );
// Cmd_CommandAdd( pAbc, "I/O", "write_list", IoCommandWriteList, 0 );
Cmd_CommandAdd( pAbc, "I/O", "write_pla", IoCommandWritePla, 0 );
-// Cmd_CommandAdd( pAbc, "I/O", "write_verilog", IoCommandWriteVerilog, 0 );
+ Cmd_CommandAdd( pAbc, "I/O", "write_verilog", IoCommandWriteVerilog, 0 );
// Cmd_CommandAdd( pAbc, "I/O", "write_verlib", IoCommandWriteVerLib, 0 );
}
@@ -995,7 +995,7 @@ int IoCommandWriteHie( Abc_Frame_t * pAbc, int argc, char **argv )
pFileName = argv[globalUtilOptind+1];
// call the corresponding file writer
// Io_Write( pAbc->pNtkCur, pFileName, Io_ReadFileType(pFileName) );
- Io_WriteHie( pAbc->pNtkCur, pFileName, Io_ReadFileType(pFileName), pBaseName );
+ Io_WriteHie( pAbc->pNtkCur, pBaseName, pFileName );
return 0;
usage:
diff --git a/src/base/io/io.h b/src/base/io/io.h
index 91be5ee5..8ce7c690 100644
--- a/src/base/io/io.h
+++ b/src/base/io/io.h
@@ -82,10 +82,10 @@ extern Abc_Ntk_t * Io_ReadBench( char * pFileName, int fCheck );
extern Abc_Ntk_t * Io_ReadEdif( char * pFileName, int fCheck );
/*=== abcReadEqn.c ============================================================*/
extern Abc_Ntk_t * Io_ReadEqn( char * pFileName, int fCheck );
-/*=== abcReadVerilog.c ========================================================*/
-extern Abc_Ntk_t * Io_ReadVerilog( char * pFileName, int fCheck );
/*=== abcReadPla.c ============================================================*/
extern Abc_Ntk_t * Io_ReadPla( char * pFileName, int fCheck );
+/*=== abcReadVerilog.c ========================================================*/
+extern Abc_Ntk_t * Io_ReadVerilog( char * pFileName, int fCheck );
/*=== abcWriteAiger.c =========================================================*/
extern void Io_WriteAiger( Abc_Ntk_t * pNtk, char * pFileName );
/*=== abcWriteBaf.c ===========================================================*/
@@ -114,14 +114,14 @@ extern void Io_WriteList( Abc_Ntk_t * pNtk, char * pFileName, int
/*=== abcWritePla.c ===========================================================*/
extern int Io_WritePla( Abc_Ntk_t * pNtk, char * FileName );
/*=== abcWriteVerilog.c =======================================================*/
-extern void Io_WriteVerilog( Abc_Ntk_t * pNtk, char * FileName, int fVerLibStyle );
+extern void Io_WriteVerilog( Abc_Ntk_t * pNtk, char * FileName );
/*=== abcUtil.c ===============================================================*/
extern Io_FileType_t Io_ReadFileType( char * pFileName );
extern Abc_Ntk_t * Io_ReadNetlist( char * pFileName, Io_FileType_t FileType, int fCheck );
extern Abc_Ntk_t * Io_Read( char * pFileName, Io_FileType_t FileType, int fCheck );
extern Abc_Ntk_t * Io_ReadHie( char * pFileName, Io_FileType_t FileType, int fCheck );
extern void Io_Write( Abc_Ntk_t * pNtk, char * pFileName, Io_FileType_t FileType );
-extern void Io_WriteHie( Abc_Ntk_t * pNtk, char * pFileName, Io_FileType_t FileType, char * pBaseName );
+extern void Io_WriteHie( Abc_Ntk_t * pNtk, char * pBaseName, char * pFileName );
extern Abc_Obj_t * Io_ReadCreatePi( Abc_Ntk_t * pNtk, char * pName );
extern Abc_Obj_t * Io_ReadCreatePo( Abc_Ntk_t * pNtk, char * pName );
extern Abc_Obj_t * Io_ReadCreateAssert( Abc_Ntk_t * pNtk, char * pName );
diff --git a/src/base/io/ioReadVerilog.c b/src/base/io/ioReadVerilog.c
index 4550d286..eda2d0b0 100644
--- a/src/base/io/ioReadVerilog.c
+++ b/src/base/io/ioReadVerilog.c
@@ -6,7 +6,7 @@
PackageName [Command processing package.]
- Synopsis [Procedures to read a subset of structural Verilog from IWLS 2005 benchmark.]
+ Synopsis [Procedure to read network from file.]
Author [Alan Mishchenko]
@@ -24,99 +24,7 @@
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
-typedef struct Io_ReadVer_t_ Io_ReadVer_t; // all reading info
-struct Io_ReadVer_t_
-{
- // general info about file
- char * pFileName; // the name of the file
- Extra_FileReader_t* pReader; // the input file reader
- // current processing info
- st_table * tKeywords; // mapping of keywords into codes
- Abc_Ntk_t * pNtk; // the primary network
- // the error message
- FILE * Output; // the output stream
- char sError[1000]; // the error string generated during parsing
- int LineCur; // the line currently being parsed
- Vec_Ptr_t * vSkipped; // temporary storage for skipped objects
-};
-
-// verilog keyword types
-typedef enum {
- VER_NONE = 0,
- VER_MODULE = -1,
- VER_ENDMODULE = -2,
- VER_INPUT = -3,
- VER_OUTPUT = -4,
- VER_INOUT = -5,
- VER_WIRE = -6,
- VER_ASSIGN = -7
-} Ver_KeywordType_t;
-
-// the list of verilog keywords
-static char * s_Keywords[10] =
-{
- NULL, // unused
- "module", // -1
- "endmodule", // -2
- "input", // -3
- "output", // -4
- "inout", // -5
- "wire", // -6
- "assign" // -7
-};
-
-// the list of gates in the Cadence library
-static char * s_CadenceGates[40][5] =
-{
- { "INVX1", "1", "1", "0 1\n", NULL }, // 0
- { "INVX2", "1", "1", "0 1\n", NULL }, // 1
- { "INVX4", "1", "1", "0 1\n", NULL }, // 2
- { "INVX8", "1", "1", "0 1\n", NULL }, // 3
- { "BUFX1", "1", "1", "1 1\n", NULL }, // 4
- { "BUFX3", "1", "1", "1 1\n", NULL }, // 5
- { "NOR2X1", "2", "1", "00 1\n", NULL }, // 6
- { "NOR3X1", "3", "1", "000 1\n", NULL }, // 7
- { "NOR4X1", "4", "1", "0000 1\n", NULL }, // 8
- { "NAND2X1", "2", "1", "11 0\n", NULL }, // 9
- { "NAND2X2", "2", "1", "11 0\n", NULL }, // 10
- { "NAND3X1", "3", "1", "111 0\n", NULL }, // 11
- { "NAND4X1", "4", "1", "1111 0\n", NULL }, // 12
- { "OR2X1", "2", "1", "00 0\n", NULL }, // 13
- { "OR4X1", "4", "1", "0000 0\n", NULL }, // 14
- { "AND2X1", "2", "1", "11 1\n", NULL }, // 15
- { "XOR2X1", "2", "1", "01 1\n10 1\n", NULL }, // 16
- { "MX2X1", "3", "1", "01- 1\n1-1 1\n", NULL }, // 17
- { "OAI21X1", "3", "1", "00- 1\n--0 1\n", NULL }, // 18
- { "OAI22X1", "4", "1", "00-- 1\n--00 1\n", NULL }, // 19
- { "OAI33X1", "6", "1", "000--- 1\n---000 1\n", NULL }, // 20
- { "AOI21X1", "3", "1", "11- 0\n--1 0\n", NULL }, // 21
- { "AOI22X1", "4", "1", "11-- 0\n--11 0\n", NULL }, // 22
- { "CLKBUFX1", "1", "1", "1 1\n", NULL }, // 23
- { "CLKBUFX2", "1", "1", "1 1\n", NULL }, // 24
- { "CLKBUFX3", "1", "1", "1 1\n", NULL }, // 25
- { "ADDHX1", "2", "2", "11 1\n", "01 1\n10 1\n" }, // 26
- { "ADDFX1", "3", "2", "11- 1\n-11 1\n1-1 1\n", "001 1\n010 1\n100 1\n111 1\n" }, // 27
- { "DFFSRX1", "1", "1", NULL, NULL }, // 28
- { "DFFX1", "1", "1", NULL, NULL }, // 29
- { "SDFFSRX1", "1", "1", NULL, NULL }, // 30
- { "TLATSRX1", "1", "1", NULL, NULL }, // 31
- { "TLATX1", "1", "1", NULL, NULL }, // 32
- { "TBUFX1", "1", "1", NULL, NULL }, // 33
- { "TBUFX2", "1", "1", NULL, NULL }, // 34
- { "TBUFX4", "1", "1", NULL, NULL }, // 35
- { "TBUFX8", "1", "1", NULL, NULL }, // 36
- { "TINVX1", "1", "1", NULL, NULL } // 37
-};
-
-static Io_ReadVer_t * Io_ReadVerFile( char * pFileName );
-static Abc_Ntk_t * Io_ReadVerNetwork( Io_ReadVer_t * p );
-static bool Io_ReadVerNetworkAssign( Io_ReadVer_t * p, Abc_Ntk_t * pNtk, Vec_Ptr_t * vTokens );
-static bool Io_ReadVerNetworkSignal( Io_ReadVer_t * p, Abc_Ntk_t * pNtk, Vec_Ptr_t * vTokens, int LineType );
-static bool Io_ReadVerNetworkGateSimple( Io_ReadVer_t * p, Abc_Ntk_t * pNtk, Vec_Ptr_t * vTokens, int LineType );
-static bool Io_ReadVerNetworkGateComplex( Io_ReadVer_t * p, Abc_Ntk_t * pNtk, Vec_Ptr_t * vTokens, int LineType );
-static bool Io_ReadVerNetworkLatch( Io_ReadVer_t * p, Abc_Ntk_t * pNtk, Vec_Ptr_t * vTokens );
-static void Io_ReadVerPrintErrorMessage( Io_ReadVer_t * p );
-static void Io_ReadVerFree( Io_ReadVer_t * p );
+extern Abc_Lib_t * Ver_ParseFile( char * pFileName, Abc_Lib_t * pGateLib, int fCheck, int fUseMemMan );
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
@@ -124,44 +32,7 @@ static void Io_ReadVerFree( Io_ReadVer_t * p );
/**Function*************************************************************
- Synopsis [Reads the network from a Verilog file.]
-
- Description [Works only for IWLS 2005 benchmarks.]
-
- SideEffects []
-
- SeeAlso []
-
-***********************************************************************/
-Abc_Ntk_t * Io_ReadVerilog( char * pFileName, int fCheck )
-{
- Io_ReadVer_t * p;
- Abc_Ntk_t * pNtk;
-
- // start the file
- p = Io_ReadVerFile( pFileName );
- if ( p == NULL )
- return NULL;
-
- // read the network
- pNtk = Io_ReadVerNetwork( p );
- Io_ReadVerFree( p );
- if ( pNtk == NULL )
- return NULL;
-
- // make sure that everything is okay with the network structure
- if ( fCheck && !Abc_NtkCheckRead( pNtk ) )
- {
- printf( "Io_ReadVerilog: The network check has failed.\n" );
- Abc_NtkDelete( pNtk );
- return NULL;
- }
- return pNtk;
-}
-
-/**Function*************************************************************
-
- Synopsis [Starts the reading data structure.]
+ Synopsis [Reads hierarchical design from the Verilog file.]
Description []
@@ -170,583 +41,32 @@ Abc_Ntk_t * Io_ReadVerilog( char * pFileName, int fCheck )
SeeAlso []
***********************************************************************/
-Io_ReadVer_t * Io_ReadVerFile( char * pFileName )
-{
- Extra_FileReader_t * pReader;
- Io_ReadVer_t * p;
- int i;
-
- // start the reader
- pReader = Extra_FileReaderAlloc( pFileName, "/", ";", " \t\r\n,()" );
- if ( pReader == NULL )
- return NULL;
-
- // start the reading data structure
- p = ALLOC( Io_ReadVer_t, 1 );
- memset( p, 0, sizeof(Io_ReadVer_t) );
- p->pFileName = pFileName;
- p->pReader = pReader;
- p->Output = stdout;
- p->vSkipped = Vec_PtrAlloc( 100 );
-
- // insert the keywords and gate names into the hash table
- p->tKeywords = st_init_table(strcmp, st_strhash);
- for ( i = 0; i < 10; i++ )
- if ( s_Keywords[i] )
- st_insert( p->tKeywords, (char *)s_Keywords[i], (char *)-i );
- for ( i = 0; i < 40; i++ )
- if ( s_CadenceGates[i][0] )
- st_insert( p->tKeywords, (char *)s_CadenceGates[i][0], (char *)i );
- return p;
-}
-
-/**Function*************************************************************
-
- Synopsis [Frees the data structure.]
-
- Description []
-
- SideEffects []
-
- SeeAlso []
-
-***********************************************************************/
-void Io_ReadVerFree( Io_ReadVer_t * p )
-{
- Extra_FileReaderFree( p->pReader );
- Vec_PtrFree( p->vSkipped );
- st_free_table( p->tKeywords );
- FREE( p );
-}
-
-/**Function*************************************************************
-
- Synopsis [Prints the error message including the file name and line number.]
-
- Description []
-
- SideEffects []
-
- SeeAlso []
-
-***********************************************************************/
-void Io_ReadVerPrintErrorMessage( Io_ReadVer_t * p )
-{
- if ( p->LineCur == 0 ) // the line number is not given
- fprintf( p->Output, "%s: %s\n", p->pFileName, p->sError );
- else // print the error message with the line number
- fprintf( p->Output, "%s (line %d): %s\n", p->pFileName, p->LineCur, p->sError );
-}
-
-/**Function*************************************************************
-
- Synopsis [Reads the verilog file.]
-
- Description []
-
- SideEffects []
-
- SeeAlso []
-
-***********************************************************************/
-Abc_Ntk_t * Io_ReadVerNetwork( Io_ReadVer_t * p )
+Abc_Ntk_t * Io_ReadVerilog( char * pFileName, int fCheck )
{
- char Buffer[1000];
- ProgressBar * pProgress;
- Ver_KeywordType_t LineType;
- Vec_Ptr_t * vTokens;
Abc_Ntk_t * pNtk;
- char * pModelName;
- int i;
+ Abc_Lib_t * pDesign;
- // read the model name
- vTokens = Extra_FileReaderGetTokens( p->pReader );
- if ( vTokens == NULL || strcmp( vTokens->pArray[0], "module" ) )
- {
- p->LineCur = 0;
- sprintf( p->sError, "Wrong input file format." );
- Io_ReadVerPrintErrorMessage( p );
+ // parse the verilog file
+ pDesign = Ver_ParseFile( pFileName, NULL, 1, fCheck );
+ if ( pDesign == NULL )
return NULL;
- }
- pModelName = vTokens->pArray[1];
- // allocate the empty network
- pNtk = Abc_NtkAlloc( ABC_NTK_NETLIST, ABC_FUNC_SOP, 1 );
- pNtk->pName = Extra_UtilStrsav( pModelName );
- pNtk->pSpec = Extra_UtilStrsav( p->pFileName );
+ // extract the master network
+ pNtk = Vec_PtrEntryLast( pDesign->vModules );
+ pNtk->pDesign = pDesign;
+ pDesign->pManFunc = NULL;
- // create constant nodes and nets
- Abc_NtkFindOrCreateNet( pNtk, "1'b0" );
- Abc_NtkFindOrCreateNet( pNtk, "1'b1" );
- Io_ReadCreateConst( pNtk, "1'b0", 0 );
- Io_ReadCreateConst( pNtk, "1'b1", 1 );
-
- // read the inputs/outputs
- pProgress = Extra_ProgressBarStart( stdout, Extra_FileReaderGetFileSize(p->pReader) );
- for ( i = 0; vTokens = Extra_FileReaderGetTokens(p->pReader); i++ )
+ // verify the design for cyclic dependence
+ assert( Vec_PtrSize(pDesign->vModules) > 0 );
+ if ( Vec_PtrSize(pDesign->vModules) == 1 )
{
- Extra_ProgressBarUpdate( pProgress, Extra_FileReaderGetCurPosition(p->pReader), NULL );
-
- // get the line type
- if ( !st_lookup( p->tKeywords, vTokens->pArray[0], (char **)&LineType ) )
- {
- p->LineCur = Extra_FileReaderGetLineNumber( p->pReader, 0 );
- sprintf( p->sError, "The first token \"%s\" cannot be recognized.", vTokens->pArray[0] );
- Io_ReadVerPrintErrorMessage( p );
- return NULL;
- }
- // consider Verilog directives
- if ( LineType < 0 )
- {
- if ( LineType == VER_ENDMODULE )
- break;
- if ( LineType == VER_ASSIGN )
- {
- if ( !Io_ReadVerNetworkAssign( p, pNtk, vTokens ) )
- return NULL;
- continue;
- }
- if ( !Io_ReadVerNetworkSignal( p, pNtk, vTokens, LineType ) )
- return NULL;
- continue;
- }
- // proces single output gates
- if ( LineType < 26 )
- {
- if ( !Io_ReadVerNetworkGateSimple( p, pNtk, vTokens, LineType ) )
- return NULL;
- continue;
- }
- // process complex gates
- if ( LineType < 28 )
- {
- if ( !Io_ReadVerNetworkGateComplex( p, pNtk, vTokens, LineType ) )
- return NULL;
- continue;
-
- }
- // process the latches
- if ( LineType < 33 )
- {
- if ( !Io_ReadVerNetworkLatch( p, pNtk, vTokens ) )
- return NULL;
- continue;
- }
- // add the tri-state element to the skipped ones
- sprintf( Buffer, "%s %s", vTokens->pArray[0], vTokens->pArray[1] );
- Vec_PtrPush( p->vSkipped, Extra_UtilStrsav(Buffer) );
- }
- Extra_ProgressBarStop( pProgress );
-
- if ( p->vSkipped->nSize > 0 )
- {
- printf( "IoReadVerilog() skipped %d tri-state elements:\n", p->vSkipped->nSize );
- for ( i = 0; i < p->vSkipped->nSize; i++ )
- {
- if ( i < 2 )
- printf( "%s,\n", p->vSkipped->pArray[i] );
- else
- {
- printf( "%s, etc.\n", p->vSkipped->pArray[i] );
- break;
- }
- }
- for ( i = 0; i < p->vSkipped->nSize; i++ )
- free( p->vSkipped->pArray[i] );
- }
- Abc_NtkFinalizeRead( pNtk );
- return pNtk;
-}
-
-/**Function*************************************************************
-
- Synopsis [Reads one assign directive in the verilog file.]
-
- Description []
-
- SideEffects []
-
- SeeAlso []
-
-***********************************************************************/
-bool Io_ReadVerNetworkAssign( Io_ReadVer_t * p, Abc_Ntk_t * pNtk, Vec_Ptr_t * vTokens )
-{
- assert( strcmp( vTokens->pArray[0], "assign" ) == 0 );
- // make sure the driving variable exists
- if ( !Abc_NtkFindNet( pNtk, vTokens->pArray[3] ) )
- {
- p->LineCur = Extra_FileReaderGetLineNumber( p->pReader, 0 );
- sprintf( p->sError, "Cannot find net \"%s\". The assign operator is handled only for assignment to a variable and a constant.", vTokens->pArray[3] );
- Io_ReadVerPrintErrorMessage( p );
- return 0;
- }
- // make sure the driven variable exists
- if ( !Abc_NtkFindNet( pNtk, vTokens->pArray[1] ) )
- {
- p->LineCur = Extra_FileReaderGetLineNumber( p->pReader, 0 );
- sprintf( p->sError, "Cannot find net \"%s\".", vTokens->pArray[1] );
- Io_ReadVerPrintErrorMessage( p );
- return 0;
- }
- // create a buffer
- Io_ReadCreateBuf( pNtk, vTokens->pArray[3], vTokens->pArray[1] );
- return 1;
-}
-
-/**Function*************************************************************
-
- Synopsis [Reads one signal the verilog file.]
-
- Description []
-
- SideEffects []
-
- SeeAlso []
-
-***********************************************************************/
-bool Io_ReadVerNetworkSignal( Io_ReadVer_t * p, Abc_Ntk_t * pNtk, Vec_Ptr_t * vTokens, int LineType )
-{
- Abc_Obj_t * pNet;
- char Buffer[1000];
- char * pToken;
- int nSignals, k, Start, s;
-
- nSignals = 0;
- pToken = vTokens->pArray[1];
- if ( pToken[0] == '[' )
- {
- nSignals = atoi(pToken + 1) + 1;
- if ( nSignals < 1 || nSignals > 1024 )
- {
- p->LineCur = Extra_FileReaderGetLineNumber( p->pReader, 0 );
- sprintf( p->sError, "Incorrect number of signals in the expression \"%s\".", pToken );
- Io_ReadVerPrintErrorMessage( p );
- return 0;
- }
- if ( nSignals == 1 )
- nSignals = 0;
- Start = 2;
+ printf( "Warning: The design is not hierarchical.\n" );
+ Abc_LibFree( pDesign, pNtk );
+ pNtk->pDesign = NULL;
}
else
- Start = 1;
- for ( k = Start; k < vTokens->nSize; k++ )
- {
- pToken = vTokens->pArray[k];
- // print the signal name
- if ( nSignals )
- {
- for ( s = 0; s < nSignals; s++ )
- {
- sprintf( Buffer, "%s[%d]", pToken, s );
- if ( LineType == VER_INPUT || LineType == VER_INOUT )
- Io_ReadCreatePi( pNtk, Buffer );
- if ( LineType == VER_OUTPUT || LineType == VER_INOUT )
- Io_ReadCreatePo( pNtk, Buffer );
- if ( LineType != VER_INPUT && LineType != VER_OUTPUT && LineType != VER_INOUT )
- pNet = Abc_NtkFindOrCreateNet( pNtk, Buffer );
- }
- }
- else
- {
- if ( LineType == VER_INPUT || LineType == VER_INOUT )
- Io_ReadCreatePi( pNtk, pToken );
- if ( LineType == VER_OUTPUT || LineType == VER_INOUT )
- Io_ReadCreatePo( pNtk, pToken );
- if ( LineType != VER_INPUT && LineType != VER_OUTPUT && LineType != VER_INOUT )
- pNet = Abc_NtkFindOrCreateNet( pNtk, pToken );
- }
- }
- return 1;
-}
-
-/**Function*************************************************************
-
- Synopsis [Reads a simple gate from the verilog file.]
-
- Description []
-
- SideEffects []
-
- SeeAlso []
-
-***********************************************************************/
-bool Io_ReadVerNetworkGateSimple( Io_ReadVer_t * p, Abc_Ntk_t * pNtk, Vec_Ptr_t * vTokens, int LineType )
-{
- Abc_Obj_t * pNet, * pNode;
- char * pToken;
- int nFanins, k;
-
- // create the node
- pNode = Abc_NtkCreateNode( pNtk );
- // add the fanin nets
- nFanins = s_CadenceGates[LineType][1][0] - '0';
- // skip the gate type and gate name
- for ( k = 2; k < vTokens->nSize - 1; k++ )
- {
- pToken = vTokens->pArray[k];
- if ( pToken[0] == '.' )
- continue;
- pNet = Abc_NtkFindNet( pNtk, pToken );
- if ( pNet )
- {
- Abc_ObjAddFanin( pNode, pNet );
- continue;
- }
- p->LineCur = Extra_FileReaderGetLineNumber( p->pReader, 0 );
- sprintf( p->sError, "Cannot find net \"%s\".", pToken );
- Io_ReadVerPrintErrorMessage( p );
- return 0;
- }
- if ( Abc_ObjFaninNum(pNode) != nFanins )
- {
- p->LineCur = Extra_FileReaderGetLineNumber( p->pReader, 0 );
- sprintf( p->sError, "Gate \"%s\" has a wrong number of inputs.", vTokens->pArray[1] );
- Io_ReadVerPrintErrorMessage( p );
- return 0;
- }
-
- // add the fanout net
- pToken = vTokens->pArray[vTokens->nSize - 1];
- if ( pToken[0] == '.' )
- {
- p->LineCur = Extra_FileReaderGetLineNumber( p->pReader, 0 );
- sprintf( p->sError, "Gate \"%s\" does not have a fanout.", vTokens->pArray[1] );
- Io_ReadVerPrintErrorMessage( p );
- return 0;
- }
- pNet = Abc_NtkFindNet( pNtk, pToken );
- if ( pNet == NULL )
- {
- p->LineCur = Extra_FileReaderGetLineNumber( p->pReader, 0 );
- sprintf( p->sError, "Cannot find net \"%s\".", pToken );
- Io_ReadVerPrintErrorMessage( p );
- return 0;
- }
- Abc_ObjAddFanin( pNet, pNode );
- // set the function
- Abc_ObjSetData( pNode, Abc_SopRegister(pNtk->pManFunc, s_CadenceGates[LineType][3]) );
- return 1;
-}
-
-/**Function*************************************************************
-
- Synopsis [Reads a complex gate from the verilog file.]
-
- Description []
-
- SideEffects []
-
- SeeAlso []
-
-***********************************************************************/
-bool Io_ReadVerNetworkGateComplex( Io_ReadVer_t * p, Abc_Ntk_t * pNtk, Vec_Ptr_t * vTokens, int LineType )
-{
- Abc_Obj_t * pNode1, * pNode2, * pNet;
- char * pToken, * pToken1, * pToken2;
- int nFanins, k;
-
- // create the nodes
- pNode1 = Abc_NtkCreateNode( pNtk );
- pNode2 = Abc_NtkCreateNode( pNtk );
- // skip the gate type and gate name
- // add the fanin nets
- nFanins = s_CadenceGates[LineType][1][0] - '0';
- for ( k = 2; k < vTokens->nSize; k++ )
- {
- pToken = vTokens->pArray[k];
- if ( pToken[0] == '.' )
- continue;
- pNet = Abc_NtkFindNet( pNtk, pToken );
- if ( pNet == NULL )
- {
- p->LineCur = Extra_FileReaderGetLineNumber( p->pReader, 0 );
- sprintf( p->sError, "Cannot find net \"%s\".", pToken );
- Io_ReadVerPrintErrorMessage( p );
- return 0;
- }
- Abc_ObjAddFanin( pNode1, pNet );
- Abc_ObjAddFanin( pNode2, pNet );
- if ( Abc_ObjFaninNum(pNode1) == nFanins )
- {
- k++;
- break;
- }
- }
- // find the tokens corresponding to the output
- pToken1 = pToken2 = NULL;
- for ( ; k < vTokens->nSize; k++ )
- {
- pToken = vTokens->pArray[k];
- if ( pToken[0] == '.' )
- continue;
- if ( pToken1 == NULL )
- pToken1 = pToken;
- else
- pToken2 = pToken;
- }
- // quit if one of the tokens is not given
- if ( pToken1 == NULL || pToken2 == NULL )
- {
- p->LineCur = Extra_FileReaderGetLineNumber( p->pReader, 0 );
- sprintf( p->sError, "An output of a two-output gate \"%s\" is not specified.", vTokens->pArray[1] );
- Io_ReadVerPrintErrorMessage( p );
- return 0;
- }
-
- // add the fanout net
- pNet = Abc_NtkFindNet( pNtk, pToken1 );
- if ( pNet == NULL )
- {
- p->LineCur = Extra_FileReaderGetLineNumber( p->pReader, 0 );
- sprintf( p->sError, "Cannot find net \"%s\".", pToken1 );
- Io_ReadVerPrintErrorMessage( p );
- return 0;
- }
- Abc_ObjAddFanin( pNet, pNode1 );
-
- // add the fanout net
- pNet = Abc_NtkFindNet( pNtk, pToken2 );
- if ( pNet == NULL )
- {
- p->LineCur = Extra_FileReaderGetLineNumber( p->pReader, 0 );
- sprintf( p->sError, "Cannot find net \"%s\".", pToken2 );
- Io_ReadVerPrintErrorMessage( p );
- return 0;
- }
- Abc_ObjAddFanin( pNet, pNode2 );
- Abc_ObjSetData( pNode1, Abc_SopRegister(pNtk->pManFunc, s_CadenceGates[LineType][3]) );
- Abc_ObjSetData( pNode2, Abc_SopRegister(pNtk->pManFunc, s_CadenceGates[LineType][4]) );
- return 1;
-}
-
-/**Function*************************************************************
-
- Synopsis [Reads a latch from the verilog file.]
-
- Description [This procedure treats T-latch as if it were D-latch.]
-
- SideEffects []
-
- SeeAlso []
-
-***********************************************************************/
-bool Io_ReadVerNetworkLatch( Io_ReadVer_t * p, Abc_Ntk_t * pNtk, Vec_Ptr_t * vTokens )
-{
- Abc_Obj_t * pLatch, * pNet;
- char * pLatchName;
- char * pToken, * pToken2, * pTokenRN, * pTokenSN, * pTokenSI, * pTokenSE, * pTokenD, * pTokenQ, * pTokenQN;
- int k, fRN1, fSN1;
-
- // get the latch name
- pLatchName = vTokens->pArray[1];
-
- // collect the FF signals
- pTokenRN = pTokenSN = pTokenSI = pTokenSE = pTokenD = pTokenQ = pTokenQN = NULL;
- for ( k = 2; k < vTokens->nSize-1; k++ )
- {
- pToken = vTokens->pArray[k];
- pToken2 = vTokens->pArray[k+1];
- if ( pToken[1] == 'R' && pToken[2] == 'N' && pToken[3] == 0 )
- pTokenRN = (pToken2[0] == '.')? NULL : pToken2;
- else if ( pToken[1] == 'S' && pToken[2] == 'N' && pToken[3] == 0 )
- pTokenSN = (pToken2[0] == '.')? NULL : pToken2;
- else if ( pToken[1] == 'S' && pToken[2] == 'I' && pToken[3] == 0 )
- pTokenSI = (pToken2[0] == '.')? NULL : pToken2;
- else if ( pToken[1] == 'S' && pToken[2] == 'E' && pToken[3] == 0 )
- pTokenSE = (pToken2[0] == '.')? NULL : pToken2;
- else if ( pToken[1] == 'D' && pToken[2] == 0 )
- pTokenD = (pToken2[0] == '.')? NULL : pToken2;
- else if ( pToken[1] == 'Q' && pToken[2] == 0 )
- pTokenQ = (pToken2[0] == '.')? NULL : pToken2;
- else if ( pToken[1] == 'Q' && pToken[2] == 'N' && pToken[3] == 0 )
- pTokenQN = (pToken2[0] == '.')? NULL : pToken2;
- else if ( pToken[1] == 'C' && pToken[2] == 'K' && pToken[3] == 0 ) {}
- else
- assert( 0 );
- if ( pToken2[0] != '.' )
- k++;
- }
-
- if ( pTokenD == NULL )
- {
- p->LineCur = Extra_FileReaderGetLineNumber( p->pReader, 1 );
- sprintf( p->sError, "Cannot read pin D of the latch \"%s\".", pLatchName );
- Io_ReadVerPrintErrorMessage( p );
- return 0;
- }
- if ( pTokenQ == NULL && pTokenQN == NULL )
- {
- p->LineCur = Extra_FileReaderGetLineNumber( p->pReader, 1 );
- sprintf( p->sError, "Cannot read pins Q/QN of the latch \"%s\".", pLatchName );
- Io_ReadVerPrintErrorMessage( p );
- return 0;
- }
- if ( (pTokenRN == NULL) ^ (pTokenSN == NULL) )
- {
- p->LineCur = Extra_FileReaderGetLineNumber( p->pReader, 1 );
- sprintf( p->sError, "Cannot read pins RN/SN of the latch \"%s\".", pLatchName );
- Io_ReadVerPrintErrorMessage( p );
- return 0;
- }
- if ( Abc_NtkFindNet( pNtk, pTokenD ) == NULL )
- {
- p->LineCur = Extra_FileReaderGetLineNumber( p->pReader, 0 );
- sprintf( p->sError, "Cannot find latch input net \"%s\".", pTokenD );
- Io_ReadVerPrintErrorMessage( p );
- return 0;
- }
-
- // create the latch
- pLatch = Io_ReadCreateLatch( pNtk, pTokenD, pLatchName );
-
- // create the buffer if Q signal is available
- if ( pTokenQ )
- {
- pNet = Abc_NtkFindNet( pNtk, pTokenQ );
- if ( pNet == NULL )
- {
- p->LineCur = Extra_FileReaderGetLineNumber( p->pReader, 0 );
- sprintf( p->sError, "Cannot find latch output net \"%s\".", pTokenQ );
- Io_ReadVerPrintErrorMessage( p );
- return 0;
- }
- Io_ReadCreateBuf( pNtk, pLatchName, pTokenQ );
- }
- if ( pTokenQN )
- {
- pNet = Abc_NtkFindNet( pNtk, pTokenQN );
- if ( pNet == NULL )
- {
- p->LineCur = Extra_FileReaderGetLineNumber( p->pReader, 0 );
- sprintf( p->sError, "Cannot find latch output net \"%s\".", pTokenQN );
- Io_ReadVerPrintErrorMessage( p );
- return 0;
- }
- Io_ReadCreateInv( pNtk, pLatchName, pTokenQN );
- }
-
- // set the initial value
- if ( pTokenRN == NULL && pTokenSN == NULL )
- Abc_LatchSetInitDc( pLatch );
- else
- {
- fRN1 = (strcmp( pTokenRN, "1'b1" ) == 0);
- fSN1 = (strcmp( pTokenSN, "1'b1" ) == 0);
- if ( fRN1 && fSN1 )
- Abc_LatchSetInitDc( pLatch );
- else if ( fRN1 )
- Abc_LatchSetInit1( pLatch );
- else if ( fSN1 )
- Abc_LatchSetInit0( pLatch );
- else
- {
- p->LineCur = Extra_FileReaderGetLineNumber( p->pReader, 0 );
- sprintf( p->sError, "Cannot read the initial value of latch \"%s\".", pLatchName );
- Io_ReadVerPrintErrorMessage( p );
- return 0;
- }
- }
- return 1;
+ Abc_NtkIsAcyclicHierarchy( pNtk );
+ return pNtk;
}
////////////////////////////////////////////////////////////////////////
diff --git a/src/base/io/ioUtil.c b/src/base/io/ioUtil.c
index ca9f06b4..7b4c7c76 100644
--- a/src/base/io/ioUtil.c
+++ b/src/base/io/ioUtil.c
@@ -132,6 +132,8 @@ Abc_Ntk_t * Io_ReadNetlist( char * pFileName, Io_FileType_t FileType, int fCheck
pNtk = Io_ReadEqn( pFileName, fCheck );
else if ( FileType == IO_FILE_PLA )
pNtk = Io_ReadPla( pFileName, fCheck );
+ else if ( FileType == IO_FILE_VERILOG )
+ pNtk = Io_ReadVerilog( pFileName, fCheck );
else
{
fprintf( stderr, "Unknown file format.\n" );
@@ -142,6 +144,12 @@ Abc_Ntk_t * Io_ReadNetlist( char * pFileName, Io_FileType_t FileType, int fCheck
fprintf( stdout, "Reading network from file has failed.\n" );
return NULL;
}
+ if ( Abc_NtkBlackboxNum(pNtk) || Abc_NtkBlackboxNum(pNtk) )
+ {
+ fprintf( stdout, "The network contains hierarchy. Use \"read_hie\".\n" );
+ Abc_NtkDelete( pNtk );
+ return NULL;
+ }
return pNtk;
}
@@ -197,6 +205,8 @@ Abc_Ntk_t * Io_ReadHie( char * pFileName, Io_FileType_t FileType, int fCheck )
pNtk = Io_ReadBlifMv( pFileName, 0, fCheck );
// else if ( Io_ReadFileType(pFileName) == IO_FILE_BLIFMV )
// pNtk = Io_ReadBlifMv( pFileName, 1, fCheck );
+ else if ( Io_ReadFileType(pFileName) == IO_FILE_VERILOG )
+ pNtk = Io_ReadVerilog( pFileName, fCheck );
else
{
printf( "Wrong file type.\n" );
@@ -220,7 +230,7 @@ Abc_Ntk_t * Io_ReadHie( char * pFileName, Io_FileType_t FileType, int fCheck )
// convert blackboxes
if ( Abc_NtkBlackboxNum(pNtk) > 0 )
{
- printf( "Hierarchical parser is converting %d blackboxes.\n", Abc_NtkBlackboxNum(pNtk) );
+ printf( "Hierarchical parser converted %d blackboxes.\n", Abc_NtkBlackboxNum(pNtk) );
pNtk = Abc_NtkConvertBlackboxes( pTemp = pNtk );
Abc_NtkDelete( pTemp );
if ( pNtk == NULL )
@@ -347,7 +357,7 @@ void Io_Write( Abc_Ntk_t * pNtk, char * pFileName, Io_FileType_t FileType )
{
if ( Abc_NtkIsSopNetlist(pNtkTemp) )
Abc_NtkSopToAig( pNtkTemp );
- Io_WriteVerilog( pNtkTemp, pFileName, 1 );
+ Io_WriteVerilog( pNtkTemp, pFileName );
}
else
fprintf( stderr, "Unknown file format.\n" );
@@ -365,50 +375,64 @@ void Io_Write( Abc_Ntk_t * pNtk, char * pFileName, Io_FileType_t FileType )
SeeAlso []
***********************************************************************/
-void Io_WriteHie( Abc_Ntk_t * pNtk, char * pFileName, Io_FileType_t FileType, char * pBaseName )
+void Io_WriteHie( Abc_Ntk_t * pNtk, char * pBaseName, char * pFileName )
{
- Abc_Ntk_t * pNtkTemp, * pNtkBase, * pNtkResult;
+ Abc_Ntk_t * pNtkTemp, * pNtkResult, * pNtkBase = NULL;
// check if the current network is available
if ( pNtk == NULL )
{
fprintf( stdout, "Empty network.\n" );
return;
}
- // check if the file extension if given
- if ( FileType == IO_FILE_NONE || FileType == IO_FILE_UNKNOWN )
- {
- fprintf( stdout, "The generic file writer requires a known file extension.\n" );
+
+ // read the base network
+ assert( Abc_NtkIsStrash(pNtk) || Abc_NtkIsLogic(pNtk) );
+ if ( Io_ReadFileType(pBaseName) == IO_FILE_BLIF )
+ pNtkBase = Io_ReadBlifMv( pBaseName, 0, 1 );
+ else
+ fprintf( stderr, "Unknown input file format.\n" );
+ if ( pNtkBase == NULL )
return;
- }
- // write the AIG formats
- if ( FileType == IO_FILE_BLIF )
+
+ if ( Abc_NtkWhiteboxNum(pNtkBase) > 0 )
{
- pNtkBase = Io_ReadBlifMv( pBaseName, 0, 1 );
- if ( Abc_NtkWhiteboxNum(pNtk) > 0 )
- {
- pNtkBase = Abc_NtkFlattenLogicHierarchy( pNtkTemp = pNtkBase );
- Abc_NtkDelete( pNtkTemp );
- }
- if ( Abc_NtkBlackboxNum(pNtk) > 0 )
- {
- pNtkResult = Abc_NtkLogicToNetlist( pNtk, 0 );
- pNtkResult = Abc_NtkInsertNewLogic( pNtkBase, pNtkTemp = pNtkResult );
- Abc_NtkDelete( pNtkTemp );
- printf( "Hierarchy writer reintroduced %d blackboxes.\n", Abc_NtkBlackboxNum(pNtk) );
- }
- else
- {
- printf( "Warning: The output network does not contain blackboxes.\n" );
- pNtkResult = Abc_NtkLogicToNetlist( pNtk, 0 );
- }
- Abc_NtkDelete( pNtkBase );
- if ( pNtkResult == NULL )
+ pNtkBase = Abc_NtkFlattenLogicHierarchy( pNtkTemp = pNtkBase );
+ if ( pNtkBase == NULL )
return;
- Io_WriteBlif( pNtkResult, pFileName, 0 );
- Abc_NtkDelete( pNtkResult );
+ Abc_NtkDelete( pNtkTemp );
+ }
+
+ // reintroduce the boxes into the netlist
+ if ( Abc_NtkBlackboxNum(pNtkBase) > 0 )
+ {
+ pNtkResult = Abc_NtkLogicToNetlist( pNtk, 0 );
+ pNtkResult = Abc_NtkInsertNewLogic( pNtkBase, pNtkTemp = pNtkResult );
+ Abc_NtkDelete( pNtkTemp );
+ if ( pNtkResult )
+ printf( "Hierarchy writer reintroduced %d blackboxes.\n", Abc_NtkBlackboxNum(pNtkBase) );
+ }
+ else
+ {
+ printf( "Warning: The output network does not contain blackboxes.\n" );
+ pNtkResult = Abc_NtkLogicToNetlist( pNtk, 0 );
+ }
+ Abc_NtkDelete( pNtkBase );
+ if ( pNtkResult == NULL )
+ return;
+
+ // write the resulting network
+ if ( Io_ReadFileType(pFileName) == IO_FILE_BLIF )
+ Io_WriteBlif( pNtkResult, pFileName, 1 );
+ else if ( Io_ReadFileType(pFileName) == IO_FILE_VERILOG )
+ {
+ if ( Abc_NtkIsSopNetlist(pNtkResult) )
+ Abc_NtkSopToAig( pNtkResult );
+ Io_WriteVerilog( pNtkResult, pFileName );
}
else
- fprintf( stderr, "Unknown file format.\n" );
+ fprintf( stderr, "Unknown output file format.\n" );
+
+ Abc_NtkDelete( pNtkResult );
}
/**Function*************************************************************
diff --git a/src/base/io/ioWriteBlif.c b/src/base/io/ioWriteBlif.c
index 7c9db8bb..94580e33 100644
--- a/src/base/io/ioWriteBlif.c
+++ b/src/base/io/ioWriteBlif.c
@@ -102,6 +102,7 @@ void Io_WriteBlif( Abc_Ntk_t * pNtk, char * FileName, int fWriteLatches )
{
pNtkTemp = pObj->pData;
assert( pNtkTemp != NULL && Abc_NtkHasBlackbox(pNtkTemp) );
+ fprintf( pFile, "\n\n", Abc_NtkName(pNtk) );
Io_NtkWrite( pFile, pNtkTemp, fWriteLatches );
}
}
diff --git a/src/base/io/ioWriteVerAux.c b/src/base/io/ioWriteVerAux.c
deleted file mode 100644
index 9fd71750..00000000
--- a/src/base/io/ioWriteVerAux.c
+++ /dev/null
@@ -1,444 +0,0 @@
-/**CFile****************************************************************
-
- FileName [ioWriteVerilog.c]
-
- SystemName [ABC: Logic synthesis and verification system.]
-
- PackageName [Command processing package.]
-
- Synopsis [Procedures to output a special subset of Verilog.]
-
- Author [Alan Mishchenko]
-
- Affiliation [UC Berkeley]
-
- Date [Ver. 1.0. Started - June 20, 2005.]
-
- Revision [$Id: ioWriteVerilog.c,v 1.00 2005/06/20 00:00:00 alanmi Exp $]
-
-***********************************************************************/
-
-#include "io.h"
-
-////////////////////////////////////////////////////////////////////////
-/// DECLARATIONS ///
-////////////////////////////////////////////////////////////////////////
-
-static void Io_WriteVerilogAuxInt( FILE * pFile, Abc_Ntk_t * pNtk );
-static void Io_WriteVerilogAuxPis( FILE * pFile, Abc_Ntk_t * pNtk, int Start );
-static void Io_WriteVerilogAuxPos( FILE * pFile, Abc_Ntk_t * pNtk, int Start );
-static void Io_WriteVerilogAuxWires( FILE * pFile, Abc_Ntk_t * pNtk, int Start );
-static void Io_WriteVerilogAuxNodes( FILE * pFile, Abc_Ntk_t * pNtk );
-static void Io_WriteVerilogAuxArgs( FILE * pFile, Abc_Obj_t * pObj, int nInMax, int fPadZeros );
-static int Io_WriteVerilogAuxCheckNtk( Abc_Ntk_t * pNtk );
-static char * Io_WriteVerilogAuxGetName( Abc_Obj_t * pObj );
-
-////////////////////////////////////////////////////////////////////////
-/// FUNCTION DEFINITIONS ///
-////////////////////////////////////////////////////////////////////////
-
-/**Function*************************************************************
-
- Synopsis [Write verilog.]
-
- Description []
-
- SideEffects []
-
- SeeAlso []
-
-***********************************************************************/
-void Io_WriteVerilogAux( Abc_Ntk_t * pNtk, char * pFileName )
-{
- FILE * pFile;
-
- if ( !Abc_NtkIsSopNetlist(pNtk) || !Io_WriteVerilogAuxCheckNtk(pNtk) )
- {
- printf( "Io_WriteVerilogAux(): Can write Verilog for a very special subset of logic networks.\n" );
- printf( "The current network is not in the subset; writing Verilog is not performed.\n" );
- return;
- }
-
- if ( Abc_NtkLatchNum(pNtk) > 0 )
- printf( "Io_WriteVerilogAux(): Warning: only combinational portion is being written.\n" );
-
- // start the output stream
- pFile = fopen( pFileName, "w" );
- if ( pFile == NULL )
- {
- fprintf( stdout, "Io_WriteVerilogAux(): Cannot open the output file \"%s\".\n", pFileName );
- return;
- }
-
- // write the equations for the network
- Io_WriteVerilogAuxInt( pFile, pNtk );
- fprintf( pFile, "\n" );
- fclose( pFile );
-}
-
-/**Function*************************************************************
-
- Synopsis [Writes verilog.]
-
- Description []
-
- SideEffects []
-
- SeeAlso []
-
-***********************************************************************/
-void Io_WriteVerilogAuxInt( FILE * pFile, Abc_Ntk_t * pNtk )
-{
- // write inputs and outputs
- fprintf( pFile, "// Benchmark \"%s\" written by ABC on %s\n", pNtk->pName, Extra_TimeStamp() );
- fprintf( pFile, "module %s (\n ", Abc_NtkName(pNtk) );
- Io_WriteVerilogAuxPis( pFile, pNtk, 3 );
- fprintf( pFile, ",\n " );
- Io_WriteVerilogAuxPos( pFile, pNtk, 3 );
- fprintf( pFile, " );\n" );
- // write inputs, outputs and wires
- fprintf( pFile, " input" );
- Io_WriteVerilogAuxPis( pFile, pNtk, 5 );
- fprintf( pFile, ";\n" );
- fprintf( pFile, " output" );
- Io_WriteVerilogAuxPos( pFile, pNtk, 5 );
- fprintf( pFile, ";\n" );
- fprintf( pFile, " wire" );
- Io_WriteVerilogAuxWires( pFile, pNtk, 4 );
- fprintf( pFile, ";\n" );
- // write the nodes
- Io_WriteVerilogAuxNodes( pFile, pNtk );
- // finalize the file
- fprintf( pFile, "endmodule\n\n" );
- fclose( pFile );
-}
-
-/**Function*************************************************************
-
- Synopsis [Writes the primary inputs.]
-
- Description []
-
- SideEffects []
-
- SeeAlso []
-
-***********************************************************************/
-void Io_WriteVerilogAuxPis( FILE * pFile, Abc_Ntk_t * pNtk, int Start )
-{
- Abc_Obj_t * pTerm, * pNet;
- int LineLength;
- int AddedLength;
- int NameCounter;
- int i;
-
- LineLength = Start;
- NameCounter = 0;
- Abc_NtkForEachCi( pNtk, pTerm, i )
- {
- pNet = Abc_ObjFanout0(pTerm);
- // get the line length after this name is written
- AddedLength = strlen(Abc_ObjName(pNet)) + 2;
- if ( NameCounter && LineLength + AddedLength + 3 > IO_WRITE_LINE_LENGTH )
- { // write the line extender
- fprintf( pFile, "\n " );
- // reset the line length
- LineLength = 3;
- NameCounter = 0;
- }
- fprintf( pFile, " %s%s", Abc_ObjName(pNet), (i==Abc_NtkCiNum(pNtk)-1)? "" : "," );
- LineLength += AddedLength;
- NameCounter++;
- }
-}
-
-/**Function*************************************************************
-
- Synopsis [Writes the primary outputs.]
-
- Description []
-
- SideEffects []
-
- SeeAlso []
-
-***********************************************************************/
-void Io_WriteVerilogAuxPos( FILE * pFile, Abc_Ntk_t * pNtk, int Start )
-{
- Abc_Obj_t * pTerm, * pNet;
- int LineLength;
- int AddedLength;
- int NameCounter;
- int i;
-
- LineLength = Start;
- NameCounter = 0;
- Abc_NtkForEachCo( pNtk, pTerm, i )
- {
- pNet = Abc_ObjFanin0(pTerm);
- // get the line length after this name is written
- AddedLength = strlen(Abc_ObjName(pNet)) + 2;
- if ( NameCounter && LineLength + AddedLength + 3 > IO_WRITE_LINE_LENGTH )
- { // write the line extender
- fprintf( pFile, "\n " );
- // reset the line length
- LineLength = 3;
- NameCounter = 0;
- }
- fprintf( pFile, " %s%s", Abc_ObjName(pNet), (i==Abc_NtkCoNum(pNtk)-1)? "" : "," );
- LineLength += AddedLength;
- NameCounter++;
- }
-}
-
-/**Function*************************************************************
-
- Synopsis [Writes the wires.]
-
- Description []
-
- SideEffects []
-
- SeeAlso []
-
-***********************************************************************/
-void Io_WriteVerilogAuxWires( FILE * pFile, Abc_Ntk_t * pNtk, int Start )
-{
- Abc_Obj_t * pTerm, * pNet;
- int LineLength;
- int AddedLength;
- int NameCounter;
- int i, Counter, nNodes;
-
- // count the number of wires
- nNodes = 0;
- Abc_NtkForEachNode( pNtk, pTerm, i )
- {
- if ( i == 0 )
- continue;
- pNet = Abc_ObjFanout0(pTerm);
- if ( Abc_ObjIsCo(Abc_ObjFanout0(pNet)) )
- continue;
- nNodes++;
- }
-
- // write the wires
- Counter = 0;
- LineLength = Start;
- NameCounter = 0;
- Abc_NtkForEachNode( pNtk, pTerm, i )
- {
- if ( i == 0 )
- continue;
- pNet = Abc_ObjFanout0(pTerm);
- if ( Abc_ObjIsCo(Abc_ObjFanout0(pNet)) )
- continue;
- Counter++;
- // get the line length after this name is written
- AddedLength = strlen(Abc_ObjName(pNet)) + 2;
- if ( NameCounter && LineLength + AddedLength + 3 > IO_WRITE_LINE_LENGTH )
- { // write the line extender
- fprintf( pFile, "\n " );
- // reset the line length
- LineLength = 3;
- NameCounter = 0;
- }
- fprintf( pFile, " %s%s", Io_WriteVerilogAuxGetName(pNet), (Counter==nNodes)? "" : "," );
- LineLength += AddedLength;
- NameCounter++;
- }
-}
-
-/**Function*************************************************************
-
- Synopsis [Writes the wires.]
-
- Description []
-
- SideEffects []
-
- SeeAlso []
-
-***********************************************************************/
-void Io_WriteVerilogAuxNodes( FILE * pFile, Abc_Ntk_t * pNtk )
-{
- Abc_Obj_t * pObj;
- int i, nCubes, nFanins, Counter, nDigits, fPadZeros;
- char * pName;
-
- nDigits = Extra_Base10Log( Abc_NtkNodeNum(pNtk) );
- Counter = 1;
- Abc_NtkForEachNode( pNtk, pObj, i )
- {
- nFanins = Abc_ObjFaninNum(pObj);
- nCubes = Abc_SopGetCubeNum(pObj->pData);
- if ( Abc_SopIsAndType(pObj->pData) )
- pName = "ts_and", fPadZeros = 1;
- else if ( Abc_SopIsExorType(pObj->pData) )
- pName = "ts_xor", fPadZeros = 1;
- else // if ( Abc_SopIsOrType(pObj->pData) )
- pName = "ts_or", fPadZeros = 0;
-
- assert( nCubes < 2 );
- if ( nCubes == 0 )
- {
- fprintf( pFile, " ts_gnd g%0*d ", nDigits, Counter++ );
- Io_WriteVerilogAuxArgs( pFile, pObj, 0, fPadZeros );
- }
- else if ( nCubes == 1 && nFanins == 0 )
- {
- fprintf( pFile, " ts_vdd g%0*d ", nDigits, Counter++ );
- Io_WriteVerilogAuxArgs( pFile, pObj, 0, fPadZeros );
- }
- else if ( nFanins == 1 && Abc_SopIsInv(pObj->pData) )
- {
- fprintf( pFile, " ts_inv g%0*d ", nDigits, Counter++ );
- Io_WriteVerilogAuxArgs( pFile, pObj, 1, fPadZeros );
- }
- else if ( nFanins == 1 )
- {
- fprintf( pFile, " ts_buf g%0*d ", nDigits, Counter++ );
- Io_WriteVerilogAuxArgs( pFile, pObj, 1, fPadZeros );
- }
- else if ( nFanins <= 4 )
- {
- fprintf( pFile, " %s%d g%0*d ", pName, 4, nDigits, Counter++ );
- Io_WriteVerilogAuxArgs( pFile, pObj, 4, fPadZeros );
- }
- else if ( nFanins <= 6 )
- {
- fprintf( pFile, " %s%d g%0*d ", pName, 6, nDigits, Counter++ );
- Io_WriteVerilogAuxArgs( pFile, pObj, 6, fPadZeros );
- }
- else if ( nFanins == 7 )
- {
- fprintf( pFile, " %s%d g%0*d ", pName, 7, nDigits, Counter++ );
- Io_WriteVerilogAuxArgs( pFile, pObj, 7, fPadZeros );
- }
- else if ( nFanins == 8 )
- {
- fprintf( pFile, " %s%d g%0*d ", pName, 8, nDigits, Counter++ );
- Io_WriteVerilogAuxArgs( pFile, pObj, 8, fPadZeros );
- }
- else if ( nFanins <= 16 )
- {
- fprintf( pFile, " %s%d g%0*d ", pName, 16, nDigits, Counter++ );
- Io_WriteVerilogAuxArgs( pFile, pObj, 16, fPadZeros );
- }
- else if ( nFanins <= 32 )
- {
- fprintf( pFile, " %s%d g%0*d ", pName, 32, nDigits, Counter++ );
- Io_WriteVerilogAuxArgs( pFile, pObj, 32, fPadZeros );
- }
- else if ( nFanins <= 64 )
- {
- fprintf( pFile, " %s%d g%0*d ", pName, 64, nDigits, Counter++ );
- Io_WriteVerilogAuxArgs( pFile, pObj, 64, fPadZeros );
- }
- else if ( nFanins <= 128 )
- {
- fprintf( pFile, " %s%d g%0*d ", pName, 128, nDigits, Counter++ );
- Io_WriteVerilogAuxArgs( pFile, pObj, 128, fPadZeros );
- }
- }
-}
-
-/**Function*************************************************************
-
- Synopsis [Writes the inputs.]
-
- Description []
-
- SideEffects []
-
- SeeAlso []
-
-***********************************************************************/
-void Io_WriteVerilogAuxArgs( FILE * pFile, Abc_Obj_t * pObj, int nInMax, int fPadZeros )
-{
- Abc_Obj_t * pFanin;
- int i, Counter = 2;
- fprintf( pFile, "(.z (%s)", Io_WriteVerilogAuxGetName(Abc_ObjFanout0(pObj)) );
- Abc_ObjForEachFanin( pObj, pFanin, i )
- {
- if ( Counter++ % 4 == 0 )
- fprintf( pFile, "\n " );
- fprintf( pFile, " .i%d (%s)", i+1, Io_WriteVerilogAuxGetName(Abc_ObjFanin(pObj,i)) );
- }
- for ( ; i < nInMax; i++ )
- {
- if ( Counter++ % 4 == 0 )
- fprintf( pFile, "\n " );
- fprintf( pFile, " .i%d (%s)", i+1, fPadZeros? "1\'b0" : "1\'b1" );
- }
- fprintf( pFile, ");\n" );
-}
-
-/**Function*************************************************************
-
- Synopsis []
-
- Description []
-
- SideEffects []
-
- SeeAlso []
-
-***********************************************************************/
-int Io_WriteVerilogAuxCheckNtk( Abc_Ntk_t * pNtk )
-{
- Abc_Obj_t * pObj;
- char * pSop;
- int i, k, nFanins;
- Abc_NtkForEachNode( pNtk, pObj, i )
- {
- if ( Abc_SopGetCubeNum(pObj->pData) > 1 )
- {
- printf( "Node %s contains a cover with more than one cube.\n", Abc_ObjName(pObj) );
- return 0;
- }
- nFanins = Abc_ObjFaninNum(pObj);
- if ( nFanins < 2 )
- continue;
- pSop = pObj->pData;
- for ( k = 0; k < nFanins; k++ )
- if ( pSop[k] != '1' )
- {
- printf( "Node %s contains a cover with non-positive literals.\n", Abc_ObjName(pObj) );
- return 0;
- }
- }
- return 1;
-}
-
-/**Function*************************************************************
-
- Synopsis [Prepares the name for writing the Verilog file.]
-
- Description []
-
- SideEffects []
-
- SeeAlso []
-
-***********************************************************************/
-char * Io_WriteVerilogAuxGetName( Abc_Obj_t * pObj )
-{
- static char Buffer[20];
- char * pName;
- pName = Abc_ObjName(pObj);
- if ( pName[0] != '[' )
- return pName;
- // replace opening bracket by the escape sign and closing bracket by space
- // as a result of this transformation, the length of the name does not change
- strcpy( Buffer, pName );
- Buffer[0] = '\\';
- Buffer[strlen(Buffer)-1] = ' ';
- return Buffer;
-}
-
-////////////////////////////////////////////////////////////////////////
-/// END OF FILE ///
-////////////////////////////////////////////////////////////////////////
-
-
diff --git a/src/base/io/ioWriteVer.c b/src/base/io/ioWriteVerilog.c
index 20e10583..9524bdef 100644
--- a/src/base/io/ioWriteVer.c
+++ b/src/base/io/ioWriteVerilog.c
@@ -26,18 +26,15 @@
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
-static void Io_WriteVerilogInt( FILE * pFile, Abc_Ntk_t * pNtk, int fVerLibStyle );
+static void Io_WriteVerilogInt( FILE * pFile, Abc_Ntk_t * pNtk );
static void Io_WriteVerilogPis( FILE * pFile, Abc_Ntk_t * pNtk, int Start );
static void Io_WriteVerilogPos( FILE * pFile, Abc_Ntk_t * pNtk, int Start );
static void Io_WriteVerilogWires( FILE * pFile, Abc_Ntk_t * pNtk, int Start );
static void Io_WriteVerilogRegs( FILE * pFile, Abc_Ntk_t * pNtk, int Start );
-static void Io_WriteVerilogGates( FILE * pFile, Abc_Ntk_t * pNtk );
-static void Io_WriteVerilogNodes( FILE * pFile, Abc_Ntk_t * pNtk );
static void Io_WriteVerilogLatches( FILE * pFile, Abc_Ntk_t * pNtk );
-static void Io_WriteVerilogVerLibStyle( FILE * pFile, Abc_Ntk_t * pNtk );
-static int Io_WriteVerilogCheckNtk( Abc_Ntk_t * pNtk );
+static void Io_WriteVerilogObjects( FILE * pFile, Abc_Ntk_t * pNtk );
+static int Io_WriteVerilogWiresCount( Abc_Ntk_t * pNtk );
static char * Io_WriteVerilogGetName( Abc_Obj_t * pObj );
-static int Io_WriteVerilogWiresCount( Abc_Ntk_t * pNtk );
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
@@ -54,29 +51,17 @@ static int Io_WriteVerilogWiresCount( Abc_Ntk_t * pNtk );
SeeAlso []
***********************************************************************/
-void Io_WriteVerilog( Abc_Ntk_t * pNtk, char * pFileName, int fVerLibStyle )
+void Io_WriteVerilog( Abc_Ntk_t * pNtk, char * pFileName )
{
+ Abc_Ntk_t * pNetlist;
FILE * pFile;
+ int i;
+ // can only write nodes represented using local AIGs
if ( !Abc_NtkIsAigNetlist(pNtk) )
{
printf( "Io_WriteVerilog(): Can produce Verilog for AIG netlists only.\n" );
return;
}
- if ( Abc_NtkLatchNum(pNtk) > 0 )
- {
- printf( "Io_WriteVerilog(): Currently cannot write verilog for sequential networks.\n" );
- return;
- }
-
-/*
- if ( !(Abc_NtkIsNetlist(pNtk) && (Abc_NtkHasMapping(pNtk) || Io_WriteVerilogCheckNtk(pNtk))) )
- {
- printf( "Io_WriteVerilog(): Can produce Verilog for a subset of logic networks.\n" );
- printf( "The network should be either an AIG or a network after technology mapping.\n" );
- printf( "The current network is not in the subset; the output files is not written.\n" );
- return;
- }
-*/
// start the output stream
pFile = fopen( pFileName, "w" );
if ( pFile == NULL )
@@ -87,52 +72,28 @@ void Io_WriteVerilog( Abc_Ntk_t * pNtk, char * pFileName, int fVerLibStyle )
// write the equations for the network
fprintf( pFile, "// Benchmark \"%s\" written by ABC on %s\n", pNtk->pName, Extra_TimeStamp() );
- Io_WriteVerilogInt( pFile, pNtk, fVerLibStyle );
fprintf( pFile, "\n" );
- fclose( pFile );
-}
-
-/**Function*************************************************************
-
- Synopsis [Write verilog.]
-
- Description []
-
- SideEffects []
-
- SeeAlso []
-
-***********************************************************************/
-void Io_WriteVerilogLibrary( Abc_Lib_t * pLibrary, char * pFileName )
-{
- FILE * pFile;
- Abc_Ntk_t * pNtk, * pNetlist;
- int i;
- // start the output stream
- pFile = fopen( pFileName, "w" );
- if ( pFile == NULL )
+ // write modules
+ if ( pNtk->pDesign )
{
- fprintf( stdout, "Io_WriteVerilogLibrary(): Cannot open the output file \"%s\".\n", pFileName );
- return;
+ Vec_PtrForEachEntry( pNtk->pDesign->vModules, pNetlist, i )
+ {
+ assert( Abc_NtkIsNetlist(pNetlist) );
+ if ( pNetlist == pNtk )
+ continue;
+ Io_WriteVerilogInt( pFile, pNetlist );
+ fprintf( pFile, "\n" );
+ }
+ // write the network last
+ Io_WriteVerilogInt( pFile, pNtk );
}
-
- fprintf( pFile, "// Verilog library \"%s\" written by ABC on %s\n", pFileName, Extra_TimeStamp() );
- fprintf( pFile, "\n" );
- // write modules
- Vec_PtrForEachEntry( pLibrary->vModules, pNtk, i )
+ else
{
- // create netlist
-// pNetlist = Abc_NtkLogicToNetlist( pNtk, 0 );
- assert( Abc_NtkIsNetlist(pNtk) );
- pNetlist = pNtk;
- // write the equations for the network
- Io_WriteVerilogInt( pFile, pNetlist, 1 );
- fprintf( pFile, "\n" );
- // delete the netlist
-// Abc_NtkDelete( pNetlist );
+ Io_WriteVerilogInt( pFile, pNtk );
}
+ fprintf( pFile, "\n" );
fclose( pFile );
}
@@ -147,44 +108,54 @@ void Io_WriteVerilogLibrary( Abc_Lib_t * pLibrary, char * pFileName )
SeeAlso []
***********************************************************************/
-void Io_WriteVerilogInt( FILE * pFile, Abc_Ntk_t * pNtk, int fVerLibStyle )
+void Io_WriteVerilogInt( FILE * pFile, Abc_Ntk_t * pNtk )
{
// write inputs and outputs
// fprintf( pFile, "module %s ( gclk,\n ", Abc_NtkName(pNtk) );
fprintf( pFile, "module %s ( \n ", Abc_NtkName(pNtk) );
- Io_WriteVerilogPis( pFile, pNtk, 3 );
- fprintf( pFile, ",\n " );
- Io_WriteVerilogPos( pFile, pNtk, 3 );
+ if ( Abc_NtkPiNum(pNtk) > 0 )
+ {
+ Io_WriteVerilogPis( pFile, pNtk, 3 );
+ fprintf( pFile, ",\n " );
+ }
+ if ( Abc_NtkPoNum(pNtk) > 0 )
+ Io_WriteVerilogPos( pFile, pNtk, 3 );
fprintf( pFile, " );\n" );
// write inputs, outputs, registers, and wires
-// fprintf( pFile, " input gclk," );
- fprintf( pFile, " input " );
- Io_WriteVerilogPis( pFile, pNtk, 10 );
- fprintf( pFile, ";\n" );
- fprintf( pFile, " output" );
- Io_WriteVerilogPos( pFile, pNtk, 5 );
- fprintf( pFile, ";\n" );
- if ( Abc_NtkLatchNum(pNtk) > 0 )
+ if ( Abc_NtkPiNum(pNtk) > 0 )
{
- fprintf( pFile, " reg" );
- Io_WriteVerilogRegs( pFile, pNtk, 4 );
- fprintf( pFile, ";\n" );
+// fprintf( pFile, " input gclk," );
+ fprintf( pFile, " input " );
+ Io_WriteVerilogPis( pFile, pNtk, 10 );
+ fprintf( pFile, ";\n" );
}
- if ( Io_WriteVerilogWiresCount(pNtk) > 0 )
+ if ( Abc_NtkPoNum(pNtk) > 0 )
{
- fprintf( pFile, " wire" );
- Io_WriteVerilogWires( pFile, pNtk, 4 );
- fprintf( pFile, ";\n" );
+ fprintf( pFile, " output" );
+ Io_WriteVerilogPos( pFile, pNtk, 5 );
+ fprintf( pFile, ";\n" );
+ }
+ // if this is not a blackbox, write internal signals
+ if ( !Abc_NtkHasBlackbox(pNtk) )
+ {
+ if ( Abc_NtkLatchNum(pNtk) > 0 )
+ {
+ fprintf( pFile, " reg" );
+ Io_WriteVerilogRegs( pFile, pNtk, 4 );
+ fprintf( pFile, ";\n" );
+ }
+ if ( Io_WriteVerilogWiresCount(pNtk) > 0 )
+ {
+ fprintf( pFile, " wire" );
+ Io_WriteVerilogWires( pFile, pNtk, 4 );
+ fprintf( pFile, ";\n" );
+ }
+ // write nodes
+ Io_WriteVerilogObjects( pFile, pNtk );
+ // write registers
+ if ( Abc_NtkLatchNum(pNtk) > 0 )
+ Io_WriteVerilogLatches( pFile, pNtk );
}
- // write nodes
- if ( fVerLibStyle )
- Io_WriteVerilogVerLibStyle( pFile, pNtk );
- else if ( Abc_NtkHasMapping(pNtk) )
- Io_WriteVerilogGates( pFile, pNtk );
- else
- Io_WriteVerilogNodes( pFile, pNtk );
- // write registers
- Io_WriteVerilogLatches( pFile, pNtk );
// finalize the file
fprintf( pFile, "endmodule\n\n" );
}
@@ -269,34 +240,6 @@ void Io_WriteVerilogPos( FILE * pFile, Abc_Ntk_t * pNtk, int Start )
/**Function*************************************************************
- Synopsis [Counts the number of wires.]
-
- Description []
-
- SideEffects []
-
- SeeAlso []
-
-***********************************************************************/
-int Io_WriteVerilogWiresCount( Abc_Ntk_t * pNtk )
-{
- Abc_Obj_t * pTerm, * pNet;
- int i, nNodes;
- nNodes = Abc_NtkLatchNum(pNtk);
- Abc_NtkForEachNode( pNtk, pTerm, i )
- {
- if ( i == 0 )
- continue;
- pNet = Abc_ObjFanout0(pTerm);
- if ( Abc_ObjIsCo(Abc_ObjFanout0(pNet)) )
- continue;
- nNodes++;
- }
- return nNodes;
-}
-
-/**Function*************************************************************
-
Synopsis [Writes the wires.]
Description []
@@ -308,11 +251,11 @@ int Io_WriteVerilogWiresCount( Abc_Ntk_t * pNtk )
***********************************************************************/
void Io_WriteVerilogWires( FILE * pFile, Abc_Ntk_t * pNtk, int Start )
{
- Abc_Obj_t * pTerm, * pNet;
+ Abc_Obj_t * pObj, * pNet, * pBox, * pTerm;
int LineLength;
int AddedLength;
int NameCounter;
- int i, Counter, nNodes;
+ int i, k, Counter, nNodes;
// count the number of wires
nNodes = Io_WriteVerilogWiresCount( pNtk );
@@ -321,12 +264,12 @@ void Io_WriteVerilogWires( FILE * pFile, Abc_Ntk_t * pNtk, int Start )
Counter = 0;
LineLength = Start;
NameCounter = 0;
- Abc_NtkForEachNode( pNtk, pTerm, i )
+ Abc_NtkForEachNode( pNtk, pObj, i )
{
if ( i == 0 )
continue;
- pNet = Abc_ObjFanout0(pTerm);
- if ( Abc_ObjIsCo(Abc_ObjFanout0(pNet)) )
+ pNet = Abc_ObjFanout0(pObj);
+ if ( Abc_ObjFanoutNum(pNet) > 0 && Abc_ObjIsCo(Abc_ObjFanout0(pNet)) )
continue;
Counter++;
// get the line length after this name is written
@@ -342,9 +285,9 @@ void Io_WriteVerilogWires( FILE * pFile, Abc_Ntk_t * pNtk, int Start )
LineLength += AddedLength;
NameCounter++;
}
- Abc_NtkForEachLatch( pNtk, pTerm, i )
+ Abc_NtkForEachLatch( pNtk, pObj, i )
{
- pNet = Abc_ObjFanin0(Abc_ObjFanin0(pTerm));
+ pNet = Abc_ObjFanin0(Abc_ObjFanin0(pObj));
Counter++;
// get the line length after this name is written
AddedLength = strlen(Io_WriteVerilogGetName(pNet)) + 2;
@@ -359,6 +302,47 @@ void Io_WriteVerilogWires( FILE * pFile, Abc_Ntk_t * pNtk, int Start )
LineLength += AddedLength;
NameCounter++;
}
+ Abc_NtkForEachBox( pNtk, pBox, i )
+ {
+ if ( Abc_ObjIsLatch(pBox) )
+ continue;
+ Abc_ObjForEachFanin( pBox, pTerm, k )
+ {
+ pNet = Abc_ObjFanin0(pTerm);
+ Counter++;
+ // get the line length after this name is written
+ AddedLength = strlen(Io_WriteVerilogGetName(pNet)) + 2;
+ if ( NameCounter && LineLength + AddedLength + 3 > IO_WRITE_LINE_LENGTH )
+ { // write the line extender
+ fprintf( pFile, "\n " );
+ // reset the line length
+ LineLength = 3;
+ NameCounter = 0;
+ }
+ fprintf( pFile, " %s%s", Io_WriteVerilogGetName(pNet), (Counter==nNodes)? "" : "," );
+ LineLength += AddedLength;
+ NameCounter++;
+ }
+ Abc_ObjForEachFanout( pBox, pTerm, k )
+ {
+ pNet = Abc_ObjFanout0(pTerm);
+ if ( Abc_ObjFanoutNum(pNet) > 0 && Abc_ObjIsCo(Abc_ObjFanout0(pNet)) )
+ continue;
+ Counter++;
+ // get the line length after this name is written
+ AddedLength = strlen(Io_WriteVerilogGetName(pNet)) + 2;
+ if ( NameCounter && LineLength + AddedLength + 3 > IO_WRITE_LINE_LENGTH )
+ { // write the line extender
+ fprintf( pFile, "\n " );
+ // reset the line length
+ LineLength = 3;
+ NameCounter = 0;
+ }
+ fprintf( pFile, " %s%s", Io_WriteVerilogGetName(pNet), (Counter==nNodes)? "" : "," );
+ LineLength += AddedLength;
+ NameCounter++;
+ }
+ }
assert( Counter == nNodes );
}
@@ -418,13 +402,13 @@ void Io_WriteVerilogRegs( FILE * pFile, Abc_Ntk_t * pNtk, int Start )
SeeAlso []
***********************************************************************/
-void Io_WriteVerilogLatches( FILE * pFile, Abc_Ntk_t * pNtk )
+void Io_WriteVerilogLatches2( FILE * pFile, Abc_Ntk_t * pNtk )
{
Abc_Obj_t * pLatch;
int i;
Abc_NtkForEachLatch( pNtk, pLatch, i )
{
-// fprintf( pFile, " always@(posedge gclk) begin %s", Abc_ObjName(Abc_ObjFanout0(pLatch)) );
+// fprintf( pFile, " always @(posedge gclk) begin %s", Abc_ObjName(Abc_ObjFanout0(pLatch)) );
fprintf( pFile, " always begin %s", Io_WriteVerilogGetName(Abc_ObjFanout0(Abc_ObjFanout0(pLatch))) );
fprintf( pFile, " = %s; end\n", Io_WriteVerilogGetName(Abc_ObjFanin0(Abc_ObjFanin0(pLatch))) );
if ( Abc_LatchInit(pLatch) == ABC_INIT_ZERO )
@@ -436,22 +420,49 @@ void Io_WriteVerilogLatches( FILE * pFile, Abc_Ntk_t * pNtk )
}
}
-/* // fix by Zhihong
+/**Function*************************************************************
+
+ Synopsis [Writes the latches.]
+
+ Description []
+
+ SideEffects []
+
+ SeeAlso []
+
+***********************************************************************/
void Io_WriteVerilogLatches( FILE * pFile, Abc_Ntk_t * pNtk )
{
Abc_Obj_t * pLatch;
int i;
+ if ( Abc_NtkLatchNum(pNtk) == 0 )
+ return;
+ // write the latches
+// fprintf( pFile, " always @(posedge %s) begin\n", Io_WriteVerilogGetName(Abc_ObjFanout0(Abc_NtkPi(pNtk,0))) );
+ fprintf( pFile, " always begin\n" );
+ Abc_NtkForEachLatch( pNtk, pLatch, i )
+ {
+ fprintf( pFile, " %s", Io_WriteVerilogGetName(Abc_ObjFanout0(Abc_ObjFanout0(pLatch))) );
+ fprintf( pFile, " <= %s;\n", Io_WriteVerilogGetName(Abc_ObjFanin0(Abc_ObjFanin0(pLatch))) );
+ }
+ fprintf( pFile, " end\n" );
+ // check if there are initial values
+ Abc_NtkForEachLatch( pNtk, pLatch, i )
+ if ( Abc_LatchInit(pLatch) == ABC_INIT_ZERO || Abc_LatchInit(pLatch) == ABC_INIT_ONE )
+ break;
+ if ( i == Abc_NtkLatchNum(pNtk) )
+ return;
+ // write the initial values
+ fprintf( pFile, " initial begin\n", Io_WriteVerilogGetName(Abc_ObjFanout0(Abc_NtkPi(pNtk,0))) );
Abc_NtkForEachLatch( pNtk, pLatch, i )
{
if ( Abc_LatchInit(pLatch) == ABC_INIT_ZERO )
- fprintf( pFile, " initial begin %s <= 1\'b0; end\n", Io_WriteVerilogGetName(Abc_ObjFanout0(Abc_ObjFanout0(pLatch))) );
+ fprintf( pFile, " %s <= 1\'b0;\n", Io_WriteVerilogGetName(Abc_ObjFanout0(Abc_ObjFanout0(pLatch))) );
else if ( Abc_LatchInit(pLatch) == ABC_INIT_ONE )
- fprintf( pFile, " initial begin %s <= 1\'b1; end\n", Io_WriteVerilogGetName(Abc_ObjFanout0(Abc_ObjFanout0(pLatch))) );
- fprintf( pFile, " always@(posedge gclk) begin %s", Io_WriteVerilogGetName(Abc_ObjFanout0(Abc_ObjFanout0(pLatch))) );
- fprintf( pFile, " <= %s; end\n", Io_WriteVerilogGetName(Abc_ObjFanin0(Abc_ObjFanin0(pLatch))) );
+ fprintf( pFile, " %s <= 1\'b1;\n", Io_WriteVerilogGetName(Abc_ObjFanout0(Abc_ObjFanout0(pLatch))) );
}
+ fprintf( pFile, " end\n" );
}
-*/
/**Function*************************************************************
@@ -464,10 +475,10 @@ void Io_WriteVerilogLatches( FILE * pFile, Abc_Ntk_t * pNtk )
SeeAlso []
***********************************************************************/
-void Io_WriteVerilogVerLibStyle( FILE * pFile, Abc_Ntk_t * pNtk )
+void Io_WriteVerilogObjects( FILE * pFile, Abc_Ntk_t * pNtk )
{
Vec_Vec_t * vLevels;
- Abc_Ntk_t * pNtkGate;
+ Abc_Ntk_t * pNtkBox;
Abc_Obj_t * pObj, * pTerm, * pFanin;
Hop_Obj_t * pFunc;
int i, k, Counter, nDigits;
@@ -478,18 +489,20 @@ void Io_WriteVerilogVerLibStyle( FILE * pFile, Abc_Ntk_t * pNtk )
// write boxes
Abc_NtkForEachBox( pNtk, pObj, i )
{
- pNtkGate = pObj->pData;
- fprintf( pFile, " %s g%0*d", pNtkGate->pName, nDigits, Counter++ );
+ if ( Abc_ObjIsLatch(pObj) )
+ continue;
+ pNtkBox = pObj->pData;
+ fprintf( pFile, " %s g%0*d", pNtkBox->pName, nDigits, Counter++ );
fprintf( pFile, "(" );
- Abc_NtkForEachPi( pNtkGate, pTerm, k )
+ Abc_NtkForEachPi( pNtkBox, pTerm, k )
{
fprintf( pFile, ".%s ", Io_WriteVerilogGetName(Abc_ObjFanout0(pTerm)) );
- fprintf( pFile, "(%s), ", Io_WriteVerilogGetName(Abc_ObjFanin(pObj,k)) );
+ fprintf( pFile, "(%s), ", Io_WriteVerilogGetName(Abc_ObjFanin0(Abc_ObjFanin(pObj,k))) );
}
- Abc_NtkForEachPo( pNtkGate, pTerm, k )
+ Abc_NtkForEachPo( pNtkBox, pTerm, k )
{
fprintf( pFile, ".%s ", Io_WriteVerilogGetName(Abc_ObjFanin0(pTerm)) );
- fprintf( pFile, "(%s)%s", Io_WriteVerilogGetName(Abc_ObjFanout(pObj,k)), k==Abc_NtkPoNum(pNtkGate)-1? "":", " );
+ fprintf( pFile, "(%s)%s", Io_WriteVerilogGetName(Abc_ObjFanout0(Abc_ObjFanout(pObj,k))), k==Abc_NtkPoNum(pNtkBox)-1? "":", " );
}
fprintf( pFile, ");\n" );
}
@@ -514,40 +527,7 @@ void Io_WriteVerilogVerLibStyle( FILE * pFile, Abc_Ntk_t * pNtk )
/**Function*************************************************************
- Synopsis [Writes the gates.]
-
- Description []
-
- SideEffects []
-
- SeeAlso []
-
-***********************************************************************/
-void Io_WriteVerilogGates( FILE * pFile, Abc_Ntk_t * pNtk )
-{
- Mio_Gate_t * pGate;
- Mio_Pin_t * pGatePin;
- Abc_Obj_t * pObj;
- int i, k, Counter, nDigits, nFanins;
-
- Counter = 1;
- nDigits = Extra_Base10Log( Abc_NtkNodeNum(pNtk) );
- Abc_NtkForEachNode( pNtk, pObj, i )
- {
- pGate = pObj->pData;
- nFanins = Abc_ObjFaninNum(pObj);
- fprintf( pFile, " %s g%0*d", Mio_GateReadName(pGate), nDigits, Counter++ );
- fprintf( pFile, "(.%s (%s),", Mio_GateReadOutName(pGate), Io_WriteVerilogGetName(Abc_ObjFanout0(pObj)) );
- for ( pGatePin = Mio_GateReadPins(pGate), k = 0; pGatePin; pGatePin = Mio_PinReadNext(pGatePin), k++ )
- fprintf( pFile, " .%s (%s)%s", Mio_PinReadName(pGatePin), Io_WriteVerilogGetName(Abc_ObjFanin(pObj,k)), k==nFanins-1? "":"," );
- fprintf( pFile, ");\n" );
- }
-}
-
-
-/**Function*************************************************************
-
- Synopsis [Writes the nodes.]
+ Synopsis [Counts the number of wires.]
Description []
@@ -556,106 +536,34 @@ void Io_WriteVerilogGates( FILE * pFile, Abc_Ntk_t * pNtk )
SeeAlso []
***********************************************************************/
-void Io_WriteVerilogNodes2( FILE * pFile, Abc_Ntk_t * pNtk )
+int Io_WriteVerilogWiresCount( Abc_Ntk_t * pNtk )
{
- Abc_Obj_t * pObj, * pFanin;
- int i, k, nFanins;
- char * pName;
-
+ Abc_Obj_t * pObj, * pNet, * pBox;
+ int i, k, nWires;
+ nWires = Abc_NtkLatchNum(pNtk);
Abc_NtkForEachNode( pNtk, pObj, i )
{
- assert( Abc_SopGetCubeNum(pObj->pData) == 1 );
- nFanins = Abc_ObjFaninNum(pObj);
- if ( nFanins == 0 )
- {
-// fprintf( pFile, " assign %s = 1'b%d;\n", Io_WriteVerilogGetName(Abc_ObjFanout0(pObj)), !Abc_SopIsComplement(pObj->pData) );
- fprintf( pFile, " assign %s = %d;\n", Io_WriteVerilogGetName(Abc_ObjFanout0(pObj)), !Abc_SopIsComplement(pObj->pData) );
+ if ( i == 0 )
continue;
- }
- if ( nFanins == 1 )
- {
- pName = Abc_SopIsInv(pObj->pData)? "not" : "and";
- fprintf( pFile, " %s(%s, ", pName, Io_WriteVerilogGetName(Abc_ObjFanout0(pObj)) );
- fprintf( pFile, "%s);\n", Io_WriteVerilogGetName(Abc_ObjFanin0(pObj)) );
+ pNet = Abc_ObjFanout0(pObj);
+ if ( Abc_ObjFanoutNum(pNet) > 0 && Abc_ObjIsCo(Abc_ObjFanout0(pNet)) )
continue;
- }
- pName = Abc_SopIsComplement(pObj->pData)? "or" : "and";
- fprintf( pFile, " %s(%s, ", pName, Io_WriteVerilogGetName(Abc_ObjFanout0(pObj)) );
-// Abc_ObjForEachFanin( pObj, pFanin, k )
-// fprintf( pFile, "%s%s", Io_WriteVerilogGetName(pFanin), (k==nFanins-1? "" : ", ") );
- Abc_ObjForEachFanin( pObj, pFanin, k )
- {
- char *cube = pObj->pData;
- fprintf( pFile, "%s", cube[k] == '0' ? "~" : "");
- fprintf( pFile, "%s%s", Io_WriteVerilogGetName(pFanin), (k==nFanins-1? "" : ", ") );
- }
- fprintf( pFile, ");\n" );
+ nWires++;
}
-}
-
-/**Function*************************************************************
-
- Synopsis [Writes the nodes.]
-
- Description []
-
- SideEffects []
-
- SeeAlso []
-
-***********************************************************************/
-void Io_WriteVerilogNodes( FILE * pFile, Abc_Ntk_t * pNtk )
-{
- Abc_Obj_t * pObj, * pFanin;
- int i, k, nFanins;
- char pOper[] = " ? ", Symb;
- Abc_NtkForEachNode( pNtk, pObj, i )
+ Abc_NtkForEachBox( pNtk, pBox, i )
{
- assert( Abc_SopGetCubeNum(pObj->pData) == 1 );
- nFanins = Abc_ObjFaninNum(pObj);
- if ( nFanins == 0 )
- {
- fprintf( pFile, " assign %s = 1'b%d;\n", Io_WriteVerilogGetName(Abc_ObjFanout0(pObj)), !Abc_SopIsComplement(pObj->pData) );
+ if ( Abc_ObjIsLatch(pBox) )
continue;
- }
- fprintf( pFile, " assign %s = ", Io_WriteVerilogGetName(Abc_ObjFanout0(pObj)) );
- pOper[1] = Abc_SopIsComplement(pObj->pData) ? '|' : '&';
- Abc_ObjForEachFanin( pObj, pFanin, k )
- {
- Symb = ((char*)pObj->pData)[k];
- assert( Symb == '0' || Symb == '1' );
- if ( Symb == '0' )
- fprintf( pFile, "~" );
- fprintf( pFile, "%s%s", Io_WriteVerilogGetName(pFanin), (k==nFanins-1? "" : pOper) );
- }
- fprintf( pFile, ";\n" );
- }
-}
-
-/**Function*************************************************************
-
- Synopsis []
-
- Description []
-
- SideEffects []
-
- SeeAlso []
-
-***********************************************************************/
-int Io_WriteVerilogCheckNtk( Abc_Ntk_t * pNtk )
-{
- Abc_Obj_t * pObj;
- int i;
- Abc_NtkForEachNode( pNtk, pObj, i )
- {
- if ( Abc_SopGetCubeNum(pObj->pData) > 1 )
+ nWires += Abc_ObjFaninNum(pBox);
+ Abc_ObjForEachFanout( pBox, pObj, k )
{
- printf( "Node %s contains a cover with more than one cube.\n", Abc_ObjName(pObj) );
- return 0;
+ pNet = Abc_ObjFanout0(pObj);
+ if ( Abc_ObjFanoutNum(pNet) > 0 && Abc_ObjIsCo(Abc_ObjFanout0(pNet)) )
+ continue;
+ nWires++;
}
}
- return 1;
+ return nWires;
}
/**Function*************************************************************
diff --git a/src/base/io/module.make b/src/base/io/module.make
index fd66dd22..4b6f762c 100644
--- a/src/base/io/module.make
+++ b/src/base/io/module.make
@@ -8,6 +8,7 @@ SRC += src/base/io/io.c \
src/base/io/ioReadEdif.c \
src/base/io/ioReadEqn.c \
src/base/io/ioReadPla.c \
+ src/base/io/ioReadVerilog.c \
src/base/io/ioUtil.c \
src/base/io/ioWriteAiger.c \
src/base/io/ioWriteBaf.c \
@@ -20,5 +21,4 @@ SRC += src/base/io/io.c \
src/base/io/ioWriteGml.c \
src/base/io/ioWriteList.c \
src/base/io/ioWritePla.c \
- src/base/io/ioWriteVer.c \
- src/base/io/ioWriteVerAux.c
+ src/base/io/ioWriteVerilog.c
diff --git a/src/base/ver/ver.h b/src/base/ver/ver.h
index c7c18f79..575ae7bb 100644
--- a/src/base/ver/ver.h
+++ b/src/base/ver/ver.h
@@ -48,6 +48,7 @@ struct Ver_Man_t_
// input file stream
char * pFileName;
Ver_Stream_t * pReader;
+ int fNameLast;
ProgressBar * pProgress;
// current network and library
Abc_Ntk_t * pNtkCur; // the network under construction
diff --git a/src/base/ver/verCore.c b/src/base/ver/verCore.c
index bbef90be..3a1a9584 100644
--- a/src/base/ver/verCore.c
+++ b/src/base/ver/verCore.c
@@ -60,7 +60,8 @@ static int Ver_ParseGateStandard( Ver_Man_t * pMan, Ver_GateType_t GateType );
static Abc_Obj_t * Ver_ParseCreatePi( Abc_Ntk_t * pNtk, char * pName );
static Abc_Obj_t * Ver_ParseCreatePo( Abc_Ntk_t * pNtk, char * pName );
-static Abc_Obj_t * Ver_ParseCreateLatch( Abc_Ntk_t * pNtk, char * pNetLI, char * pNetLO );
+static Abc_Obj_t * Ver_ParseCreateLatch( Abc_Ntk_t * pNtk, Abc_Obj_t * pNetLI, Abc_Obj_t * pNetLO );
+static Abc_Obj_t * Ver_ParseCreateInv( Abc_Ntk_t * pNtk, Abc_Obj_t * pNet );
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
@@ -281,8 +282,8 @@ int Ver_ParseModule( Ver_Man_t * pMan )
pNtk->pSpec = NULL;
// create constant nets
- Abc_NtkFindOrCreateNet( pNtk, "1'b0" );
- Abc_NtkFindOrCreateNet( pNtk, "1'b1" );
+ Abc_NtkFindOrCreateNet( pNtk, "1\'b0" );
+ Abc_NtkFindOrCreateNet( pNtk, "1\'b1" );
// make sure we stopped at the opening paranthesis
if ( Ver_StreamPopChar(p) != '(' )
@@ -383,13 +384,13 @@ int Ver_ParseModule( Ver_Man_t * pMan )
}
// check if constant 0 net is used
- pNet = Abc_NtkFindOrCreateNet( pNtk, "1'b0" );
+ pNet = Abc_NtkFindOrCreateNet( pNtk, "1\'b0" );
if ( Abc_ObjFanoutNum(pNet) == 0 )
Abc_NtkDeleteObj(pNet);
else
Abc_ObjAddFanin( pNet, Abc_NtkCreateNodeConst0(pNtk) );
// check if constant 1 net is used
- pNet = Abc_NtkFindOrCreateNet( pNtk, "1'b1" );
+ pNet = Abc_NtkFindOrCreateNet( pNtk, "1\'b1" );
if ( Abc_ObjFanoutNum(pNet) == 0 )
Abc_NtkDeleteObj(pNet);
else
@@ -397,6 +398,13 @@ int Ver_ParseModule( Ver_Man_t * pMan )
// fix the dangling nets
Abc_NtkFinalizeRead( pNtk );
+
+ // check the functionality to blackbox if insides are not defined
+ if ( Abc_NtkNodeNum(pNtk) == 0 && Abc_NtkBoxNum(pNtk) == 0 )
+ {
+ pNtk->ntkFunc = ABC_FUNC_BLACKBOX;
+ pNtk->pManFunc = NULL;
+ }
return 1;
}
@@ -415,6 +423,8 @@ int Ver_ParseSignal( Ver_Man_t * pMan, Ver_SignalType_t SigType )
{
Ver_Stream_t * p = pMan->pReader;
Abc_Ntk_t * pNtk = pMan->pNtkCur;
+ char Buffer[1000];
+ int Lower, Upper, i;
char * pWord;
char Symbol;
while ( 1 )
@@ -422,12 +432,41 @@ int Ver_ParseSignal( Ver_Man_t * pMan, Ver_SignalType_t SigType )
pWord = Ver_ParseGetName( pMan );
if ( pWord == NULL )
return 0;
- if ( SigType == VER_SIG_INPUT || SigType == VER_SIG_INOUT )
- Ver_ParseCreatePi( pNtk, pWord );
- if ( SigType == VER_SIG_OUTPUT || SigType == VER_SIG_INOUT )
- Ver_ParseCreatePo( pNtk, pWord );
- if ( SigType == VER_SIG_WIRE || SigType == VER_SIG_REG )
- Abc_NtkFindOrCreateNet( pNtk, pWord );
+ if ( pWord[0] == '[' && !pMan->fNameLast )
+ {
+ Lower = atoi( pWord + 1 );
+ while ( *pWord && *pWord != ':' )
+ pWord++;
+ if ( *pWord == 0 )
+ Upper = Lower;
+ else
+ Upper = atoi( pWord + 1 );
+ if ( Lower > Upper )
+ i = Lower, Lower = Upper, Upper = i;
+ // get the signal name
+ pWord = Ver_ParseGetName( pMan );
+ if ( pWord == NULL )
+ return 0;
+ for ( i = Lower; i <= Upper; i++ )
+ {
+ sprintf( Buffer, "%s[%d]", pWord, i );
+ if ( SigType == VER_SIG_INPUT || SigType == VER_SIG_INOUT )
+ Ver_ParseCreatePi( pNtk, Buffer );
+ if ( SigType == VER_SIG_OUTPUT || SigType == VER_SIG_INOUT )
+ Ver_ParseCreatePo( pNtk, Buffer );
+ if ( SigType == VER_SIG_WIRE || SigType == VER_SIG_REG )
+ Abc_NtkFindOrCreateNet( pNtk, Buffer );
+ }
+ }
+ else
+ {
+ if ( SigType == VER_SIG_INPUT || SigType == VER_SIG_INOUT )
+ Ver_ParseCreatePi( pNtk, pWord );
+ if ( SigType == VER_SIG_OUTPUT || SigType == VER_SIG_INOUT )
+ Ver_ParseCreatePo( pNtk, pWord );
+ if ( SigType == VER_SIG_WIRE || SigType == VER_SIG_REG )
+ Abc_NtkFindOrCreateNet( pNtk, pWord );
+ }
Symbol = Ver_StreamPopChar(p);
if ( Symbol == ',' )
continue;
@@ -461,6 +500,11 @@ int Ver_ParseAssign( Ver_Man_t * pMan )
char Symbol;
int i, Length, fReduction;
+// if ( Ver_StreamGetLineNumber(p) == 2756 )
+// {
+// int x = 0;
+// }
+
// convert from the mapped netlist into the BDD netlist
if ( pNtk->ntkFunc == ABC_FUNC_BLACKBOX )
{
@@ -482,7 +526,9 @@ int Ver_ParseAssign( Ver_Man_t * pMan )
if ( pWord == NULL )
return 0;
// consider the case of reduction operations
- fReduction = (pWord[0] == '{');
+ fReduction = 0;
+ if ( pWord[0] == '{' && !pMan->fNameLast )
+ fReduction = 1;
if ( fReduction )
{
pWord++;
@@ -497,7 +543,7 @@ int Ver_ParseAssign( Ver_Man_t * pMan )
Ver_ParsePrintErrorMessage( pMan );
return 0;
}
- // get the equal sign
+ // get the equality sign
if ( Ver_StreamPopChar(p) != '=' )
{
sprintf( pMan->sError, "Cannot read the assign statement for %s (expected equality sign).", pWord );
@@ -572,28 +618,39 @@ int Ver_ParseAlways( Ver_Man_t * pMan )
Ver_Stream_t * p = pMan->pReader;
Abc_Ntk_t * pNtk = pMan->pNtkCur;
Abc_Obj_t * pNet, * pNet2;
+ int fStopAfterOne;
char * pWord, * pWord2;
char Symbol;
// parse the directive
pWord = Ver_ParseGetName( pMan );
if ( pWord == NULL )
return 0;
- if ( strcmp( pWord, "begin" ) )
+ if ( pWord[0] == '@' )
{
- sprintf( pMan->sError, "Cannot parse the always statement (expected \"begin\")." );
- Ver_ParsePrintErrorMessage( pMan );
- return 0;
+ Ver_StreamSkipToChars( p, ")" );
+ Ver_StreamPopChar(p);
+ // parse the directive
+ pWord = Ver_ParseGetName( pMan );
+ if ( pWord == NULL )
+ return 0;
}
+ // decide how many statements to parse
+ fStopAfterOne = 0;
+ if ( strcmp( pWord, "begin" ) )
+ fStopAfterOne = 1;
// iterate over the initial states
while ( 1 )
{
- // get the name of the output signal
- pWord = Ver_ParseGetName( pMan );
- if ( pWord == NULL )
- return 0;
- // look for the end of directive
- if ( !strcmp( pWord, "end" ) )
- break;
+ if ( !fStopAfterOne )
+ {
+ // get the name of the output signal
+ pWord = Ver_ParseGetName( pMan );
+ if ( pWord == NULL )
+ return 0;
+ // look for the end of directive
+ if ( !strcmp( pWord, "end" ) )
+ break;
+ }
// get the fanout net
pNet = Abc_NtkFindNet( pNtk, pWord );
if ( pNet == NULL )
@@ -602,13 +659,16 @@ int Ver_ParseAlways( Ver_Man_t * pMan )
Ver_ParsePrintErrorMessage( pMan );
return 0;
}
- // get the equal sign
- if ( Ver_StreamPopChar(p) != '=' )
+ // get the equality sign
+ Symbol = Ver_StreamPopChar(p);
+ if ( Symbol != '<' && Symbol != '=' )
{
- sprintf( pMan->sError, "Cannot read the always statement for %s (expected equality sign).", pWord );
+ sprintf( pMan->sError, "Cannot read the assign statement for %s (expected <= or =).", pWord );
Ver_ParsePrintErrorMessage( pMan );
return 0;
}
+ if ( Symbol == '<' )
+ Ver_StreamPopChar(p);
// skip the comments
if ( !Ver_ParseSkipComments( pMan ) )
return 0;
@@ -616,8 +676,14 @@ int Ver_ParseAlways( Ver_Man_t * pMan )
pWord2 = Ver_ParseGetName( pMan );
if ( pWord2 == NULL )
return 0;
- // get the fanin net
- pNet2 = Abc_NtkFindNet( pNtk, pWord2 );
+ // check if the name is complemented
+ if ( pWord2[0] == '~' )
+ {
+ pNet2 = Abc_NtkFindNet( pNtk, pWord2+1 );
+ pNet2 = Ver_ParseCreateInv( pNtk, pNet2 );
+ }
+ else
+ pNet2 = Abc_NtkFindNet( pNtk, pWord2 );
if ( pNet2 == NULL )
{
sprintf( pMan->sError, "Cannot read the always statement for %s (input wire is not defined).", pWord2 );
@@ -625,10 +691,13 @@ int Ver_ParseAlways( Ver_Man_t * pMan )
return 0;
}
// create the latch
- Ver_ParseCreateLatch( pNtk, pNet2->pData, pNet->pData );
+ Ver_ParseCreateLatch( pNtk, pNet2, pNet );
// remove the last symbol
Symbol = Ver_StreamPopChar(p);
assert( Symbol == ';' );
+ // quit if only one directive
+ if ( fStopAfterOne )
+ break;
}
return 1;
}
@@ -649,28 +718,30 @@ int Ver_ParseInitial( Ver_Man_t * pMan )
Ver_Stream_t * p = pMan->pReader;
Abc_Ntk_t * pNtk = pMan->pNtkCur;
Abc_Obj_t * pNode, * pNet;
+ int fStopAfterOne;
char * pWord, * pEquation;
char Symbol;
// parse the directive
pWord = Ver_ParseGetName( pMan );
if ( pWord == NULL )
return 0;
+ // decide how many statements to parse
+ fStopAfterOne = 0;
if ( strcmp( pWord, "begin" ) )
- {
- sprintf( pMan->sError, "Cannot parse the initial statement (expected \"begin\")." );
- Ver_ParsePrintErrorMessage( pMan );
- return 0;
- }
+ fStopAfterOne = 1;
// iterate over the initial states
while ( 1 )
{
- // get the name of the output signal
- pWord = Ver_ParseGetName( pMan );
- if ( pWord == NULL )
- return 0;
- // look for the end of directive
- if ( !strcmp( pWord, "end" ) )
- break;
+ if ( !fStopAfterOne )
+ {
+ // get the name of the output signal
+ pWord = Ver_ParseGetName( pMan );
+ if ( pWord == NULL )
+ return 0;
+ // look for the end of directive
+ if ( !strcmp( pWord, "end" ) )
+ break;
+ }
// get the fanout net
pNet = Abc_NtkFindNet( pNtk, pWord );
if ( pNet == NULL )
@@ -679,13 +750,16 @@ int Ver_ParseInitial( Ver_Man_t * pMan )
Ver_ParsePrintErrorMessage( pMan );
return 0;
}
- // get the equal sign
- if ( Ver_StreamPopChar(p) != '=' )
+ // get the equality sign
+ Symbol = Ver_StreamPopChar(p);
+ if ( Symbol != '<' && Symbol != '=' )
{
- sprintf( pMan->sError, "Cannot read the initial statement for %s (expected equality sign).", pWord );
+ sprintf( pMan->sError, "Cannot read the assign statement for %s (expected <= or =).", pWord );
Ver_ParsePrintErrorMessage( pMan );
return 0;
}
+ if ( Symbol == '<' )
+ Ver_StreamPopChar(p);
// skip the comments
if ( !Ver_ParseSkipComments( pMan ) )
return 0;
@@ -694,24 +768,33 @@ int Ver_ParseInitial( Ver_Man_t * pMan )
if ( pEquation == NULL )
return 0;
// find the corresponding latch
- pNode = Abc_ObjFanin0(pNet);
+ if ( Abc_ObjFaninNum(pNet) == 0 )
+ {
+ sprintf( pMan->sError, "Cannot find the latch to assign the initial value." );
+ Ver_ParsePrintErrorMessage( pMan );
+ return 0;
+ }
+ pNode = Abc_ObjFanin0(Abc_ObjFanin0(pNet));
assert( Abc_ObjIsLatch(pNode) );
// set the initial state
- if ( pEquation[0] == '2' )
- Abc_LatchSetInitDc( pNode );
- else if ( pEquation[0] == '1')
- Abc_LatchSetInit1( pNode );
- else if ( pEquation[0] == '0' )
+ if ( !strcmp(pEquation, "0") || !strcmp(pEquation, "1\'b0") )
Abc_LatchSetInit0( pNode );
- else
+ else if ( !strcmp(pEquation, "1") || !strcmp(pEquation, "1\'b1") )
+ Abc_LatchSetInit1( pNode );
+// else if ( !strcmp(pEquation, "2") )
+// Abc_LatchSetInitDc( pNode );
+ else
{
- sprintf( pMan->sError, "Incorrect initial value of the latch %s (expected equality sign).", pWord );
+ sprintf( pMan->sError, "Incorrect initial value of the latch %s.", Abc_ObjName(pNet) );
Ver_ParsePrintErrorMessage( pMan );
return 0;
}
// remove the last symbol
Symbol = Ver_StreamPopChar(p);
assert( Symbol == ';' );
+ // quit if only one directive
+ if ( fStopAfterOne )
+ break;
}
return 1;
}
@@ -732,7 +815,7 @@ int Ver_ParseGate( Ver_Man_t * pMan, Abc_Ntk_t * pNtkGate )
Ver_Stream_t * p = pMan->pReader;
Abc_Ntk_t * pNtk = pMan->pNtkCur;
Abc_Obj_t * pNetFormal, * pNetActual;
- Abc_Obj_t * pObj, * pNode;
+ Abc_Obj_t * pObj, * pNode, * pTerm;
char * pWord, Symbol, * pGateName;
int i, fCompl, fComplUsed = 0;
unsigned * pPolarity;
@@ -820,9 +903,9 @@ int Ver_ParseGate( Ver_Man_t * pMan, Abc_Ntk_t * pNtkGate )
}
// process the pair
- if ( Abc_ObjIsPi(Abc_ObjFanin0Ntk(pNetFormal)) ) // PI net (with polarity!)
+ if ( Abc_ObjFaninNum(pNetFormal) > 0 && Abc_ObjIsPi(Abc_ObjFanin0Ntk(pNetFormal)) ) // PI net (with polarity!)
Abc_ObjFanin0Ntk(pNetFormal)->pCopy = Abc_ObjNotCond( pNetActual, fCompl );
- else if ( Abc_ObjIsPo(Abc_ObjFanout0Ntk(pNetFormal)) ) // P0 net
+ else if ( Abc_ObjFanoutNum(pNetFormal) > 0 && Abc_ObjIsPo(Abc_ObjFanout0Ntk(pNetFormal)) ) // P0 net
{
assert( fCompl == 0 );
Abc_ObjFanout0Ntk(pNetFormal)->pCopy = pNetActual; // Abc_ObjNotCond( pNetActual, fCompl );
@@ -862,7 +945,7 @@ int Ver_ParseGate( Ver_Man_t * pMan, Abc_Ntk_t * pNtkGate )
Abc_NtkForEachPi( pNtkGate, pObj, i )
if ( pObj->pCopy == NULL )
{
- sprintf( pMan->sError, "Formal input %s of gate %s has no actual input.", Abc_ObjFanout0(pObj)->pData, pNtkGate->pName );
+ sprintf( pMan->sError, "Formal input %s of gate %s has no actual input.", Abc_ObjName(Abc_ObjFanout0(pObj)), pNtkGate->pName );
Ver_ParsePrintErrorMessage( pMan );
return 0;
}
@@ -871,7 +954,7 @@ int Ver_ParseGate( Ver_Man_t * pMan, Abc_Ntk_t * pNtkGate )
Abc_NtkForEachPo( pNtkGate, pObj, i )
if ( pObj->pCopy == NULL )
{
- sprintf( pMan->sError, "Formal output %s of gate %s has no actual output.", Abc_ObjFanin0(pObj)->pData, pNtkGate->pName );
+ sprintf( pMan->sError, "Formal output %s of gate %s has no actual output.", Abc_ObjName(Abc_ObjFanin0(pObj)), pNtkGate->pName );
Ver_ParsePrintErrorMessage( pMan );
return 0;
}
@@ -887,12 +970,6 @@ int Ver_ParseGate( Ver_Man_t * pMan, Abc_Ntk_t * pNtkGate )
}
// create box to represent this gate
pNode = Abc_NtkCreateBlackbox( pMan->pNtkCur );
-/*
- if ( pNode->Id == 57548 )
- {
- int x = 0;
- }
-*/
pNode->pNext = (Abc_Obj_t *)pPolarity;
pNode->pData = pNtkGate;
// connect to fanin nets
@@ -904,15 +981,20 @@ int Ver_ParseGate( Ver_Man_t * pMan, Abc_Ntk_t * pNtkGate )
pObj->pCopy = Abc_ObjRegular( pObj->pCopy );
}
assert( !Abc_ObjIsComplement(pObj->pCopy) );
- Abc_ObjAddFanin( pNode, pObj->pCopy );
+// Abc_ObjAddFanin( pNode, pObj->pCopy );
+ pTerm = Abc_NtkCreateBi( pNtk );
+ Abc_ObjAddFanin( pTerm, pObj->pCopy );
+ Abc_ObjAddFanin( pNode, pTerm );
}
// connect to fanout nets
Abc_NtkForEachPo( pNtkGate, pObj, i )
{
- if ( pObj->pCopy )
- Abc_ObjAddFanin( pObj->pCopy, pNode );
- else
- Abc_ObjAddFanin( Abc_NtkFindOrCreateNet(pNtk, NULL), pNode );
+ if ( pObj->pCopy == NULL )
+ pObj->pCopy = Abc_NtkFindOrCreateNet(pNtk, NULL);
+// Abc_ObjAddFanin( pObj->pCopy, pNode );
+ pTerm = Abc_NtkCreateBo( pNtk );
+ Abc_ObjAddFanin( pTerm, pNode );
+ Abc_ObjAddFanin( pObj->pCopy, pTerm );
}
return 1;
}
@@ -1063,27 +1145,52 @@ Abc_Obj_t * Ver_ParseCreatePo( Abc_Ntk_t * pNtk, char * pName )
Synopsis [Create a latch with the given input/output.]
- Description [By default, the latch value is unknown (ABC_INIT_NONE).]
+ Description [By default, the latch value is a don't-care.]
SideEffects []
SeeAlso []
***********************************************************************/
-Abc_Obj_t * Ver_ParseCreateLatch( Abc_Ntk_t * pNtk, char * pNetLI, char * pNetLO )
+Abc_Obj_t * Ver_ParseCreateLatch( Abc_Ntk_t * pNtk, Abc_Obj_t * pNetLI, Abc_Obj_t * pNetLO )
{
- Abc_Obj_t * pLatch, * pNet;
- // create a new latch and add it to the network
+ Abc_Obj_t * pLatch, * pTerm;
+ // add the BO terminal
+ pTerm = Abc_NtkCreateBi( pNtk );
+ Abc_ObjAddFanin( pTerm, pNetLI );
+ // add the latch box
pLatch = Abc_NtkCreateLatch( pNtk );
- // get the LI net
- pNet = Abc_NtkFindOrCreateNet( pNtk, pNetLI );
- Abc_ObjAddFanin( pLatch, pNet );
+ Abc_ObjAddFanin( pLatch, pTerm );
+ // add the BI terminal
+ pTerm = Abc_NtkCreateBo( pNtk );
+ Abc_ObjAddFanin( pTerm, pLatch );
// get the LO net
- pNet = Abc_NtkFindOrCreateNet( pNtk, pNetLO );
- Abc_ObjAddFanin( pNet, pLatch );
+ Abc_ObjAddFanin( pNetLO, pTerm );
+ // set latch name
+ Abc_ObjAssignName( pLatch, Abc_ObjName(pNetLO), "L" );
+ Abc_LatchSetInitDc( pLatch );
return pLatch;
}
+/**Function*************************************************************
+
+ Synopsis [Creates inverter and returns its net.]
+
+ Description []
+
+ SideEffects []
+
+ SeeAlso []
+
+***********************************************************************/
+Abc_Obj_t * Ver_ParseCreateInv( Abc_Ntk_t * pNtk, Abc_Obj_t * pNet )
+{
+ Abc_Obj_t * pObj;
+ pObj = Abc_NtkCreateNodeInv( pNtk, pNet );
+ pNet = Abc_NtkCreateObj( pNtk, ABC_OBJ_NET );
+ Abc_ObjAddFanin( pNet, pObj );
+ return pNet;
+}
////////////////////////////////////////////////////////////////////////
/// END OF FILE ///
diff --git a/src/base/ver/verFormula.c b/src/base/ver/verFormula.c
index cfe3e0c8..16192f6a 100644
--- a/src/base/ver/verFormula.c
+++ b/src/base/ver/verFormula.c
@@ -83,6 +83,11 @@ void * Ver_FormulaParser( char * pFormula, void * pMan, Vec_Ptr_t * vNames, Vec_
Vec_PtrClear( vStackFn );
Vec_IntClear( vStackOp );
+ if ( !strcmp(pFormula, "0") || !strcmp(pFormula, "1\'b0") )
+ return Hop_ManConst0(pMan);
+ if ( !strcmp(pFormula, "1") || !strcmp(pFormula, "1\'b1") )
+ return Hop_ManConst1(pMan);
+
// make sure that the number of opening and closing parantheses is the same
nParans = 0;
for ( pTemp = pFormula; *pTemp; pTemp++ )
diff --git a/src/base/ver/verParse.c b/src/base/ver/verParse.c
index 8a78e75b..f3afaca0 100644
--- a/src/base/ver/verParse.c
+++ b/src/base/ver/verParse.c
@@ -90,6 +90,7 @@ char * Ver_ParseGetName( Ver_Man_t * pMan )
Ver_Stream_t * p = pMan->pReader;
char Symbol;
char * pWord;
+ pMan->fNameLast = 0;
if ( !Ver_StreamIsOkey(p) )
return NULL;
if ( !Ver_ParseSkipComments( pMan ) )
@@ -97,6 +98,7 @@ char * Ver_ParseGetName( Ver_Man_t * pMan )
Symbol = Ver_StreamScanChar( p );
if ( Symbol == '\\' )
{
+ pMan->fNameLast = 1;
Ver_StreamPopChar( p );
pWord = Ver_StreamGetWord( p, " " );
}
diff --git a/src/base/ver/verStream.c b/src/base/ver/verStream.c
index 7956b13c..0edbcdcb 100644
--- a/src/base/ver/verStream.c
+++ b/src/base/ver/verStream.c
@@ -279,6 +279,9 @@ char Ver_StreamPopChar( Ver_Stream_t * p )
p->fStop = 1;
return -1;
}
+ // count the lines
+ if ( *p->pBufferCur == '\n' )
+ p->nLineCounter++;
return *p->pBufferCur++;
}
@@ -359,6 +362,9 @@ void Ver_StreamSkipToChars( Ver_Stream_t * p, char * pCharsToStop )
if ( *pTemp == 0 ) // pChar is not found in the list
continue;
// the symbol is found - move position and return
+ if ( *pChar == '\n' )
+ p->nLineCounter--;
+ // update buffer
p->pBufferCur = pChar;
return;
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-13 01:56:24 +0000