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authorAlan Mishchenko <alanmi@berkeley.edu>2009-04-05 08:01:00 -0700
committerAlan Mishchenko <alanmi@berkeley.edu>2009-04-05 08:01:00 -0700
commite3e2918eb8a4750b9ce51de821ea6b58941fe65c (patch)
treed678ac6820fb09638f5196501f94aa4c31c60d97 /src/aig/cec/cec.h
parent23fd11037a006089898cb13494305e402a11ec76 (diff)
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Version abc90405
Diffstat (limited to 'src/aig/cec/cec.h')
-rw-r--r--src/aig/cec/cec.h3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/aig/cec/cec.h b/src/aig/cec/cec.h
index e26455ba..a965730f 100644
--- a/src/aig/cec/cec.h
+++ b/src/aig/cec/cec.h
@@ -4,7 +4,7 @@
SystemName [ABC: Logic synthesis and verification system.]
- PackageName [Combinatinoal equivalence checking.]
+ PackageName [Combinational equivalence checking.]
Synopsis [External declarations.]
@@ -44,6 +44,7 @@ struct Cec_ParSat_t_
int nBTLimit; // conflict limit at a node
int nSatVarMax; // the max number of SAT variables
int nCallsRecycle; // calls to perform before recycling SAT solver
+ int fNonChrono; // use non-chronological backtracling (for circuit SAT only)
int fPolarFlip; // flops polarity of variables
int fCheckMiter; // the circuit is the miter
int fFirstStop; // stop on the first sat output