Version abc71001

68 files changed, 0 insertions, 24471 deletions

diff --git a/abc70930/src/map/fpga/fpga.c b/abc70930/src/map/fpga/fpga.c
deleted file mode 100644
index 40423f4f..00000000
--- a/abc70930/src/map/fpga/fpga.c
+++ /dev/null
@@ -1,283 +0,0 @@
-/**CFile****************************************************************
-
-  FileName    [fpga.c]
-
-  PackageName [MVSIS 1.3: Multi-valued logic synthesis system.]
-
-  Synopsis    [Command file for the FPGA package.]
-
-  Author      [MVSIS Group]
-  
-  Affiliation [UC Berkeley]
-
-  Date        [Ver. 2.0. Started - August 18, 2004.]
-
-  Revision    [$Id: fpga.c,v 1.4 2004/10/28 17:36:07 alanmi Exp $]
-
-***********************************************************************/
-
-#include "fpgaInt.h"
-#include "main.h"
-
-////////////////////////////////////////////////////////////////////////
-///                        DECLARATIONS                              ///
-////////////////////////////////////////////////////////////////////////
-
-static int Fpga_CommandReadLibrary( Abc_Frame_t * pAbc, int argc, char **argv );
-static int Fpga_CommandPrintLibrary( Abc_Frame_t * pAbc, int argc, char **argv );
-
-// the library file format should be as follows:
-/*
-# The area/delay of k-variable LUTs:
-# k  area   delay
-1      1      1
-2      2      2
-3      4      3
-4      8      4
-5     16      5
-6     32      6
-*/
-
-////////////////////////////////////////////////////////////////////////
-///                     FUNCTION DEFINITIONS                         ///
-////////////////////////////////////////////////////////////////////////
-
-/**Function*************************************************************
-
-  Synopsis    [Package initialization procedure.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Fpga_Init( Abc_Frame_t * pAbc )
-{
-    // set the default library
-    //Fpga_LutLib_t s_LutLib = { "lutlib", 6, 0, {0,1,2,4,8,16,32}, {{0},{1},{2},{3},{4},{5},{6}} };
-//    Fpga_LutLib_t s_LutLib = { "lutlib", 5, 0, {0,1,1,1,1,1}, {{0},{1},{1},{1},{1},{1}} };
-    Fpga_LutLib_t s_LutLib = { "lutlib", 4, 0, {0,1,1,1,1}, {{0},{1},{1},{1},{1}} };
-    //Fpga_LutLib_t s_LutLib = { "lutlib", 3, 0, {0,1,1,1}, {{0},{1},{1},{1}} };
-
-    Abc_FrameSetLibLut( Fpga_LutLibDup(&s_LutLib) );
-
-    Cmd_CommandAdd( pAbc, "FPGA mapping", "read_lut",   Fpga_CommandReadLibrary,   0 ); 
-    Cmd_CommandAdd( pAbc, "FPGA mapping", "print_lut",  Fpga_CommandPrintLibrary,  0 ); 
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Package ending procedure.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Fpga_End()
-{
-    Fpga_LutLibFree( Abc_FrameReadLibLut() );
-}
-
-
-/**Function*************************************************************
-
-  Synopsis    [Command procedure to read LUT libraries.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Fpga_CommandReadLibrary( Abc_Frame_t * pAbc, int argc, char **argv )
-{
-    FILE * pFile;
-    FILE * pOut, * pErr;
-    Fpga_LutLib_t * pLib;
-    Abc_Ntk_t * pNet;
-    char * FileName;
-    int fVerbose;
-    int c;
-
-    pNet = Abc_FrameReadNtk(pAbc);
-    pOut = Abc_FrameReadOut(pAbc);
-    pErr = Abc_FrameReadErr(pAbc);
-
-    // set the defaults
-    fVerbose = 1;
-    Extra_UtilGetoptReset();
-    while ( (c = Extra_UtilGetopt(argc, argv, "vh")) != EOF ) 
-    {
-        switch (c) 
-        {
-            case 'v':
-                fVerbose ^= 1;
-                break;
-            case 'h':
-                goto usage;
-                break;
-            default:
-                goto usage;
-        }
-    }
-
-
-    if ( argc != globalUtilOptind + 1 )
-    {
-        goto usage;
-    }
-
-    // get the input file name
-    FileName = argv[globalUtilOptind];
-    if ( (pFile = fopen( FileName, "r" )) == NULL )
-    {
-        fprintf( pErr, "Cannot open input file \"%s\". ", FileName );
-        if ( FileName = Extra_FileGetSimilarName( FileName, ".genlib", ".lib", ".gen", ".g", NULL ) )
-            fprintf( pErr, "Did you mean \"%s\"?", FileName );
-        fprintf( pErr, "\n" );
-        return 1;
-    }
-    fclose( pFile );
-
-    // set the new network
-    pLib = Fpga_LutLibCreate( FileName, fVerbose );
-    if ( pLib == NULL )
-    {
-        fprintf( pErr, "Reading LUT library has failed.\n" );
-        goto usage;
-    }
-    // replace the current library
-    Fpga_LutLibFree( Abc_FrameReadLibLut() );
-    Abc_FrameSetLibLut( pLib );
-    return 0;
-
-usage:
-    fprintf( pErr, "\nusage: read_lut [-vh]\n");
-    fprintf( pErr, "\t          read the LUT library from the file\n" );  
-    fprintf( pErr, "\t-v      : toggles enabling of verbose output [default = %s]\n", (fVerbose? "yes" : "no") );
-    fprintf( pErr, "\t-h      : print the command usage\n");
-    fprintf( pErr, "\t                                        \n");
-    fprintf( pErr, "\t          File format for a LUT library:\n");
-    fprintf( pErr, "\t          (the default library is shown)\n");
-    fprintf( pErr, "\t                                        \n");
-    fprintf( pErr, "\t          # The area/delay of k-variable LUTs:\n");
-    fprintf( pErr, "\t          # k  area   delay\n");
-    fprintf( pErr, "\t          1      1      1\n");
-    fprintf( pErr, "\t          2      2      2\n");
-    fprintf( pErr, "\t          3      4      3\n");
-    fprintf( pErr, "\t          4      8      4\n");
-    fprintf( pErr, "\t          5     16      5\n");
-    fprintf( pErr, "\t          6     32      6\n");
-    return 1;       /* error exit */
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Command procedure to read LUT libraries.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Fpga_CommandPrintLibrary( Abc_Frame_t * pAbc, int argc, char **argv )
-{
-    FILE * pOut, * pErr;
-    Abc_Ntk_t * pNet;
-    int fVerbose;
-    int c;
-
-    pNet = Abc_FrameReadNtk(pAbc);
-    pOut = Abc_FrameReadOut(pAbc);
-    pErr = Abc_FrameReadErr(pAbc);
-
-    // set the defaults
-    fVerbose = 1;
-    Extra_UtilGetoptReset();
-    while ( (c = Extra_UtilGetopt(argc, argv, "vh")) != EOF ) 
-    {
-        switch (c) 
-        {
-            case 'v':
-                fVerbose ^= 1;
-                break;
-            case 'h':
-                goto usage;
-                break;
-            default:
-                goto usage;
-        }
-    }
-
-
-    if ( argc != globalUtilOptind )
-    {
-        goto usage;
-    }
-
-    // set the new network
-    Fpga_LutLibPrint( Abc_FrameReadLibLut() );
-    return 0;
-
-usage:
-    fprintf( pErr, "\nusage: read_print [-vh]\n");
-    fprintf( pErr, "\t          print the current LUT library\n" );  
-    fprintf( pErr, "\t-v      : toggles enabling of verbose output [default = %s]\n", (fVerbose? "yes" : "no") );
-    fprintf( pErr, "\t-h      : print the command usage\n");
-    return 1;       /* error exit */
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Sets simple LUT library.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Fpga_SetSimpleLutLib( int nLutSize )
-{
-    Fpga_LutLib_t s_LutLib10= { "lutlib",10, 0, {0,1,1,1,1,1,1,1,1,1,1}, {{0},{1},{1},{1},{1},{1},{1},{1},{1},{1},{1}} };
-    Fpga_LutLib_t s_LutLib9 = { "lutlib", 9, 0, {0,1,1,1,1,1,1,1,1,1}, {{0},{1},{1},{1},{1},{1},{1},{1},{1},{1}} };
-    Fpga_LutLib_t s_LutLib8 = { "lutlib", 8, 0, {0,1,1,1,1,1,1,1,1}, {{0},{1},{1},{1},{1},{1},{1},{1},{1}} };
-    Fpga_LutLib_t s_LutLib7 = { "lutlib", 7, 0, {0,1,1,1,1,1,1,1}, {{0},{1},{1},{1},{1},{1},{1},{1}} };
-    Fpga_LutLib_t s_LutLib6 = { "lutlib", 6, 0, {0,1,1,1,1,1,1}, {{0},{1},{1},{1},{1},{1},{1}} };
-    Fpga_LutLib_t s_LutLib5 = { "lutlib", 5, 0, {0,1,1,1,1,1}, {{0},{1},{1},{1},{1},{1}} };
-    Fpga_LutLib_t s_LutLib4 = { "lutlib", 4, 0, {0,1,1,1,1}, {{0},{1},{1},{1},{1}} };
-    Fpga_LutLib_t s_LutLib3 = { "lutlib", 3, 0, {0,1,1,1}, {{0},{1},{1},{1}} };
-    Fpga_LutLib_t * pLutLib;
-    assert( nLutSize >= 3 && nLutSize <= 10 );
-    switch ( nLutSize )
-    {
-        case 3:  pLutLib = &s_LutLib3; break;
-        case 4:  pLutLib = &s_LutLib4; break;
-        case 5:  pLutLib = &s_LutLib5; break;
-        case 6:  pLutLib = &s_LutLib6; break;
-        case 7:  pLutLib = &s_LutLib7; break;
-        case 8:  pLutLib = &s_LutLib8; break;
-        case 9:  pLutLib = &s_LutLib9; break;
-        case 10: pLutLib = &s_LutLib10; break;
-        default: pLutLib = NULL; break;
-    }
-    if ( pLutLib == NULL )
-        return;
-    Fpga_LutLibFree( Abc_FrameReadLibLut() );
-    Abc_FrameSetLibLut( Fpga_LutLibDup(pLutLib) );
-}
-
-////////////////////////////////////////////////////////////////////////
-///                       END OF FILE                                ///
-////////////////////////////////////////////////////////////////////////
-
-
diff --git a/abc70930/src/map/fpga/fpga.h b/abc70930/src/map/fpga/fpga.h
deleted file mode 100644
index 188420b1..00000000
--- a/abc70930/src/map/fpga/fpga.h
+++ /dev/null
@@ -1,172 +0,0 @@
-/**CFile****************************************************************
-
-  FileName    [fpga.h]
-
-  PackageName [MVSIS 2.0: Multi-valued logic synthesis system.]
-
-  Synopsis    [Technology mapping for variable-size-LUT FPGAs.]
-
-  Author      [MVSIS Group]
-  
-  Affiliation [UC Berkeley]
-
-  Date        [Ver. 2.0. Started - August 18, 2004.]
-
-  Revision    [$Id: fpga.h,v 1.7 2004/09/30 21:18:09 satrajit Exp $]
-
-***********************************************************************/
-
-#ifndef __FPGA_H__
-#define __FPGA_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-////////////////////////////////////////////////////////////////////////
-///                          INCLUDES                                ///
-////////////////////////////////////////////////////////////////////////
-
-////////////////////////////////////////////////////////////////////////
-///                         PARAMETERS                               ///
-////////////////////////////////////////////////////////////////////////
-
-// the maximum size of LUTs used for mapping
-#define FPGA_MAX_LUTSIZE   32
-
-////////////////////////////////////////////////////////////////////////
-///                    STRUCTURE DEFINITIONS                         ///
-////////////////////////////////////////////////////////////////////////
-
-typedef struct Fpga_ManStruct_t_         Fpga_Man_t;
-typedef struct Fpga_NodeStruct_t_        Fpga_Node_t;
-typedef struct Fpga_NodeVecStruct_t_     Fpga_NodeVec_t;
-typedef struct Fpga_CutStruct_t_         Fpga_Cut_t;
-typedef struct Fpga_LutLibStruct_t_      Fpga_LutLib_t;
-
-////////////////////////////////////////////////////////////////////////
-///                       GLOBAL VARIABLES                           ///
-////////////////////////////////////////////////////////////////////////
-
-////////////////////////////////////////////////////////////////////////
-///                       MACRO DEFINITIONS                          ///
-////////////////////////////////////////////////////////////////////////
- 
-#define Fpga_IsComplement(p)    (((int)((unsigned long) (p) & 01)))
-#define Fpga_Regular(p)         ((Fpga_Node_t *)((unsigned long)(p) & ~01)) 
-#define Fpga_Not(p)             ((Fpga_Node_t *)((unsigned long)(p) ^ 01)) 
-#define Fpga_NotCond(p,c)       ((Fpga_Node_t *)((unsigned long)(p) ^ (c)))
-
-#define Fpga_Ref(p)   
-#define Fpga_Deref(p)
-#define Fpga_RecursiveDeref(p,c)
-
-////////////////////////////////////////////////////////////////////////
-///                     FUNCTION DEFINITIONS                         ///
-////////////////////////////////////////////////////////////////////////
-
-/*=== fpgaCreate.c =============================================================*/
-extern Fpga_Man_t *    Fpga_ManCreate( int nInputs, int nOutputs, int fVerbose );
-extern Fpga_Node_t *   Fpga_NodeCreate( Fpga_Man_t * p, Fpga_Node_t * p1, Fpga_Node_t * p2 );
-extern void            Fpga_ManFree( Fpga_Man_t * pMan );
-extern void            Fpga_ManPrintTimeStats( Fpga_Man_t * p );
-
-extern int             Fpga_ManReadInputNum( Fpga_Man_t * p );
-extern int             Fpga_ManReadOutputNum( Fpga_Man_t * p );
-extern Fpga_Node_t **  Fpga_ManReadInputs ( Fpga_Man_t * p );
-extern Fpga_Node_t **  Fpga_ManReadOutputs( Fpga_Man_t * p );
-extern Fpga_Node_t *   Fpga_ManReadConst1 ( Fpga_Man_t * p );
-extern float *         Fpga_ManReadInputArrivals( Fpga_Man_t * p );
-extern int             Fpga_ManReadVerbose( Fpga_Man_t * p );
-extern float *         Fpga_ManReadLutAreas( Fpga_Man_t * p );
-extern void            Fpga_ManSetTimeToMap( Fpga_Man_t * p, int Time );
-extern void            Fpga_ManSetTimeToNet( Fpga_Man_t * p, int Time );
-extern void            Fpga_ManSetTimeTotal( Fpga_Man_t * p, int Time );
-extern void            Fpga_ManSetOutputNames( Fpga_Man_t * p, char ** ppNames );
-extern void            Fpga_ManSetInputArrivals( Fpga_Man_t * p, float * pArrivals );
-extern void            Fpga_ManSetAreaRecovery( Fpga_Man_t * p, int fAreaRecovery );
-extern void            Fpga_ManSetDelayLimit( Fpga_Man_t * p, float DelayLimit );
-extern void            Fpga_ManSetAreaLimit( Fpga_Man_t * p, float AreaLimit );
-extern void            Fpga_ManSetTimeLimit( Fpga_Man_t * p, float TimeLimit );
-extern void            Fpga_ManSetObeyFanoutLimits( Fpga_Man_t * p, int fObeyFanoutLimits );              
-extern void            Fpga_ManSetNumIterations( Fpga_Man_t * p, int nNumIterations );
-extern int             Fpga_ManReadFanoutViolations( Fpga_Man_t * p );
-extern void            Fpga_ManSetFanoutViolations( Fpga_Man_t * p, int nVio );
-extern void            Fpga_ManSetChoiceNodeNum( Fpga_Man_t * p, int nChoiceNodes );
-extern void            Fpga_ManSetChoiceNum( Fpga_Man_t * p, int nChoices );
-extern void            Fpga_ManSetVerbose( Fpga_Man_t * p, int fVerbose );
-extern void            Fpga_ManSetSwitching( Fpga_Man_t * p, int fSwitching );
-extern void            Fpga_ManSetLatchPaths( Fpga_Man_t * p, int fLatchPaths );
-extern void            Fpga_ManSetLatchNum( Fpga_Man_t * p, int nLatches );
-extern void            Fpga_ManSetDelayTarget( Fpga_Man_t * p, float DelayTarget );
-extern void            Fpga_ManSetName( Fpga_Man_t * p, char * pFileName );
-
-extern int             Fpga_LibReadLutMax( Fpga_LutLib_t * pLib );
-
-extern char *          Fpga_NodeReadData0( Fpga_Node_t * p );
-extern Fpga_Node_t *   Fpga_NodeReadData1( Fpga_Node_t * p );
-extern int             Fpga_NodeReadRefs( Fpga_Node_t * p );
-extern int             Fpga_NodeReadNum( Fpga_Node_t * p );
-extern int             Fpga_NodeReadLevel( Fpga_Node_t * p );
-extern Fpga_Cut_t *    Fpga_NodeReadCuts( Fpga_Node_t * p );
-extern Fpga_Cut_t *    Fpga_NodeReadCutBest( Fpga_Node_t * p );
-extern Fpga_Node_t *   Fpga_NodeReadOne( Fpga_Node_t * p );
-extern Fpga_Node_t *   Fpga_NodeReadTwo( Fpga_Node_t * p );
-extern void            Fpga_NodeSetLevel( Fpga_Node_t * p, Fpga_Node_t * pNode );
-extern void            Fpga_NodeSetData0( Fpga_Node_t * p, char * pData );
-extern void            Fpga_NodeSetData1( Fpga_Node_t * p, Fpga_Node_t * pNode );
-extern void            Fpga_NodeSetArrival( Fpga_Node_t * p, float Time );
-extern void            Fpga_NodeSetNextE( Fpga_Node_t * p, Fpga_Node_t * pNextE );
-extern void            Fpga_NodeSetRepr( Fpga_Node_t * p, Fpga_Node_t * pRepr );
-extern void            Fpga_NodeSetSwitching( Fpga_Node_t * p, float Switching );
-
-extern int             Fpga_NodeIsConst( Fpga_Node_t * p );
-extern int             Fpga_NodeIsVar( Fpga_Node_t * p );
-extern int             Fpga_NodeIsAnd( Fpga_Node_t * p );
-extern int             Fpga_NodeComparePhase( Fpga_Node_t * p1, Fpga_Node_t * p2 );
-
-extern int             Fpga_CutReadLeavesNum( Fpga_Cut_t * p );
-extern Fpga_Node_t **  Fpga_CutReadLeaves( Fpga_Cut_t * p );
-
-extern Fpga_Node_t *   Fpga_NodeAnd( Fpga_Man_t * p, Fpga_Node_t * p1, Fpga_Node_t * p2 );
-extern Fpga_Node_t *   Fpga_NodeOr( Fpga_Man_t * p, Fpga_Node_t * p1, Fpga_Node_t * p2 );
-extern Fpga_Node_t *   Fpga_NodeExor( Fpga_Man_t * p, Fpga_Node_t * p1, Fpga_Node_t * p2 );
-extern Fpga_Node_t *   Fpga_NodeMux( Fpga_Man_t * p, Fpga_Node_t * pNode, Fpga_Node_t * pNodeT, Fpga_Node_t * pNodeE );
-extern void            Fpga_NodeSetChoice( Fpga_Man_t * pMan, Fpga_Node_t * pNodeOld, Fpga_Node_t * pNodeNew );
-
-extern void            Fpga_ManStats( Fpga_Man_t * p );
-
-/*=== fpgaCore.c =============================================================*/
-extern int             Fpga_Mapping( Fpga_Man_t * p );
-/*=== fpgaCut.c ===============================================================*/
-extern void            Fpga_MappingCreatePiCuts( Fpga_Man_t * p );
-extern void            Fpga_CutsCleanSign( Fpga_Man_t * pMan );
-/*=== fpgaCutUtils.c =============================================================*/
-extern void            Fpga_CutCreateFromNode( Fpga_Man_t * p, int iRoot, int * pLeaves, int nLeaves );
-extern void            Fpga_MappingSetUsedCuts( Fpga_Man_t * p );
-/*=== fpgaLib.c =============================================================*/
-extern Fpga_LutLib_t * Fpga_LutLibDup( Fpga_LutLib_t * p );
-extern int             Fpga_LutLibReadVarMax( Fpga_LutLib_t * p );
-extern float *         Fpga_LutLibReadLutAreas( Fpga_LutLib_t * p );
-extern float *         Fpga_LutLibReadLutDelays( Fpga_LutLib_t * p );
-extern float           Fpga_LutLibReadLutArea( Fpga_LutLib_t * p, int Size );
-extern float           Fpga_LutLibReadLutDelay( Fpga_LutLib_t * p, int Size );
-/*=== fpgaTruth.c =============================================================*/
-extern void *          Fpga_TruthsCutBdd( void * dd, Fpga_Cut_t * pCut );
-extern int             Fpga_CutVolume( Fpga_Cut_t * pCut );
-/*=== fpgaUtil.c =============================================================*/
-extern int             Fpga_ManCheckConsistency( Fpga_Man_t * p );
-extern void            Fpga_ManCleanData0( Fpga_Man_t * pMan );
-extern Fpga_NodeVec_t * Fpga_CollectNodeTfo( Fpga_Man_t * pMan, Fpga_Node_t * pNode );
-/*=== fpga.c =============================================================*/
-extern void            Fpga_SetSimpleLutLib( int nLutSize );
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-////////////////////////////////////////////////////////////////////////
-///                       END OF FILE                                ///
-////////////////////////////////////////////////////////////////////////
diff --git a/abc70930/src/map/fpga/fpgaCore.c b/abc70930/src/map/fpga/fpgaCore.c
deleted file mode 100644
index 634a8eb1..00000000
--- a/abc70930/src/map/fpga/fpgaCore.c
+++ /dev/null
@@ -1,188 +0,0 @@
-/**CFile****************************************************************
-
-  FileName    [fpgaCore.c]
-
-  PackageName [MVSIS 1.3: Multi-valued logic synthesis system.]
-
-  Synopsis    [Technology mapping for variable-size-LUT FPGAs.]
-
-  Author      [MVSIS Group]
-  
-  Affiliation [UC Berkeley]
-
-  Date        [Ver. 2.0. Started - August 18, 2004.]
-
-  Revision    [$Id: fpgaCore.c,v 1.7 2004/10/01 23:41:04 satrajit Exp $]
-
-***********************************************************************/
-
-#include "fpgaInt.h"
-
-////////////////////////////////////////////////////////////////////////
-///                        DECLARATIONS                              ///
-////////////////////////////////////////////////////////////////////////
-
-static int  Fpga_MappingPostProcess( Fpga_Man_t * p );
-
-extern int s_MappingTime;
-extern int s_MappingMem;
-
-
-////////////////////////////////////////////////////////////////////////
-///                     FUNCTION DEFINITIONS                         ///
-////////////////////////////////////////////////////////////////////////
-
-/**Function*************************************************************
-
-  Synopsis    [Performs technology mapping for the given object graph.]
-
-  Description [The object graph is stored in the mapping manager.
-  First, all the AND-nodes, which fanout into the POs, are collected
-  in the DFS fashion. Next, three steps are performed: the k-feasible
-  cuts are computed for each node, the truth tables are computed for
-  each cut, and the delay-optimal matches are assigned for each node.]
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Fpga_Mapping( Fpga_Man_t * p )
-{
-    int clk, clkTotal = clock();
- 
-    // collect the nodes reachable from POs in the DFS order (including the choices)
-    p->vAnds = Fpga_MappingDfs( p, 1 );
-    Fpga_ManReportChoices( p ); // recomputes levels
-    Fpga_MappingSetChoiceLevels( p );
-
-    // compute the cuts of nodes in the DFS order
-    clk = clock();
-    Fpga_MappingCuts( p );
-    p->timeCuts = clock() - clk;
-
-    // match the truth tables to the supergates
-    clk = clock();
-    if ( !Fpga_MappingMatches( p, 1 ) )
-        return 0;
-    p->timeMatch = clock() - clk;
-
-    // perform area recovery
-    clk = clock();
-    if ( !Fpga_MappingPostProcess( p ) )
-        return 0;
-    p->timeRecover = clock() - clk;
-//PRT( "Total mapping time", clock() - clkTotal );
-
-    s_MappingTime = clock() - clkTotal;
-    s_MappingMem = Fpga_CutCountAll(p) * (sizeof(Fpga_Cut_t) - sizeof(int) * (FPGA_MAX_LEAVES - p->nVarsMax));
-
-    // print the AI-graph used for mapping
-    //Fpga_ManShow( p, "test" );
-//    if ( p->fVerbose )
-//        Fpga_MappingPrintOutputArrivals( p );
-    if ( p->fVerbose )
-    {
-        PRT( "Total time", clock() - clkTotal );
-    }
-    return 1;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Postprocesses the mapped network for area recovery.]
-
-  Description [This procedure assumes that the mapping is assigned.
-  It iterates the loop, in which the required times are computed and
-  the mapping is updated. It is conceptually similar to the paper: 
-  V. Manohararajah, S. D. Brown, Z. G. Vranesic, Heuristics for area 
-  minimization in LUT-based FPGA technology mapping. Proc. IWLS '04.]
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Fpga_MappingPostProcess( Fpga_Man_t * p )
-{
-    int fShowSwitching    = 0;
-    int fRecoverAreaFlow  = 1;
-    int fRecoverArea      = 1;
-    float aAreaTotalCur, aAreaTotalCur2;
-    int Iter, clk;
-
-//if ( p->fVerbose )
-//    printf( "Best clock period = %5.2f\n", Fpga_TimeComputeArrivalMax(p) );
-
-    // compute area, set references, and collect nodes used in the mapping
-    Iter = 1;
-    aAreaTotalCur = Fpga_MappingSetRefsAndArea( p );
-if ( p->fVerbose )
-{
-printf( "Iteration %dD :  Area = %8.1f  ", Iter++, aAreaTotalCur );
-if ( fShowSwitching )
-printf( "Switch = %8.1f  ", Fpga_MappingGetSwitching(p,p->vMapping) );
-else
-printf( "Delay = %5.2f  ", Fpga_TimeComputeArrivalMax(p) );
-
-PRT( "Time", p->timeMatch );
-}
-
-    if ( !p->fAreaRecovery )
-        return 1;
-
-    if ( fRecoverAreaFlow )
-    {
-clk = clock();
-        // compute the required times and the fanouts
-        Fpga_TimeComputeRequiredGlobal( p, 1 );
-        // remap topologically
-        Fpga_MappingMatches( p, 0 );
-        // get the resulting area
-//        aAreaTotalCur = Fpga_MappingSetRefsAndArea( p );
-        aAreaTotalCur = Fpga_MappingAreaTrav( p );
-        // note that here we do not update the reference counter
-        // for some reason, this works better on benchmarks
-if ( p->fVerbose )
-{
-printf( "Iteration %dF :  Area = %8.1f  ", Iter++, aAreaTotalCur );
-if ( fShowSwitching )
-printf( "Switch = %8.1f  ", Fpga_MappingGetSwitching(p,p->vMapping) );
-else
-printf( "Delay = %5.2f  ", Fpga_TimeComputeArrivalMax(p) );
-PRT( "Time", clock() - clk );
-}
-    }
-
-    // update reference counters
-    aAreaTotalCur2 = Fpga_MappingSetRefsAndArea( p );
-    assert( aAreaTotalCur == aAreaTotalCur2 );
-
-    if ( fRecoverArea )
-    {
-clk = clock();
-        // compute the required times and the fanouts
-        Fpga_TimeComputeRequiredGlobal( p, 0 );
-        // remap topologically
-        if ( p->fSwitching )
-            Fpga_MappingMatchesSwitch( p );
-        else
-            Fpga_MappingMatchesArea( p );
-        // get the resulting area
-        aAreaTotalCur = Fpga_MappingSetRefsAndArea( p );
-if ( p->fVerbose )
-{
-printf( "Iteration %d%s :  Area = %8.1f  ", Iter++, (p->fSwitching?"S":"A"), aAreaTotalCur );
-if ( fShowSwitching )
-printf( "Switch = %8.1f  ", Fpga_MappingGetSwitching(p,p->vMapping) );
-else
-printf( "Delay = %5.2f  ", Fpga_TimeComputeArrivalMax(p) );
-PRT( "Time", clock() - clk );
-}
-    }
-
-    p->fAreaGlo = aAreaTotalCur;
-    return 1;
-}
-
-
diff --git a/abc70930/src/map/fpga/fpgaCreate.c b/abc70930/src/map/fpga/fpgaCreate.c
deleted file mode 100644
index fa0f80d1..00000000
--- a/abc70930/src/map/fpga/fpgaCreate.c
+++ /dev/null
@@ -1,580 +0,0 @@
-/**CFile****************************************************************
-
-  FileName    [fpgaCreate.c]
-
-  PackageName [MVSIS 1.3: Multi-valued logic synthesis system.]
-
-  Synopsis    [Technology mapping for variable-size-LUT FPGAs.]
-
-  Author      [MVSIS Group]
-  
-  Affiliation [UC Berkeley]
-
-  Date        [Ver. 2.0. Started - August 18, 2004.]
-
-  Revision    [$Id: fpgaCreate.c,v 1.8 2004/09/30 21:18:09 satrajit Exp $]
-
-***********************************************************************/
-
-#include "fpgaInt.h"
-#include "main.h"
-
-////////////////////////////////////////////////////////////////////////
-///                        DECLARATIONS                              ///
-////////////////////////////////////////////////////////////////////////
-
-static void            Fpga_TableCreate( Fpga_Man_t * p );
-static void            Fpga_TableResize( Fpga_Man_t * p );
-static Fpga_Node_t *   Fpga_TableLookup( Fpga_Man_t * p, Fpga_Node_t * p1, Fpga_Node_t * p2 );
-
-// hash key for the structural hash table
-static inline unsigned Fpga_HashKey2( Fpga_Node_t * p0, Fpga_Node_t * p1, int TableSize ) { return ((unsigned)(p0) + (unsigned)(p1) * 12582917) % TableSize; }
-
-////////////////////////////////////////////////////////////////////////
-///                     FUNCTION DEFINITIONS                         ///
-////////////////////////////////////////////////////////////////////////
-
-/**Function*************************************************************
-
-  Synopsis    [Reads parameters of the mapping manager.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int             Fpga_ManReadInputNum( Fpga_Man_t * p )                    { return p->nInputs;    }
-int             Fpga_ManReadOutputNum( Fpga_Man_t * p )                   { return p->nOutputs;   }
-Fpga_Node_t **  Fpga_ManReadInputs ( Fpga_Man_t * p )                     { return p->pInputs;    }
-Fpga_Node_t **  Fpga_ManReadOutputs( Fpga_Man_t * p )                     { return p->pOutputs;   }
-Fpga_Node_t *   Fpga_ManReadConst1 ( Fpga_Man_t * p )                     { return p->pConst1;    }
-float *         Fpga_ManReadInputArrivals( Fpga_Man_t * p )               { return p->pInputArrivals;}
-int             Fpga_ManReadVerbose( Fpga_Man_t * p )                     { return p->fVerbose;   }
-float *         Fpga_ManReadLutAreas( Fpga_Man_t * p )                    { return p->pLutLib->pLutAreas;  }
-void            Fpga_ManSetTimeToMap( Fpga_Man_t * p, int Time )          { p->timeToMap = Time;  }
-void            Fpga_ManSetTimeToNet( Fpga_Man_t * p, int Time )          { p->timeToNet = Time;  }
-void            Fpga_ManSetTimeTotal( Fpga_Man_t * p, int Time )          { p->timeTotal = Time;  }
-void            Fpga_ManSetOutputNames( Fpga_Man_t * p, char ** ppNames ) { p->ppOutputNames = ppNames; }
-void            Fpga_ManSetInputArrivals( Fpga_Man_t * p, float * pArrivals ) { p->pInputArrivals = pArrivals; }
-void            Fpga_ManSetAreaRecovery( Fpga_Man_t * p, int fAreaRecovery ) { p->fAreaRecovery = fAreaRecovery;}
-void            Fpga_ManSetDelayLimit( Fpga_Man_t * p, float DelayLimit )    { p->DelayLimit   = DelayLimit;    }
-void            Fpga_ManSetAreaLimit( Fpga_Man_t * p, float AreaLimit )      { p->AreaLimit    = AreaLimit;     }
-void            Fpga_ManSetTimeLimit( Fpga_Man_t * p, float TimeLimit )      { p->TimeLimit    = TimeLimit;     }
-void            Fpga_ManSetChoiceNodeNum( Fpga_Man_t * p, int nChoiceNodes ) { p->nChoiceNodes = nChoiceNodes;  }  
-void            Fpga_ManSetChoiceNum( Fpga_Man_t * p, int nChoices )         { p->nChoices = nChoices;          }   
-void            Fpga_ManSetVerbose( Fpga_Man_t * p, int fVerbose )           { p->fVerbose = fVerbose;          }   
-void            Fpga_ManSetSwitching( Fpga_Man_t * p, int fSwitching )       { p->fSwitching = fSwitching;      }   
-void            Fpga_ManSetLatchPaths( Fpga_Man_t * p, int fLatchPaths )     { p->fLatchPaths = fLatchPaths;    }   
-void            Fpga_ManSetLatchNum( Fpga_Man_t * p, int nLatches )          { p->nLatches = nLatches;          }   
-void            Fpga_ManSetDelayTarget( Fpga_Man_t * p, float DelayTarget )  { p->DelayTarget = DelayTarget;    }   
-void            Fpga_ManSetName( Fpga_Man_t * p, char * pFileName )          { p->pFileName = pFileName;        }   
-
-/**Function*************************************************************
-
-  Synopsis    [Reads the parameters of the LUT library.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int             Fpga_LibReadLutMax( Fpga_LutLib_t * pLib )  { return pLib->LutMax; }
-
-/**Function*************************************************************
-
-  Synopsis    [Reads parameters of the mapping node.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-char *          Fpga_NodeReadData0( Fpga_Node_t * p )                   { return p->pData0;    }
-Fpga_Node_t *   Fpga_NodeReadData1( Fpga_Node_t * p )                   { return p->pLevel;    }
-int             Fpga_NodeReadRefs( Fpga_Node_t * p )                    { return p->nRefs;     }
-int             Fpga_NodeReadNum( Fpga_Node_t * p )                     { return p->Num;       }
-int             Fpga_NodeReadLevel( Fpga_Node_t * p )                   { return Fpga_Regular(p)->Level;  }
-Fpga_Cut_t *    Fpga_NodeReadCuts( Fpga_Node_t * p )                    { return p->pCuts;     }
-Fpga_Cut_t *    Fpga_NodeReadCutBest( Fpga_Node_t * p )                 { return p->pCutBest;  }
-Fpga_Node_t *   Fpga_NodeReadOne( Fpga_Node_t * p )                     { return p->p1;        }
-Fpga_Node_t *   Fpga_NodeReadTwo( Fpga_Node_t * p )                     { return p->p2;        }
-void            Fpga_NodeSetData0( Fpga_Node_t * p, char * pData )         { p->pData0 = pData;  }
-void            Fpga_NodeSetData1( Fpga_Node_t * p, Fpga_Node_t * pNode )  { p->pLevel = pNode;  }
-void            Fpga_NodeSetNextE( Fpga_Node_t * p, Fpga_Node_t * pNextE ) { p->pNextE = pNextE; }
-void            Fpga_NodeSetRepr( Fpga_Node_t * p, Fpga_Node_t * pRepr )   { p->pRepr = pRepr;   }
-void            Fpga_NodeSetSwitching( Fpga_Node_t * p, float Switching )  { p->Switching = Switching;   }
-
-/**Function*************************************************************
-
-  Synopsis    [Checks the type of the node.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int             Fpga_NodeIsConst( Fpga_Node_t * p )    {  return (Fpga_Regular(p))->Num == -1;    }
-int             Fpga_NodeIsVar( Fpga_Node_t * p )      {  return (Fpga_Regular(p))->p1 == NULL && (Fpga_Regular(p))->Num >= 0; }
-int             Fpga_NodeIsAnd( Fpga_Node_t * p )      {  return (Fpga_Regular(p))->p1 != NULL;  }
-int             Fpga_NodeComparePhase( Fpga_Node_t * p1, Fpga_Node_t * p2 ) { assert( !Fpga_IsComplement(p1) ); assert( !Fpga_IsComplement(p2) ); return p1->fInv ^ p2->fInv; }
-
-/**Function*************************************************************
-
-  Synopsis    [Reads parameters from the cut.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int             Fpga_CutReadLeavesNum( Fpga_Cut_t * p )            {  return p->nLeaves;  }
-Fpga_Node_t **  Fpga_CutReadLeaves( Fpga_Cut_t * p )               {  return p->ppLeaves; }
-
-
-/**Function*************************************************************
-
-  Synopsis    [Create the mapping manager.]
-
-  Description [The number of inputs and outputs is assumed to be
-  known is advance. It is much simpler to have them fixed upfront.
-  When it comes to representing the object graph in the form of
-  AIG, the resulting manager is similar to the regular AIG manager, 
-  except that it does not use reference counting (and therefore
-  does not have garbage collections). It does have table resizing.
-  The data structure is more flexible to represent additional 
-  information needed for mapping.]
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-Fpga_Man_t * Fpga_ManCreate( int nInputs, int nOutputs, int fVerbose )
-{
-    Fpga_Man_t * p;
-    int i;
-
-    // start the manager
-    p = ALLOC( Fpga_Man_t, 1 );
-    memset( p, 0, sizeof(Fpga_Man_t) );
-    p->pLutLib   = Abc_FrameReadLibLut();
-    p->nVarsMax  = p->pLutLib->LutMax;
-    p->fVerbose  = fVerbose;
-    p->fAreaRecovery = 1;
-    p->fEpsilon  = (float)0.001;
-
-    Fpga_TableCreate( p );
-//if ( p->fVerbose )
-//    printf( "Node = %d (%d) bytes. Cut = %d bytes.\n", sizeof(Fpga_Node_t), FPGA_NUM_BYTES(sizeof(Fpga_Node_t)), sizeof(Fpga_Cut_t) ); 
-    p->mmNodes  = Extra_MmFixedStart( FPGA_NUM_BYTES(sizeof(Fpga_Node_t)) );
-    p->mmCuts   = Extra_MmFixedStart( sizeof(Fpga_Cut_t) );
-
-    assert( p->nVarsMax > 0 );
-//    Fpga_MappingSetupTruthTables( p->uTruths );
-
-    // make sure the constant node will get index -1
-    p->nNodes = -1;
-    // create the constant node
-    p->pConst1 = Fpga_NodeCreate( p, NULL, NULL );
-    p->vNodesAll = Fpga_NodeVecAlloc( 1000 );
-    p->vMapping = Fpga_NodeVecAlloc( 1000 );
-
-    // create the PI nodes
-    p->nInputs = nInputs;
-    p->pInputs = ALLOC( Fpga_Node_t *, nInputs );
-    for ( i = 0; i < nInputs; i++ )
-        p->pInputs[i] = Fpga_NodeCreate( p, NULL, NULL );
-
-    // create the place for the output nodes
-    p->nOutputs = nOutputs;
-    p->pOutputs = ALLOC( Fpga_Node_t *, nOutputs );
-    memset( p->pOutputs, 0, sizeof(Fpga_Node_t *) * nOutputs );
-    return p;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Deallocates the mapping manager.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Fpga_ManFree( Fpga_Man_t * p )
-{
-//    Fpga_ManStats( p );
-//    int i;
-//    for ( i = 0; i < p->vNodesAll->nSize; i++ )
-//        Fpga_NodeVecFree( p->vNodesAll->pArray[i]->vFanouts );
-//    Fpga_NodeVecFree( p->pConst1->vFanouts );
-    if ( p->vMapping )
-        Fpga_NodeVecFree( p->vMapping );
-    if ( p->vAnds )    
-        Fpga_NodeVecFree( p->vAnds );
-    if ( p->vNodesAll )    
-        Fpga_NodeVecFree( p->vNodesAll );
-    Extra_MmFixedStop( p->mmNodes );
-    Extra_MmFixedStop( p->mmCuts );
-    FREE( p->ppOutputNames );
-    FREE( p->pInputArrivals );
-    FREE( p->pInputs );
-    FREE( p->pOutputs );
-    FREE( p->pBins );
-    FREE( p );
-}
-
-
-/**Function*************************************************************
-
-  Synopsis    [Prints runtime statistics of the mapping manager.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Fpga_ManPrintTimeStats( Fpga_Man_t * p )
-{
-    extern char * pNetName;
-    extern int TotalLuts;
-//    FILE * pTable;
-
-    
-/*
-    pTable = fopen( "stats.txt", "a+" );
-    fprintf( pTable, "%s ", pNetName );
-    fprintf( pTable, "%.0f ", p->fRequiredGlo );
-//    fprintf( pTable, "%.0f ", p->fAreaGlo );//+ (float)nOutputInvs );
-    fprintf( pTable, "%.0f ", (float)TotalLuts );
-    fprintf( pTable, "%4.2f\n", (float)(p->timeTotal-p->timeToMap)/(float)(CLOCKS_PER_SEC) );
-    fclose( pTable );
-*/
-
-//    printf( "N-canonical = %d. Matchings = %d.  ", p->nCanons, p->nMatches );
-//    printf( "Choice nodes = %d. Choices = %d.\n", p->nChoiceNodes, p->nChoices );
-    PRT( "ToMap", p->timeToMap );
-    PRT( "Cuts ", p->timeCuts );
-    PRT( "Match", p->timeMatch );
-    PRT( "Area ", p->timeRecover );
-    PRT( "ToNet", p->timeToNet );
-    PRT( "TOTAL", p->timeTotal );
-    if ( p->time1 ) { PRT( "time1", p->time1 ); }
-    if ( p->time2 ) { PRT( "time2", p->time2 ); }
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Creates a new node.]
-
-  Description [This procedure should be called to create the constant
-  node and the PI nodes first.]
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-Fpga_Node_t * Fpga_NodeCreate( Fpga_Man_t * p, Fpga_Node_t * p1, Fpga_Node_t * p2 )
-{
-    Fpga_Node_t * pNode;
-    // create the node
-    pNode = (Fpga_Node_t *)Extra_MmFixedEntryFetch( p->mmNodes );
-    memset( pNode, 0, sizeof(Fpga_Node_t) );
-    // set very large required time
-    pNode->tRequired = FPGA_FLOAT_LARGE;
-    pNode->aEstFanouts = -1;
-    pNode->p1  = p1; 
-    pNode->p2  = p2;
-    // set the number of this node
-    pNode->Num = p->nNodes++;
-    // place to store the fanouts
-//    pNode->vFanouts = Fpga_NodeVecAlloc( 5 );
-    // store this node in the internal array
-    if ( pNode->Num >= 0 )
-        Fpga_NodeVecPush( p->vNodesAll, pNode );
-    else
-        pNode->fInv = 1;
-    // set the level of this node
-    if ( p1 ) 
-    {
-#ifdef FPGA_ALLOCATE_FANOUT
-        // create the fanout info
-        Fpga_NodeAddFaninFanout( Fpga_Regular(p1), pNode );
-        Fpga_NodeAddFaninFanout( Fpga_Regular(p2), pNode );
-#endif
-        // compute the level
-        pNode->Level = 1 + FPGA_MAX(Fpga_Regular(p1)->Level, Fpga_Regular(p2)->Level);
-        pNode->fInv  = Fpga_NodeIsSimComplement(p1) & Fpga_NodeIsSimComplement(p2);
-    }
-    // reference the inputs 
-    if ( p1 ) Fpga_NodeRef(p1);
-    if ( p2 ) Fpga_NodeRef(p2);
-    return pNode;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Create the unique table of AND gates.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Fpga_TableCreate( Fpga_Man_t * pMan )
-{
-    assert( pMan->pBins == NULL );
-    pMan->nBins = Cudd_Prime(50000);
-    pMan->pBins = ALLOC( Fpga_Node_t *, pMan->nBins );
-    memset( pMan->pBins, 0, sizeof(Fpga_Node_t *) * pMan->nBins );
-    pMan->nNodes = 0;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Looks up the AND2 node in the unique table.]
-
-  Description [This procedure implements one-level hashing. All the nodes
-  are hashed by their children. If the node with the same children was already
-  created, it is returned by the call to this procedure. If it does not exist,
-  this procedure creates a new node with these children. ]
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-Fpga_Node_t * Fpga_TableLookup( Fpga_Man_t * pMan, Fpga_Node_t * p1, Fpga_Node_t * p2 )
-{
-    Fpga_Node_t * pEnt;
-    unsigned Key;
-
-    if ( p1 == p2 )
-        return p1;
-    if ( p1 == Fpga_Not(p2) )
-        return Fpga_Not(pMan->pConst1);
-    if ( Fpga_NodeIsConst(p1) )
-    {
-        if ( p1 == pMan->pConst1 )
-            return p2;
-        return Fpga_Not(pMan->pConst1);
-    }
-    if ( Fpga_NodeIsConst(p2) )
-    {
-        if ( p2 == pMan->pConst1 )
-            return p1;
-        return Fpga_Not(pMan->pConst1);
-    }
-
-    if ( Fpga_Regular(p1)->Num > Fpga_Regular(p2)->Num )
-        pEnt = p1, p1 = p2, p2 = pEnt;
-
-    Key = Fpga_HashKey2( p1, p2, pMan->nBins );
-    for ( pEnt = pMan->pBins[Key]; pEnt; pEnt = pEnt->pNext )
-        if ( pEnt->p1 == p1 && pEnt->p2 == p2 )
-            return pEnt;
-    // resize the table
-    if ( pMan->nNodes >= 2 * pMan->nBins )
-    {
-        Fpga_TableResize( pMan );
-        Key = Fpga_HashKey2( p1, p2, pMan->nBins );
-    }
-    // create the new node
-    pEnt = Fpga_NodeCreate( pMan, p1, p2 );
-    // add the node to the corresponding linked list in the table
-    pEnt->pNext = pMan->pBins[Key];
-    pMan->pBins[Key] = pEnt;
-    return pEnt;
-}
-
-
-/**Function*************************************************************
-
-  Synopsis    [Resizes the table.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Fpga_TableResize( Fpga_Man_t * pMan )
-{
-    Fpga_Node_t ** pBinsNew;
-    Fpga_Node_t * pEnt, * pEnt2;
-    int nBinsNew, Counter, i, clk;
-    unsigned Key;
-
-clk = clock();
-    // get the new table size
-    nBinsNew = Cudd_Prime(2 * pMan->nBins); 
-    // allocate a new array
-    pBinsNew = ALLOC( Fpga_Node_t *, nBinsNew );
-    memset( pBinsNew, 0, sizeof(Fpga_Node_t *) * nBinsNew );
-    // rehash the entries from the old table
-    Counter = 0;
-    for ( i = 0; i < pMan->nBins; i++ )
-        for ( pEnt = pMan->pBins[i], pEnt2 = pEnt? pEnt->pNext: NULL; pEnt; 
-              pEnt = pEnt2, pEnt2 = pEnt? pEnt->pNext: NULL )
-        {
-            Key = Fpga_HashKey2( pEnt->p1, pEnt->p2, nBinsNew );
-            pEnt->pNext = pBinsNew[Key];
-            pBinsNew[Key] = pEnt;
-            Counter++;
-        }
-    assert( Counter == pMan->nNodes - pMan->nInputs );
-    if ( pMan->fVerbose )
-    {
-//        printf( "Increasing the unique table size from %6d to %6d. ", pMan->nBins, nBinsNew );
-//        PRT( "Time", clock() - clk );
-    }
-    // replace the table and the parameters
-    free( pMan->pBins );
-    pMan->pBins = pBinsNew;
-    pMan->nBins = nBinsNew;
-}
-
-
-
-/**Function*************************************************************
-
-  Synopsis    [Elementary AND operation on the AIG.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-Fpga_Node_t * Fpga_NodeAnd( Fpga_Man_t * p, Fpga_Node_t * p1, Fpga_Node_t * p2 )
-{
-    Fpga_Node_t * pNode;
-    pNode = Fpga_TableLookup( p, p1, p2 );     
-    return pNode;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Elementary OR operation on the AIG.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-Fpga_Node_t * Fpga_NodeOr( Fpga_Man_t * p, Fpga_Node_t * p1, Fpga_Node_t * p2 )
-{
-    Fpga_Node_t * pNode;
-    pNode = Fpga_Not( Fpga_TableLookup( p, Fpga_Not(p1), Fpga_Not(p2) ) );  
-    return pNode;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Elementary EXOR operation on the AIG.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-Fpga_Node_t * Fpga_NodeExor( Fpga_Man_t * p, Fpga_Node_t * p1, Fpga_Node_t * p2 )
-{
-    return Fpga_NodeMux( p, p1, Fpga_Not(p2), p2 );
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Elementary MUX operation on the AIG.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-Fpga_Node_t * Fpga_NodeMux( Fpga_Man_t * p, Fpga_Node_t * pC, Fpga_Node_t * pT, Fpga_Node_t * pE )
-{
-    Fpga_Node_t * pAnd1, * pAnd2, * pRes;
-    pAnd1 = Fpga_TableLookup( p, pC,           pT ); 
-    pAnd2 = Fpga_TableLookup( p, Fpga_Not(pC), pE ); 
-    pRes  = Fpga_NodeOr( p, pAnd1, pAnd2 );           
-    return pRes;
-}
-
-
-/**Function*************************************************************
-
-  Synopsis    [Sets the node to be equivalent to the given one.]
-
-  Description [This procedure is a work-around for the equivalence check.
-  Does not verify the equivalence. Use at the user's risk.]
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Fpga_NodeSetChoice( Fpga_Man_t * pMan, Fpga_Node_t * pNodeOld, Fpga_Node_t * pNodeNew )
-{
-    pNodeNew->pNextE = pNodeOld->pNextE;
-    pNodeOld->pNextE = pNodeNew;
-    pNodeNew->pRepr  = pNodeOld;
-}
-
-
-    
-/**Function*************************************************************
-
-  Synopsis    [Prints some interesting stats.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Fpga_ManStats( Fpga_Man_t * p )
-{
-    FILE * pTable;
-    pTable = fopen( "stats.txt", "a+" );
-    fprintf( pTable, "%s ", p->pFileName );
-    fprintf( pTable, "%4d ", p->nInputs - p->nLatches );
-    fprintf( pTable, "%4d ", p->nOutputs - p->nLatches );
-    fprintf( pTable, "%4d ", p->nLatches );
-    fprintf( pTable, "%7d ", p->vAnds->nSize );
-    fprintf( pTable, "%7d ", Fpga_CutCountAll(p) );
-    fprintf( pTable, "%2d\n", (int)p->fRequiredGlo );
-    fclose( pTable );
-}
-
-
-////////////////////////////////////////////////////////////////////////
-///                       END OF FILE                                ///
-////////////////////////////////////////////////////////////////////////
-
diff --git a/abc70930/src/map/fpga/fpgaCut.c b/abc70930/src/map/fpga/fpgaCut.c
deleted file mode 100644
index a5505e72..00000000
--- a/abc70930/src/map/fpga/fpgaCut.c
+++ /dev/null
@@ -1,1159 +0,0 @@
-/**CFile****************************************************************
-
-  FileName    [fpgaCut.c]
-
-  PackageName [MVSIS 1.3: Multi-valued logic synthesis system.]
-
-  Synopsis    [Generic technology mapping engine.]
-
-  Author      [MVSIS Group]
-  
-  Affiliation [UC Berkeley]
-
-  Date        [Ver. 2.0. Started - August 18, 2004.]
-
-  Revision    [$Id: fpgaCut.c,v 1.3 2004/07/06 04:55:57 alanmi Exp $]
-
-***********************************************************************/
- 
-#include "fpgaInt.h"
-
-////////////////////////////////////////////////////////////////////////
-///                        DECLARATIONS                              ///
-////////////////////////////////////////////////////////////////////////
-
-typedef struct Fpga_CutTableStrutct_t Fpga_CutTable_t;
-struct Fpga_CutTableStrutct_t
-{
-    Fpga_Cut_t ** pBins;        // the table used for linear probing
-    int           nBins;        // the size of the table
-    int *         pCuts;        // the array of cuts currently stored 
-    int           nCuts;        // the number of cuts currently stored 
-    Fpga_Cut_t ** pArray;       // the temporary array of cuts
-    Fpga_Cut_t ** pCuts1;       // the temporary array of cuts
-    Fpga_Cut_t ** pCuts2;       // the temporary array of cuts
-};
-
-// the largest number of cuts considered
-//#define  FPGA_CUTS_MAX_COMPUTE   500
-#define  FPGA_CUTS_MAX_COMPUTE   2000
-// the largest number of cuts used
-//#define  FPGA_CUTS_MAX_USE       200
-#define  FPGA_CUTS_MAX_USE       1000
-
-// primes used to compute the hash key
-static int s_HashPrimes[10] = { 109, 499, 557, 619, 631, 709, 797, 881, 907, 991 };
-
-static int bit_count[256] = {
-  0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5,
-  1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5,2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6,
-  1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5,2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6,
-  2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6,3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7,
-  1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5,2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6,
-  2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6,3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7,
-  2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6,3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7,
-  3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7,4,5,5,6,5,6,6,7,5,6,6,7,6,7,7,8
-};
-
-#define FPGA_COUNT_ONES(u) (bit_count[(u)&255]+bit_count[((u)>>8)&255]+bit_count[((u)>>16)&255]+bit_count[(u)>>24])
-
-static Fpga_Cut_t *      Fpga_CutCompute( Fpga_Man_t * p, Fpga_CutTable_t * pTable, Fpga_Node_t * pNode );
-static void              Fpga_CutFilter( Fpga_Man_t * p, Fpga_Node_t * pNode );
-static Fpga_Cut_t *      Fpga_CutMergeLists( Fpga_Man_t * p, Fpga_CutTable_t * pTable, Fpga_Cut_t * pList1, Fpga_Cut_t * pList2, int fComp1, int fComp2, int fPivot1, int fPivot2 );
-static int               Fpga_CutMergeTwo( Fpga_Cut_t * pCut1, Fpga_Cut_t * pCut2, Fpga_Node_t * ppNodes[], int nNodesMax );
-static Fpga_Cut_t *      Fpga_CutUnionLists( Fpga_Cut_t * pList1, Fpga_Cut_t * pList2 );
-static int               Fpga_CutBelongsToList( Fpga_Cut_t * pList, Fpga_Node_t * ppNodes[], int nNodes );
-extern Fpga_Cut_t *      Fpga_CutAlloc( Fpga_Man_t * p );
-extern int               Fpga_CutCountAll( Fpga_Man_t * pMan );
-
-static void              Fpga_CutListPrint( Fpga_Man_t * pMan, Fpga_Node_t * pRoot );
-static void              Fpga_CutListPrint2( Fpga_Man_t * pMan, Fpga_Node_t * pRoot );
-static void              Fpga_CutPrint_( Fpga_Man_t * pMan, Fpga_Cut_t * pCut, Fpga_Node_t * pRoot );
-
-static Fpga_CutTable_t * Fpga_CutTableStart( Fpga_Man_t * pMan );
-static void              Fpga_CutTableStop( Fpga_CutTable_t * p );
-static unsigned          Fpga_CutTableHash( Fpga_Node_t * ppNodes[], int nNodes );
-static int               Fpga_CutTableLookup( Fpga_CutTable_t * p, Fpga_Node_t * ppNodes[], int nNodes );
-static Fpga_Cut_t *      Fpga_CutTableConsider( Fpga_Man_t * pMan, Fpga_CutTable_t * p, Fpga_Node_t * ppNodes[], int nNodes );
-static void              Fpga_CutTableRestart( Fpga_CutTable_t * p );
-
-static int               Fpga_CutSortCutsCompare( Fpga_Cut_t ** pC1, Fpga_Cut_t ** pC2 );
-static Fpga_Cut_t *      Fpga_CutSortCuts( Fpga_Man_t * pMan, Fpga_CutTable_t * p, Fpga_Cut_t * pList );
-static int               Fpga_CutList2Array( Fpga_Cut_t ** pArray, Fpga_Cut_t * pList );
-static Fpga_Cut_t *      Fpga_CutArray2List( Fpga_Cut_t ** pArray, int nCuts );
-
-
-// iterator through all the cuts of the list
-#define Fpga_ListForEachCut( pList, pCut )                \
-    for ( pCut = pList;                                   \
-          pCut;                                           \
-          pCut = pCut->pNext )
-#define Fpga_ListForEachCutSafe( pList, pCut, pCut2 )     \
-    for ( pCut = pList,                                   \
-          pCut2 = pCut? pCut->pNext: NULL;                \
-          pCut;                                           \
-          pCut = pCut2,                                   \
-          pCut2 = pCut? pCut->pNext: NULL )
-
-
-////////////////////////////////////////////////////////////////////////
-///                     FUNCTION DEFINITIONS                         ///
-////////////////////////////////////////////////////////////////////////
-
-/**Function*************************************************************
-
-  Synopsis    [Computes the cuts for each node in the object graph.]
-
-  Description [The cuts are computed in one sweep over the mapping graph. 
-  First, the elementary cuts, which include the node itself, are assigned 
-  to the PI nodes. The internal nodes are considered in the DFS order.
-  Each node is two-input AND-gate. So to compute the cuts at a node, we
-  need to merge the sets of cuts of its two predecessors. The merged set
-  contains only unique cuts with the number of inputs equal to k or less.
-  Finally, the elementary cut, composed of the node itself, is added to
-  the set of cuts for the node.
-  
-  This procedure is pretty fast for 5-feasible cuts, but it dramatically
-  slows down on some "dense" networks when computing 6-feasible cuts.
-  The problem is that there are too many cuts in this case. We should
-  think how to heuristically trim the number of cuts in such cases, 
-  to have reasonable runtime.]
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Fpga_MappingCuts( Fpga_Man_t * p )
-{
-    ProgressBar * pProgress;
-    Fpga_CutTable_t * pTable;
-    Fpga_Node_t * pNode;
-    int nCuts, nNodes, i;
-    int clk = clock();
-
-    // set the elementary cuts for the PI variables
-    assert( p->nVarsMax > 1 && p->nVarsMax < 11 );
-    Fpga_MappingCreatePiCuts( p );
-
-    // compute the cuts for the internal nodes
-    nNodes = p->vAnds->nSize;
-    pProgress = Extra_ProgressBarStart( stdout, nNodes );
-    pTable = Fpga_CutTableStart( p );
-    for ( i = 0; i < nNodes; i++ )
-    {
-        Extra_ProgressBarUpdate( pProgress, i, "Cuts ..." );
-        pNode = p->vAnds->pArray[i];
-        if ( !Fpga_NodeIsAnd( pNode ) )
-            continue;
-        Fpga_CutCompute( p, pTable, pNode );
-    }
-    Extra_ProgressBarStop( pProgress );
-    Fpga_CutTableStop( pTable );
-
-    // report the stats
-    if ( p->fVerbose )
-    {
-        nCuts = Fpga_CutCountAll(p);
-        printf( "Nodes = %6d. Total %d-cuts = %d. Cuts per node = %.1f. ", 
-               p->nNodes, p->nVarsMax, nCuts, ((float)nCuts)/p->nNodes );
-        PRT( "Time", clock() - clk );
-    }
-
-    // print the cuts for the first primary output
-//    Fpga_CutListPrint( p, Fpga_Regular(p->pOutputs[0]) );
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Performs technology mapping for variable-size-LUTs.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Fpga_MappingCreatePiCuts( Fpga_Man_t * p )
-{
-    Fpga_Cut_t * pCut;
-    int i;
-
-    // set the elementary cuts for the PI variables
-    for ( i = 0; i < p->nInputs; i++ )
-    {
-        pCut = Fpga_CutAlloc( p );
-        pCut->nLeaves = 1;
-        pCut->ppLeaves[0] = p->pInputs[i];
-        pCut->uSign = (1 << (i%31));
-        p->pInputs[i]->pCuts   = pCut;
-        p->pInputs[i]->pCutBest = pCut;
-        // set the input arrival times
-//        p->pInputs[i]->pCut[1]->tArrival = p->pInputArrivals[i];
-    }
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Computes the cuts for one node.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-Fpga_Cut_t * Fpga_CutCompute( Fpga_Man_t * p, Fpga_CutTable_t * pTable, Fpga_Node_t * pNode )
-{
-    Fpga_Node_t * pTemp;
-    Fpga_Cut_t * pList, * pList1, * pList2;
-    Fpga_Cut_t * pCut;
-    int fTree = 0;
-    int fPivot1 = fTree && (Fpga_NodeReadRef(pNode->p1)>2);
-    int fPivot2 = fTree && (Fpga_NodeReadRef(pNode->p2)>2);
-
-    // if the cuts are computed return them
-    if ( pNode->pCuts )
-        return pNode->pCuts;
-
-    // compute the cuts for the children
-    pList1 = Fpga_Regular(pNode->p1)->pCuts;
-    pList2 = Fpga_Regular(pNode->p2)->pCuts;
-    // merge the lists
-    pList = Fpga_CutMergeLists( p, pTable, pList1, pList2, 
-        Fpga_IsComplement(pNode->p1), Fpga_IsComplement(pNode->p2),
-        fPivot1, fPivot2 );
-    // if there are functionally equivalent nodes, union them with this list
-    assert( pList );
-    // only add to the list of cuts if the node is a representative one
-    if ( pNode->pRepr == NULL )
-    {
-        for ( pTemp = pNode->pNextE; pTemp; pTemp = pTemp->pNextE )
-        {
-            assert( pTemp->pCuts );
-            pList = Fpga_CutUnionLists( pList, pTemp->pCuts );
-            assert( pTemp->pCuts );
-            pList = Fpga_CutSortCuts( p, pTable, pList );
-        }
-    }
-    // add the new cut
-    pCut = Fpga_CutAlloc( p );
-    pCut->nLeaves = 1;
-    pCut->ppLeaves[0] = pNode;
-    pCut->uSign = (1 << (pNode->Num%31));
-    pCut->fLevel = (float)pCut->ppLeaves[0]->Level;
-    // append (it is important that the elementary cut is appended first)
-    pCut->pNext = pList;
-    // set at the node
-    pNode->pCuts = pCut;
-    // remove the dominated cuts
-//    Fpga_CutFilter( p, pNode );
-    // set the phase correctly
-    if ( pNode->pRepr && Fpga_NodeComparePhase(pNode, pNode->pRepr) )
-    {
-        Fpga_ListForEachCut( pNode->pCuts, pCut )
-            pCut->Phase = 1;
-    }
-
-
-/*
-    { 
-        Fpga_Cut_t * pPrev;
-        int i, Counter = 0;
-        for ( pCut = pNode->pCuts->pNext, pPrev = pNode->pCuts; pCut; pCut = pCut->pNext )
-        {
-            for ( i = 0; i < pCut->nLeaves; i++ )
-                if ( pCut->ppLeaves[i]->Level >= pNode->Level )
-                    break;
-            if ( i != pCut->nLeaves )
-                pPrev->pNext = pCut->pNext;
-            else 
-                pPrev = pCut; 
-        }
-    }
-    { 
-        int i, Counter = 0;;
-        for ( pCut = pNode->pCuts->pNext; pCut; pCut = pCut->pNext )
-            for ( i = 0; i < pCut->nLeaves; i++ )
-                Counter += (pCut->ppLeaves[i]->Level >= pNode->Level);
-        if ( Counter )
-            printf( " %d", Counter );
-    }
-*/
-
-    return pCut;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Filter the cuts using dominance.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Fpga_CutFilter( Fpga_Man_t * p, Fpga_Node_t * pNode )
-{ 
-    Fpga_Cut_t * pTemp, * pPrev, * pCut, * pCut2;
-    int i, k, Counter;
-
-    Counter = 0;
-    pPrev = pNode->pCuts;
-    Fpga_ListForEachCutSafe( pNode->pCuts->pNext, pCut, pCut2 )
-    {
-        // go through all the previous cuts up to pCut
-        for ( pTemp = pNode->pCuts->pNext; pTemp != pCut; pTemp = pTemp->pNext )
-        {
-            // check if every node in pTemp is contained in pCut
-            for ( i = 0; i < pTemp->nLeaves; i++ )
-            {
-                for ( k = 0; k < pCut->nLeaves; k++ )
-                    if ( pTemp->ppLeaves[i] == pCut->ppLeaves[k] )
-                        break;
-                if ( k == pCut->nLeaves ) // node i in pTemp is not contained in pCut
-                    break;
-            }
-            if ( i == pTemp->nLeaves ) // every node in pTemp is contained in pCut
-            {
-                Counter++;
-                break;
-            }
-        }
-        if ( pTemp != pCut ) // pTemp contain pCut
-        {
-            pPrev->pNext = pCut->pNext;  // skip pCut
-            // recycle pCut
-            Fpga_CutFree( p, pCut );
-        }
-        else 
-            pPrev = pCut; 
-    }
-//  printf( "Dominated = %3d. \n", Counter );
-}
-
-
-/**Function*************************************************************
-
-  Synopsis    [Merges two lists of cuts.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-Fpga_Cut_t * Fpga_CutMergeLists( Fpga_Man_t * p, Fpga_CutTable_t * pTable, 
-    Fpga_Cut_t * pList1, Fpga_Cut_t * pList2, int fComp1, int fComp2, int fPivot1, int fPivot2 )
-{
-    Fpga_Node_t * ppNodes[FPGA_MAX_LEAVES];
-    Fpga_Cut_t * pListNew, ** ppListNew, * pLists[FPGA_MAX_LEAVES+1] = { NULL };
-    Fpga_Cut_t * pCut, * pPrev, * pTemp1, * pTemp2;
-    int nNodes, Counter, i;
-    Fpga_Cut_t ** ppArray1, ** ppArray2, ** ppArray3;
-    int nCuts1, nCuts2, nCuts3, k, fComp3;
-
-    ppArray1 = pTable->pCuts1;
-    ppArray2 = pTable->pCuts2;
-    nCuts1 = Fpga_CutList2Array( ppArray1, pList1 );
-    nCuts2 = Fpga_CutList2Array( ppArray2, pList2 );
-    if ( fPivot1 )
-        nCuts1 = 1;
-    if ( fPivot2 )
-        nCuts2 = 1;
-    // swap the lists based on their length
-    if ( nCuts1 > nCuts2 )
-    {
-         ppArray3 = ppArray1;
-         ppArray1 = ppArray2;
-         ppArray2 = ppArray3;
-
-         nCuts3 = nCuts1;
-         nCuts1 = nCuts2;
-         nCuts2 = nCuts3;
-
-         fComp3 = fComp1;
-         fComp1 = fComp2;
-         fComp2 = fComp3;
-    }
-    // pList1 is shorter or equal length compared to pList2
- 
-    // prepare the manager for the cut computation
-    Fpga_CutTableRestart( pTable );
-    // go through the cut pairs
-    Counter = 0;
-//    for ( pTemp1 = pList1; pTemp1; pTemp1 = fPivot1? NULL: pTemp1->pNext )
-//        for ( pTemp2 = pList2; pTemp2; pTemp2 = fPivot2? NULL: pTemp2->pNext )
-    for ( i = 0; i < nCuts1; i++ )
-    {
-        for ( k = 0; k <= i; k++ )
-        {
-            pTemp1 = ppArray1[i];
-            pTemp2 = ppArray2[k];
-
-            if ( pTemp1->nLeaves == p->nVarsMax && pTemp2->nLeaves == p->nVarsMax )
-            {
-                if ( pTemp1->ppLeaves[0] != pTemp2->ppLeaves[0] )
-                    continue;
-                if ( pTemp1->ppLeaves[1] != pTemp2->ppLeaves[1] )
-                    continue;
-            }
-
-            // check if k-feasible cut exists
-            nNodes = Fpga_CutMergeTwo( pTemp1, pTemp2, ppNodes, p->nVarsMax );
-            if ( nNodes == 0 )
-                continue;
-            // consider the cut for possible addition to the set of new cuts
-            pCut = Fpga_CutTableConsider( p, pTable, ppNodes, nNodes );
-            if ( pCut == NULL )
-                continue;
-            // add data to the cut
-            pCut->pOne = Fpga_CutNotCond( pTemp1, fComp1 );
-            pCut->pTwo = Fpga_CutNotCond( pTemp2, fComp2 );
-            // create the signature
-            pCut->uSign = pTemp1->uSign | pTemp2->uSign;
-            // add it to the corresponding list
-            pCut->pNext = pLists[pCut->nLeaves];
-            pLists[pCut->nLeaves] = pCut;
-            // count this cut and quit if limit is reached
-            Counter++;
-            if ( Counter == FPGA_CUTS_MAX_COMPUTE )
-                goto QUITS;
-        }
-        for ( k = 0; k < i; k++ )
-        {
-            pTemp1 = ppArray1[k];
-            pTemp2 = ppArray2[i];
-
-            if ( pTemp1->nLeaves == p->nVarsMax && pTemp2->nLeaves == p->nVarsMax )
-            {
-                if ( pTemp1->ppLeaves[0] != pTemp2->ppLeaves[0] )
-                    continue;
-                if ( pTemp1->ppLeaves[1] != pTemp2->ppLeaves[1] )
-                    continue;
-            }
-
-
-            // check if k-feasible cut exists
-            nNodes = Fpga_CutMergeTwo( pTemp1, pTemp2, ppNodes, p->nVarsMax );
-            if ( nNodes == 0 )
-                continue;
-            // consider the cut for possible addition to the set of new cuts
-            pCut = Fpga_CutTableConsider( p, pTable, ppNodes, nNodes );
-            if ( pCut == NULL )
-                continue;
-            // add data to the cut
-            pCut->pOne = Fpga_CutNotCond( pTemp1, fComp1 );
-            pCut->pTwo = Fpga_CutNotCond( pTemp2, fComp2 );
-            // create the signature
-            pCut->uSign = pTemp1->uSign | pTemp2->uSign;
-            // add it to the corresponding list
-            pCut->pNext = pLists[pCut->nLeaves];
-            pLists[pCut->nLeaves] = pCut;
-            // count this cut and quit if limit is reached
-            Counter++;
-            if ( Counter == FPGA_CUTS_MAX_COMPUTE )
-                goto QUITS;
-        }
-    }
-    // consider the rest of them
-    for ( i = nCuts1; i < nCuts2; i++ )
-        for ( k = 0; k < nCuts1; k++ )
-        {
-            pTemp1 = ppArray1[k];
-            pTemp2 = ppArray2[i];
-
-            if ( pTemp1->nLeaves == p->nVarsMax && pTemp2->nLeaves == p->nVarsMax )
-            {
-                if ( pTemp1->ppLeaves[0] != pTemp2->ppLeaves[0] )
-                    continue;
-                if ( pTemp1->ppLeaves[1] != pTemp2->ppLeaves[1] )
-                    continue;
-                if ( pTemp1->ppLeaves[2] != pTemp2->ppLeaves[2] )
-                    continue;
-            }
-
-
-            // check if k-feasible cut exists
-            nNodes = Fpga_CutMergeTwo( pTemp1, pTemp2, ppNodes, p->nVarsMax );
-            if ( nNodes == 0 )
-                continue;
-            // consider the cut for possible addition to the set of new cuts
-            pCut = Fpga_CutTableConsider( p, pTable, ppNodes, nNodes );
-            if ( pCut == NULL )
-                continue;
-            // add data to the cut
-            pCut->pOne = Fpga_CutNotCond( pTemp1, fComp1 );
-            pCut->pTwo = Fpga_CutNotCond( pTemp2, fComp2 );
-            // create the signature
-            pCut->uSign = pTemp1->uSign | pTemp2->uSign;
-            // add it to the corresponding list
-            pCut->pNext = pLists[pCut->nLeaves];
-            pLists[pCut->nLeaves] = pCut;
-            // count this cut and quit if limit is reached
-            Counter++;
-            if ( Counter == FPGA_CUTS_MAX_COMPUTE )
-                goto QUITS;
-        }
-QUITS :
-    // combine all the lists into one
-    pListNew  = NULL;
-    ppListNew = &pListNew;
-    for ( i = 1; i <= p->nVarsMax; i++ )
-    {
-        if ( pLists[i] == NULL )
-            continue;
-        // find the last entry
-        for ( pPrev = pLists[i], pCut = pPrev->pNext; pCut; 
-            pPrev = pCut, pCut = pCut->pNext );
-        // connect these lists
-        *ppListNew = pLists[i];
-        ppListNew  = &pPrev->pNext;
-    }
-    *ppListNew = NULL;
-    // sort the cuts by arrival times and use only the first FPGA_CUTS_MAX_USE
-    pListNew = Fpga_CutSortCuts( p, pTable, pListNew );
-    return pListNew;
-}
-
-
-/**Function*************************************************************
-
-  Synopsis    [Merges two lists of cuts.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-Fpga_Cut_t * Fpga_CutMergeLists2( Fpga_Man_t * p, Fpga_CutTable_t * pTable, 
-    Fpga_Cut_t * pList1, Fpga_Cut_t * pList2, int fComp1, int fComp2, int fPivot1, int fPivot2 )
-{
-    Fpga_Node_t * ppNodes[FPGA_MAX_LEAVES];
-    Fpga_Cut_t * pListNew, ** ppListNew, * pLists[FPGA_MAX_LEAVES+1] = { NULL };
-    Fpga_Cut_t * pCut, * pPrev, * pTemp1, * pTemp2;
-    int nNodes, Counter, i;
-
-    // prepare the manager for the cut computation
-    Fpga_CutTableRestart( pTable );
-    // go through the cut pairs
-    Counter = 0;
-    for ( pTemp1 = pList1; pTemp1; pTemp1 = fPivot1? NULL: pTemp1->pNext )
-        for ( pTemp2 = pList2; pTemp2; pTemp2 = fPivot2? NULL: pTemp2->pNext )
-        {
-            // check if k-feasible cut exists
-            nNodes = Fpga_CutMergeTwo( pTemp1, pTemp2, ppNodes, p->nVarsMax );
-            if ( nNodes == 0 )
-                continue;
-            // consider the cut for possible addition to the set of new cuts
-            pCut = Fpga_CutTableConsider( p, pTable, ppNodes, nNodes );
-            if ( pCut == NULL )
-                continue;
-            // add data to the cut
-            pCut->pOne = Fpga_CutNotCond( pTemp1, fComp1 );
-            pCut->pTwo = Fpga_CutNotCond( pTemp2, fComp2 );
-            // add it to the corresponding list
-            pCut->pNext = pLists[pCut->nLeaves];
-            pLists[pCut->nLeaves] = pCut;
-            // count this cut and quit if limit is reached
-            Counter++;
-            if ( Counter == FPGA_CUTS_MAX_COMPUTE )
-                goto QUITS;
-        }
-QUITS :
-    // combine all the lists into one
-    pListNew  = NULL;
-    ppListNew = &pListNew;
-    for ( i = 1; i <= p->nVarsMax; i++ )
-    {
-        if ( pLists[i] == NULL )
-            continue;
-        // find the last entry
-        for ( pPrev = pLists[i], pCut = pPrev->pNext; pCut; 
-            pPrev = pCut, pCut = pCut->pNext );
-        // connect these lists
-        *ppListNew = pLists[i];
-        ppListNew  = &pPrev->pNext;
-    }
-    *ppListNew = NULL;
-    // sort the cuts by arrival times and use only the first FPGA_CUTS_MAX_USE
-    pListNew = Fpga_CutSortCuts( p, pTable, pListNew );
-    return pListNew;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Merges two cuts.]
-
-  Description [Returns the number of nodes in the resulting cut, or 0 if the
-  cut is infeasible. Returns the resulting nodes in the array ppNodes[].]
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Fpga_CutMergeTwo( Fpga_Cut_t * pCut1, Fpga_Cut_t * pCut2, Fpga_Node_t * ppNodes[], int nNodesMax )
-{
-    Fpga_Node_t * pNodeTemp;
-    int nTotal, i, k, min, Counter;
-    unsigned uSign;
-
-    // use quick prefiltering
-    uSign = pCut1->uSign | pCut2->uSign;
-    Counter = FPGA_COUNT_ONES(uSign);
-    if ( Counter > nNodesMax )
-        return 0;
-/*
-    // check the special case when at least of the cuts is the largest
-    if ( pCut1->nLeaves == nNodesMax )
-    {
-        if ( pCut2->nLeaves == nNodesMax )
-        {
-            // return 0 if the cuts are different
-            for ( i = 0; i < nNodesMax; i++ )
-                if ( pCut1->ppLeaves[i] != pCut2->ppLeaves[i] )
-                    return 0;
-            // return nNodesMax if they are the same
-            for ( i = 0; i < nNodesMax; i++ )
-                ppNodes[i] = pCut1->ppLeaves[i];
-            return nNodesMax;
-        }
-        else if ( pCut2->nLeaves == nNodesMax - 1 ) 
-        {
-            // return 0 if the cuts are different
-            fMismatch = 0;
-            for ( i = 0; i < nNodesMax; i++ )
-                if ( pCut1->ppLeaves[i] != pCut2->ppLeaves[i - fMismatch] )
-                {
-                    if ( fMismatch == 1 )
-                        return 0;
-                    fMismatch = 1;
-                }
-            // return nNodesMax if they are the same
-            for ( i = 0; i < nNodesMax; i++ )
-                ppNodes[i] = pCut1->ppLeaves[i];
-            return nNodesMax;
-        }
-    }
-    else if ( pCut1->nLeaves == nNodesMax - 1 && pCut2->nLeaves == nNodesMax )
-    {
-        // return 0 if the cuts are different
-        fMismatch = 0;
-        for ( i = 0; i < nNodesMax; i++ )
-            if ( pCut1->ppLeaves[i - fMismatch] != pCut2->ppLeaves[i] )
-            {
-                if ( fMismatch == 1 )
-                    return 0;
-                fMismatch = 1;
-            }
-        // return nNodesMax if they are the same
-        for ( i = 0; i < nNodesMax; i++ )
-            ppNodes[i] = pCut2->ppLeaves[i];
-        return nNodesMax;
-    }
-*/
-    // count the number of unique entries in pCut2
-    nTotal = pCut1->nLeaves;
-    for ( i = 0; i < pCut2->nLeaves; i++ )
-    {
-        // try to find this entry among the leaves of pCut1
-        for ( k = 0; k < pCut1->nLeaves; k++ )
-            if ( pCut2->ppLeaves[i] == pCut1->ppLeaves[k] )
-                break;
-        if ( k < pCut1->nLeaves ) // found
-            continue;
-        // we found a new entry to add
-        if ( nTotal == nNodesMax )
-            return 0;
-        ppNodes[nTotal++] = pCut2->ppLeaves[i];
-    }
-    // we know that the feasible cut exists
-
-    // add the starting entries
-    for ( k = 0; k < pCut1->nLeaves; k++ )
-        ppNodes[k] = pCut1->ppLeaves[k];
-
-    // selection-sort the entries
-    for ( i = 0; i < nTotal - 1; i++ )
-    {
-        min = i;
-        for ( k = i+1; k < nTotal; k++ )
-//            if ( ppNodes[k] < ppNodes[min] ) // reported bug fix (non-determinism!)
-            if ( ppNodes[k]->Num < ppNodes[min]->Num )
-                min = k;
-        pNodeTemp    = ppNodes[i];
-        ppNodes[i]   = ppNodes[min];
-        ppNodes[min] = pNodeTemp;
-    }
-
-    return nTotal;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Computes the union of the two lists of cuts.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-Fpga_Cut_t * Fpga_CutUnionLists( Fpga_Cut_t * pList1, Fpga_Cut_t * pList2 )
-{
-    Fpga_Cut_t * pTemp, * pRoot;
-    // find the last cut in the first list
-    pRoot = pList1;
-    Fpga_ListForEachCut( pList1, pTemp )
-        pRoot = pTemp;
-    // attach the non-trival part of the second cut to the end of the first
-    assert( pRoot->pNext == NULL );
-    pRoot->pNext = pList2->pNext;   
-    pList2->pNext = NULL;
-    return pList1;
-}
-
-
-/**Function*************************************************************
-
-  Synopsis    [Checks whether the given cut belongs to the list.]
-
-  Description [This procedure takes most of the runtime in the cut 
-  computation.]
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Fpga_CutBelongsToList( Fpga_Cut_t * pList, Fpga_Node_t * ppNodes[], int nNodes )
-{
-    Fpga_Cut_t * pTemp;
-    int i;
-    for ( pTemp = pList; pTemp; pTemp = pTemp->pNext )
-    {
-        for ( i = 0; i < nNodes; i++ )
-            if ( pTemp->ppLeaves[i] != ppNodes[i] )
-                break;
-        if ( i == nNodes )
-            return 1;
-    }
-    return 0;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Counts all the cuts.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Fpga_CutCountAll( Fpga_Man_t * pMan )
-{
-    Fpga_Node_t * pNode;
-    Fpga_Cut_t * pCut;
-    int i, nCuts;
-    // go through all the nodes in the unique table of the manager
-    nCuts = 0;
-    for ( i = 0; i < pMan->nBins; i++ )
-        for ( pNode = pMan->pBins[i]; pNode; pNode = pNode->pNext )
-            for ( pCut = pNode->pCuts; pCut; pCut = pCut->pNext )
-                if ( pCut->nLeaves > 1 ) // skip the elementary cuts
-                {
-//                    Fpga_CutVolume( pCut );
-                    nCuts++;
-                }
-    return nCuts;
-}
-
-
-/**Function*************************************************************
-
-  Synopsis    [Clean the signatures.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Fpga_CutsCleanSign( Fpga_Man_t * pMan )
-{
-    Fpga_Node_t * pNode;
-    Fpga_Cut_t * pCut;
-    int i;
-    for ( i = 0; i < pMan->nBins; i++ )
-        for ( pNode = pMan->pBins[i]; pNode; pNode = pNode->pNext )
-            for ( pCut = pNode->pCuts; pCut; pCut = pCut->pNext )
-                pCut->uSign = 0;
-}
-
-
-
-/**Function*************************************************************
-
-  Synopsis    [Prints the cuts in the list.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Fpga_CutListPrint( Fpga_Man_t * pMan, Fpga_Node_t * pRoot )
-{
-    Fpga_Cut_t * pTemp;
-    int Counter;
-    for ( Counter = 0, pTemp = pRoot->pCuts; pTemp; pTemp = pTemp->pNext, Counter++ )
-    {
-        printf( "%2d : ", Counter + 1 );
-        Fpga_CutPrint_( pMan, pTemp, pRoot );
-    }
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Prints the cuts in the list.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Fpga_CutListPrint2( Fpga_Man_t * pMan, Fpga_Node_t * pRoot )
-{
-    Fpga_Cut_t * pTemp;
-    int Counter;
-    for ( Counter = 0, pTemp = pRoot->pCuts; pTemp; pTemp = pTemp->pNext, Counter++ )
-    {
-        printf( "%2d : ", Counter + 1 );
-        Fpga_CutPrint_( pMan, pTemp, pRoot );
-    }
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Prints the cut.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Fpga_CutPrint_( Fpga_Man_t * pMan, Fpga_Cut_t * pCut, Fpga_Node_t * pRoot )
-{
-    int i;
-    printf( "(%3d)  {", pRoot->Num );
-    for ( i = 0; i < pMan->nVarsMax; i++ )
-        if ( pCut->ppLeaves[i] )
-            printf( " %3d", pCut->ppLeaves[i]->Num );
-    printf( " }\n" );
-}
-
-
-
-
-
-
-
-
-/**Function*************************************************************
-
-  Synopsis    [Starts the hash table to canonicize cuts.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-Fpga_CutTable_t * Fpga_CutTableStart( Fpga_Man_t * pMan )
-{
-    Fpga_CutTable_t * p;
-    // allocate the table
-    p = ALLOC( Fpga_CutTable_t, 1 );
-    memset( p, 0, sizeof(Fpga_CutTable_t) );
-    p->nBins = Cudd_Prime( 10 * FPGA_CUTS_MAX_COMPUTE );
-    p->pBins = ALLOC( Fpga_Cut_t *, p->nBins );
-    memset( p->pBins, 0, sizeof(Fpga_Cut_t *) * p->nBins );
-    p->pCuts = ALLOC( int, 2 * FPGA_CUTS_MAX_COMPUTE );
-    p->pArray = ALLOC( Fpga_Cut_t *, 2 * FPGA_CUTS_MAX_COMPUTE );
-    p->pCuts1 = ALLOC( Fpga_Cut_t *, 2 * FPGA_CUTS_MAX_COMPUTE );
-    p->pCuts2 = ALLOC( Fpga_Cut_t *, 2 * FPGA_CUTS_MAX_COMPUTE );
-    return p;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Stops the hash table.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Fpga_CutTableStop( Fpga_CutTable_t * p )
-{
-    free( p->pCuts1 );
-    free( p->pCuts2 );
-    free( p->pArray );
-    free( p->pBins );
-    free( p->pCuts );
-    free( p );
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Computes the hash value of the cut.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-unsigned Fpga_CutTableHash( Fpga_Node_t * ppNodes[], int nNodes )
-{
-    unsigned uRes;
-    int i;
-    uRes = 0;
-    for ( i = 0; i < nNodes; i++ )
-        uRes += s_HashPrimes[i] * ppNodes[i]->Num;
-    return uRes;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Looks up the table for the available cut.]
-
-  Description [Returns -1 if the same cut is found. Returns the index
-  of the cell where the cut should be added, if it does not exist.]
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Fpga_CutTableLookup( Fpga_CutTable_t * p, Fpga_Node_t * ppNodes[], int nNodes )
-{
-    Fpga_Cut_t * pCut;
-    unsigned Key;
-    int b, i;
-
-    Key = Fpga_CutTableHash(ppNodes, nNodes) % p->nBins; 
-    for ( b = Key; p->pBins[b]; b = (b+1) % p->nBins )
-    {
-        pCut = p->pBins[b];
-        if ( pCut->nLeaves != nNodes )
-            continue;
-        for ( i = 0; i < nNodes; i++ )
-            if ( pCut->ppLeaves[i] != ppNodes[i] )
-                break;
-        if ( i == nNodes )
-            return -1;
-    }
-    return b;
-}
-
-
-/**Function*************************************************************
-
-  Synopsis    [Starts the hash table to canonicize cuts.]
-
-  Description [Considers addition of the cut to the hash table.]
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-Fpga_Cut_t * Fpga_CutTableConsider( Fpga_Man_t * pMan, Fpga_CutTable_t * p, Fpga_Node_t * ppNodes[], int nNodes )
-{
-    Fpga_Cut_t * pCut;
-    int Place, i;
-    // check the cut
-    Place = Fpga_CutTableLookup( p, ppNodes, nNodes );
-    if ( Place == -1 )
-        return NULL;
-    assert( nNodes > 0 );
-    // create the new cut
-    pCut = Fpga_CutAlloc( pMan );
-    pCut->nLeaves = nNodes;
-    pCut->fLevel = 0.0;
-    for ( i = 0; i < nNodes; i++ )
-    {
-        pCut->ppLeaves[i] = ppNodes[i];
-        pCut->fLevel += ppNodes[i]->Level;
-    }
-    pCut->fLevel /= nNodes;
-    // add the cut to the table
-    assert( p->pBins[Place] == NULL );
-    p->pBins[Place] = pCut;
-    // add the cut to the new list
-    p->pCuts[ p->nCuts++ ] = Place;
-    return pCut;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Prepares the table to be used with other cuts.]
-
-  Description [Restarts the table by cleaning the info about cuts stored
-  when the previous node was considered.]
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Fpga_CutTableRestart( Fpga_CutTable_t * p )
-{
-    int i;
-    for ( i = 0; i < p->nCuts; i++ )
-    {
-        assert( p->pBins[ p->pCuts[i] ] );
-        p->pBins[ p->pCuts[i] ] = NULL;
-    }
-    p->nCuts = 0;
-}
-
-
-
-/**Function*************************************************************
-
-  Synopsis    [Compares the cuts by the number of leaves and then by delay.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Fpga_CutSortCutsCompare( Fpga_Cut_t ** pC1, Fpga_Cut_t ** pC2 )
-{
-    if ( (*pC1)->nLeaves < (*pC2)->nLeaves )
-        return -1;
-    if ( (*pC1)->nLeaves > (*pC2)->nLeaves )
-        return 1;
-/*
-    if ( (*pC1)->fLevel > (*pC2)->fLevel )
-        return -1;
-    if ( (*pC1)->fLevel < (*pC2)->fLevel )
-        return 1;
-*/
-    return 0;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Sorts the cuts by average arrival time.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-Fpga_Cut_t * Fpga_CutSortCuts( Fpga_Man_t * pMan, Fpga_CutTable_t * p, Fpga_Cut_t * pList )
-{
-    Fpga_Cut_t * pListNew;
-    int nCuts, i;
-    // move the cuts from the list into the array
-    nCuts = Fpga_CutList2Array( p->pCuts1, pList );
-    assert( nCuts <= FPGA_CUTS_MAX_COMPUTE );
-    // sort the cuts
-    qsort( (void *)p->pCuts1, nCuts, sizeof(void *), 
-            (int (*)(const void *, const void *)) Fpga_CutSortCutsCompare );
-    // move them back into the list
-    if ( nCuts > FPGA_CUTS_MAX_USE - 1 )
-    {
-//        printf( "*" );
-        // free the remaining cuts
-        for ( i = FPGA_CUTS_MAX_USE - 1; i < nCuts; i++ )
-            Extra_MmFixedEntryRecycle( pMan->mmCuts, (char *)p->pCuts1[i] );
-        // update the number of cuts
-        nCuts = FPGA_CUTS_MAX_USE - 1;
-    }
-    pListNew = Fpga_CutArray2List( p->pCuts1, nCuts );
-    return pListNew;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Moves the nodes from the list into the array.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Fpga_CutList2Array( Fpga_Cut_t ** pArray, Fpga_Cut_t * pList )
-{
-    int i;
-    for ( i = 0; pList; pList = pList->pNext, i++ )
-        pArray[i] = pList;
-    return i;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Moves the nodes from the array into the list.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-Fpga_Cut_t * Fpga_CutArray2List( Fpga_Cut_t ** pArray, int nCuts )
-{
-    Fpga_Cut_t * pListNew, ** ppListNew;
-    int i;
-    pListNew  = NULL;
-    ppListNew = &pListNew;
-    for ( i = 0; i < nCuts; i++ )
-    {
-        // connect these lists
-        *ppListNew = pArray[i];
-        ppListNew  = &pArray[i]->pNext;
-//printf( " %d(%.2f)", pArray[i]->nLeaves, pArray[i]->fLevel );
-    }
-//printf( "\n" );
-
-    *ppListNew = NULL;
-    return pListNew;
-}
-
-
-////////////////////////////////////////////////////////////////////////
-///                       END OF FILE                                ///
-////////////////////////////////////////////////////////////////////////
-
diff --git a/abc70930/src/map/fpga/fpgaCutUtils.c b/abc70930/src/map/fpga/fpgaCutUtils.c
deleted file mode 100644
index e60a1dee..00000000
--- a/abc70930/src/map/fpga/fpgaCutUtils.c
+++ /dev/null
@@ -1,470 +0,0 @@
-/**CFile****************************************************************
-
-  FileName    [fpgaCutUtils.c]
-
-  PackageName [MVSIS 1.3: Multi-valued logic synthesis system.]
-
-  Synopsis    [Generic technology mapping engine.]
-
-  Author      [MVSIS Group]
-  
-  Affiliation [UC Berkeley]
-
-  Date        [Ver. 2.0. Started - August 18, 2004.]
-
-  Revision    [$Id: fpgaCutUtils.h,v 1.0 2003/09/08 00:00:00 alanmi Exp $]
-
-***********************************************************************/
-
-#include "fpgaInt.h"
-
-////////////////////////////////////////////////////////////////////////
-///                        DECLARATIONS                              ///
-////////////////////////////////////////////////////////////////////////
-
-////////////////////////////////////////////////////////////////////////
-///                     FUNCTION DEFINITIONS                         ///
-////////////////////////////////////////////////////////////////////////
-
-/**Function*************************************************************
-
-  Synopsis    [Allocates the cut.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-Fpga_Cut_t * Fpga_CutAlloc( Fpga_Man_t * p )
-{
-    Fpga_Cut_t * pCut;
-    pCut = (Fpga_Cut_t *)Extra_MmFixedEntryFetch( p->mmCuts );
-    memset( pCut, 0, sizeof(Fpga_Cut_t) );
-    return pCut;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Duplicates the cut.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-Fpga_Cut_t * Fpga_CutDup( Fpga_Man_t * p, Fpga_Cut_t * pCutOld )
-{
-    Fpga_Cut_t * pCutNew;
-    int i;
-    pCutNew = Fpga_CutAlloc( p );
-    pCutNew->pRoot   = pCutOld->pRoot;
-    pCutNew->nLeaves = pCutOld->nLeaves;
-    for ( i = 0; i < pCutOld->nLeaves; i++ )
-        pCutNew->ppLeaves[i] = pCutOld->ppLeaves[i];
-    return pCutNew;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Deallocates the cut.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Fpga_CutFree( Fpga_Man_t * p, Fpga_Cut_t * pCut )
-{
-    if ( pCut )
-    Extra_MmFixedEntryRecycle( p->mmCuts, (char *)pCut );
-}
-
-/**Function*************************************************************
-
-  Synopsis    []
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Fpga_CutPrint( Fpga_Man_t * p, Fpga_Node_t * pRoot, Fpga_Cut_t * pCut )
-{
-    int i;
-    printf( "CUT:  Delay = %4.2f. Area = %4.2f. Nodes = %d -> {", 
-        pCut->tArrival, pCut->aFlow, pRoot->Num );
-    for ( i = 0; i < pCut->nLeaves; i++ )
-        printf( " %d", pCut->ppLeaves[i]->Num );
-    printf( " } \n" );
-}
-
-/**Function*************************************************************
-
-  Synopsis    []
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-Fpga_Cut_t * Fpga_CutCreateSimple( Fpga_Man_t * p, Fpga_Node_t * pNode )
-{
-    Fpga_Cut_t * pCut;
-    pCut = Fpga_CutAlloc( p );
-    pCut->pRoot       = pNode;
-    pCut->nLeaves     = 1;
-    pCut->ppLeaves[0] = pNode;
-    pCut->uSign = FPGA_SEQ_SIGN(pCut->ppLeaves[0]);
-    return pCut;
-}
-
-
-/**function*************************************************************
-
-  synopsis    [Computes the exact area associated with the cut.]
-
-  description []
-               
-  sideeffects []
-
-  seealso     []
-
-***********************************************************************/
-float Fpga_CutGetRootArea( Fpga_Man_t * p, Fpga_Cut_t * pCut )
-{
-    return p->pLutLib->pLutAreas[pCut->nLeaves];
-}
-
-/**Function*************************************************************
-
-  Synopsis    []
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-Fpga_Cut_t * Fpga_CutListAppend( Fpga_Cut_t * pSetAll, Fpga_Cut_t * pSets )
-{
-    Fpga_Cut_t * pPrev, * pTemp;
-    if ( pSetAll == NULL )
-        return pSets;
-    if ( pSets == NULL )
-        return pSetAll;
-    // find the last one
-    for ( pTemp = pSets; pTemp; pTemp = pTemp->pNext )
-        pPrev = pTemp;
-    // append all the end of the current set
-    assert( pPrev->pNext == NULL );
-    pPrev->pNext = pSetAll;
-    return pSets;
-}
-
-/**Function*************************************************************
-
-  Synopsis    []
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Fpga_CutListRecycle( Fpga_Man_t * p, Fpga_Cut_t * pSetList, Fpga_Cut_t * pSave )
-{
-    Fpga_Cut_t * pNext, * pTemp;
-    for ( pTemp = pSetList, pNext = pTemp? pTemp->pNext : NULL; 
-          pTemp; 
-          pTemp = pNext, pNext = pNext? pNext->pNext : NULL )
-        if ( pTemp != pSave )
-            Extra_MmFixedEntryRecycle( p->mmCuts, (char *)pTemp );
-}
-
-/**Function*************************************************************
-
-  Synopsis    []
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Fpga_CutListCount( Fpga_Cut_t * pSets )
-{
-    Fpga_Cut_t * pTemp;
-    int i;
-    for ( i = 0, pTemp = pSets; pTemp; pTemp = pTemp->pNext, i++ );
-    return i;
-}
-
-#if 0
-
-/**function*************************************************************
-
-  synopsis    [Removes the fanouts of the cut.]
-
-  description []
-               
-  sideeffects []
-
-  seealso     []
-
-***********************************************************************/
-void Fpga_CutRemoveFanouts( Fpga_Man_t * p, Fpga_Node_t * pNode, Fpga_Cut_t * pCut )
-{
-    Fpga_NodeVec_t * vFanouts;
-    int i, k;
-    for ( i = 0; i < pCut->nLeaves; i++ )
-    {
-        vFanouts = pCut->ppLeaves[i]->vFanouts;
-        for ( k = 0; k < vFanouts->nSize; k++ )
-            if ( vFanouts->pArray[k] == pNode )
-                break;
-        assert( k != vFanouts->nSize );
-        for ( k++; k < vFanouts->nSize; k++ )
-            vFanouts->pArray[k-1] = vFanouts->pArray[k];
-        vFanouts->nSize--;
-    }
-}
-
-/**function*************************************************************
-
-  synopsis    [Removes the fanouts of the cut.]
-
-  description []
-               
-  sideeffects []
-
-  seealso     []
-
-***********************************************************************/
-void Fpga_CutInsertFanouts( Fpga_Man_t * p, Fpga_Node_t * pNode, Fpga_Cut_t * pCut )
-{
-    int i;
-    for ( i = 0; i < pCut->nLeaves; i++ )
-        Fpga_NodeVecPush( pCut->ppLeaves[i]->vFanouts, pNode );
-}
-#endif
-
-/**Function*************************************************************
-
-  Synopsis    [Computes the arrival time and the area flow of the cut.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Fpga_CutGetParameters( Fpga_Man_t * pMan, Fpga_Cut_t * pCut )
-{
-    Fpga_Cut_t * pFaninCut;
-    int i;
-    pCut->tArrival = -FPGA_FLOAT_LARGE;
-    pCut->aFlow    = pMan->pLutLib->pLutAreas[pCut->nLeaves];
-    for ( i = 0; i < pCut->nLeaves; i++ )
-    {
-        pFaninCut = pCut->ppLeaves[i]->pCutBest;
-        if ( pCut->tArrival < pFaninCut->tArrival )
-             pCut->tArrival = pFaninCut->tArrival;
-        // if the fanout count is not set, assume it to be 1
-        if ( pCut->ppLeaves[i]->nRefs == 0 )
-            pCut->aFlow += pFaninCut->aFlow;
-        else
-//            pCut->aFlow += pFaninCut->aFlow / pCut->ppLeaves[i]->nRefs;
-            pCut->aFlow += pFaninCut->aFlow / pCut->ppLeaves[i]->aEstFanouts;
-    }
-    // use the first pin to compute the delay of the LUT 
-    // (this mapper does not support the variable pin delay model)
-    pCut->tArrival += pMan->pLutLib->pLutDelays[pCut->nLeaves][0];
-}
-
-
-/**function*************************************************************
-
-  synopsis    [Computes the area flow of the cut.]
-
-  description []
-               
-  sideeffects []
-
-  seealso     []
-
-***********************************************************************/
-float Fpga_CutGetAreaFlow( Fpga_Man_t * pMan, Fpga_Cut_t * pCut )
-{
-    Fpga_Cut_t * pCutFanin;
-    int i;
-    pCut->aFlow = pMan->pLutLib->pLutAreas[pCut->nLeaves];
-    for ( i = 0; i < pCut->nLeaves; i++ )
-    {
-        // get the cut implementing this phase of the fanin
-        pCutFanin  = pCut->ppLeaves[i]->pCutBest;   
-        assert( pCutFanin );
-        pCut->aFlow  += pCutFanin->aFlow / pCut->ppLeaves[i]->nRefs;
-    }
-    return pCut->aFlow;
-}
-
-/**function*************************************************************
-
-  synopsis    [Computes the exact area associated with the cut.]
-
-  description []
-               
-  sideeffects []
-
-  seealso     []
-
-***********************************************************************/
-float Fpga_CutGetAreaRefed( Fpga_Man_t * pMan, Fpga_Cut_t * pCut )
-{
-    float aResult, aResult2;
-    if ( pCut->nLeaves == 1 )
-        return 0;
-    aResult  = Fpga_CutDeref( pMan, NULL, pCut, 0 );
-    aResult2 = Fpga_CutRef( pMan, NULL, pCut, 0 );
-    assert( Fpga_FloatEqual( pMan, aResult, aResult2 ) );
-    return aResult;
-}
-
-/**function*************************************************************
-
-  synopsis    [Computes the exact area associated with the cut.]
-
-  description []
-               
-  sideeffects []
-
-  seealso     []
-
-***********************************************************************/
-float Fpga_CutGetAreaDerefed( Fpga_Man_t * pMan, Fpga_Cut_t * pCut )
-{
-    float aResult, aResult2;
-    if ( pCut->nLeaves == 1 )
-        return 0;
-    aResult2 = Fpga_CutRef( pMan, NULL, pCut, 0 );
-    aResult  = Fpga_CutDeref( pMan, NULL, pCut, 0 );
-    assert( Fpga_FloatEqual( pMan, aResult, aResult2 ) );
-    return aResult;
-}
-
-/**function*************************************************************
-
-  synopsis    [References the cut.]
-
-  description [This procedure is similar to the procedure NodeReclaim.]
-               
-  sideeffects []
-
-  seealso     []
-
-***********************************************************************/
-float Fpga_CutRef( Fpga_Man_t * pMan, Fpga_Node_t * pNode, Fpga_Cut_t * pCut, int fFanouts )
-{
-    Fpga_Node_t * pNodeChild;
-    float aArea;
-    int i;
-
-    // deref the fanouts
-//    if ( fFanouts ) 
-//        Fpga_CutInsertFanouts( pMan, pNode, pCut );
-
-    // start the area of this cut
-    aArea = pMan->pLutLib->pLutAreas[pCut->nLeaves];
-    // go through the children
-    for ( i = 0; i < pCut->nLeaves; i++ )
-    {
-        pNodeChild = pCut->ppLeaves[i];
-        assert( pNodeChild->nRefs >= 0 );
-        if ( pNodeChild->nRefs++ > 0 )  
-            continue;
-        if ( !Fpga_NodeIsAnd(pNodeChild) ) 
-            continue;
-        aArea += Fpga_CutRef( pMan, pNodeChild, pNodeChild->pCutBest, fFanouts );
-    }
-    return aArea;
-}
-
-/**function*************************************************************
-
-  synopsis    [Dereferences the cut.]
-
-  description [This procedure is similar to the procedure NodeRecusiveDeref.]
-               
-  sideeffects []
-
-  seealso     []
-
-***********************************************************************/
-float Fpga_CutDeref( Fpga_Man_t * pMan, Fpga_Node_t * pNode, Fpga_Cut_t * pCut, int fFanouts )
-{
-    Fpga_Node_t * pNodeChild;
-    float aArea;
-    int i;
-
-    // deref the fanouts
-//    if ( fFanouts ) 
-//        Fpga_CutRemoveFanouts( pMan, pNode, pCut );
-
-    // start the area of this cut
-    aArea = pMan->pLutLib->pLutAreas[pCut->nLeaves];
-    // go through the children
-    for ( i = 0; i < pCut->nLeaves; i++ )
-    {
-        pNodeChild = pCut->ppLeaves[i];
-        assert( pNodeChild->nRefs > 0 );
-        if ( --pNodeChild->nRefs > 0 )  
-            continue;
-        if ( !Fpga_NodeIsAnd(pNodeChild) ) 
-            continue;
-        aArea += Fpga_CutDeref( pMan, pNodeChild, pNodeChild->pCutBest, fFanouts );
-    }
-    return aArea;
-}
-
-
-/**Function*************************************************************
-
-  Synopsis    [Sets the used cuts to be the currently selected ones.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Fpga_MappingSetUsedCuts( Fpga_Man_t * pMan )
-{
-    int i;
-    for ( i = 0; i < pMan->vNodesAll->nSize; i++ )
-        if ( pMan->vNodesAll->pArray[i]->pCutOld )
-        {
-            pMan->vNodesAll->pArray[i]->pCutBest = pMan->vNodesAll->pArray[i]->pCutOld;
-            pMan->vNodesAll->pArray[i]->pCutOld  = NULL;
-        }
-}
-
-////////////////////////////////////////////////////////////////////////
-///                       END OF FILE                                ///
-////////////////////////////////////////////////////////////////////////
-
-
diff --git a/abc70930/src/map/fpga/fpgaFanout.c b/abc70930/src/map/fpga/fpgaFanout.c
deleted file mode 100644
index c28a8799..00000000
--- a/abc70930/src/map/fpga/fpgaFanout.c
+++ /dev/null
@@ -1,141 +0,0 @@
-/**CFile****************************************************************
-
-  FileName    [fpgaFanout.c]
-
-  PackageName [FRAIG: Functionally reduced AND-INV graphs.]
-
-  Synopsis    [Procedures to manipulate fanouts of the FRAIG nodes.]
-
-  Author      [Alan Mishchenko <alanmi@eecs.berkeley.edu>]
-  
-  Affiliation [UC Berkeley]
-
-  Date        [Ver. 2.0. Started - August 18, 2004.]
-
-  Revision    [$Id: fpgaFanout.c,v 1.1 2005/01/23 06:59:41 alanmi Exp $]
-
-***********************************************************************/
-
-#include "fpgaInt.h"
-
-#ifdef MAP_ALLOCATE_FANOUT
-
-////////////////////////////////////////////////////////////////////////
-///                        DECLARATIONS                              ///
-////////////////////////////////////////////////////////////////////////
-
-////////////////////////////////////////////////////////////////////////
-///                     FUNCTION DEFINITIONS                         ///
-////////////////////////////////////////////////////////////////////////
-
-/**Function*************************************************************
-
-  Synopsis    [Add the fanout to the node.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Fpga_NodeAddFaninFanout( Fpga_Node_t * pFanin, Fpga_Node_t * pFanout )
-{
-    Fpga_Node_t * pPivot;
-
-    // pFanins is a fanin of pFanout
-    assert( !Fpga_IsComplement(pFanin) );
-    assert( !Fpga_IsComplement(pFanout) );
-    assert( Fpga_Regular(pFanout->p1) == pFanin || Fpga_Regular(pFanout->p2) == pFanin );
-
-    pPivot = pFanin->pFanPivot;
-    if ( pPivot == NULL )
-    {
-        pFanin->pFanPivot = pFanout;
-        return;
-    }
-
-    if ( Fpga_Regular(pPivot->p1) == pFanin )
-    {
-        if ( Fpga_Regular(pFanout->p1) == pFanin )
-        {
-            pFanout->pFanFanin1 = pPivot->pFanFanin1;
-            pPivot->pFanFanin1  = pFanout;
-        }
-        else // if ( Fpga_Regular(pFanout->p2) == pFanin )
-        {
-            pFanout->pFanFanin2 = pPivot->pFanFanin1;
-            pPivot->pFanFanin1  = pFanout;
-        }
-    }
-    else // if ( Fpga_Regular(pPivot->p2) == pFanin )
-    {
-        assert( Fpga_Regular(pPivot->p2) == pFanin );
-        if ( Fpga_Regular(pFanout->p1) == pFanin )
-        {
-            pFanout->pFanFanin1 = pPivot->pFanFanin2;
-            pPivot->pFanFanin2  = pFanout;
-        }
-        else // if ( Fpga_Regular(pFanout->p2) == pFanin )
-        {
-            pFanout->pFanFanin2 = pPivot->pFanFanin2;
-            pPivot->pFanFanin2  = pFanout;
-        }
-    }
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Add the fanout to the node.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Fpga_NodeRemoveFaninFanout( Fpga_Node_t * pFanin, Fpga_Node_t * pFanoutToRemove )
-{
-    Fpga_Node_t * pFanout, * pFanout2, ** ppFanList;
-    // start the linked list of fanouts
-    ppFanList = &pFanin->pFanPivot; 
-    // go through the fanouts
-    Fpga_NodeForEachFanoutSafe( pFanin, pFanout, pFanout2 )
-    {
-        // skip the fanout-to-remove
-        if ( pFanout == pFanoutToRemove )
-            continue;
-        // add useful fanouts to the list
-        *ppFanList = pFanout;
-        ppFanList = Fpga_NodeReadNextFanoutPlace( pFanin, pFanout );
-    }
-    *ppFanList = NULL;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Returns the number of fanouts of a node.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Fpga_NodeGetFanoutNum( Fpga_Node_t * pNode )
-{
-    Fpga_Node_t * pFanout;
-    int Counter = 0;
-    Fpga_NodeForEachFanout( pNode, pFanout )
-        Counter++;
-    return Counter;
-}
-
-////////////////////////////////////////////////////////////////////////
-///                       END OF FILE                                ///
-////////////////////////////////////////////////////////////////////////
-
-#endif
-
diff --git a/abc70930/src/map/fpga/fpgaGENERIC.c b/abc70930/src/map/fpga/fpgaGENERIC.c
deleted file mode 100644
index 4483c215..00000000
--- a/abc70930/src/map/fpga/fpgaGENERIC.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/**CFile****************************************************************
-
-  FileName    [fpga__.c]
-
-  PackageName [MVSIS 1.3: Multi-valued logic synthesis system.]
-
-  Synopsis    [Generic technology mapping engine.]
-
-  Author      [MVSIS Group]
-  
-  Affiliation [UC Berkeley]
-
-  Date        [Ver. 1.0. Started - September 8, 2003.]
-
-  Revision    [$Id: fpga__.h,v 1.0 2003/09/08 00:00:00 alanmi Exp $]
-
-***********************************************************************/
-
-#include "fpgaInt.h"
-
-////////////////////////////////////////////////////////////////////////
-///                        DECLARATIONS                              ///
-////////////////////////////////////////////////////////////////////////
-
-////////////////////////////////////////////////////////////////////////
-///                     FUNCTION DEFINITIONS                         ///
-////////////////////////////////////////////////////////////////////////
-
-/**Function*************************************************************
-
-  Synopsis    []
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-
-
-////////////////////////////////////////////////////////////////////////
-///                       END OF FILE                                ///
-////////////////////////////////////////////////////////////////////////
-
-
diff --git a/abc70930/src/map/fpga/fpgaInt.h b/abc70930/src/map/fpga/fpgaInt.h
deleted file mode 100644
index b93eacab..00000000
--- a/abc70930/src/map/fpga/fpgaInt.h
+++ /dev/null
@@ -1,388 +0,0 @@
-/**CFile****************************************************************
-
-  FileName    [fpgaInt.h]
-
-  PackageName [MVSIS 2.0: Multi-valued logic synthesis system.]
-
-  Synopsis    [Technology mapping for variable-size-LUT FPGAs.]
-
-  Author      [MVSIS Group]
-  
-  Affiliation [UC Berkeley]
-
-  Date        [Ver. 2.0. Started - August 18, 2004.]
-
-  Revision    [$Id: fpgaInt.h,v 1.8 2004/09/30 21:18:10 satrajit Exp $]
-
-***********************************************************************/
- 
-#ifndef __FPGA_INT_H__
-#define __FPGA_INT_H__
-
-////////////////////////////////////////////////////////////////////////
-///                          INCLUDES                                ///
-////////////////////////////////////////////////////////////////////////
-
-//#include "leaks.h"       
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include "extra.h"
-#include "fpga.h"
-
-////////////////////////////////////////////////////////////////////////
-///                         PARAMETERS                               ///
-////////////////////////////////////////////////////////////////////////
- 
-// uncomment to have fanouts represented in the mapping graph
-//#define FPGA_ALLOCATE_FANOUT  1
-
-////////////////////////////////////////////////////////////////////////
-///                       MACRO DEFINITIONS                          ///
-////////////////////////////////////////////////////////////////////////
-
-#ifdef _WIN32
-#define inline __inline // compatible with MS VS 6.0
-#endif
-
-// the maximum number of cut leaves (currently does not work for 7)
-#define FPGA_MAX_LEAVES           6   
-
-// the bit masks
-#define FPGA_MASK(n)             ((~((unsigned)0)) >> (32-(n)))
-#define FPGA_FULL                 (~((unsigned)0))
-#define FPGA_NO_VAR               (-9999.0)
-#define FPGA_NUM_BYTES(n)         (((n)/16 + (((n)%16) > 0))*16)
-
-// maximum/minimum operators
-#define FPGA_MIN(a,b)             (((a) < (b))? (a) : (b))
-#define FPGA_MAX(a,b)             (((a) > (b))? (a) : (b))
-
-// the small and large numbers (min/max float are 1.17e-38/3.40e+38)
-#define FPGA_FLOAT_LARGE          ((float)1.0e+20)
-#define FPGA_FLOAT_SMALL          ((float)1.0e-20)
-#define FPGA_INT_LARGE            (10000000)
-
-// the macro to compute the signature
-#define FPGA_SEQ_SIGN(p)        (1 << (((unsigned)p)%31));
-
-// internal macros to work with cuts
-#define Fpga_CutIsComplement(p)  (((int)((unsigned long) (p) & 01)))
-#define Fpga_CutRegular(p)       ((Fpga_Cut_t *)((unsigned long)(p) & ~01)) 
-#define Fpga_CutNot(p)           ((Fpga_Cut_t *)((unsigned long)(p) ^ 01)) 
-#define Fpga_CutNotCond(p,c)     ((Fpga_Cut_t *)((unsigned long)(p) ^ (c)))
-
-// the cut nodes
-#define Fpga_SeqIsComplement( p )      (((int)((unsigned long) (p) & 01)))
-#define Fpga_SeqRegular( p )           ((Fpga_Node_t *)((unsigned long)(p) & ~015))
-#define Fpga_SeqIndex( p )             ((((unsigned long)(p)) >> 1) & 07)
-#define Fpga_SeqIndexCreate( p, Ind )  (((unsigned long)(p)) | (1 << (((unsigned)(Ind)) & 07)))
-
-// internal macros for referencing of nodes
-#define Fpga_NodeReadRef(p)      ((Fpga_Regular(p))->nRefs)
-#define Fpga_NodeRef(p)          ((Fpga_Regular(p))->nRefs++)
-
-// returns the complemented attribute of the node
-#define Fpga_NodeIsSimComplement(p) (Fpga_IsComplement(p)? !(Fpga_Regular(p)->fInv) : (p)->fInv)
-
-// generating random unsigned (#define RAND_MAX 0x7fff)
-#define FPGA_RANDOM_UNSIGNED   ((((unsigned)rand()) << 24) ^ (((unsigned)rand()) << 12) ^ ((unsigned)rand()))
-
-// outputs the runtime in seconds
-#define PRT(a,t)  printf("%s = ", (a)); printf("%6.2f sec\n", (float)(t)/(float)(CLOCKS_PER_SEC))
-
-////////////////////////////////////////////////////////////////////////
-///                    STRUCTURE DEFINITIONS                         ///
-////////////////////////////////////////////////////////////////////////
-
-// the mapping manager
-struct Fpga_ManStruct_t_
-{
-    // the mapping graph
-    Fpga_Node_t **      pBins;         // the table of nodes hashed by their children
-    int                 nBins;         // the size of the table
-    Fpga_Node_t **      pInputs;       // the array of inputs
-    int                 nInputs;       // the number of inputs
-    Fpga_Node_t **      pOutputs;      // the array of outputs
-    int                 nOutputs;      // the number of outputs
-    int                 nNodes;        // the total number of nodes
-    int                 nLatches;      // the number of latches in the circuit
-    Fpga_Node_t *       pConst1;       // the constant 1 node
-    Fpga_NodeVec_t *    vNodesAll;     // the nodes by number
-    Fpga_NodeVec_t *    vAnds;         // the nodes reachable from COs
-    Fpga_NodeVec_t *    vMapping;      // the nodes used in the current mapping
-
-    // info about the original circuit
-    char *              pFileName;     // the file name
-    char **             ppOutputNames; // the primary output names
-    float *             pInputArrivals;// the PI arrival times
-
-    // mapping parameters
-    int                 nVarsMax;      // the max number of variables
-    int                 fAreaRecovery; // the flag to use area flow as the first parameter
-    int                 fVerbose;      // the verbosiness flag
-    int                 fSwitching;    // minimize the switching activity (instead of area)
-    int                 fLatchPaths;   // optimize latch paths for delay, other paths for area
-    int                 nTravIds;      // the counter of traversal IDs
-    float               DelayTarget;   // the target required times
-
-    // support of choice nodes
-    int                 nChoiceNodes;  // the number of choice nodes
-    int                 nChoices;      // the number of all choices
-
-    int                 nCanons;
-    int                 nMatches;
- 
-    // the supergate library
-    Fpga_LutLib_t *     pLutLib;       // the current LUT library
-
-    // the memory managers
-    Extra_MmFixed_t *   mmNodes;       // the memory manager for nodes
-    Extra_MmFixed_t *   mmCuts;        // the memory manager for cuts
-
-    // resynthesis parameters
-    int                 fResynthesis;  // the resynthesis flag
-    float               fRequiredGlo;  // the global required times
-    float               fRequiredShift;// the shift of the required times
-    float               fRequiredStart;// the starting global required times
-    float               fRequiredGain; // the reduction in delay
-    float               fAreaGlo;      // the total area
-    float               fAreaGain;     // the reduction in area
-    float               fEpsilon;      // the epsilon used to compare floats
-    float               fDelayWindow;  // the delay window for delay-oriented resynthesis
-    float               DelayLimit;    // for resynthesis
-    float               AreaLimit;     // for resynthesis
-    float               TimeLimit;     // for resynthesis
-
-    // runtime statistics
-    int                 timeToMap;     // time to transfer to the mapping structure
-    int                 timeCuts;      // time to compute k-feasible cuts
-    int                 timeTruth;     // time to compute the truth table for each cut
-    int                 timeMatch;     // time to perform matching for each node
-    int                 timeRecover;   // time to perform area recovery
-    int                 timeToNet;     // time to transfer back to the network
-    int                 timeTotal;     // the total mapping time
-    int                 time1;         // time to transfer to the mapping structure
-    int                 time2;         // time to transfer to the mapping structure
-};
-
-// the LUT library
-struct Fpga_LutLibStruct_t_
-{
-    char *              pName;         // the name of the LUT library
-    int                 LutMax;        // the maximum LUT size 
-    int                 fVarPinDelays; // set to 1 if variable pin delays are specified
-    float               pLutAreas[FPGA_MAX_LUTSIZE+1]; // the areas of LUTs
-    float               pLutDelays[FPGA_MAX_LUTSIZE+1][FPGA_MAX_LUTSIZE+1];// the delays of LUTs
-};
-
-// the mapping node
-struct Fpga_NodeStruct_t_ 
-{
-    // general information about the node
-    Fpga_Node_t *       pNext;         // the next node in the hash table
-    Fpga_Node_t *       pLevel;        // the next node in the linked list by level
-    int                 Num;           // the unique number of this node
-    int                 NumA;          // the unique number of this node
-    short               Num2;          // the temporary number of this node
-    short               nRefs;         // the number of references (fanouts) of the given node
-    unsigned            fMark0 : 1;    // the mark used for traversals
-    unsigned            fMark1 : 1;    // the mark used for traversals
-    unsigned            fInv   : 1;    // the complemented attribute for the equivalent nodes
-    unsigned            Value  : 2;    // the value of the nodes
-    unsigned            fUsed  : 1;    // the flag indicating that the node is used in the mapping
-    unsigned            fTemp  : 1;    // unused
-    unsigned            Level  :11;    // the level of the given node
-    unsigned            uData  :14;    // used to mark the fanins, for which resynthesis was tried
-    int                 TravId;
-
-    // the successors of this node     
-    Fpga_Node_t *       p1;            // the first child
-    Fpga_Node_t *       p2;            // the second child
-    Fpga_Node_t *       pNextE;        // the next functionally equivalent node
-    Fpga_Node_t *       pRepr;         // the representative of the functionally equivalent class
-
-#ifdef FPGA_ALLOCATE_FANOUT
-    // representation of node's fanouts
-    Fpga_Node_t *       pFanPivot;     // the first fanout of this node
-    Fpga_Node_t *       pFanFanin1;    // the next fanout of p1
-    Fpga_Node_t *       pFanFanin2;    // the next fanout of p2
-//    Fpga_NodeVec_t *    vFanouts;      // the array of fanouts of the gate
-#endif
-
-    // the delay information
-    float               tRequired;     // the best area flow 
-    float               aEstFanouts;   // the fanout estimation
-    float               Switching;     // the probability of switching
-    int                 LValue;        // the l-value of the node
-    short               nLatches1;     // the number of latches on the first edge
-    short               nLatches2;     // the number of latches on the second edge
-
-    // cut information
-    Fpga_Cut_t *        pCutBest;      // the best mapping
-    Fpga_Cut_t *        pCutOld;       // the old mapping
-    Fpga_Cut_t *        pCuts;         // mapping choices for the node (elementary comes first)
-    Fpga_Cut_t *        pCutsN;        // mapping choices for the node (elementary comes first)
-
-    // misc information  
-    char *              pData0;        // temporary storage for the corresponding network node
-}; 
-  
-// the cuts used for matching
-struct Fpga_CutStruct_t_  
-{
-    Fpga_Cut_t *        pOne;          // the father of this cut
-    Fpga_Cut_t *        pTwo;          // the mother of this cut
-    Fpga_Node_t *       pRoot;         // the root of the cut
-    Fpga_Node_t *       ppLeaves[FPGA_MAX_LEAVES+1];   // the leaves of this cut
-    float               fLevel;        // the average level of the fanins
-    unsigned            uSign;         // signature for quick comparison
-    char                fMark;         // the mark to denote visited cut
-    char                Phase;         // the mark to denote complemented cut
-    char                nLeaves;       // the number of leaves of this cut
-    char                nVolume;       // the volume of this cut
-    float               tArrival;      // the arrival time 
-    float               aFlow;         // the area flow of the cut
-    Fpga_Cut_t *        pNext;         // the pointer to the next cut in the list
-};
-
-// the vector of nodes
-struct Fpga_NodeVecStruct_t_
-{
-    Fpga_Node_t **      pArray;        // the array of nodes
-    int                 nSize;         // the number of entries in the array
-    int                 nCap;          // the number of allocated entries
-};
-
-// getting hold of the next fanout of the node
-#define Fpga_NodeReadNextFanout( pNode, pFanout )                \
-    ( ( pFanout == NULL )? NULL :                                \
-        ((Fpga_Regular((pFanout)->p1) == (pNode))?               \
-             (pFanout)->pFanFanin1 : (pFanout)->pFanFanin2) )
-
-// getting hold of the place where the next fanout will be attached
-#define Fpga_NodeReadNextFanoutPlace( pNode, pFanout )           \
-    ( (Fpga_Regular((pFanout)->p1) == (pNode))?                  \
-         &(pFanout)->pFanFanin1 : &(pFanout)->pFanFanin2 )
-
-// iterator through the fanouts of the node
-#define Fpga_NodeForEachFanout( pNode, pFanout )                 \
-    for ( pFanout = (pNode)->pFanPivot; pFanout;                 \
-          pFanout = Fpga_NodeReadNextFanout(pNode, pFanout) )
-
-// safe iterator through the fanouts of the node
-#define Fpga_NodeForEachFanoutSafe( pNode, pFanout, pFanout2 )   \
-    for ( pFanout  = (pNode)->pFanPivot,                         \
-          pFanout2 = Fpga_NodeReadNextFanout(pNode, pFanout);    \
-          pFanout;                                               \
-          pFanout  = pFanout2,                                   \
-          pFanout2 = Fpga_NodeReadNextFanout(pNode, pFanout) )
-
-static inline Fpga_FloatMoreThan( Fpga_Man_t * p, float Arg1, float Arg2 ) { return Arg1 > Arg2 + p->fEpsilon; }
-static inline Fpga_FloatLessThan( Fpga_Man_t * p, float Arg1, float Arg2 ) { return Arg1 < Arg2 - p->fEpsilon; }
-static inline Fpga_FloatEqual( Fpga_Man_t * p, float Arg1, float Arg2 )    { return Arg1 > Arg2 - p->fEpsilon && Arg1 < Arg2 + p->fEpsilon; }
-
-////////////////////////////////////////////////////////////////////////
-///                       GLOBAL VARIABLES                           ///
-////////////////////////////////////////////////////////////////////////
-
-////////////////////////////////////////////////////////////////////////
-///                     FUNCTION DEFINITIONS                         ///
-////////////////////////////////////////////////////////////////////////
-
-/*=== fpgaCut.c ===============================================================*/
-extern void              Fpga_MappingCuts( Fpga_Man_t * p );
-extern void              Fpga_MappingCreatePiCuts( Fpga_Man_t * p );
-extern int               Fpga_CutCountAll( Fpga_Man_t * pMan );
-/*=== fpgaCutUtils.c ===============================================================*/
-extern Fpga_Cut_t *      Fpga_CutAlloc( Fpga_Man_t * p );
-extern Fpga_Cut_t *      Fpga_CutDup( Fpga_Man_t * p, Fpga_Cut_t * pCutOld );
-extern void              Fpga_CutFree( Fpga_Man_t * p, Fpga_Cut_t * pCut );
-extern void              Fpga_CutPrint( Fpga_Man_t * p, Fpga_Node_t * pRoot, Fpga_Cut_t * pCut );
-extern Fpga_Cut_t *      Fpga_CutCreateSimple( Fpga_Man_t * p, Fpga_Node_t * pNode );
-extern float             Fpga_CutGetRootArea( Fpga_Man_t * p, Fpga_Cut_t * pCut );
-extern Fpga_Cut_t *      Fpga_CutListAppend( Fpga_Cut_t * pSetAll, Fpga_Cut_t * pSets );
-extern void              Fpga_CutListRecycle( Fpga_Man_t * p, Fpga_Cut_t * pSetList, Fpga_Cut_t * pSave );
-extern int               Fpga_CutListCount( Fpga_Cut_t * pSets );
-extern void              Fpga_CutRemoveFanouts( Fpga_Man_t * p, Fpga_Node_t * pNode, Fpga_Cut_t * pCut );
-extern void              Fpga_CutInsertFanouts( Fpga_Man_t * p, Fpga_Node_t * pNode, Fpga_Cut_t * pCut );
-extern float             Fpga_CutGetAreaRefed( Fpga_Man_t * pMan, Fpga_Cut_t * pCut );
-extern float             Fpga_CutGetAreaDerefed( Fpga_Man_t * pMan, Fpga_Cut_t * pCut );
-extern float             Fpga_CutRef( Fpga_Man_t * pMan, Fpga_Node_t * pNode, Fpga_Cut_t * pCut, int fFanouts );
-extern float             Fpga_CutDeref( Fpga_Man_t * pMan, Fpga_Node_t * pNode, Fpga_Cut_t * pCut, int fFanouts );
-extern float             Fpga_CutGetAreaFlow( Fpga_Man_t * pMan, Fpga_Cut_t * pCut );
-extern void              Fpga_CutGetParameters( Fpga_Man_t * pMan, Fpga_Cut_t * pCut );
-/*=== fraigFanout.c =============================================================*/
-extern void              Fpga_NodeAddFaninFanout( Fpga_Node_t * pFanin, Fpga_Node_t * pFanout );
-extern void              Fpga_NodeRemoveFaninFanout( Fpga_Node_t * pFanin, Fpga_Node_t * pFanoutToRemove );
-extern int               Fpga_NodeGetFanoutNum( Fpga_Node_t * pNode );
-/*=== fpgaLib.c ============================================================*/
-extern Fpga_LutLib_t *   Fpga_LutLibCreate( char * FileName, int fVerbose );
-extern void              Fpga_LutLibFree( Fpga_LutLib_t * p );
-extern void              Fpga_LutLibPrint( Fpga_LutLib_t * pLutLib );
-extern int               Fpga_LutLibDelaysAreDiscrete( Fpga_LutLib_t * pLutLib );
-/*=== fpgaMatch.c ===============================================================*/
-extern int               Fpga_MappingMatches( Fpga_Man_t * p, int fDelayOriented );
-extern int               Fpga_MappingMatchesArea( Fpga_Man_t * p );
-extern int               Fpga_MappingMatchesSwitch( Fpga_Man_t * p );
-/*=== fpgaShow.c =============================================================*/
-extern void              Fpga_MappingShow( Fpga_Man_t * pMan, char * pFileName );
-extern void              Fpga_MappingShowNodes( Fpga_Man_t * pMan, Fpga_Node_t ** ppRoots, int nRoots, char * pFileName );
-/*=== fpgaSwitch.c =============================================================*/
-extern float             Fpga_CutGetSwitchDerefed( Fpga_Man_t * pMan, Fpga_Node_t * pNode, Fpga_Cut_t * pCut );
-extern float             Fpga_CutRefSwitch( Fpga_Man_t * pMan, Fpga_Node_t * pNode, Fpga_Cut_t * pCut, int fFanouts );
-extern float             Fpga_CutDerefSwitch( Fpga_Man_t * pMan, Fpga_Node_t * pNode, Fpga_Cut_t * pCut, int fFanouts );
-extern float             Fpga_MappingGetSwitching( Fpga_Man_t * pMan, Fpga_NodeVec_t * vMapping );
-/*=== fpgaTime.c ===============================================================*/
-extern float             Fpga_TimeCutComputeArrival( Fpga_Man_t * pMan, Fpga_Cut_t * pCut );
-extern float             Fpga_TimeCutComputeArrival_rec( Fpga_Man_t * pMan, Fpga_Cut_t * pCut );
-extern float             Fpga_TimeComputeArrivalMax( Fpga_Man_t * p );
-extern void              Fpga_TimeComputeRequiredGlobal( Fpga_Man_t * p, int fFirstTime );
-extern void              Fpga_TimeComputeRequired( Fpga_Man_t * p, float fRequired );
-extern void              Fpga_TimePropagateRequired( Fpga_Man_t * p, Fpga_NodeVec_t * vNodes );
-extern void              Fpga_TimePropagateArrival( Fpga_Man_t * p );
-/*=== fpgaVec.c =============================================================*/
-extern Fpga_NodeVec_t *  Fpga_NodeVecAlloc( int nCap );
-extern void              Fpga_NodeVecFree( Fpga_NodeVec_t * p );
-extern Fpga_Node_t **    Fpga_NodeVecReadArray( Fpga_NodeVec_t * p );
-extern int               Fpga_NodeVecReadSize( Fpga_NodeVec_t * p );
-extern void              Fpga_NodeVecGrow( Fpga_NodeVec_t * p, int nCapMin );
-extern void              Fpga_NodeVecShrink( Fpga_NodeVec_t * p, int nSizeNew );
-extern void              Fpga_NodeVecClear( Fpga_NodeVec_t * p );
-extern void              Fpga_NodeVecPush( Fpga_NodeVec_t * p, Fpga_Node_t * Entry );
-extern int               Fpga_NodeVecPushUnique( Fpga_NodeVec_t * p, Fpga_Node_t * Entry );
-extern Fpga_Node_t *     Fpga_NodeVecPop( Fpga_NodeVec_t * p );
-extern void              Fpga_NodeVecWriteEntry( Fpga_NodeVec_t * p, int i, Fpga_Node_t * Entry );
-extern Fpga_Node_t *     Fpga_NodeVecReadEntry( Fpga_NodeVec_t * p, int i );
-extern void              Fpga_NodeVecSortByLevel( Fpga_NodeVec_t * p );
-extern void              Fpga_SortNodesByArrivalTimes( Fpga_NodeVec_t * p );
-extern void              Fpga_NodeVecUnion( Fpga_NodeVec_t * p, Fpga_NodeVec_t * p1, Fpga_NodeVec_t * p2 );
-extern void              Fpga_NodeVecPushOrder( Fpga_NodeVec_t * vNodes, Fpga_Node_t * pNode, int fIncreasing );
-extern void              Fpga_NodeVecReverse( Fpga_NodeVec_t * vNodes );
-
-/*=== fpgaUtils.c ===============================================================*/
-extern Fpga_NodeVec_t *  Fpga_MappingDfs( Fpga_Man_t * pMan, int fCollectEquiv );
-extern Fpga_NodeVec_t *  Fpga_MappingDfsNodes( Fpga_Man_t * pMan, Fpga_Node_t ** ppNodes, int nNodes, int fEquiv );
-extern int               Fpga_CountLevels( Fpga_Man_t * pMan );
-extern float             Fpga_MappingGetAreaFlow( Fpga_Man_t * p );
-extern float             Fpga_MappingArea( Fpga_Man_t * pMan );
-extern float             Fpga_MappingAreaTrav( Fpga_Man_t * pMan );
-extern float             Fpga_MappingSetRefsAndArea( Fpga_Man_t * pMan );
-extern void              Fpga_MappingPrintOutputArrivals( Fpga_Man_t * p );
-extern void              Fpga_MappingSetupTruthTables( unsigned uTruths[][2] );
-extern void              Fpga_MappingSetupMask( unsigned uMask[], int nVarsMax );
-extern void              Fpga_MappingSortByLevel( Fpga_Man_t * pMan, Fpga_NodeVec_t * vNodes, int fIncreasing );
-extern Fpga_NodeVec_t *  Fpga_DfsLim( Fpga_Man_t * pMan, Fpga_Node_t * pNode, int nLevels );
-extern Fpga_NodeVec_t *  Fpga_MappingLevelize( Fpga_Man_t * pMan, Fpga_NodeVec_t * vNodes );
-extern int               Fpga_MappingMaxLevel( Fpga_Man_t * pMan );
-extern void              Fpga_ManReportChoices( Fpga_Man_t * pMan );
-extern void              Fpga_MappingSetChoiceLevels( Fpga_Man_t * pMan );
-
-/*=== CUDD package.c ===============================================================*/
-extern unsigned int      Cudd_Prime( unsigned int p );
-
-#endif
-
-////////////////////////////////////////////////////////////////////////
-///                       END OF FILE                                ///
-////////////////////////////////////////////////////////////////////////
diff --git a/abc70930/src/map/fpga/fpgaLib.c b/abc70930/src/map/fpga/fpgaLib.c
deleted file mode 100644
index e74def32..00000000
--- a/abc70930/src/map/fpga/fpgaLib.c
+++ /dev/null
@@ -1,249 +0,0 @@
-/**CFile****************************************************************
-
-  FileName    [fpgaLib.c]
-
-  PackageName [MVSIS 1.3: Multi-valued logic synthesis system.]
-
-  Synopsis    [Technology mapping for variable-size-LUT FPGAs.]
-
-  Author      [MVSIS Group]
-  
-  Affiliation [UC Berkeley]
-
-  Date        [Ver. 2.0. Started - August 18, 2004.]
-
-  Revision    [$Id: fpgaLib.c,v 1.4 2005/01/23 06:59:41 alanmi Exp $]
-
-***********************************************************************/
-
-#include "fpgaInt.h"
-
-////////////////////////////////////////////////////////////////////////
-///                        DECLARATIONS                              ///
-////////////////////////////////////////////////////////////////////////
-
-////////////////////////////////////////////////////////////////////////
-///                     FUNCTION DEFINITIONS                         ///
-////////////////////////////////////////////////////////////////////////
-
-/**Function*************************************************************
-
-  Synopsis    [APIs to access LUT library.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int         Fpga_LutLibReadVarMax( Fpga_LutLib_t * p )               { return p->LutMax;     }
-float *     Fpga_LutLibReadLutAreas( Fpga_LutLib_t * p )             { return p->pLutAreas;  }
-float       Fpga_LutLibReadLutArea( Fpga_LutLib_t * p, int Size )    { assert( Size <= p->LutMax ); return p->pLutAreas[Size];  }
-
-/**Function*************************************************************
-
-  Synopsis    [Reads the description of LUTs from the LUT library file.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-Fpga_LutLib_t * Fpga_LutLibCreate( char * FileName, int fVerbose )
-{
-    char pBuffer[1000], * pToken;
-    Fpga_LutLib_t * p;
-    FILE * pFile;
-    int i, k;
-
-    pFile = fopen( FileName, "r" );
-    if ( pFile == NULL )
-    {
-        printf( "Cannot open LUT library file \"%s\".\n", FileName );
-        return NULL;
-    }
-
-    p = ALLOC( Fpga_LutLib_t, 1 );
-    memset( p, 0, sizeof(Fpga_LutLib_t) );
-    p->pName = Extra_UtilStrsav( FileName );
-
-    i = 1;
-    while ( fgets( pBuffer, 1000, pFile ) != NULL )
-    {
-        pToken = strtok( pBuffer, " \t\n" );
-        if ( pToken == NULL )
-            continue;
-        if ( pToken[0] == '#' )
-            continue;
-        if ( i != atoi(pToken) )
-        {
-            printf( "Error in the LUT library file \"%s\".\n", FileName );
-            free( p );
-            return NULL;
-        }
-
-        // read area
-        pToken = strtok( NULL, " \t\n" );
-        p->pLutAreas[i] = (float)atof(pToken);
-
-        // read delays
-        k = 0;
-        while ( pToken = strtok( NULL, " \t\n" ) )
-            p->pLutDelays[i][k++] = (float)atof(pToken);
-
-        // check for out-of-bound
-        if ( k > i )
-        {
-            printf( "LUT %d has too many pins (%d). Max allowed is %d.\n", i, k, i );
-            return NULL;
-        }
-
-        // check if var delays are specifies
-        if ( k > 1 )
-            p->fVarPinDelays = 1;
-
-        if ( i == FPGA_MAX_LUTSIZE )
-        {
-            printf( "Skipping LUTs of size more than %d.\n", i );
-            return NULL;
-        }
-        i++;
-    }
-    p->LutMax = i-1;
-    if ( p->LutMax > FPGA_MAX_LEAVES )
-    {
-        p->LutMax = FPGA_MAX_LEAVES;
-        printf( "Warning: LUTs with more than %d input will not be used.\n", FPGA_MAX_LEAVES );
-    }
-
-    // check the library
-    if ( p->fVarPinDelays )
-    {
-        for ( i = 1; i <= p->LutMax; i++ )
-            for ( k = 0; k < i; k++ )
-            {
-                if ( p->pLutDelays[i][k] <= 0.0 )
-                    printf( "Warning: Pin %d of LUT %d has delay %f. Pin delays should be non-negative numbers. Technology mapping may not work correctly.\n", 
-                        k, i, p->pLutDelays[i][k] );
-                if ( k && p->pLutDelays[i][k-1] > p->pLutDelays[i][k] )
-                    printf( "Warning: Pin %d of LUT %d has delay %f. Pin %d of LUT %d has delay %f. Pin delays should be in non-decreasing order. Technology mapping may not work correctly.\n", 
-                        k-1, i, p->pLutDelays[i][k-1], 
-                        k, i, p->pLutDelays[i][k] );
-            }
-    }
-    else
-    {
-        for ( i = 1; i <= p->LutMax; i++ )
-        {
-            if ( p->pLutDelays[i][0] <= 0.0 )
-                printf( "Warning: LUT %d has delay %f. Pin delays should be non-negative numbers. Technology mapping may not work correctly.\n", 
-                    k, i, p->pLutDelays[i][0] );
-        }
-    }
-
-    return p;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Duplicates the LUT library.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-Fpga_LutLib_t * Fpga_LutLibDup( Fpga_LutLib_t * p )
-{
-    Fpga_LutLib_t * pNew;
-    pNew = ALLOC( Fpga_LutLib_t, 1 );
-    *pNew = *p;
-    pNew->pName = Extra_UtilStrsav( pNew->pName );
-    return pNew;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Frees the LUT library.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Fpga_LutLibFree( Fpga_LutLib_t * pLutLib )
-{
-    if ( pLutLib == NULL )
-        return;
-    FREE( pLutLib->pName );
-    FREE( pLutLib );
-}
-
-
-/**Function*************************************************************
-
-  Synopsis    [Prints the LUT library.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Fpga_LutLibPrint( Fpga_LutLib_t * pLutLib )
-{
-    int i, k;
-    printf( "# The area/delay of k-variable LUTs:\n" );
-    printf( "# k    area     delay\n" );
-    if ( pLutLib->fVarPinDelays )
-    {
-        for ( i = 1; i <= pLutLib->LutMax; i++ )
-        {
-            printf( "%d   %7.2f  ", i, pLutLib->pLutAreas[i] );
-            for ( k = 0; k < i; k++ )
-                printf( " %7.2f", pLutLib->pLutDelays[i][k] );
-            printf( "\n" );
-        }
-    }
-    else
-        for ( i = 1; i <= pLutLib->LutMax; i++ )
-            printf( "%d   %7.2f   %7.2f\n", i, pLutLib->pLutAreas[i], pLutLib->pLutDelays[i][0] );
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Returns 1 if the delays are discrete.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Fpga_LutLibDelaysAreDiscrete( Fpga_LutLib_t * pLutLib )
-{
-    float Delay;
-    int i;
-    for ( i = 1; i <= pLutLib->LutMax; i++ )
-    {
-        Delay = pLutLib->pLutDelays[i][0];
-        if ( ((float)((int)Delay)) != Delay )
-            return 0;
-    }
-    return 1;
-}
-
-////////////////////////////////////////////////////////////////////////
-///                       END OF FILE                                ///
-////////////////////////////////////////////////////////////////////////
-
-
diff --git a/abc70930/src/map/fpga/fpgaMatch.c b/abc70930/src/map/fpga/fpgaMatch.c
deleted file mode 100644
index 73fa1258..00000000
--- a/abc70930/src/map/fpga/fpgaMatch.c
+++ /dev/null
@@ -1,794 +0,0 @@
-/**CFile****************************************************************
-
-  FileName    [fpgaMatch.c]
-
-  PackageName [MVSIS 1.3: Multi-valued logic synthesis system.]
-
-  Synopsis    [Technology mapping for variable-size-LUT FPGAs.]
-
-  Author      [MVSIS Group]
-  
-  Affiliation [UC Berkeley]
-
-  Date        [Ver. 2.0. Started - August 18, 2004.]
-
-  Revision    [$Id: fpgaMatch.c,v 1.7 2004/09/30 21:18:10 satrajit Exp $]
-
-***********************************************************************/
-
-#include "fpgaInt.h"
-
-////////////////////////////////////////////////////////////////////////
-///                        DECLARATIONS                              ///
-////////////////////////////////////////////////////////////////////////
-
-static int          Fpga_MatchNode( Fpga_Man_t * p, Fpga_Node_t * pNode, int fDelayOriented );
-static int          Fpga_MatchNodeArea( Fpga_Man_t * p, Fpga_Node_t * pNode );
-static int          Fpga_MatchNodeSwitch( Fpga_Man_t * p, Fpga_Node_t * pNode );
-
-static Fpga_Cut_t * Fpga_MappingAreaWithoutNode( Fpga_Man_t * p, Fpga_Node_t * pFanout, Fpga_Node_t * pNodeNo );
-static int          Fpga_MappingMatchesAreaArray( Fpga_Man_t * p, Fpga_NodeVec_t * vNodes );
-
-////////////////////////////////////////////////////////////////////////
-///                     FUNCTION DEFINITIONS                         ///
-////////////////////////////////////////////////////////////////////////
-
-/**Function*************************************************************
-
-  Synopsis    [Finds the best delay assignment of LUTs.]
-
-  Description [This procedure iterates through all the nodes
-  of the object graph reachable from the POs and assigns the best
-  match to each of them. If the flag fDelayOriented is set to 1, it 
-  tries to minimize the arrival time and uses the area flow as a
-  tie-breaker. If the flag is set to 0, it considers all the cuts,
-  whose arrival times matches the required time at the node, and
-  minimizes the area flow using the arrival time as a tie-breaker.
-  
-  Before this procedure is called, the required times should be set
-  and the fanout counts should be computed. In the first iteration,
-  the required times are set to very large number (by NodeCreate) 
-  and the fanout counts are set to the number of fanouts in the AIG.
-  In the following iterations, the required times are set by the
-  backward traversal, while the fanouts are estimated approximately.
-  
-  If the arrival times of the PI nodes are given, they should be 
-  assigned to the PIs after the cuts are computed and before this
-  procedure is called for the first time.]
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Fpga_MappingMatches( Fpga_Man_t * p, int fDelayOriented )
-{
-    ProgressBar * pProgress;
-    Fpga_Node_t * pNode;
-    int i, nNodes;
-    
-    // assign the arrival times of the PIs
-    for ( i = 0; i < p->nInputs; i++ )
-        p->pInputs[i]->pCutBest->tArrival = p->pInputArrivals[i];
-
-    // match LUTs with nodes in the topological order
-    nNodes = p->vAnds->nSize;
-    pProgress = Extra_ProgressBarStart( stdout, nNodes );
-    for ( i = 0; i < nNodes; i++ )
-    {
-        pNode = p->vAnds->pArray[i];
-        if ( !Fpga_NodeIsAnd( pNode ) )
-            continue;
-        // skip a secondary node
-        if ( pNode->pRepr )
-            continue;
-        // match the node
-        Fpga_MatchNode( p, pNode, fDelayOriented );
-        Extra_ProgressBarUpdate( pProgress, i, "Matches ..." );
-    }
-    Extra_ProgressBarStop( pProgress );
-/*
-    if ( !fDelayOriented )
-    {
-        float Area = 0.0;
-        for ( i = 0; i < p->nOutputs; i++ )
-        {
-            printf( "%5.2f ", Fpga_Regular(p->pOutputs[i])->pCutBest->aFlow );
-            Area += Fpga_Regular(p->pOutputs[i])->pCutBest->aFlow;
-        }
-        printf( "\nTotal = %5.2f\n", Area );
-    }
-*/
-    return 1;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Computes the best matching for one node.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Fpga_MatchNode( Fpga_Man_t * p, Fpga_Node_t * pNode, int fDelayOriented )
-{
-    Fpga_Cut_t * pCut, * pCutBestOld;
-    int clk;
-    // make sure that at least one cut other than the trivial is present
-    if ( pNode->pCuts->pNext == NULL )
-    {
-        printf( "\nError: A node in the mapping graph does not have feasible cuts.\n" );
-        return 0;
-    }
-
-    // estimate the fanouts of the node
-    if ( pNode->aEstFanouts < 0 )
-        pNode->aEstFanouts = (float)pNode->nRefs;
-    else
-        pNode->aEstFanouts = (float)((2.0 * pNode->aEstFanouts + pNode->nRefs) / 3.0);
-//        pNode->aEstFanouts = (float)pNode->nRefs;
-
-    pCutBestOld = pNode->pCutBest;
-    pNode->pCutBest = NULL;
-    for ( pCut = pNode->pCuts->pNext; pCut; pCut = pCut->pNext )
-    {
-        // compute the arrival time of the cut and its area flow
-clk = clock();
-        Fpga_CutGetParameters( p, pCut );
-//p->time2 += clock() - clk;
-        // drop the cut if it does not meet the required times
-        if ( Fpga_FloatMoreThan(p, pCut->tArrival, pNode->tRequired) )
-            continue;
-        // if no cut is assigned, use the current one
-        if ( pNode->pCutBest == NULL )
-        {
-            pNode->pCutBest = pCut;
-            continue;
-        }
-        // choose the best cut using one of the two criteria:
-        // (1) delay oriented mapping (first traversal), delay first, area-flow as a tie-breaker
-        // (2) area recovery (subsequent traversals), area-flow first, delay as a tie-breaker
-        if ( (fDelayOriented && 
-               (Fpga_FloatMoreThan(p, pNode->pCutBest->tArrival, pCut->tArrival) || 
-                Fpga_FloatEqual(p, pNode->pCutBest->tArrival, pCut->tArrival) && Fpga_FloatMoreThan(p, pNode->pCutBest->aFlow, pCut->aFlow) )) ||
-             (!fDelayOriented && 
-               (Fpga_FloatMoreThan(p, pNode->pCutBest->aFlow, pCut->aFlow) || 
-                Fpga_FloatEqual(p, pNode->pCutBest->aFlow, pCut->aFlow) && Fpga_FloatMoreThan(p, pNode->pCutBest->tArrival, pCut->tArrival)))  )
-        {
-            pNode->pCutBest = pCut;
-        }
-    }
-
-    // make sure the match is found
-    if ( pNode->pCutBest == NULL )
-    {
-        if ( pCutBestOld == NULL )
-        {
-//            printf( "\nError: Could not match a node in the object graph.\n" );
-            return 0;
-        }
-        pNode->pCutBest = pCutBestOld;
-    }
-    return 1;
-}
-
-
-
-
-
-/**Function*************************************************************
-
-  Synopsis    [Finds the best area assignment of LUTs.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Fpga_MappingMatchesArea( Fpga_Man_t * p )
-{
-    ProgressBar * pProgress;
-    Fpga_Node_t * pNode;
-    int i, nNodes;
-    
-    // assign the arrival times of the PIs
-    for ( i = 0; i < p->nInputs; i++ )
-        p->pInputs[i]->pCutBest->tArrival = p->pInputArrivals[i];
-
-    // match LUTs with nodes in the topological order
-    nNodes = p->vAnds->nSize;
-    pProgress = Extra_ProgressBarStart( stdout, nNodes );
-    for ( i = 0; i < nNodes; i++ )
-    {
-        pNode = p->vAnds->pArray[i];
-        if ( !Fpga_NodeIsAnd( pNode ) )
-            continue;
-        // skip a secondary node
-        if ( pNode->pRepr )
-            continue;
-        // match the node
-        Fpga_MatchNodeArea( p, pNode );
-        Extra_ProgressBarUpdate( pProgress, i, "Matches ..." );
-    }
-    Extra_ProgressBarStop( pProgress );
-    return 1;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Finds the best area assignment of LUTs.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Fpga_MappingMatchesAreaArray( Fpga_Man_t * p, Fpga_NodeVec_t * vNodes )
-{
-    Fpga_Node_t * pNode;
-    int i;
-
-    // match LUTs with nodes in the topological order
-    for ( i = 0; i < vNodes->nSize; i++ )
-    {
-        pNode = vNodes->pArray[i];
-        if ( !Fpga_NodeIsAnd( pNode ) )
-            continue;
-        // skip a secondary node
-        if ( pNode->pRepr )
-            continue;
-        // match the node
-        if ( !Fpga_MatchNodeArea( p, pNode ) )
-            return 0;
-    }
-    return 1;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Computes the best matching for one node.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Fpga_MatchNodeArea( Fpga_Man_t * p, Fpga_Node_t * pNode )
-{
-    Fpga_Cut_t * pCut, * pCutBestOld;
-    float aAreaCutBest;
-    int clk;
-    // make sure that at least one cut other than the trivial is present
-    if ( pNode->pCuts->pNext == NULL )
-    {
-        printf( "\nError: A node in the mapping graph does not have feasible cuts.\n" );
-        return 0;
-    }
-
-    // remember the old cut
-    pCutBestOld = pNode->pCutBest;
-    // deref the old cut
-    if ( pNode->nRefs ) 
-        aAreaCutBest = Fpga_CutDeref( p, pNode, pNode->pCutBest, 0 );
-
-    // search for a better cut
-    pNode->pCutBest = NULL;
-    for ( pCut = pNode->pCuts->pNext; pCut; pCut = pCut->pNext )
-    {
-        // compute the arrival time of the cut and its area flow
-clk = clock();
-        pCut->tArrival = Fpga_TimeCutComputeArrival( p, pCut );
-//p->time2 += clock() - clk;
-        // drop the cut if it does not meet the required times
-        if ( Fpga_FloatMoreThan( p, pCut->tArrival, pNode->tRequired ) )
-            continue;
-        // get the area of this cut
-        pCut->aFlow = Fpga_CutGetAreaDerefed( p, pCut );
-        // if no cut is assigned, use the current one
-        if ( pNode->pCutBest == NULL )
-        {
-            pNode->pCutBest = pCut;
-            continue;
-        }
-        // choose the best cut as follows: exact area first, delay as a tie-breaker
-        if ( Fpga_FloatMoreThan(p, pNode->pCutBest->aFlow, pCut->aFlow) || 
-             Fpga_FloatEqual(p, pNode->pCutBest->aFlow, pCut->aFlow) && Fpga_FloatMoreThan(p, pNode->pCutBest->tArrival, pCut->tArrival) )
-        {
-            pNode->pCutBest = pCut;
-        }
-    }
-
-    // make sure the match is found
-    if ( pNode->pCutBest == NULL )
-    {
-        pNode->pCutBest = pCutBestOld; 
-        // insert the new cut
-        if ( pNode->nRefs ) 
-            pNode->pCutBest->aFlow = Fpga_CutRef( p, pNode, pNode->pCutBest, 0 );
-//        printf( "\nError: Could not match a node in the object graph.\n" );
-        return 0;
-    }
-
-    // insert the new cut
-    // make sure the area selected is not worse then the original area
-    if ( pNode->nRefs ) 
-    {
-        pNode->pCutBest->aFlow = Fpga_CutRef( p, pNode, pNode->pCutBest, 0 );
-//        assert( pNode->pCutBest->aFlow <= aAreaCutBest );
-//        assert( pNode->tRequired < FPGA_FLOAT_LARGE );
-    }
-    return 1;
-}
-
-
-
-
-/**Function*************************************************************
-
-  Synopsis    [Finds the best area assignment of LUTs.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Fpga_MappingMatchesSwitch( Fpga_Man_t * p )
-{
-    ProgressBar * pProgress;
-    Fpga_Node_t * pNode;
-    int i, nNodes;
-    
-    // assign the arrival times of the PIs
-    for ( i = 0; i < p->nInputs; i++ )
-        p->pInputs[i]->pCutBest->tArrival = p->pInputArrivals[i];
-
-    // match LUTs with nodes in the topological order
-    nNodes = p->vAnds->nSize;
-    pProgress = Extra_ProgressBarStart( stdout, nNodes );
-    for ( i = 0; i < nNodes; i++ )
-    {
-        pNode = p->vAnds->pArray[i];
-        if ( !Fpga_NodeIsAnd( pNode ) )
-            continue;
-        // skip a secondary node
-        if ( pNode->pRepr )
-            continue;
-        // match the node
-        Fpga_MatchNodeSwitch( p, pNode );
-        Extra_ProgressBarUpdate( pProgress, i, "Matches ..." );
-    }
-    Extra_ProgressBarStop( pProgress );
-    return 1;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Computes the best matching for one node.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Fpga_MatchNodeSwitch( Fpga_Man_t * p, Fpga_Node_t * pNode )
-{
-    Fpga_Cut_t * pCut, * pCutBestOld;
-    float aAreaCutBest;
-    int clk;
-    // make sure that at least one cut other than the trivial is present
-    if ( pNode->pCuts->pNext == NULL )
-    {
-        printf( "\nError: A node in the mapping graph does not have feasible cuts.\n" );
-        return 0;
-    }
-
-    // remember the old cut
-    pCutBestOld = pNode->pCutBest;
-    // deref the old cut
-    if ( pNode->nRefs ) 
-        aAreaCutBest = Fpga_CutDerefSwitch( p, pNode, pNode->pCutBest, 0 );
-
-    // search for a better cut
-    pNode->pCutBest = NULL;
-    for ( pCut = pNode->pCuts->pNext; pCut; pCut = pCut->pNext )
-    {
-        // compute the arrival time of the cut and its area flow
-clk = clock();
-        pCut->tArrival = Fpga_TimeCutComputeArrival( p, pCut );
-//p->time2 += clock() - clk;
-        // drop the cut if it does not meet the required times
-        if ( Fpga_FloatMoreThan( p, pCut->tArrival, pNode->tRequired ) )
-            continue;
-        // get the area of this cut
-        pCut->aFlow = Fpga_CutGetSwitchDerefed( p, pNode, pCut );
-        // if no cut is assigned, use the current one
-        if ( pNode->pCutBest == NULL )
-        {
-            pNode->pCutBest = pCut;
-            continue;
-        }
-        // choose the best cut as follows: exact area first, delay as a tie-breaker
-        if ( Fpga_FloatMoreThan(p, pNode->pCutBest->aFlow, pCut->aFlow) || 
-             Fpga_FloatEqual(p, pNode->pCutBest->aFlow, pCut->aFlow) && Fpga_FloatMoreThan(p, pNode->pCutBest->tArrival, pCut->tArrival) )
-        {
-            pNode->pCutBest = pCut;
-        }
-    }
-
-    // make sure the match is found
-    if ( pNode->pCutBest == NULL )
-    {
-        pNode->pCutBest = pCutBestOld; 
-        // insert the new cut
-        if ( pNode->nRefs ) 
-            pNode->pCutBest->aFlow = Fpga_CutRefSwitch( p, pNode, pNode->pCutBest, 0 );
-//        printf( "\nError: Could not match a node in the object graph.\n" );
-        return 0;
-    }
-
-    // insert the new cut
-    // make sure the area selected is not worse then the original area
-    if ( pNode->nRefs ) 
-    {
-        pNode->pCutBest->aFlow = Fpga_CutRefSwitch( p, pNode, pNode->pCutBest, 0 );
-        assert( pNode->pCutBest->aFlow <= aAreaCutBest + 0.001 );
-//        assert( pNode->tRequired < FPGA_FLOAT_LARGE );
-    }
-    return 1;
-}
-
-
-#if 0
-/**function*************************************************************
-
-  synopsis    [References the cut.]
-
-  description [This procedure is similar to the procedure NodeReclaim.]
-               
-  sideeffects []
-
-  seealso     []
-
-***********************************************************************/
-void Fpga_Experiment( Fpga_Man_t * p )
-{
-    int Counter[10] = {0};
-    Fpga_Node_t * pNode;
-    int i;
-
-    for ( i = 0; i < p->nOutputs; i++ )
-    {
-        pNode = Fpga_Regular(p->pOutputs[i]);
-        pNode->vFanouts = NULL;
-    }
-
-    for ( i = 0; i < p->vAnds->nSize; i++ )
-    {
-        pNode = p->vAnds->pArray[i];
-        if ( !Fpga_NodeIsAnd( pNode ) )
-            continue;
-        if ( pNode->vFanouts == NULL )
-            continue;
-        if ( pNode->vFanouts->nSize >= 10 )
-            continue;
-        Counter[pNode->vFanouts->nSize]++;
-    }
-
-    printf( "Fanout stats: " );
-    for ( i = 0; i < 10; i++ )
-        printf( " %d=%d", i, Counter[i] );
-    printf( "\n" );
-    printf( "Area before = %4.2f.\n", Fpga_MappingArea(p) );
-
-    for ( i = 0; i < p->vAnds->nSize; i++ )
-    {
-        Fpga_NodeVec_t * vNodesTfo;
-        float AreaBefore;
-
-        pNode = p->vAnds->pArray[i];
-        if ( !Fpga_NodeIsAnd( pNode ) )
-            continue;
-        if ( pNode->vFanouts == NULL )
-            continue;
-        if ( pNode->vFanouts->nSize != 1 && pNode->vFanouts->nSize != 2 && pNode->vFanouts->nSize != 3 )
-            continue;
-
-//        assert( pNode->nRefs > 0 );
-        if ( pNode->nRefs == 0 )
-            continue;
-
-        AreaBefore = pNode->pCutBest->aFlow;
-        pNode->pCutBest->aFlow = FPGA_FLOAT_LARGE;
-
-        Fpga_TimeComputeRequiredGlobal( p, 0 );
-
-        vNodesTfo = Fpga_CollectNodeTfo( p, pNode );
-        if ( Fpga_MappingMatchesAreaArray( p, vNodesTfo ) == 0 )
-            printf( "attempt failed\n" );
-        else
-            printf( "attempt succeeded\n" );
-        Fpga_NodeVecFree( vNodesTfo );
-
-        pNode->pCutBest->aFlow = AreaBefore;
-//        break;
-    }
-    printf( "Area after = %4.2f.\n", Fpga_MappingArea(p) );
-//    printf( "AREA GAIN = %4.2f (%.2f %%)\n", GainTotal, 100.0 * GainTotal / Fpga_MappingArea(p) );
-}
-
-
-
-/**function*************************************************************
-
-  synopsis    [References the cut.]
-
-  description [This procedure is similar to the procedure NodeReclaim.]
-               
-  sideeffects []
-
-  seealso     []
-
-***********************************************************************/
-void Fpga_Experiment2( Fpga_Man_t * p )
-{
-    int Counter[10] = {0};
-    Fpga_Cut_t * ppCutsNew[10];
-    Fpga_Cut_t * ppCutsOld[10];
-    Fpga_Node_t * pFanout, * pNode;
-    float Gain, Loss, GainTotal,  Area1, Area2;
-    int i, k;
-
-    for ( i = 0; i < p->nOutputs; i++ )
-    {
-        pNode = Fpga_Regular(p->pOutputs[i]);
-        pNode->vFanouts = NULL;
-    }
-
-    for ( i = 0; i < p->vAnds->nSize; i++ )
-    {
-        pNode = p->vAnds->pArray[i];
-        if ( !Fpga_NodeIsAnd( pNode ) )
-            continue;
-        if ( pNode->vFanouts == NULL )
-            continue;
-        if ( pNode->vFanouts->nSize >= 10 )
-            continue;
-        Counter[pNode->vFanouts->nSize]++;
-    }
-
-    printf( "Fanout stats: " );
-    for ( i = 0; i < 10; i++ )
-        printf( " %d=%d", i, Counter[i] );
-    printf( "\n" );
-    printf( "Area before = %4.2f.\n", Fpga_MappingArea(p) );
-
-    GainTotal = 0;
-    for ( i = 0; i < p->vAnds->nSize; i++ )
-    {
-        pNode = p->vAnds->pArray[i];
-        if ( !Fpga_NodeIsAnd( pNode ) )
-            continue;
-        if ( pNode->vFanouts == NULL )
-            continue;
-        if ( pNode->vFanouts->nSize != 2 )//&& pNode->vFanouts->nSize != 2 && pNode->vFanouts->nSize != 3 )
-            continue;
-
-        assert( pNode->nRefs > 0 );
-
-        // for all fanouts, find the best cut without this node
-        for ( k = 0; k < pNode->vFanouts->nSize; k++ )
-        {
-            pFanout = pNode->vFanouts->pArray[k];
-            ppCutsOld[k] = pFanout->pCutBest;
-            ppCutsNew[k] = Fpga_MappingAreaWithoutNode( p, pFanout, pNode );
-            if ( ppCutsNew[k] == NULL )
-                break;
-        }
-        if ( k != pNode->vFanouts->nSize )
-        {
-            printf( "Node %4d: Skipped.\n", pNode->Num );
-            continue;
-        }
-
-
-        // compute the area after replacing all the cuts
-        Gain = 0;
-        for ( k = 0; k < pNode->vFanouts->nSize; k++ )
-        {
-            pFanout = pNode->vFanouts->pArray[k];
-            // deref old cut
-            Area1 = Fpga_MatchAreaDeref( p, ppCutsOld[k] );
-            // assign new cut
-            pFanout->pCutBest = ppCutsNew[k];
-            // ref new cut
-            Area2 = Fpga_MatchAreaRef( p, ppCutsNew[k] );
-            // compute the gain
-            Gain += Area1 - Area2;
-        }
-
-        printf( "%d ", pNode->nRefs );
-
-        // undo the whole thing
-        Loss = 0;
-        for ( k = 0; k < pNode->vFanouts->nSize; k++ )
-        {
-            pFanout = pNode->vFanouts->pArray[k];
-            // deref old cut
-            Area1 = Fpga_MatchAreaDeref( p, ppCutsNew[k] );
-            // assign new cut
-            pFanout->pCutBest = ppCutsOld[k];
-            // ref new cut
-            Area2 = Fpga_MatchAreaRef( p, ppCutsOld[k] );
-            // compute the gain
-            Loss += Area2 - Area1;
-        }
-        assert( Gain == Loss );
-
-
-        printf( "Node %4d: Fanouts = %d. Cut area = %4.2f. Gain = %4.2f.\n", 
-            pNode->Num, pNode->nRefs, pNode->pCutBest->aFlow, Gain );
-
-        if ( Gain > 0 )
-            GainTotal += Gain;
-    }
-    printf( "Area after = %4.2f.\n", Fpga_MappingArea(p) );
-    printf( "AREA GAIN = %4.2f (%.2f %%)\n", GainTotal, 100.0 * GainTotal / Fpga_MappingArea(p) );
-}
-
-
-/**function*************************************************************
-
-  synopsis    [Computes the loss of area when node is not allowed.]
-
-  description [Returning FPGA_FLOAT_LARGE means it does not exist.]
-               
-  sideeffects []
-
-  seealso     []
-
-***********************************************************************/
-Fpga_Cut_t * Fpga_MappingAreaWithoutNode( Fpga_Man_t * p, Fpga_Node_t * pNode, Fpga_Node_t * pNodeNo )
-{
-    Fpga_Cut_t * pCut, * pCutBestOld, * pCutRes;
-    float aAreaCutBest;
-    int i, clk;
-    // make sure that at least one cut other than the trivial is present
-    if ( pNode->pCuts->pNext == NULL )
-    {
-        printf( "\nError: A node in the mapping graph does not have feasible cuts.\n" );
-        return 0;
-    }
-
-    assert( pNode->nRefs > 0 );
-
-    // remember the old cut
-    pCutBestOld = pNode->pCutBest;
-    // deref the old cut
-    aAreaCutBest = Fpga_MatchAreaDeref( p, pNode->pCutBest );
-
-    // search for a better cut
-    pNode->pCutBest = NULL;
-    for ( pCut = pNode->pCuts->pNext; pCut; pCut = pCut->pNext )
-    {
-        // compute the arrival time of the cut and its area flow
-clk = clock();
-        Fpga_MatchCutGetArrTime( p, pCut );
-//p->time2 += clock() - clk;
-        // drop the cut if it does not meet the required times
-        if ( pCut->tArrival > pNode->tRequired )
-            continue;
-
-        // skip the cut if it contains the no-node
-        for ( i = 0; i < pCut->nLeaves; i++ )
-            if ( pCut->ppLeaves[i] == pNodeNo )
-                break;
-        if ( i != pCut->nLeaves )
-            continue;
-
-        // get the area of this cut
-        pCut->aFlow = Fpga_MatchAreaCount( p, pCut );
-        // if no cut is assigned, use the current one
-        if ( pNode->pCutBest == NULL )
-        {
-            pNode->pCutBest = pCut;
-            continue;
-        }
-        // choose the best cut as follows: exact area first, delay as a tie-breaker
-        if ( pNode->pCutBest->aFlow >  pCut->aFlow || 
-             pNode->pCutBest->aFlow == pCut->aFlow && pNode->pCutBest->tArrival > pCut->tArrival  )
-        {
-            pNode->pCutBest = pCut;
-        }
-    }
-
-    // make sure the match is found
-    if ( pNode->pCutBest == NULL )
-    {
-        pNode->pCutBest = pCutBestOld;
-        // insert the new cut
-        pNode->pCutBest->aFlow = Fpga_MatchAreaRef( p, pNode->pCutBest );
-        return NULL;
-    }
-
-    pCutRes = pNode->pCutBest;
-    pNode->pCutBest = pCutBestOld;
-
-    // insert the new cut
-    pNode->pCutBest->aFlow = Fpga_MatchAreaRef( p, pNode->pCutBest );
-
-    // make sure the area selected is not worse then the original area
-    assert( pNode->pCutBest->aFlow == aAreaCutBest );
-    assert( pNode->tRequired < FPGA_FLOAT_LARGE );
-    return pCutRes;
-}
-
-#endif
-
-
-/**function*************************************************************
-
-  synopsis    [Performs area minimization using a heuristic algorithm.]
-
-  description []
-               
-  sideeffects []
-
-  seealso     []
-
-***********************************************************************/
-float Fpga_FindBestNode( Fpga_Man_t * p, Fpga_NodeVec_t * vNodes, Fpga_Node_t ** ppNode, Fpga_Cut_t ** ppCutBest )
-{
-    Fpga_Node_t * pNode;
-    Fpga_Cut_t * pCut;
-    float Gain, CutArea1, CutArea2, CutArea3;
-    int i;
-
-    Gain = 0;
-    for ( i = 0; i < vNodes->nSize; i++ )
-    {
-        pNode = vNodes->pArray[i];
-        // deref the current cut
-        CutArea1 = Fpga_CutDeref( p, pNode, pNode->pCutBest, 0 );
-
-        // ref all the cuts
-        for ( pCut = pNode->pCuts->pNext; pCut; pCut = pCut->pNext )
-        {
-            if ( pCut == pNode->pCutBest )
-                continue;
-            if ( pCut->tArrival > pNode->tRequired )
-                continue;
-
-            CutArea2 = Fpga_CutGetAreaDerefed( p, pCut );
-            if ( Gain < CutArea1 - CutArea2 )
-            {
-                *ppNode = pNode;
-                *ppCutBest = pCut;
-                Gain = CutArea1 - CutArea2;
-            }
-        }
-        // ref the old cut
-        CutArea3 = Fpga_CutRef( p, pNode, pNode->pCutBest, 0 );
-        assert( CutArea1 == CutArea3 );
-    }
-    if ( Gain == 0 )
-        printf( "Returning no gain.\n" );
-
-    return Gain;
-}
-
-////////////////////////////////////////////////////////////////////////
-///                       END OF FILE                                ///
-////////////////////////////////////////////////////////////////////////
diff --git a/abc70930/src/map/fpga/fpgaSwitch.c b/abc70930/src/map/fpga/fpgaSwitch.c
deleted file mode 100644
index c93e0de4..00000000
--- a/abc70930/src/map/fpga/fpgaSwitch.c
+++ /dev/null
@@ -1,151 +0,0 @@
-/**CFile****************************************************************
-
-  FileName    [fpgaSwitch.c]
-
-  PackageName [MVSIS 1.3: Multi-valued logic synthesis system.]
-
-  Synopsis    [Generic technology mapping engine.]
-
-  Author      [MVSIS Group]
-  
-  Affiliation [UC Berkeley]
-
-  Date        [Ver. 1.0. Started - September 8, 2003.]
-
-  Revision    [$Id: fpgaSwitch.h,v 1.0 2003/09/08 00:00:00 alanmi Exp $]
-
-***********************************************************************/
-
-#include "fpgaInt.h"
-
-////////////////////////////////////////////////////////////////////////
-///                        DECLARATIONS                              ///
-////////////////////////////////////////////////////////////////////////
-
-////////////////////////////////////////////////////////////////////////
-///                     FUNCTION DEFINITIONS                         ///
-////////////////////////////////////////////////////////////////////////
-
-/**function*************************************************************
-
-  synopsis    [Computes the exact area associated with the cut.]
-
-  description []
-               
-  sideeffects []
-
-  seealso     []
-
-***********************************************************************/
-float Fpga_CutGetSwitchDerefed( Fpga_Man_t * pMan, Fpga_Node_t * pNode, Fpga_Cut_t * pCut )
-{
-    float aResult, aResult2;
-    aResult2 = Fpga_CutRefSwitch( pMan, pNode, pCut, 0 );
-    aResult  = Fpga_CutDerefSwitch( pMan, pNode, pCut, 0 );
-//    assert( aResult == aResult2 );
-    return aResult;
-}
-
-/**function*************************************************************
-
-  synopsis    [References the cut.]
-
-  description [This procedure is similar to the procedure NodeReclaim.]
-               
-  sideeffects []
-
-  seealso     []
-
-***********************************************************************/
-float Fpga_CutRefSwitch( Fpga_Man_t * pMan, Fpga_Node_t * pNode, Fpga_Cut_t * pCut, int fFanouts )
-{
-    Fpga_Node_t * pNodeChild;
-    float aArea;
-    int i;
-    // start the area of this cut
-    aArea = pNode->Switching;
-    if ( pCut->nLeaves == 1 )
-        return aArea;
-    // go through the children
-    for ( i = 0; i < pCut->nLeaves; i++ )
-    {
-        pNodeChild = pCut->ppLeaves[i];
-        assert( pNodeChild->nRefs >= 0 );
-        if ( pNodeChild->nRefs++ > 0 )  
-            continue;
-        aArea += Fpga_CutRefSwitch( pMan, pNodeChild, pNodeChild->pCutBest, fFanouts );
-    }
-    return aArea;
-}
-
-/**function*************************************************************
-
-  synopsis    [Dereferences the cut.]
-
-  description [This procedure is similar to the procedure NodeRecusiveDeref.]
-               
-  sideeffects []
-
-  seealso     []
-
-***********************************************************************/
-float Fpga_CutDerefSwitch( Fpga_Man_t * pMan, Fpga_Node_t * pNode, Fpga_Cut_t * pCut, int fFanouts )
-{
-    Fpga_Node_t * pNodeChild;
-    float aArea;
-    int i;
-    // start the area of this cut
-    aArea = pNode->Switching;
-    if ( pCut->nLeaves == 1 )
-        return aArea;
-    // go through the children
-    for ( i = 0; i < pCut->nLeaves; i++ )
-    {
-        pNodeChild = pCut->ppLeaves[i];
-        assert( pNodeChild->nRefs > 0 );
-        if ( --pNodeChild->nRefs > 0 )  
-            continue;
-        aArea += Fpga_CutDerefSwitch( pMan, pNodeChild, pNodeChild->pCutBest, fFanouts );
-    }
-    return aArea;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Computes the array of mapping.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-float Fpga_MappingGetSwitching( Fpga_Man_t * pMan, Fpga_NodeVec_t * vMapping )
-{
-    Fpga_Node_t * pNode;
-    float Switch;
-    int i;
-    Switch = 0.0;
-    for ( i = 0; i < vMapping->nSize; i++ )
-    {
-        pNode = vMapping->pArray[i];
-        // at least one phase has the best cut assigned
-        assert( !Fpga_NodeIsAnd(pNode) || pNode->pCutBest != NULL );
-        // at least one phase is used in the mapping
-        assert( pNode->nRefs > 0 );
-        // compute the array due to the supergate
-        Switch += pNode->Switching;
-    }
-    // add buffer for each CO driven by a CI
-    for ( i = 0; i < pMan->nOutputs; i++ )
-        if ( Fpga_NodeIsVar(pMan->pOutputs[i]) && !Fpga_IsComplement(pMan->pOutputs[i]) )
-            Switch += pMan->pOutputs[i]->Switching;
-    return Switch;
-}
-
-////////////////////////////////////////////////////////////////////////
-///                       END OF FILE                                ///
-////////////////////////////////////////////////////////////////////////
-
-
diff --git a/abc70930/src/map/fpga/fpgaTime.c b/abc70930/src/map/fpga/fpgaTime.c
deleted file mode 100644
index 879cad4d..00000000
--- a/abc70930/src/map/fpga/fpgaTime.c
+++ /dev/null
@@ -1,262 +0,0 @@
-/**CFile****************************************************************
-
-  FileName    [fpgaTime.c]
-
-  PackageName [MVSIS 1.3: Multi-valued logic synthesis system.]
-
-  Synopsis    [Technology mapping for variable-size-LUT FPGAs.]
-
-  Author      [MVSIS Group]
-  
-  Affiliation [UC Berkeley]
-
-  Date        [Ver. 2.0. Started - August 18, 2004.]
-
-  Revision    [$Id: fpgaTime.c,v 1.1 2005/01/23 06:59:42 alanmi Exp $]
-
-***********************************************************************/
-
-#include "fpgaInt.h"
-
-////////////////////////////////////////////////////////////////////////
-///                        DECLARATIONS                              ///
-////////////////////////////////////////////////////////////////////////
-
-////////////////////////////////////////////////////////////////////////
-///                     FUNCTION DEFINITIONS                         ///
-////////////////////////////////////////////////////////////////////////
-
-/**Function*************************************************************
-
-  Synopsis    [Computes the arrival times of the cut.]
-
-  Description [Computes the maximum arrival time of the cut leaves and
-  adds the delay of the LUT.]
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-float Fpga_TimeCutComputeArrival( Fpga_Man_t * pMan, Fpga_Cut_t * pCut )
-{
-    int i;
-    float tArrival;
-    tArrival = -FPGA_FLOAT_LARGE;
-    for ( i = 0; i < pCut->nLeaves; i++ )
-        if ( tArrival < pCut->ppLeaves[i]->pCutBest->tArrival )
-            tArrival = pCut->ppLeaves[i]->pCutBest->tArrival;
-    tArrival += pMan->pLutLib->pLutDelays[pCut->nLeaves][0];
-    return tArrival;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Computes the arrival times of the cut recursively.]
-
-  Description [When computing the arrival time for the previously unused 
-  cuts, their arrival time may be incorrect because their fanins have 
-  incorrect arrival time. This procedure is called to fix this problem.]
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-float Fpga_TimeCutComputeArrival_rec( Fpga_Man_t * pMan, Fpga_Cut_t * pCut )
-{
-    int i;
-    for ( i = 0; i < pCut->nLeaves; i++ )
-        if ( pCut->ppLeaves[i]->nRefs == 0 )
-            Fpga_TimeCutComputeArrival_rec( pMan, pCut->ppLeaves[i]->pCutBest );
-    return Fpga_TimeCutComputeArrival( pMan, pCut );
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Computes the maximum arrival times.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-float Fpga_TimeComputeArrivalMax( Fpga_Man_t * p )
-{
-    float fRequired;
-    int i;
-    if ( p->fLatchPaths && p->nLatches == 0 )
-    {
-        printf( "Delay optimization of latch path is not performed because there is no latches.\n" );
-        p->fLatchPaths = 0;
-    }
-    // get the critical PO arrival time
-    fRequired = -FPGA_FLOAT_LARGE;
-    if ( p->fLatchPaths )
-    {
-        for ( i = p->nOutputs - p->nLatches; i < p->nOutputs; i++ )
-        {
-            if ( Fpga_NodeIsConst(p->pOutputs[i]) )
-                continue;
-            fRequired = FPGA_MAX( fRequired, Fpga_Regular(p->pOutputs[i])->pCutBest->tArrival );
-//            printf( " %5.1f", Fpga_Regular(p->pOutputs[i])->pCutBest->tArrival );
-        }
-//        printf( "Required latches = %5.1f\n", fRequired );
-    }
-    else
-    {
-        for ( i = 0; i < p->nOutputs; i++ )
-        {
-            if ( Fpga_NodeIsConst(p->pOutputs[i]) )
-                continue;
-            fRequired = FPGA_MAX( fRequired, Fpga_Regular(p->pOutputs[i])->pCutBest->tArrival );
-//            printf( " %5.1f", Fpga_Regular(p->pOutputs[i])->pCutBest->tArrival );
-        }
-//        printf( "Required outputs = %5.1f\n", fRequired );
-    }
-    return fRequired;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Computes the required times of all nodes.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Fpga_TimeComputeRequiredGlobal( Fpga_Man_t * p, int fFirstTime )
-{
-    p->fRequiredGlo = Fpga_TimeComputeArrivalMax( p );
-    // update the required times according to the target
-    if ( p->DelayTarget != -1 )
-    {
-        if ( p->fRequiredGlo > p->DelayTarget + p->fEpsilon )
-        {
-            if ( fFirstTime )
-                printf( "Cannot meet the target required times (%4.2f). Mapping continues anyway.\n", p->DelayTarget );
-        }
-        else if ( p->fRequiredGlo < p->DelayTarget - p->fEpsilon )
-        {
-            if ( fFirstTime )
-                printf( "Relaxing the required times from (%4.2f) to the target (%4.2f).\n", p->fRequiredGlo, p->DelayTarget );
-            p->fRequiredGlo = p->DelayTarget;
-        }
-    }
-    Fpga_TimeComputeRequired( p, p->fRequiredGlo );
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Computes the required times of all nodes.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Fpga_TimeComputeRequired( Fpga_Man_t * p, float fRequired )
-{
-    int i;
-    // clean the required times and the fanout counts for all nodes
-    for ( i = 0; i < p->vAnds->nSize; i++ )
-        p->vAnds->pArray[i]->tRequired = FPGA_FLOAT_LARGE;
-    // set the required times for the POs
-    if ( p->fLatchPaths )
-        for ( i = p->nOutputs - p->nLatches; i < p->nOutputs; i++ )
-            Fpga_Regular(p->pOutputs[i])->tRequired = fRequired;
-    else
-        for ( i = 0; i < p->nOutputs; i++ )
-            Fpga_Regular(p->pOutputs[i])->tRequired = fRequired;
-    // collect nodes reachable from POs in the DFS order through the best cuts
-    Fpga_TimePropagateRequired( p, p->vMapping );
-/*
-    {
-        int Counter = 0;
-        for ( i = 0; i < p->vAnds->nSize; i++ )
-            if ( p->vAnds->pArray[i]->tRequired > FPGA_FLOAT_LARGE - 100 )
-                Counter++;
-        printf( "The number of nodes with large required times = %d.\n", Counter );
-    }
-*/
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Computes the required times of the given nodes.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Fpga_TimePropagateRequired( Fpga_Man_t * p, Fpga_NodeVec_t * vNodes )
-{
-    Fpga_Node_t * pNode, * pChild;
-    float fRequired;
-    int i, k;
-
-    // sorts the nodes in the decreasing order of levels
-//    Fpga_MappingSortByLevel( p, vNodes, 0 );
-    // the nodes area already sorted in Fpga_MappingSetRefsAndArea()
-
-    // go through the nodes in the reverse topological order
-    for ( k = 0; k < vNodes->nSize; k++ )
-    {
-        pNode = vNodes->pArray[k];
-        if ( !Fpga_NodeIsAnd(pNode) )
-            continue;
-        // get the required time for children
-        fRequired = pNode->tRequired - p->pLutLib->pLutDelays[pNode->pCutBest->nLeaves][0];
-        // update the required time of the children
-        for ( i = 0; i < pNode->pCutBest->nLeaves; i++ )
-        {
-            pChild = pNode->pCutBest->ppLeaves[i];
-            pChild->tRequired = FPGA_MIN( pChild->tRequired, fRequired );
-        }
-    }
-}
-
-
-
-/**Function*************************************************************
-
-  Synopsis    [Computes the required times of all nodes.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Fpga_TimePropagateArrival( Fpga_Man_t * p )
-{
-    Fpga_Node_t * pNode;
-    Fpga_Cut_t * pCut;
-    int i;
-
-    // clean the required times and the fanout counts for all nodes
-    for ( i = 0; i < p->vAnds->nSize; i++ )
-    {
-        pNode = p->vAnds->pArray[i];
-        for ( pCut = pNode->pCuts->pNext; pCut; pCut = pCut->pNext )
-            pCut->tArrival = Fpga_TimeCutComputeArrival( p, pCut );
-    }
-}
-
-
-////////////////////////////////////////////////////////////////////////
-///                       END OF FILE                                ///
-////////////////////////////////////////////////////////////////////////
-
-
diff --git a/abc70930/src/map/fpga/fpgaTruth.c b/abc70930/src/map/fpga/fpgaTruth.c
deleted file mode 100644
index e3eb487f..00000000
--- a/abc70930/src/map/fpga/fpgaTruth.c
+++ /dev/null
@@ -1,166 +0,0 @@
-/**CFile****************************************************************
-
-  FileName    [fpgaTruth.c]
-
-  PackageName [MVSIS 1.3: Multi-valued logic synthesis system.]
-
-  Synopsis    [Technology mapping for variable-size-LUT FPGAs.]
-
-  Author      [MVSIS Group]
-  
-  Affiliation [UC Berkeley]
-
-  Date        [Ver. 2.0. Started - August 18, 2004.]
-
-  Revision    [$Id: fpgaTruth.c,v 1.4 2005/01/23 06:59:42 alanmi Exp $]
-
-***********************************************************************/
-
-#include "fpgaInt.h"
-#include "cudd.h"
-
-////////////////////////////////////////////////////////////////////////
-///                        DECLARATIONS                              ///
-////////////////////////////////////////////////////////////////////////
-
-////////////////////////////////////////////////////////////////////////
-///                     FUNCTION DEFINITIONS                         ///
-////////////////////////////////////////////////////////////////////////
-
-/**Function*************************************************************
-
-  Synopsis    [Recursively derives the truth table for the cut.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-DdNode * Fpga_TruthsCutBdd_rec( DdManager * dd, Fpga_Cut_t * pCut, Fpga_NodeVec_t * vVisited )
-{
-    DdNode * bFunc, * bFunc0, * bFunc1;
-    assert( !Fpga_IsComplement(pCut) );
-    // if the cut is visited, return the result
-    if ( pCut->uSign )
-        return (DdNode *)pCut->uSign;
-    // compute the functions of the children
-    bFunc0 = Fpga_TruthsCutBdd_rec( dd, Fpga_CutRegular(pCut->pOne), vVisited );   Cudd_Ref( bFunc0 );
-    bFunc0 = Cudd_NotCond( bFunc0, Fpga_CutIsComplement(pCut->pOne) );
-    bFunc1 = Fpga_TruthsCutBdd_rec( dd, Fpga_CutRegular(pCut->pTwo), vVisited );   Cudd_Ref( bFunc1 );
-    bFunc1 = Cudd_NotCond( bFunc1, Fpga_CutIsComplement(pCut->pTwo) );
-    // get the function of the cut
-    bFunc  = Cudd_bddAnd( dd, bFunc0, bFunc1 );   Cudd_Ref( bFunc );
-    bFunc  = Cudd_NotCond( bFunc, pCut->Phase );
-    Cudd_RecursiveDeref( dd, bFunc0 );
-    Cudd_RecursiveDeref( dd, bFunc1 );
-    assert( pCut->uSign == 0 );
-    pCut->uSign = (unsigned)bFunc;
-    // add this cut to the visited list
-    Fpga_NodeVecPush( vVisited, (Fpga_Node_t *)pCut );
-    return bFunc;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Derives the truth table for one cut.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void * Fpga_TruthsCutBdd( void * dd, Fpga_Cut_t * pCut )
-{
-    Fpga_NodeVec_t * vVisited;
-    DdNode * bFunc;
-    int i;
-    assert( pCut->nLeaves > 1 );
-    // set the leaf variables
-    for ( i = 0; i < pCut->nLeaves; i++ )
-        pCut->ppLeaves[i]->pCuts->uSign = (unsigned)Cudd_bddIthVar( dd, i );
-    // recursively compute the function
-    vVisited = Fpga_NodeVecAlloc( 10 );
-    bFunc = Fpga_TruthsCutBdd_rec( dd, pCut, vVisited );   Cudd_Ref( bFunc );
-    // clean the intermediate BDDs
-    for ( i = 0; i < pCut->nLeaves; i++ )
-        pCut->ppLeaves[i]->pCuts->uSign = 0;
-    for ( i = 0; i < vVisited->nSize; i++ )
-    {
-        pCut = (Fpga_Cut_t *)vVisited->pArray[i];
-        Cudd_RecursiveDeref( dd, (DdNode*)pCut->uSign );
-        pCut->uSign = 0;
-    }
-//    printf( "%d ", vVisited->nSize );
-    Fpga_NodeVecFree( vVisited );
-    Cudd_Deref( bFunc );
-    return bFunc;
-}
-
-
-/**Function*************************************************************
-
-  Synopsis    [Recursively derives the truth table for the cut.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Fpga_CutVolume_rec( Fpga_Cut_t * pCut, Fpga_NodeVec_t * vVisited )
-{
-    assert( !Fpga_IsComplement(pCut) );
-    if ( pCut->fMark )
-        return;
-    pCut->fMark = 1;
-    Fpga_CutVolume_rec( Fpga_CutRegular(pCut->pOne), vVisited );
-    Fpga_CutVolume_rec( Fpga_CutRegular(pCut->pTwo), vVisited );
-    Fpga_NodeVecPush( vVisited, (Fpga_Node_t *)pCut );
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Derives the truth table for one cut.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Fpga_CutVolume( Fpga_Cut_t * pCut )
-{
-    Fpga_NodeVec_t * vVisited;
-    int Volume, i;
-    assert( pCut->nLeaves > 1 );
-    // set the leaf variables
-    for ( i = 0; i < pCut->nLeaves; i++ )
-        pCut->ppLeaves[i]->pCuts->fMark = 1;
-    // recursively compute the function
-    vVisited = Fpga_NodeVecAlloc( 10 );
-    Fpga_CutVolume_rec( pCut, vVisited ); 
-    // clean the marks
-    for ( i = 0; i < pCut->nLeaves; i++ )
-        pCut->ppLeaves[i]->pCuts->fMark = 0;
-    for ( i = 0; i < vVisited->nSize; i++ )
-    {
-        pCut = (Fpga_Cut_t *)vVisited->pArray[i];
-        pCut->fMark = 0;
-    }
-    Volume = vVisited->nSize;
-    printf( "%d ", Volume );
-    Fpga_NodeVecFree( vVisited );
-    return Volume;
-}
-
-////////////////////////////////////////////////////////////////////////
-///                       END OF FILE                                ///
-////////////////////////////////////////////////////////////////////////
-
-
diff --git a/abc70930/src/map/fpga/fpgaUtils.c b/abc70930/src/map/fpga/fpgaUtils.c
deleted file mode 100644
index b951fd8f..00000000
--- a/abc70930/src/map/fpga/fpgaUtils.c
+++ /dev/null
@@ -1,986 +0,0 @@
-/**CFile****************************************************************
-
-  FileName    [fpgaUtils.c]
-
-  PackageName [MVSIS 1.3: Multi-valued logic synthesis system.]
-
-  Synopsis    [Technology mapping for variable-size-LUT FPGAs.]
-
-  Author      [MVSIS Group]
-  
-  Affiliation [UC Berkeley]
-
-  Date        [Ver. 2.0. Started - August 18, 2004.]
-
-  Revision    [$Id: fpgaUtils.c,v 1.3 2004/07/06 04:55:58 alanmi Exp $]
-
-***********************************************************************/
-
-#include "fpgaInt.h"
-
-////////////////////////////////////////////////////////////////////////
-///                        DECLARATIONS                              ///
-////////////////////////////////////////////////////////////////////////
-
-#define FPGA_CO_LIST_SIZE  5
-
-static void  Fpga_MappingDfs_rec( Fpga_Node_t * pNode, Fpga_NodeVec_t * vNodes, int fCollectEquiv );
-static void  Fpga_MappingDfsCuts_rec( Fpga_Node_t * pNode, Fpga_NodeVec_t * vNodes );
-static int   Fpga_MappingCompareOutputDelay( Fpga_Node_t ** ppNode1, Fpga_Node_t ** ppNode2 );
-static void  Fpga_MappingFindLatest( Fpga_Man_t * p, int * pNodes, int nNodesMax );
-static void  Fpga_DfsLim_rec( Fpga_Node_t * pNode, int Level, Fpga_NodeVec_t * vNodes );
-static int   Fpga_CollectNodeTfo_rec( Fpga_Node_t * pNode, Fpga_Node_t * pPivot, Fpga_NodeVec_t * vVisited, Fpga_NodeVec_t * vTfo );
-static Fpga_NodeVec_t * Fpga_MappingOrderCosByLevel( Fpga_Man_t * pMan );
-static Fpga_Man_t * s_pMan = NULL;
-
-////////////////////////////////////////////////////////////////////////
-///                     FUNCTION DEFINITIONS                         ///
-////////////////////////////////////////////////////////////////////////
-
-
-/**Function*************************************************************
-
-  Synopsis    [Computes the DFS ordering of the nodes.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-Fpga_NodeVec_t * Fpga_MappingDfs( Fpga_Man_t * pMan, int fCollectEquiv )
-{
-    Fpga_NodeVec_t * vNodes;//, * vNodesCo;
-    Fpga_Node_t * pNode;
-    int i;
-    // collect the CO nodes by level
-//    vNodesCo = Fpga_MappingOrderCosByLevel( pMan );
-    // start the array
-    vNodes = Fpga_NodeVecAlloc( 100 );
-    // collect the PIs
-    for ( i = 0; i < pMan->nInputs; i++ )
-    {
-        pNode = pMan->pInputs[i];
-        Fpga_NodeVecPush( vNodes, pNode );
-        pNode->fMark0 = 1;
-    }
-    // perform the traversal
-    for ( i = 0; i < pMan->nOutputs; i++ )
-        Fpga_MappingDfs_rec( Fpga_Regular(pMan->pOutputs[i]), vNodes, fCollectEquiv );
-//    for ( i = vNodesCo->nSize - 1; i >= 0 ; i-- )
-//        for ( pNode = vNodesCo->pArray[i]; pNode; pNode = (Fpga_Node_t *)pNode->pData0 )
-//            Fpga_MappingDfs_rec( pNode, vNodes, fCollectEquiv );
-    // clean the node marks
-    for ( i = 0; i < vNodes->nSize; i++ )
-        vNodes->pArray[i]->fMark0 = 0;
-//    for ( i = 0; i < pMan->nOutputs; i++ )
-//        Fpga_MappingUnmark_rec( Fpga_Regular(pMan->pOutputs[i]) );
-//    Fpga_NodeVecFree( vNodesCo );
-    return vNodes;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Recursively computes the DFS ordering of the nodes.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Fpga_MappingDfs_rec( Fpga_Node_t * pNode, Fpga_NodeVec_t * vNodes, int fCollectEquiv )
-{
-    assert( !Fpga_IsComplement(pNode) );
-    if ( pNode->fMark0 )
-        return;
-    // visit the transitive fanin
-    if ( Fpga_NodeIsAnd(pNode) )
-    {
-        Fpga_MappingDfs_rec( Fpga_Regular(pNode->p1), vNodes, fCollectEquiv );
-        Fpga_MappingDfs_rec( Fpga_Regular(pNode->p2), vNodes, fCollectEquiv );
-    }
-    // visit the equivalent nodes
-    if ( fCollectEquiv && pNode->pNextE )
-        Fpga_MappingDfs_rec( pNode->pNextE, vNodes, fCollectEquiv );
-    // make sure the node is not visited through the equivalent nodes
-    assert( pNode->fMark0 == 0 );
-    // mark the node as visited
-    pNode->fMark0 = 1;
-    // add the node to the list
-    Fpga_NodeVecPush( vNodes, pNode );
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Computes the DFS ordering of the nodes.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-Fpga_NodeVec_t * Fpga_MappingDfsNodes( Fpga_Man_t * pMan, Fpga_Node_t ** ppNodes, int nNodes, int fEquiv )
-{
-    Fpga_NodeVec_t * vNodes;
-    int i;
-    // perform the traversal
-    vNodes = Fpga_NodeVecAlloc( 200 );
-    for ( i = 0; i < nNodes; i++ )
-        Fpga_MappingDfs_rec( ppNodes[i], vNodes, fEquiv );
-    for ( i = 0; i < vNodes->nSize; i++ )
-        vNodes->pArray[i]->fMark0 = 0;
-    return vNodes;
-}
-
-/**Function*************************************************************
-
-  Synopsis    []
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-float Fpga_MappingGetAreaFlow( Fpga_Man_t * p )
-{
-    float aFlowFlowTotal = 0;
-    int i;
-    for ( i = 0; i < p->nOutputs; i++ )
-    {
-        if ( Fpga_NodeIsConst(p->pOutputs[i]) )
-            continue;
-        aFlowFlowTotal += Fpga_Regular(p->pOutputs[i])->pCutBest->aFlow;
-    }
-    return aFlowFlowTotal;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Computes the area of the current mapping.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-float Fpga_MappingArea( Fpga_Man_t * pMan )
-{
-    Fpga_Node_t * pNode;
-    float aTotal;
-    int i;
-    // perform the traversal
-    aTotal = 0;
-    for ( i = 0; i < pMan->vMapping->nSize; i++ )
-    {
-        pNode = pMan->vMapping->pArray[i];
-        aTotal += pMan->pLutLib->pLutAreas[pNode->pCutBest->nLeaves];
-    }
-    return aTotal;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Recursively computes the DFS ordering of the nodes.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-float Fpga_MappingArea_rec( Fpga_Man_t * pMan, Fpga_Node_t * pNode, Fpga_NodeVec_t * vNodes )
-{
-    float aArea;
-    int i;
-    assert( !Fpga_IsComplement(pNode) );
-    if ( !Fpga_NodeIsAnd(pNode) )
-        return 0;
-    if ( pNode->fMark0 )
-        return 0;
-    assert( pNode->pCutBest != NULL );
-    // visit the transitive fanin of the selected cut
-    aArea = 0;
-    for ( i = 0; i < pNode->pCutBest->nLeaves; i++ )
-        aArea += Fpga_MappingArea_rec( pMan, pNode->pCutBest->ppLeaves[i], vNodes );
-    // make sure the node is not visited through the fanin nodes
-    assert( pNode->fMark0 == 0 );
-    // mark the node as visited
-    pNode->fMark0 = 1;
-    // add the node to the list
-    aArea += pMan->pLutLib->pLutAreas[pNode->pCutBest->nLeaves];
-    // add the node to the list
-    Fpga_NodeVecPush( vNodes, pNode );
-    return aArea;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Computes the area of the current mapping.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-float Fpga_MappingAreaTrav( Fpga_Man_t * pMan )
-{
-    Fpga_NodeVec_t * vNodes;
-    float aTotal;
-    int i;
-    // perform the traversal
-    aTotal = 0;
-    vNodes = Fpga_NodeVecAlloc( 100 );
-    for ( i = 0; i < pMan->nOutputs; i++ )
-        aTotal += Fpga_MappingArea_rec( pMan, Fpga_Regular(pMan->pOutputs[i]), vNodes );
-    for ( i = 0; i < vNodes->nSize; i++ )
-        vNodes->pArray[i]->fMark0 = 0;
-    Fpga_NodeVecFree( vNodes );
-    return aTotal;
-}
-
-
-/**Function*************************************************************
-
-  Synopsis    [Recursively computes the DFS ordering of the nodes.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-float Fpga_MappingSetRefsAndArea_rec( Fpga_Man_t * pMan, Fpga_Node_t * pNode, Fpga_Node_t ** ppStore )
-{
-    float aArea;
-    int i;
-    assert( !Fpga_IsComplement(pNode) );
-    if ( pNode->nRefs++ )
-        return 0;
-    if ( !Fpga_NodeIsAnd(pNode) )
-        return 0;
-    assert( pNode->pCutBest != NULL );
-    // store the node in the structure by level
-    pNode->pData0 = (char *)ppStore[pNode->Level]; 
-    ppStore[pNode->Level] = pNode;
-    // visit the transitive fanin of the selected cut
-    aArea = pMan->pLutLib->pLutAreas[pNode->pCutBest->nLeaves];
-    for ( i = 0; i < pNode->pCutBest->nLeaves; i++ )
-        aArea += Fpga_MappingSetRefsAndArea_rec( pMan, pNode->pCutBest->ppLeaves[i], ppStore );
-    return aArea;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Sets the correct reference counts for the mapping.]
-
-  Description [Collects the nodes in reverse topological order
-  and places in them in array pMan->vMapping.]
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-float Fpga_MappingSetRefsAndArea( Fpga_Man_t * pMan )
-{
-    Fpga_Node_t * pNode, ** ppStore;
-    float aArea;
-    int i, LevelMax;
-
-    // clean all references
-    for ( i = 0; i < pMan->vNodesAll->nSize; i++ )
-        pMan->vNodesAll->pArray[i]->nRefs = 0;
-
-    // allocate place to store the nodes
-    LevelMax = Fpga_MappingMaxLevel( pMan );
-    ppStore = ALLOC( Fpga_Node_t *, LevelMax + 1 );
-    memset( ppStore, 0, sizeof(Fpga_Node_t *) * (LevelMax + 1) );
-
-    // collect nodes reachable from POs in the DFS order through the best cuts
-    aArea = 0;
-    for ( i = 0; i < pMan->nOutputs; i++ )
-    {
-        pNode = Fpga_Regular(pMan->pOutputs[i]);
-        if ( pNode == pMan->pConst1 )
-            continue;
-        aArea += Fpga_MappingSetRefsAndArea_rec( pMan, pNode, ppStore );
-        pNode->nRefs++;
-    }
-
-    // reconnect the nodes in reverse topological order
-    pMan->vMapping->nSize = 0;
-    for ( i = LevelMax; i >= 0; i-- )
-        for ( pNode = ppStore[i]; pNode; pNode = (Fpga_Node_t *)pNode->pData0 )
-            Fpga_NodeVecPush( pMan->vMapping, pNode );
-    free( ppStore );
-    return aArea;
-}
-
-
-/**Function*************************************************************
-
-  Synopsis    [Compares the outputs by their arrival times.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Fpga_MappingCompareOutputDelay( Fpga_Node_t ** ppNode1, Fpga_Node_t ** ppNode2 )
-{
-    Fpga_Node_t * pNode1 = Fpga_Regular(*ppNode1);
-    Fpga_Node_t * pNode2 = Fpga_Regular(*ppNode2);
-    float Arrival1 = pNode1->pCutBest? pNode1->pCutBest->tArrival : 0;
-    float Arrival2 = pNode2->pCutBest? pNode2->pCutBest->tArrival : 0;
-    if ( Arrival1 < Arrival2 )
-        return -1;
-    if ( Arrival1 > Arrival2 )
-        return 1;
-    return 0;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Finds given number of latest arriving COs.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Fpga_MappingFindLatest( Fpga_Man_t * p, int * pNodes, int nNodesMax )
-{
-    int nNodes, i, k, v;
-    assert( p->nOutputs >= nNodesMax );
-    pNodes[0] = 0;
-    nNodes = 1;
-    for ( i = 1; i < p->nOutputs; i++ )
-    {
-        for ( k = nNodes - 1; k >= 0; k-- )
-            if ( Fpga_MappingCompareOutputDelay( &p->pOutputs[pNodes[k]], &p->pOutputs[i] ) >= 0 )
-                break;
-        if ( k == nNodesMax - 1 )
-            continue;
-        if ( nNodes < nNodesMax )
-            nNodes++;
-        for ( v = nNodes - 1; v > k+1; v-- )
-            pNodes[v] = pNodes[v-1];
-        pNodes[k+1] = i;
-    }
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Prints a bunch of latest arriving outputs.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Fpga_MappingPrintOutputArrivals( Fpga_Man_t * p )
-{
-    Fpga_Node_t * pNode;
-    int pSorted[FPGA_CO_LIST_SIZE];
-    int fCompl, Limit, MaxNameSize, i;
-
-    // determine the number of nodes to print
-    Limit = (p->nOutputs > FPGA_CO_LIST_SIZE)? FPGA_CO_LIST_SIZE : p->nOutputs;
-
-    // determine the order
-    Fpga_MappingFindLatest( p, pSorted, Limit );
-
-    // determine max size of the node's name
-    MaxNameSize = 0;
-    for ( i = 0; i < Limit; i++ )
-        if ( MaxNameSize < (int)strlen(p->ppOutputNames[pSorted[i]]) )
-            MaxNameSize = strlen(p->ppOutputNames[pSorted[i]]);
-
-    // print the latest outputs
-    for ( i = 0; i < Limit; i++ )
-    {
-        // get the i-th latest output
-        pNode  = Fpga_Regular(p->pOutputs[pSorted[i]]);
-        fCompl = Fpga_IsComplement(p->pOutputs[pSorted[i]]);
-        // print out the best arrival time
-        printf( "Output  %-*s : ", MaxNameSize + 3, p->ppOutputNames[pSorted[i]] );
-        printf( "Delay = %8.2f  ",     (double)pNode->pCutBest->tArrival );
-        if ( fCompl )
-            printf( "NEG" );
-        else
-            printf( "POS" );
-        printf( "\n" );
-    }
-}
-
-
-/**Function*************************************************************
-
-  Synopsis    [Sets up the truth tables.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Fpga_MappingSetupTruthTables( unsigned uTruths[][2] )
-{
-    int m, v;
-    // set up the truth tables
-    for ( m = 0; m < 32; m++ )
-        for ( v = 0; v < 5; v++ )
-            if ( m & (1 << v) )
-                uTruths[v][0] |= (1 << m);
-    // make adjustments for the case of 6 variables
-    for ( v = 0; v < 5; v++ )
-        uTruths[v][1] = uTruths[v][0];
-    uTruths[5][0] = 0;
-    uTruths[5][1] = FPGA_FULL;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Sets up the mask.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Fpga_MappingSetupMask( unsigned uMask[], int nVarsMax )
-{
-    if ( nVarsMax == 6 )
-        uMask[0] = uMask[1] = FPGA_FULL;
-    else
-    {
-        uMask[0] = FPGA_MASK(1 << nVarsMax);
-        uMask[1] = 0;
-    }
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Verify one useful property.]
-
-  Description [This procedure verifies one useful property. After 
-  the FRAIG construction with choice nodes is over, each primary node 
-  should have fanins that are primary nodes. The primary nodes is the 
-  one that does not have pNode->pRepr set to point to another node.]
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Fpga_ManCheckConsistency( Fpga_Man_t * p )
-{
-    Fpga_Node_t * pNode;
-    Fpga_NodeVec_t * pVec;
-    int i;
-    pVec = Fpga_MappingDfs( p, 0 );
-    for ( i = 0; i < pVec->nSize; i++ )
-    {
-        pNode = pVec->pArray[i];
-        if ( Fpga_NodeIsVar(pNode) )
-        {
-            if ( pNode->pRepr )
-                printf( "Primary input %d is a secondary node.\n", pNode->Num );
-        }
-        else if ( Fpga_NodeIsConst(pNode) )
-        {
-            if ( pNode->pRepr )
-                printf( "Constant 1 %d is a secondary node.\n", pNode->Num );
-        }
-        else
-        {
-            if ( pNode->pRepr )
-                printf( "Internal node %d is a secondary node.\n", pNode->Num );
-            if ( Fpga_Regular(pNode->p1)->pRepr )
-                printf( "Internal node %d has first fanin that is a secondary node.\n", pNode->Num );
-            if ( Fpga_Regular(pNode->p2)->pRepr )
-                printf( "Internal node %d has second fanin that is a secondary node.\n", pNode->Num );
-        }
-    }
-    Fpga_NodeVecFree( pVec );
-    return 1;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Compares the supergates by their level.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Fpga_CompareNodesByLevelDecreasing( Fpga_Node_t ** ppS1, Fpga_Node_t ** ppS2 )
-{
-    if ( Fpga_Regular(*ppS1)->Level > Fpga_Regular(*ppS2)->Level )
-        return -1;
-    if ( Fpga_Regular(*ppS1)->Level < Fpga_Regular(*ppS2)->Level )
-        return 1;
-    return 0;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Compares the supergates by their level.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Fpga_CompareNodesByLevelIncreasing( Fpga_Node_t ** ppS1, Fpga_Node_t ** ppS2 )
-{
-    if ( Fpga_Regular(*ppS1)->Level < Fpga_Regular(*ppS2)->Level )
-        return -1;
-    if ( Fpga_Regular(*ppS1)->Level > Fpga_Regular(*ppS2)->Level )
-        return 1;
-    return 0;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Orders the nodes in the decreasing order of levels.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Fpga_MappingSortByLevel( Fpga_Man_t * pMan, Fpga_NodeVec_t * vNodes, int fIncreasing )
-{
-    if ( fIncreasing )
-        qsort( (void *)vNodes->pArray, vNodes->nSize, sizeof(Fpga_Node_t *), 
-                (int (*)(const void *, const void *)) Fpga_CompareNodesByLevelIncreasing );
-    else
-        qsort( (void *)vNodes->pArray, vNodes->nSize, sizeof(Fpga_Node_t *), 
-                (int (*)(const void *, const void *)) Fpga_CompareNodesByLevelDecreasing );
-//    assert( Fpga_CompareNodesByLevel( vNodes->pArray, vNodes->pArray + vNodes->nSize - 1 ) <= 0 );
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Computes the limited DFS ordering for one node.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-Fpga_NodeVec_t * Fpga_DfsLim( Fpga_Man_t * pMan, Fpga_Node_t * pNode, int nLevels )
-{
-    Fpga_NodeVec_t * vNodes;
-    int i;
-    // perform the traversal
-    vNodes = Fpga_NodeVecAlloc( 100 );
-    Fpga_DfsLim_rec( pNode, nLevels, vNodes );
-    for ( i = 0; i < vNodes->nSize; i++ )
-        vNodes->pArray[i]->fMark0 = 0;
-    return vNodes;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Recursively computes the DFS ordering of the nodes.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Fpga_DfsLim_rec( Fpga_Node_t * pNode, int Level, Fpga_NodeVec_t * vNodes )
-{
-    assert( !Fpga_IsComplement(pNode) );
-    if ( pNode->fMark0 )
-        return;
-    pNode->fMark0 = 1;
-    // visit the transitive fanin
-    Level--;
-    if ( Level > 0 && Fpga_NodeIsAnd(pNode) )
-    {
-        Fpga_DfsLim_rec( Fpga_Regular(pNode->p1), Level, vNodes );
-        Fpga_DfsLim_rec( Fpga_Regular(pNode->p2), Level, vNodes );
-    }
-    // add the node to the list
-    Fpga_NodeVecPush( vNodes, pNode );
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Computes the limited DFS ordering for one node.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Fpga_ManCleanData0( Fpga_Man_t * pMan )
-{
-    int i;
-    for ( i = 0; i < pMan->vNodesAll->nSize; i++ )
-        pMan->vNodesAll->pArray[i]->pData0 = 0;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Collects the TFO of the node.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-Fpga_NodeVec_t * Fpga_CollectNodeTfo( Fpga_Man_t * pMan, Fpga_Node_t * pNode )
-{
-    Fpga_NodeVec_t * vVisited, * vTfo;
-    int i;
-    // perform the traversal
-    vVisited = Fpga_NodeVecAlloc( 100 );
-    vTfo     = Fpga_NodeVecAlloc( 100 );
-    for ( i = 0; i < pMan->nOutputs; i++ )
-        Fpga_CollectNodeTfo_rec( Fpga_Regular(pMan->pOutputs[i]), pNode, vVisited, vTfo );
-    for ( i = 0; i < vVisited->nSize; i++ )
-        vVisited->pArray[i]->fMark0 = vVisited->pArray[i]->fMark1 = 0;
-    Fpga_NodeVecFree( vVisited );
-    return vTfo;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Collects the TFO of the node.]
-
-  Description [Returns 1 if the node should be collected.]
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Fpga_CollectNodeTfo_rec( Fpga_Node_t * pNode, Fpga_Node_t * pPivot, Fpga_NodeVec_t * vVisited, Fpga_NodeVec_t * vTfo )
-{
-    int Ret1, Ret2;
-    assert( !Fpga_IsComplement(pNode) );
-    // skip visited nodes
-    if ( pNode->fMark0 )
-        return pNode->fMark1;
-    pNode->fMark0 = 1;
-    Fpga_NodeVecPush( vVisited, pNode );
-
-    // return the pivot node
-    if ( pNode == pPivot )
-    {
-        pNode->fMark1 = 1;
-        return 1;
-    }
-    if ( pNode->Level < pPivot->Level )
-    {
-        pNode->fMark1 = 0;
-        return 0;
-    }
-    // visit the transitive fanin
-    assert( Fpga_NodeIsAnd(pNode) );
-    Ret1 = Fpga_CollectNodeTfo_rec( Fpga_Regular(pNode->p1), pPivot, vVisited, vTfo );
-    Ret2 = Fpga_CollectNodeTfo_rec( Fpga_Regular(pNode->p2), pPivot, vVisited, vTfo );
-    if ( Ret1 || Ret2 )
-    {
-        pNode->fMark1 = 1;
-        Fpga_NodeVecPush( vTfo, pNode );
-    }
-    else
-        pNode->fMark1 = 0;
-    return pNode->fMark1;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Levelizes the nodes accessible from the POs.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-Fpga_NodeVec_t * Fpga_MappingLevelize( Fpga_Man_t * pMan, Fpga_NodeVec_t * vNodes )
-{
-    Fpga_NodeVec_t * vLevels;
-    Fpga_Node_t ** ppNodes;
-    Fpga_Node_t * pNode;
-    int nNodes, nLevelsMax, i;
-
-    // reassign the levels (this may be necessary for networks which choices)
-    ppNodes = vNodes->pArray;
-    nNodes  = vNodes->nSize;
-    for ( i = 0; i < nNodes; i++ )
-    {
-        pNode = ppNodes[i];
-        if ( !Fpga_NodeIsAnd(pNode) )
-        {
-            pNode->Level = 0;
-            continue;
-        }
-        pNode->Level = 1 + FPGA_MAX( Fpga_Regular(pNode->p1)->Level, Fpga_Regular(pNode->p2)->Level );
-    }
-
-    // get the max levels
-    nLevelsMax = 0;
-    for ( i = 0; i < pMan->nOutputs; i++ )
-        nLevelsMax = FPGA_MAX( nLevelsMax, (int)Fpga_Regular(pMan->pOutputs[i])->Level );
-    nLevelsMax++;
-
-    // allocate storage for levels
-    vLevels = Fpga_NodeVecAlloc( nLevelsMax );
-    for ( i = 0; i < nLevelsMax; i++ )
-        Fpga_NodeVecPush( vLevels, NULL );
-
-    // go through the nodes and add them to the levels
-    for ( i = 0; i < nNodes; i++ )
-    {
-        pNode = ppNodes[i];
-        pNode->pLevel = NULL;
-        if ( !Fpga_NodeIsAnd(pNode) )
-            continue;
-        // attach the node to this level
-        pNode->pLevel = Fpga_NodeVecReadEntry( vLevels, pNode->Level );
-        Fpga_NodeVecWriteEntry( vLevels, pNode->Level, pNode );
-    }
-    return vLevels;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Sets up the mask.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Fpga_MappingMaxLevel( Fpga_Man_t * pMan )
-{
-    int nLevelMax, i;
-    nLevelMax = 0;
-    for ( i = 0; i < pMan->nOutputs; i++ )
-        nLevelMax = nLevelMax > (int)Fpga_Regular(pMan->pOutputs[i])->Level? 
-                nLevelMax : (int)Fpga_Regular(pMan->pOutputs[i])->Level;
-    return nLevelMax;
-}
-
-
-/**Function*************************************************************
-
-  Synopsis    [Analyses choice nodes.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Fpga_MappingUpdateLevel_rec( Fpga_Man_t * pMan, Fpga_Node_t * pNode, int fMaximum )
-{
-    Fpga_Node_t * pTemp;
-    int Level1, Level2, LevelE;
-    assert( !Fpga_IsComplement(pNode) );
-    if ( !Fpga_NodeIsAnd(pNode) )
-        return pNode->Level;
-    // skip the visited node
-    if ( pNode->TravId == pMan->nTravIds )
-        return pNode->Level;
-    pNode->TravId = pMan->nTravIds;
-    // compute levels of the children nodes
-    Level1 = Fpga_MappingUpdateLevel_rec( pMan, Fpga_Regular(pNode->p1), fMaximum );
-    Level2 = Fpga_MappingUpdateLevel_rec( pMan, Fpga_Regular(pNode->p2), fMaximum );
-    pNode->Level = 1 + FPGA_MAX( Level1, Level2 );
-    if ( pNode->pNextE )
-    {
-        LevelE = Fpga_MappingUpdateLevel_rec( pMan, pNode->pNextE, fMaximum );
-        if ( fMaximum )
-        {
-            if ( pNode->Level < (unsigned)LevelE )
-                pNode->Level = LevelE;
-        }
-        else
-        {
-            if ( pNode->Level > (unsigned)LevelE )
-                pNode->Level = LevelE;
-        }
-        // set the level of all equivalent nodes to be the same minimum
-        if ( pNode->pRepr == NULL ) // the primary node
-            for ( pTemp = pNode->pNextE; pTemp; pTemp = pTemp->pNextE )
-                pTemp->Level = pNode->Level;
-    }
-    return pNode->Level;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Resets the levels of the nodes in the choice graph.]
-
-  Description [Makes the level of the choice nodes to be equal to the
-  maximum of the level of the nodes in the equivalence class. This way
-  sorting by level leads to the reverse topological order, which is
-  needed for the required time computation.]
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Fpga_MappingSetChoiceLevels( Fpga_Man_t * pMan )
-{
-    int i;
-    pMan->nTravIds++;
-    for ( i = 0; i < pMan->nOutputs; i++ )
-        Fpga_MappingUpdateLevel_rec( pMan, Fpga_Regular(pMan->pOutputs[i]), 1 );
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Reports statistics on choice nodes.]
-
-  Description [The number of choice nodes is the number of primary nodes,
-  which has pNextE set to a pointer. The number of choices is the number
-  of entries in the equivalent-node lists of the primary nodes.]
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Fpga_ManReportChoices( Fpga_Man_t * pMan )
-{
-    Fpga_Node_t * pNode, * pTemp;
-    int nChoiceNodes, nChoices;
-    int i, LevelMax1, LevelMax2;
-
-    // report the number of levels
-    LevelMax1 = Fpga_MappingMaxLevel( pMan );
-    pMan->nTravIds++;
-    for ( i = 0; i < pMan->nOutputs; i++ )
-        Fpga_MappingUpdateLevel_rec( pMan, Fpga_Regular(pMan->pOutputs[i]), 0 );
-    LevelMax2 = Fpga_MappingMaxLevel( pMan );
-
-    // report statistics about choices
-    nChoiceNodes = nChoices = 0;
-    for ( i = 0; i < pMan->vAnds->nSize; i++ )
-    {
-        pNode = pMan->vAnds->pArray[i];
-        if ( pNode->pRepr == NULL && pNode->pNextE != NULL )
-        { // this is a choice node = the primary node that has equivalent nodes
-            nChoiceNodes++;
-            for ( pTemp = pNode; pTemp; pTemp = pTemp->pNextE )
-                nChoices++;
-        }
-    }
-    if ( pMan->fVerbose )
-    {
-    printf( "Maximum level: Original = %d. Reduced due to choices = %d.\n", LevelMax1, LevelMax2 );
-    printf( "Choice stats:  Choice nodes = %d. Total choices = %d.\n", nChoiceNodes, nChoices );
-    }
-/*
-    {
-        FILE * pTable;
-        pTable = fopen( "stats_choice.txt", "a+" );
-        fprintf( pTable, "%s ", pMan->pFileName );
-        fprintf( pTable, "%4d ", LevelMax1 );
-        fprintf( pTable, "%4d ", pMan->vAnds->nSize - pMan->nInputs );
-        fprintf( pTable, "%4d ", LevelMax2 );
-        fprintf( pTable, "%7d ", nChoiceNodes );
-        fprintf( pTable, "%7d ", nChoices + nChoiceNodes );
-        fprintf( pTable, "\n" );
-        fclose( pTable );
-    }
-*/
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Returns the array of CO nodes sorted by level.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-Fpga_NodeVec_t * Fpga_MappingOrderCosByLevel( Fpga_Man_t * pMan )
-{
-    Fpga_Node_t * pNode;
-    Fpga_NodeVec_t * vNodes;
-    int i, nLevels;
-    // get the largest level of a CO
-    nLevels = Fpga_MappingMaxLevel( pMan );
-    // allocate the array of nodes
-    vNodes = Fpga_NodeVecAlloc( nLevels + 1 );
-    for ( i = 0; i <= nLevels; i++ )
-        Fpga_NodeVecPush( vNodes, NULL );
-    // clean the marks
-    for ( i = 0; i < pMan->nOutputs; i++ )
-        Fpga_Regular(pMan->pOutputs[i])->fMark0 = 0;
-    // put the nodes into the structure
-    for ( i = 0; i < pMan->nOutputs; i++ )
-    {
-        pNode = Fpga_Regular(pMan->pOutputs[i]);
-        if ( pNode->fMark0 )
-            continue;
-        pNode->fMark0 = 1;
-        pNode->pData0 = (char *)Fpga_NodeVecReadEntry( vNodes, pNode->Level );
-        Fpga_NodeVecWriteEntry( vNodes, pNode->Level, pNode );
-    }
-    for ( i = 0; i < pMan->nOutputs; i++ )
-        Fpga_Regular(pMan->pOutputs[i])->fMark0 = 0;
-    return vNodes;
-
-}
-
-////////////////////////////////////////////////////////////////////////
-///                       END OF FILE                                ///
-////////////////////////////////////////////////////////////////////////
-
-
diff --git a/abc70930/src/map/fpga/fpgaVec.c b/abc70930/src/map/fpga/fpgaVec.c
deleted file mode 100644
index 70a4a7ac..00000000
--- a/abc70930/src/map/fpga/fpgaVec.c
+++ /dev/null
@@ -1,408 +0,0 @@
-/**CFile****************************************************************
-
-  FileName    [fpgaVec.c]
-
-  PackageName [MVSIS 1.3: Multi-valued logic synthesis system.]
-
-  Synopsis    [Technology mapping for variable-size-LUT FPGAs.]
-
-  Author      [MVSIS Group]
-  
-  Affiliation [UC Berkeley]
-
-  Date        [Ver. 2.0. Started - August 18, 2004.]
-
-  Revision    [$Id: fpgaVec.c,v 1.3 2005/01/23 06:59:42 alanmi Exp $]
-
-***********************************************************************/
-
-#include "fpgaInt.h"
-
-////////////////////////////////////////////////////////////////////////
-///                        DECLARATIONS                              ///
-////////////////////////////////////////////////////////////////////////
-
-static int Fpga_NodeVecCompareLevels( Fpga_Node_t ** pp1, Fpga_Node_t ** pp2 );
-
-////////////////////////////////////////////////////////////////////////
-///                     FUNCTION DEFINITIONS                         ///
-////////////////////////////////////////////////////////////////////////
-
-/**Function*************************************************************
-
-  Synopsis    [Allocates a vector with the given capacity.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-Fpga_NodeVec_t * Fpga_NodeVecAlloc( int nCap )
-{
-    Fpga_NodeVec_t * p;
-    p = ALLOC( Fpga_NodeVec_t, 1 );
-    if ( nCap > 0 && nCap < 16 )
-        nCap = 16;
-    p->nSize  = 0;
-    p->nCap   = nCap;
-    p->pArray = p->nCap? ALLOC( Fpga_Node_t *, p->nCap ) : NULL;
-    return p;
-}
-
-/**Function*************************************************************
-
-  Synopsis    []
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Fpga_NodeVecFree( Fpga_NodeVec_t * p )
-{
-    FREE( p->pArray );
-    FREE( p );
-}
-
-/**Function*************************************************************
-
-  Synopsis    []
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-Fpga_Node_t ** Fpga_NodeVecReadArray( Fpga_NodeVec_t * p )
-{
-    return p->pArray;
-}
-
-/**Function*************************************************************
-
-  Synopsis    []
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Fpga_NodeVecReadSize( Fpga_NodeVec_t * p )
-{
-    return p->nSize;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Resizes the vector to the given capacity.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Fpga_NodeVecGrow( Fpga_NodeVec_t * p, int nCapMin )
-{
-    if ( p->nCap >= nCapMin )
-        return;
-    p->pArray = REALLOC( Fpga_Node_t *, p->pArray, nCapMin ); 
-    p->nCap   = nCapMin;
-}
-
-/**Function*************************************************************
-
-  Synopsis    []
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Fpga_NodeVecShrink( Fpga_NodeVec_t * p, int nSizeNew )
-{
-    assert( p->nSize >= nSizeNew );
-    p->nSize = nSizeNew;
-}
-
-/**Function*************************************************************
-
-  Synopsis    []
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Fpga_NodeVecClear( Fpga_NodeVec_t * p )
-{
-    p->nSize = 0;
-}
-
-/**Function*************************************************************
-
-  Synopsis    []
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Fpga_NodeVecPush( Fpga_NodeVec_t * p, Fpga_Node_t * Entry )
-{
-    if ( p->nSize == p->nCap )
-    {
-        if ( p->nCap < 16 )
-            Fpga_NodeVecGrow( p, 16 );
-        else
-            Fpga_NodeVecGrow( p, 2 * p->nCap );
-    }
-    p->pArray[p->nSize++] = Entry;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Add the element while ensuring uniqueness.]
-
-  Description [Returns 1 if the element was found, and 0 if it was new. ]
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Fpga_NodeVecPushUnique( Fpga_NodeVec_t * p, Fpga_Node_t * Entry )
-{
-    int i;
-    for ( i = 0; i < p->nSize; i++ )
-        if ( p->pArray[i] == Entry )
-            return 1;
-    Fpga_NodeVecPush( p, Entry );
-    return 0;
-}
-
-/**Function*************************************************************
-
-  Synopsis    []
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-Fpga_Node_t * Fpga_NodeVecPop( Fpga_NodeVec_t * p )
-{
-    return p->pArray[--p->nSize];
-}
-
-/**Function*************************************************************
-
-  Synopsis    []
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Fpga_NodeVecWriteEntry( Fpga_NodeVec_t * p, int i, Fpga_Node_t * Entry )
-{
-    assert( i >= 0 && i < p->nSize );
-    p->pArray[i] = Entry;
-}
-
-/**Function*************************************************************
-
-  Synopsis    []
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-Fpga_Node_t * Fpga_NodeVecReadEntry( Fpga_NodeVec_t * p, int i )
-{
-    assert( i >= 0 && i < p->nSize );
-    return p->pArray[i];
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Comparison procedure for two nodes.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Fpga_NodeVecCompareLevels( Fpga_Node_t ** pp1, Fpga_Node_t ** pp2 )
-{
-    int Level1 = Fpga_Regular(*pp1)->Level;
-    int Level2 = Fpga_Regular(*pp2)->Level;
-    if ( Level1 < Level2 )
-        return -1;
-    if ( Level1 > Level2 )
-        return 1;
-    if ( Fpga_Regular(*pp1)->Num < Fpga_Regular(*pp2)->Num )
-        return -1;
-    if ( Fpga_Regular(*pp1)->Num > Fpga_Regular(*pp2)->Num )
-        return 1;
-    return 0; 
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Sorting the entries by their integer value.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Fpga_NodeVecSortByLevel( Fpga_NodeVec_t * p )
-{
-    qsort( (void *)p->pArray, p->nSize, sizeof(Fpga_Node_t *), 
-            (int (*)(const void *, const void *)) Fpga_NodeVecCompareLevels );
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Compares the arrival times.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Fpga_NodeVecCompareArrivals( Fpga_Node_t ** ppS1, Fpga_Node_t ** ppS2 )
-{
-    if ( (*ppS1)->pCutBest->tArrival < (*ppS2)->pCutBest->tArrival )
-        return -1;
-    if ( (*ppS1)->pCutBest->tArrival > (*ppS2)->pCutBest->tArrival )
-        return 1;
-    return 0;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Orders the nodes in the increasing order of the arrival times.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Fpga_SortNodesByArrivalTimes( Fpga_NodeVec_t * p )
-{
-    qsort( (void *)p->pArray, p->nSize, sizeof(Fpga_Node_t *), 
-            (int (*)(const void *, const void *)) Fpga_NodeVecCompareArrivals );
-//    assert( Fpga_CompareNodesByLevel( p->pArray, p->pArray + p->nSize - 1 ) <= 0 );
-}
-
-
-/**Function*************************************************************
-
-  Synopsis    [Computes the union of nodes in two arrays.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Fpga_NodeVecUnion( Fpga_NodeVec_t * p, Fpga_NodeVec_t * p1, Fpga_NodeVec_t * p2 )
-{
-    int i;
-    Fpga_NodeVecClear( p );
-    for ( i = 0; i < p1->nSize; i++ )
-        Fpga_NodeVecPush( p, p1->pArray[i] );
-    for ( i = 0; i < p2->nSize; i++ )
-        Fpga_NodeVecPush( p, p2->pArray[i] );
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Inserts a new node in the order by arrival times.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Fpga_NodeVecPushOrder( Fpga_NodeVec_t * vNodes, Fpga_Node_t * pNode, int fIncreasing )
-{
-    Fpga_Node_t * pNode1, * pNode2;
-    int i;
-    Fpga_NodeVecPush( vNodes, pNode );
-    // find the place of the node
-    for ( i = vNodes->nSize-1; i > 0; i-- )
-    {
-        pNode1 = vNodes->pArray[i  ];
-        pNode2 = vNodes->pArray[i-1];
-        if ( fIncreasing && pNode1->pCutBest->tArrival >= pNode2->pCutBest->tArrival ||
-            !fIncreasing && pNode1->pCutBest->tArrival <= pNode2->pCutBest->tArrival )
-            break;
-        vNodes->pArray[i  ] = pNode2;
-        vNodes->pArray[i-1] = pNode1;
-    }
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Inserts a new node in the order by arrival times.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Fpga_NodeVecReverse( Fpga_NodeVec_t * vNodes )
-{
-    Fpga_Node_t * pNode1, * pNode2;
-    int i;
-    for ( i = 0; i < vNodes->nSize/2; i++ )
-    {
-        pNode1 = vNodes->pArray[i];
-        pNode2 = vNodes->pArray[vNodes->nSize-1-i];
-        vNodes->pArray[i]                 = pNode2;
-        vNodes->pArray[vNodes->nSize-1-i] = pNode1;
-    }
-}
-
-////////////////////////////////////////////////////////////////////////
-///                       END OF FILE                                ///
-////////////////////////////////////////////////////////////////////////
-
diff --git a/abc70930/src/map/fpga/module.make b/abc70930/src/map/fpga/module.make
deleted file mode 100644
index cc3a6573..00000000
--- a/abc70930/src/map/fpga/module.make
+++ /dev/null
@@ -1,13 +0,0 @@
-SRC +=  src/map/fpga/fpga.c \
-    src/map/fpga/fpgaCore.c \
-    src/map/fpga/fpgaCreate.c \
-    src/map/fpga/fpgaCut.c \
-    src/map/fpga/fpgaCutUtils.c \
-    src/map/fpga/fpgaFanout.c \
-    src/map/fpga/fpgaLib.c \
-    src/map/fpga/fpgaMatch.c \
-    src/map/fpga/fpgaSwitch.c \
-    src/map/fpga/fpgaTime.c \
-    src/map/fpga/fpgaTruth.c \
-    src/map/fpga/fpgaUtils.c \
-    src/map/fpga/fpgaVec.c
diff --git a/abc70930/src/map/if/if.h b/abc70930/src/map/if/if.h
deleted file mode 100644
index 706f8552..00000000
--- a/abc70930/src/map/if/if.h
+++ /dev/null
@@ -1,386 +0,0 @@
-/**CFile****************************************************************
-
-  FileName    [if.h]
-
-  SystemName  [ABC: Logic synthesis and verification system.]
-
-  PackageName [FPGA mapping based on priority cuts.]
-
-  Synopsis    [External declarations.]
-
-  Author      [Alan Mishchenko]
-  
-  Affiliation [UC Berkeley]
-
-  Date        [Ver. 1.0. Started - November 21, 2006.]
-
-  Revision    [$Id: if.h,v 1.00 2006/11/21 00:00:00 alanmi Exp $]
-
-***********************************************************************/
- 
-#ifndef __IF_H__
-#define __IF_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-////////////////////////////////////////////////////////////////////////
-///                          INCLUDES                                ///
-////////////////////////////////////////////////////////////////////////
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <assert.h>
-#include <time.h>
-#include "vec.h"
-#include "mem.h"
-
-////////////////////////////////////////////////////////////////////////
-///                         PARAMETERS                               ///
-////////////////////////////////////////////////////////////////////////
- 
-// the maximum size of LUTs used for mapping (should be the same as FPGA_MAX_LUTSIZE defined in "fpga.h"!!!)
-#define IF_MAX_LUTSIZE       32
-// the largest possible number of LUT inputs when funtionality of the LUTs are computed
-#define IF_MAX_FUNC_LUTSIZE  15
-// a very large number
-#define IF_INFINITY          100000000  
-// the largest possible user cut cost
-#define IF_COST_MAX          ((1<<14)-1)
-
-// object types
-typedef enum { 
-    IF_NONE,     // 0: non-existent object
-    IF_CONST1,   // 1: constant 1 
-    IF_CI,       // 2: combinational input
-    IF_CO,       // 3: combinational output
-    IF_AND,      // 4: AND node
-    IF_VOID      // 5: unused object
-} If_Type_t;
-
-////////////////////////////////////////////////////////////////////////
-///                         BASIC TYPES                              ///
-////////////////////////////////////////////////////////////////////////
-
-typedef struct If_Man_t_     If_Man_t;
-typedef struct If_Par_t_     If_Par_t;
-typedef struct If_Lib_t_     If_Lib_t;
-typedef struct If_Obj_t_     If_Obj_t;
-typedef struct If_Cut_t_     If_Cut_t;
-typedef struct If_Set_t_     If_Set_t;
-
-// parameters
-struct If_Par_t_
-{
-    // user-controlable paramters
-    int                nLutSize;      // the LUT size
-    int                nCutsMax;      // the max number of cuts
-    int                nFlowIters;    // the number of iterations of area recovery
-    int                nAreaIters;    // the number of iterations of area recovery
-    float              DelayTarget;   // delay target
-    int                fPreprocess;   // preprossing
-    int                fArea;         // area-oriented mapping
-    int                fFancy;        // a fancy feature
-    int                fExpRed;       // expand/reduce of the best cuts
-    int                fLatchPaths;   // reset timing on latch paths
-    int                fSeqMap;       // sequential mapping
-    int                fVerbose;      // the verbosity flag
-    // internal parameters
-    int                fAreaOnly;     // area only mode
-    int                fTruth;        // truth table computation enabled
-    int                fUsePerm;      // use permutation (delay info)
-    int                fUseBdds;      // use local BDDs as a cost function
-    int                fUseSops;      // use local SOPs as a cost function
-    int                fUseCnfs;      // use local CNFs as a cost function
-    int                fUseMv;        // use local MV-SOPs as a cost function
-    int                nLatches;      // the number of latches in seq mapping
-    int                fLiftLeaves;   // shift the leaves for seq mapping
-    If_Lib_t *         pLutLib;       // the LUT library
-    float *            pTimesArr;     // arrival times
-    float *            pTimesReq;     // required times
-    int (* pFuncCost)  (If_Cut_t *);  // procedure to compute the user's cost of a cut
-    int (* pFuncUser)  (If_Man_t *, If_Obj_t *, If_Cut_t *); //  procedure called for each cut when cut computation is finished
-    void *             pReoMan;       // reordering manager
-};
-
-// the LUT library
-struct If_Lib_t_
-{
-    char *             pName;         // the name of the LUT library
-    int                LutMax;        // the maximum LUT size 
-    int                fVarPinDelays; // set to 1 if variable pin delays are specified
-    float              pLutAreas[IF_MAX_LUTSIZE+1]; // the areas of LUTs
-    float              pLutDelays[IF_MAX_LUTSIZE+1][IF_MAX_LUTSIZE+1];// the delays of LUTs
-};
-
-// manager
-struct If_Man_t_
-{
-    // mapping parameters
-    If_Par_t *         pPars;
-    // mapping nodes
-    If_Obj_t *         pConst1;       // the constant 1 node
-    Vec_Ptr_t *        vCis;          // the primary inputs
-    Vec_Ptr_t *        vCos;          // the primary outputs
-    Vec_Ptr_t *        vObjs;         // all objects
-    Vec_Ptr_t *        vMapped;       // objects used in the mapping
-    Vec_Ptr_t *        vTemp;         // temporary array
-    int                nObjs[IF_VOID];// the number of objects by type
-    // various data
-    int                nLevelMax;     // the max number of AIG levels
-    float              fEpsilon;      // epsilon used for comparison
-    float              RequiredGlo;   // global required times
-    float              RequiredGlo2;  // global required times
-    float              AreaGlo;       // global area
-    int                nNets;         // the sum total of fanins of all LUTs in the mapping
-    int                nCutsUsed;     // the number of cuts currently used
-    int                nCutsMerged;   // the total number of cuts merged
-    unsigned *         puTemp[4];     // used for the truth table computation
-    int                SortMode;      // one of the three sorting modes
-    int                fNextRound;    // set to 1 after the first round
-    int                nChoices;      // the number of choice nodes
-    // sequential mapping
-    Vec_Ptr_t *        vLatchOrder;   // topological ordering of latches
-    Vec_Int_t *        vLags;         // sequentail lags of all nodes
-    int                nAttempts;     // the number of attempts in binary search
-    int                nMaxIters;     // the maximum number of iterations
-    int                Period;        // the current value of the clock period (for seq mapping)
-    // memory management
-    int                nTruthWords;   // the size of the truth table if allocated
-    int                nPermWords;    // the size of the permutation array (in words)
-    int                nObjBytes;     // the size of the object
-    int                nCutBytes;     // the size of the cut
-    int                nSetBytes;     // the size of the cut set
-    Mem_Fixed_t *      pMemObj;       // memory manager for objects (entrysize = nEntrySize)
-    Mem_Fixed_t *      pMemSet;       // memory manager for sets of cuts (entrysize = nCutSize*(nCutsMax+1))
-    If_Set_t *         pMemCi;        // memory for CI cutsets
-    If_Set_t *         pMemAnd;       // memory for AND cutsets
-    If_Set_t *         pFreeList;     // the list of free cutsets
-};
-
-// priority cut
-struct If_Cut_t_
-{
-    float              Delay;         // delay of the cut
-    float              Area;          // area (or area-flow) of the cut
-    float              AveRefs;       // the average number of leaf references
-    unsigned           uSign;         // cut signature
-    unsigned           Cost    : 14;  // the user's cost of the cut
-    unsigned           fCompl  :  1;  // the complemented attribute 
-    unsigned           fUser   :  1;  // using the user's area and delay
-    unsigned           nLimit  :  8;  // the maximum number of leaves
-    unsigned           nLeaves :  8;  // the number of leaves
-    int *              pLeaves;       // array of fanins
-    char *             pPerm;         // permutation
-    unsigned *         pTruth;        // the truth table
-};
-
-// set of priority cut
-struct If_Set_t_
-{
-    short              nCutsMax;      // the max number of cuts
-    short              nCuts;         // the current number of cuts
-    If_Set_t *         pNext;         // next cutset in the free list
-    If_Cut_t **        ppCuts;        // the array of pointers to the cuts
-};
-
-// node extension
-struct If_Obj_t_
-{
-    unsigned           Type    :  4;  // object
-    unsigned           fCompl0 :  1;  // complemented attribute
-    unsigned           fCompl1 :  1;  // complemented attribute
-    unsigned           fPhase  :  1;  // phase of the node
-    unsigned           fRepr   :  1;  // representative of the equivalence class
-    unsigned           fMark   :  1;  // multipurpose mark
-    unsigned           fVisit  :  1;  // multipurpose mark
-    unsigned           Level   : 22;  // logic level of the node
-    int                Id;            // integer ID
-    int                nRefs;         // the number of references
-    int                nVisits;       // the number of visits to this node
-    int                nVisitsCopy;   // the number of visits to this node
-    If_Obj_t *         pFanin0;       // the first fanin 
-    If_Obj_t *         pFanin1;       // the second fanin
-    If_Obj_t *         pEquiv;        // the choice node
-    float              EstRefs;       // estimated reference counter
-    float              Required;      // required time of the onde
-    float              LValue;        // sequential arrival time of the node
-    void *             pCopy;         // used for object duplication
-    If_Set_t *         pCutSet;       // the pointer to the cutset
-    If_Cut_t           CutBest;       // the best cut selected 
-};
-
-static inline If_Obj_t * If_Regular( If_Obj_t * p )                          { return (If_Obj_t *)((unsigned long)(p) & ~01);  }
-static inline If_Obj_t * If_Not( If_Obj_t * p )                              { return (If_Obj_t *)((unsigned long)(p) ^  01);  }
-static inline If_Obj_t * If_NotCond( If_Obj_t * p, int c )                   { return (If_Obj_t *)((unsigned long)(p) ^ (c));  }
-static inline int        If_IsComplement( If_Obj_t * p )                     { return (int )(((unsigned long)p) & 01);         }
-
-static inline int        If_ManCiNum( If_Man_t * p )                         { return p->nObjs[IF_CI];               }
-static inline int        If_ManCoNum( If_Man_t * p )                         { return p->nObjs[IF_CO];               }
-static inline int        If_ManAndNum( If_Man_t * p )                        { return p->nObjs[IF_AND];              }
-static inline int        If_ManObjNum( If_Man_t * p )                        { return Vec_PtrSize(p->vObjs);         }
-
-static inline If_Obj_t * If_ManConst1( If_Man_t * p )                        { return p->pConst1;                              }
-static inline If_Obj_t * If_ManCi( If_Man_t * p, int i )                     { return (If_Obj_t *)Vec_PtrEntry( p->vCis, i );  }
-static inline If_Obj_t * If_ManCo( If_Man_t * p, int i )                     { return (If_Obj_t *)Vec_PtrEntry( p->vCos, i );  }
-static inline If_Obj_t * If_ManLi( If_Man_t * p, int i )                     { return (If_Obj_t *)Vec_PtrEntry( p->vCos, If_ManCoNum(p) - p->pPars->nLatches + i );  }
-static inline If_Obj_t * If_ManLo( If_Man_t * p, int i )                     { return (If_Obj_t *)Vec_PtrEntry( p->vCis, If_ManCiNum(p) - p->pPars->nLatches + i );  }
-static inline If_Obj_t * If_ManObj( If_Man_t * p, int i )                    { return (If_Obj_t *)Vec_PtrEntry( p->vObjs, i ); }
-
-static inline int        If_ObjIsConst1( If_Obj_t * pObj )                   { return pObj->Type == IF_CONST1;       }
-static inline int        If_ObjIsCi( If_Obj_t * pObj )                       { return pObj->Type == IF_CI;           }
-static inline int        If_ObjIsCo( If_Obj_t * pObj )                       { return pObj->Type == IF_CO;           }
-static inline int        If_ObjIsPi( If_Obj_t * pObj )                       { return If_ObjIsCi(pObj) && pObj->pFanin0 == NULL; }
-static inline int        If_ObjIsLatch( If_Obj_t * pObj )                    { return If_ObjIsCi(pObj) && pObj->pFanin0 != NULL; }
-static inline int        If_ObjIsAnd( If_Obj_t * pObj )                      { return pObj->Type == IF_AND;          }
-
-static inline If_Obj_t * If_ObjFanin0( If_Obj_t * pObj )                     { return pObj->pFanin0;                 }
-static inline If_Obj_t * If_ObjFanin1( If_Obj_t * pObj )                     { return pObj->pFanin1;                 }
-static inline int        If_ObjFaninC0( If_Obj_t * pObj )                    { return pObj->fCompl0;                 }
-static inline int        If_ObjFaninC1( If_Obj_t * pObj )                    { return pObj->fCompl1;                 }
-static inline void *     If_ObjCopy( If_Obj_t * pObj )                       { return pObj->pCopy;                   }
-static inline void       If_ObjSetCopy( If_Obj_t * pObj, void * pCopy )      { pObj->pCopy = pCopy;                  }
-static inline void       If_ObjSetChoice( If_Obj_t * pObj, If_Obj_t * pEqu ) { pObj->pEquiv = pEqu;                  }
-
-static inline If_Cut_t * If_ObjCutBest( If_Obj_t * pObj )                    { return &pObj->CutBest;                }
-static inline unsigned   If_ObjCutSign( unsigned ObjId )                     { return (1 << (ObjId % 31));           }
-
-static inline float      If_ObjArrTime( If_Obj_t * pObj )                    { return If_ObjCutBest(pObj)->Delay;    }
-static inline void       If_ObjSetArrTime( If_Obj_t * pObj, float ArrTime )  { If_ObjCutBest(pObj)->Delay = ArrTime; }
-
-static inline float      If_ObjLValue( If_Obj_t * pObj )                     { return pObj->LValue;                  }
-static inline void       If_ObjSetLValue( If_Obj_t * pObj, float LValue )    { pObj->LValue = LValue;                }
-
-static inline void *     If_CutData( If_Cut_t * pCut )                       { return *(void **)pCut;                }
-static inline void       If_CutSetData( If_Cut_t * pCut, void * pData )      { *(void **)pCut = pData;               }
-
-static inline int        If_CutLeaveNum( If_Cut_t * pCut )                   { return pCut->nLeaves;                             }
-static inline unsigned * If_CutTruth( If_Cut_t * pCut )                      { return pCut->pTruth;                              }
-static inline int        If_CutTruthWords( int nVarsMax )                    { return nVarsMax <= 5 ? 1 : (1 << (nVarsMax - 5)); }
-static inline int        If_CutPermWords( int nVarsMax )                     { return nVarsMax / sizeof(int) + ((nVarsMax % sizeof(int)) > 0); }
-
-static inline float      If_CutLutArea( If_Man_t * p, If_Cut_t * pCut )      { return pCut->fUser? (float)pCut->Cost : (p->pPars->pLutLib? p->pPars->pLutLib->pLutAreas[pCut->nLeaves] : (float)1.0); }
-
-////////////////////////////////////////////////////////////////////////
-///                      MACRO DEFINITIONS                           ///
-////////////////////////////////////////////////////////////////////////
-
-#define IF_MIN(a,b)      (((a) < (b))? (a) : (b))
-#define IF_MAX(a,b)      (((a) > (b))? (a) : (b))
-
-// the small and large numbers (min/max float are 1.17e-38/3.40e+38)
-#define IF_FLOAT_LARGE   ((float)1.0e+20)
-#define IF_FLOAT_SMALL   ((float)1.0e-20)
-#define IF_INT_LARGE     (10000000)
-
-// iterator over the primary inputs
-#define If_ManForEachCi( p, pObj, i )                                          \
-    Vec_PtrForEachEntry( p->vCis, pObj, i )
-// iterator over the primary outputs
-#define If_ManForEachCo( p, pObj, i )                                          \
-    Vec_PtrForEachEntry( p->vCos, pObj, i )
-// iterator over the primary inputs
-#define If_ManForEachPi( p, pObj, i )                                          \
-    Vec_PtrForEachEntryStop( p->vCis, pObj, i, If_ManCiNum(p) - p->pPars->nLatches )
-// iterator over the primary outputs
-#define If_ManForEachPo( p, pObj, i )                                          \
-    Vec_PtrForEachEntryStop( p->vCos, pObj, i, If_ManCoNum(p) - p->pPars->nLatches )
-// iterator over the latches 
-#define If_ManForEachLatchInput( p, pObj, i )                                  \
-    Vec_PtrForEachEntryStart( p->vCos, pObj, i, If_ManCoNum(p) - p->pPars->nLatches )
-#define If_ManForEachLatchOutput( p, pObj, i )                                 \
-    Vec_PtrForEachEntryStart( p->vCis, pObj, i, If_ManCiNum(p) - p->pPars->nLatches )
-// iterator over all objects, including those currently not used
-#define If_ManForEachObj( p, pObj, i )                                         \
-    Vec_PtrForEachEntry( p->vObjs, pObj, i )
-// iterator over logic nodes 
-#define If_ManForEachNode( p, pObj, i )                                        \
-    If_ManForEachObj( p, pObj, i ) if ( pObj->Type != IF_AND ) {} else
-// iterator over cuts of the node
-#define If_ObjForEachCut( pObj, pCut, i )                                      \
-    for ( i = 0; (i < (pObj)->pCutSet->nCuts) && ((pCut) = (pObj)->pCutSet->ppCuts[i]); i++ )
-// iterator over the leaves of the cut
-#define If_CutForEachLeaf( p, pCut, pLeaf, i )                                 \
-    for ( i = 0; (i < (int)(pCut)->nLeaves) && ((pLeaf) = If_ManObj(p, (pCut)->pLeaves[i])); i++ )
-#define If_CutForEachLeafReverse( p, pCut, pLeaf, i )                                 \
-    for ( i = (int)(pCut)->nLeaves - 1; (i >= 0) && ((pLeaf) = If_ManObj(p, (pCut)->pLeaves[i])); i-- )
-//#define If_CutForEachLeaf( p, pCut, pLeaf, i )                                 \
-//    for ( i = 0; (i < (int)(pCut)->nLeaves) && ((pLeaf) = If_ManObj(p, p->pPars->fLiftLeaves? (pCut)->pLeaves[i] >> 8 : (pCut)->pLeaves[i])); i++ )
-// iterator over the leaves of the sequential cut
-#define If_CutForEachLeafSeq( p, pCut, pLeaf, Shift, i )                       \
-    for ( i = 0; (i < (int)(pCut)->nLeaves) && ((pLeaf) = If_ManObj(p, (pCut)->pLeaves[i] >> 8)) && (((Shift) = ((pCut)->pLeaves[i] & 255)) >= 0); i++ )
-
-////////////////////////////////////////////////////////////////////////
-///                    FUNCTION DECLARATIONS                         ///
-////////////////////////////////////////////////////////////////////////
-
-/*=== ifCore.c ===========================================================*/
-extern int             If_ManPerformMapping( If_Man_t * p );
-extern int             If_ManPerformMappingComb( If_Man_t * p );
-/*=== ifCut.c ============================================================*/
-extern float           If_CutAreaDerefed( If_Man_t * p, If_Cut_t * pCut, int nLevels );
-extern float           If_CutAreaRefed( If_Man_t * p, If_Cut_t * pCut, int nLevels );
-extern float           If_CutDeref( If_Man_t * p, If_Cut_t * pCut, int nLevels );
-extern float           If_CutRef( If_Man_t * p, If_Cut_t * pCut, int nLevels );
-extern void            If_CutPrint( If_Man_t * p, If_Cut_t * pCut );
-extern void            If_CutPrintTiming( If_Man_t * p, If_Cut_t * pCut );
-extern float           If_CutFlow( If_Man_t * p, If_Cut_t * pCut );
-extern float           If_CutAverageRefs( If_Man_t * p, If_Cut_t * pCut );
-extern int             If_CutFilter( If_Set_t * pCutSet, If_Cut_t * pCut );
-extern void            If_CutSort( If_Man_t * p, If_Set_t * pCutSet, If_Cut_t * pCut );
-extern int             If_CutMerge( If_Cut_t * pCut0, If_Cut_t * pCut1, If_Cut_t * pCut );
-extern void            If_CutLift( If_Cut_t * pCut );
-extern void            If_CutCopy( If_Man_t * p, If_Cut_t * pCutDest, If_Cut_t * pCutSrc );
-extern void            If_ManSortCuts( If_Man_t * p, int Mode );
-/*=== ifMan.c =============================================================*/
-extern If_Man_t *      If_ManStart( If_Par_t * pPars );
-extern void            If_ManRestart( If_Man_t * p );
-extern void            If_ManStop( If_Man_t * p );
-extern If_Obj_t *      If_ManCreateCi( If_Man_t * p );
-extern If_Obj_t *      If_ManCreateCo( If_Man_t * p, If_Obj_t * pDriver );
-extern If_Obj_t *      If_ManCreateAnd( If_Man_t * p, If_Obj_t * pFan0, If_Obj_t * pFan1 );
-extern If_Obj_t *      If_ManCreateXor( If_Man_t * p, If_Obj_t * pFan0, If_Obj_t * pFan1 );
-extern If_Obj_t *      If_ManCreateMux( If_Man_t * p, If_Obj_t * pFan0, If_Obj_t * pFan1, If_Obj_t * pCtrl );
-extern void            If_ManCreateChoice( If_Man_t * p, If_Obj_t * pRepr );
-extern void            If_ManSetupCutTriv( If_Man_t * p, If_Cut_t * pCut, int ObjId );
-extern void            If_ManSetupCiCutSets( If_Man_t * p );
-extern If_Set_t *      If_ManSetupNodeCutSet( If_Man_t * p, If_Obj_t * pObj );
-extern void            If_ManDerefNodeCutSet( If_Man_t * p, If_Obj_t * pObj );
-extern void            If_ManDerefChoiceCutSet( If_Man_t * p, If_Obj_t * pObj );
-extern void            If_ManSetupSetAll( If_Man_t * p, int nCrossCut );
-/*=== ifMap.c =============================================================*/
-extern void            If_ObjPerformMappingAnd( If_Man_t * p, If_Obj_t * pObj, int Mode, int fPreprocess );
-extern void            If_ObjPerformMappingChoice( If_Man_t * p, If_Obj_t * pObj, int Mode, int fPreprocess );
-extern int             If_ManPerformMappingRound( If_Man_t * p, int nCutsUsed, int Mode, int fPreprocess, char * pLabel );
-/*=== ifReduce.c ==========================================================*/
-extern void            If_ManImproveMapping( If_Man_t * p );
-/*=== ifSeq.c =============================================================*/
-extern int             If_ManPerformMappingSeq( If_Man_t * p );
-/*=== ifTime.c ============================================================*/
-extern float           If_CutDelay( If_Man_t * p, If_Cut_t * pCut );
-extern void            If_CutPropagateRequired( If_Man_t * p, If_Cut_t * pCut, float Required );
-/*=== ifTruth.c ===========================================================*/
-extern void            If_CutComputeTruth( If_Man_t * p, If_Cut_t * pCut, If_Cut_t * pCut0, If_Cut_t * pCut1, int fCompl0, int fCompl1 );
-/*=== ifUtil.c ============================================================*/
-extern void            If_ManCleanNodeCopy( If_Man_t * p );
-extern void            If_ManCleanCutData( If_Man_t * p );
-extern void            If_ManCleanMarkV( If_Man_t * p );
-extern float           If_ManDelayMax( If_Man_t * p, int fSeq );
-extern void            If_ManComputeRequired( If_Man_t * p );
-extern float           If_ManScanMapping( If_Man_t * p );
-extern float           If_ManScanMappingSeq( If_Man_t * p );
-extern void            If_ManResetOriginalRefs( If_Man_t * p );
-extern int             If_ManCrossCut( If_Man_t * p );
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-////////////////////////////////////////////////////////////////////////
-///                       END OF FILE                                ///
-////////////////////////////////////////////////////////////////////////
-
diff --git a/abc70930/src/map/if/ifCore.c b/abc70930/src/map/if/ifCore.c
deleted file mode 100644
index 59ad5a1c..00000000
--- a/abc70930/src/map/if/ifCore.c
+++ /dev/null
@@ -1,146 +0,0 @@
-/**CFile****************************************************************
-
-  FileName    [ifCore.c]
-
-  SystemName  [ABC: Logic synthesis and verification system.]
-
-  PackageName [FPGA mapping based on priority cuts.]
-
-  Synopsis    [The central part of the mapper.]
-
-  Author      [Alan Mishchenko]
-  
-  Affiliation [UC Berkeley]
-
-  Date        [Ver. 1.0. Started - November 21, 2006.]
-
-  Revision    [$Id: ifCore.c,v 1.00 2006/11/21 00:00:00 alanmi Exp $]
-
-***********************************************************************/
-
-#include "if.h"
-
-////////////////////////////////////////////////////////////////////////
-///                        DECLARATIONS                              ///
-////////////////////////////////////////////////////////////////////////
-
-extern int s_MappingTime;
-
-////////////////////////////////////////////////////////////////////////
-///                     FUNCTION DEFINITIONS                         ///
-////////////////////////////////////////////////////////////////////////
-
-/**Function*************************************************************
-
-  Synopsis    []
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int If_ManPerformMapping( If_Man_t * p )
-{
-    p->pPars->fAreaOnly = p->pPars->fArea; // temporary
-
-    // create the CI cutsets
-    If_ManSetupCiCutSets( p );
-    // allocate memory for other cutsets
-    If_ManSetupSetAll( p, If_ManCrossCut(p) );
-
-    // try sequential mapping
-    if ( p->pPars->fSeqMap )
-    {
-        int RetValue;
-//        printf( "Currently sequential mapping is not performed.\n" );
-        RetValue = If_ManPerformMappingSeq( p );
-        return RetValue;
-//        return 1;
-    }
-
-    return If_ManPerformMappingComb( p );
-}
-
-
-/**Function*************************************************************
-
-  Synopsis    []
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int If_ManPerformMappingComb( If_Man_t * p )
-{
-    If_Obj_t * pObj;
-    int clkTotal = clock();
-    int i;
-
-    // set arrival times and fanout estimates
-    If_ManForEachCi( p, pObj, i )
-    {
-        If_ObjSetArrTime( pObj, p->pPars->pTimesArr[i] );
-        pObj->EstRefs = (float)1.0;
-    }
-
-    // delay oriented mapping
-    if ( p->pPars->fPreprocess && !p->pPars->fArea )
-    {
-        // map for delay
-        If_ManPerformMappingRound( p, p->pPars->nCutsMax, 0, 1, "Delay" );
-        // map for delay second option
-        p->pPars->fFancy = 1;
-        If_ManResetOriginalRefs( p );
-        If_ManPerformMappingRound( p, p->pPars->nCutsMax, 0, 1, "Delay-2" );
-        p->pPars->fFancy = 0;
-        // map for area
-        p->pPars->fArea = 1;
-        If_ManResetOriginalRefs( p );
-        If_ManPerformMappingRound( p, p->pPars->nCutsMax, 0, 1, "Area" );
-        p->pPars->fArea = 0;
-    }
-    else
-        If_ManPerformMappingRound( p, p->pPars->nCutsMax, 0, 0, "Delay" );
-
-    // try to improve area by expanding and reducing the cuts
-    if ( p->pPars->fExpRed && !p->pPars->fTruth )
-        If_ManImproveMapping( p );
-
-    // area flow oriented mapping
-    for ( i = 0; i < p->pPars->nFlowIters; i++ )
-    {
-        If_ManPerformMappingRound( p, p->pPars->nCutsMax, 1, 0, "Flow" );
-        if ( p->pPars->fExpRed && !p->pPars->fTruth )
-            If_ManImproveMapping( p );
-    }
-
-    // area oriented mapping
-    for ( i = 0; i < p->pPars->nAreaIters; i++ )
-    {
-        If_ManPerformMappingRound( p, p->pPars->nCutsMax, 2, 0, "Area" );
-        if ( p->pPars->fExpRed && !p->pPars->fTruth )
-            If_ManImproveMapping( p );
-    }
-
-    if ( p->pPars->fVerbose )
-    {
-//        printf( "Total memory = %7.2f Mb. Peak cut memory = %7.2f Mb.  ", 
-//            1.0 * (p->nObjBytes + 2*sizeof(void *)) * If_ManObjNum(p) / (1<<20), 
-//            1.0 * p->nSetBytes * Mem_FixedReadMaxEntriesUsed(p->pMemSet) / (1<<20) );
-        PRT( "Total time", clock() - clkTotal );
-    }
-//    printf( "Cross cut memory = %d.\n", Mem_FixedReadMaxEntriesUsed(p->pMemSet) );
-    s_MappingTime = clock() - clkTotal;
-    return 1;
-}
-
-////////////////////////////////////////////////////////////////////////
-///                       END OF FILE                                ///
-////////////////////////////////////////////////////////////////////////
-
-
diff --git a/abc70930/src/map/if/ifCut.c b/abc70930/src/map/if/ifCut.c
deleted file mode 100644
index 1a7ecc2c..00000000
--- a/abc70930/src/map/if/ifCut.c
+++ /dev/null
@@ -1,777 +0,0 @@
-/**CFile****************************************************************
-
-  FileName    [ifCut.c]
-
-  SystemName  [ABC: Logic synthesis and verification system.]
-
-  PackageName [FPGA mapping based on priority cuts.]
-
-  Synopsis    [Cut computation.]
-
-  Author      [Alan Mishchenko]
-  
-  Affiliation [UC Berkeley]
-
-  Date        [Ver. 1.0. Started - November 21, 2006.]
-
-  Revision    [$Id: ifCut.c,v 1.00 2006/11/21 00:00:00 alanmi Exp $]
-
-***********************************************************************/
-
-#include "if.h"
-
-////////////////////////////////////////////////////////////////////////
-///                        DECLARATIONS                              ///
-////////////////////////////////////////////////////////////////////////
-
-////////////////////////////////////////////////////////////////////////
-///                     FUNCTION DEFINITIONS                         ///
-////////////////////////////////////////////////////////////////////////
-
-
-/**Function*************************************************************
-
-  Synopsis    [Returns 1 if pDom is contained in pCut.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-static inline int If_CutCheckDominance( If_Cut_t * pDom, If_Cut_t * pCut )
-{
-    int i, k;
-    for ( i = 0; i < (int)pDom->nLeaves; i++ )
-    {
-        for ( k = 0; k < (int)pCut->nLeaves; k++ )
-            if ( pDom->pLeaves[i] == pCut->pLeaves[k] )
-                break;
-        if ( k == (int)pCut->nLeaves ) // node i in pDom is not contained in pCut
-            return 0;
-    }
-    // every node in pDom is contained in pCut
-    return 1;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Returns 1 if pDom is equal to pCut.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-static inline int If_CutCheckEquality( If_Cut_t * pDom, If_Cut_t * pCut )
-{
-    int i;
-    if ( (int)pDom->nLeaves != (int)pCut->nLeaves )
-        return 0;
-    for ( i = 0; i < (int)pDom->nLeaves; i++ )
-        if ( pDom->pLeaves[i] != pCut->pLeaves[i] )
-            return 0;
-    return 1;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Returns 1 if the cut is contained.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int If_CutFilter( If_Set_t * pCutSet, If_Cut_t * pCut )
-{ 
-    If_Cut_t * pTemp;
-    int i, k;
-    assert( pCutSet->ppCuts[pCutSet->nCuts] == pCut );
-    for ( i = 0; i < pCutSet->nCuts; i++ )
-    {
-        pTemp = pCutSet->ppCuts[i];
-        if ( pTemp->nLeaves > pCut->nLeaves )
-        {
-            // do not fiter the first cut
-            if ( i == 0 )
-                continue;
-            // skip the non-contained cuts
-            if ( (pTemp->uSign & pCut->uSign) != pCut->uSign )
-                continue;
-            // check containment seriously
-            if ( If_CutCheckDominance( pCut, pTemp ) )
-            {
-//                p->ppCuts[i] = p->ppCuts[p->nCuts-1];
-//                p->ppCuts[p->nCuts-1] = pTemp;
-//                p->nCuts--;
-//                i--;
-                // remove contained cut
-                for ( k = i; k < pCutSet->nCuts; k++ )
-                    pCutSet->ppCuts[k] = pCutSet->ppCuts[k+1];
-                pCutSet->ppCuts[pCutSet->nCuts] = pTemp;
-                pCutSet->nCuts--;
-                i--;
-            }
-         }
-        else
-        {
-            // skip the non-contained cuts
-            if ( (pTemp->uSign & pCut->uSign) != pTemp->uSign )
-                continue;
-            // check containment seriously
-            if ( If_CutCheckDominance( pTemp, pCut ) )
-                return 1;
-        }
-    }
-    return 0;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Merges two cuts.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-static inline int If_CutMergeOrdered( If_Cut_t * pC0, If_Cut_t * pC1, If_Cut_t * pC )
-{ 
-    int i, k, c;
-    assert( pC0->nLeaves >= pC1->nLeaves );
-    // the case of the largest cut sizes
-    if ( pC0->nLeaves == pC->nLimit && pC1->nLeaves == pC->nLimit )
-    {
-        for ( i = 0; i < (int)pC0->nLeaves; i++ )
-            if ( pC0->pLeaves[i] != pC1->pLeaves[i] )
-                return 0;
-        for ( i = 0; i < (int)pC0->nLeaves; i++ )
-            pC->pLeaves[i] = pC0->pLeaves[i];
-        pC->nLeaves = pC0->nLeaves;
-        return 1;
-    }
-    // the case when one of the cuts is the largest
-    if ( pC0->nLeaves == pC->nLimit )
-    {
-        for ( i = 0; i < (int)pC1->nLeaves; i++ )
-        {
-            for ( k = (int)pC0->nLeaves - 1; k >= 0; k-- )
-                if ( pC0->pLeaves[k] == pC1->pLeaves[i] )
-                    break;
-            if ( k == -1 ) // did not find
-                return 0;
-        }
-        for ( i = 0; i < (int)pC0->nLeaves; i++ )
-            pC->pLeaves[i] = pC0->pLeaves[i];
-        pC->nLeaves = pC0->nLeaves;
-        return 1;
-    }
-
-    // compare two cuts with different numbers
-    i = k = 0;
-    for ( c = 0; c < (int)pC->nLimit; c++ )
-    {
-        if ( k == (int)pC1->nLeaves )
-        {
-            if ( i == (int)pC0->nLeaves )
-            {
-                pC->nLeaves = c;
-                return 1;
-            }
-            pC->pLeaves[c] = pC0->pLeaves[i++];
-            continue;
-        }
-        if ( i == (int)pC0->nLeaves )
-        {
-            if ( k == (int)pC1->nLeaves )
-            {
-                pC->nLeaves = c;
-                return 1;
-            }
-            pC->pLeaves[c] = pC1->pLeaves[k++];
-            continue;
-        }
-        if ( pC0->pLeaves[i] < pC1->pLeaves[k] )
-        {
-            pC->pLeaves[c] = pC0->pLeaves[i++];
-            continue;
-        }
-        if ( pC0->pLeaves[i] > pC1->pLeaves[k] )
-        {
-            pC->pLeaves[c] = pC1->pLeaves[k++];
-            continue;
-        }
-        pC->pLeaves[c] = pC0->pLeaves[i++]; 
-        k++;
-    }
-    if ( i < (int)pC0->nLeaves || k < (int)pC1->nLeaves )
-        return 0;
-    pC->nLeaves = c;
-    return 1;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Merges two cuts.]
-
-  Description [Special case when the cut is known to exist.]
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-static inline int If_CutMergeOrdered2( If_Cut_t * pC0, If_Cut_t * pC1, If_Cut_t * pC )
-{ 
-    int i, k, c;
-    assert( pC0->nLeaves >= pC1->nLeaves );
-    // copy the first cut
-    for ( i = 0; i < (int)pC0->nLeaves; i++ )
-        pC->pLeaves[i] = pC0->pLeaves[i];
-    pC->nLeaves = pC0->nLeaves;
-    // the case when one of the cuts is the largest
-    if ( pC0->nLeaves == pC->nLimit )
-        return 1;
-    // add nodes of the second cut
-    k = 0;
-    for ( i = 0; i < (int)pC1->nLeaves; i++ )
-    {
-        // find k-th node before which i-th node should be added
-        for ( ; k < (int)pC->nLeaves; k++ )
-            if ( pC->pLeaves[k] >= pC1->pLeaves[i] )
-                break;
-        // check the case when this should be the last node
-        if ( k == (int)pC->nLeaves )
-        {
-            pC->pLeaves[k++] = pC1->pLeaves[i];
-            pC->nLeaves++;
-            continue;
-        }
-        // check the case when equal node is found
-        if ( pC1->pLeaves[i] == pC->pLeaves[k] )
-            continue;
-        // add the node
-        for ( c = (int)pC->nLeaves; c > k; c-- )
-            pC->pLeaves[c] = pC->pLeaves[c-1];
-        pC->pLeaves[k++] = pC1->pLeaves[i];
-        pC->nLeaves++;
-    }
-/*
-    assert( pC->nLeaves <= pC->nLimit );
-    for ( i = 1; i < (int)pC->nLeaves; i++ )
-        assert( pC->pLeaves[i-1] < pC->pLeaves[i] );
-*/
-    return 1;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Prepares the object for FPGA mapping.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int If_CutMerge( If_Cut_t * pCut0, If_Cut_t * pCut1, If_Cut_t * pCut )
-{ 
-    assert( pCut->nLimit > 0 );
-    // merge the nodes
-    if ( pCut0->nLeaves < pCut1->nLeaves )
-    {
-        if ( !If_CutMergeOrdered( pCut1, pCut0, pCut ) )
-            return 0;
-    }
-    else
-    {
-        if ( !If_CutMergeOrdered( pCut0, pCut1, pCut ) )
-            return 0;
-    }
-    pCut->uSign = pCut0->uSign | pCut1->uSign;
-    return 1;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Prepares the object for FPGA mapping.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int If_CutCompareDelay( If_Cut_t ** ppC0, If_Cut_t ** ppC1 )
-{
-    If_Cut_t * pC0 = *ppC0;
-    If_Cut_t * pC1 = *ppC1;
-    if ( pC0->Delay < pC1->Delay - 0.0001 )
-        return -1;
-    if ( pC0->Delay > pC1->Delay + 0.0001 )
-        return 1;
-    if ( pC0->nLeaves < pC1->nLeaves )
-        return -1;
-    if ( pC0->nLeaves > pC1->nLeaves )
-        return 1;
-    if ( pC0->Area < pC1->Area - 0.0001 )
-        return -1;
-    if ( pC0->Area > pC1->Area + 0.0001 )
-        return 1;
-    return 0;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Prepares the object for FPGA mapping.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int If_CutCompareDelayOld( If_Cut_t ** ppC0, If_Cut_t ** ppC1 )
-{
-    If_Cut_t * pC0 = *ppC0;
-    If_Cut_t * pC1 = *ppC1;
-    if ( pC0->Delay < pC1->Delay - 0.0001 )
-        return -1;
-    if ( pC0->Delay > pC1->Delay + 0.0001 )
-        return 1;
-    if ( pC0->Area < pC1->Area - 0.0001 )
-        return -1;
-    if ( pC0->Area > pC1->Area + 0.0001 )
-        return 1;
-    if ( pC0->nLeaves < pC1->nLeaves )
-        return -1;
-    if ( pC0->nLeaves > pC1->nLeaves )
-        return 1;
-    return 0;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Prepares the object for FPGA mapping.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int If_CutCompareArea( If_Cut_t ** ppC0, If_Cut_t ** ppC1 )
-{
-    If_Cut_t * pC0 = *ppC0;
-    If_Cut_t * pC1 = *ppC1;
-    if ( pC0->Area < pC1->Area - 0.0001 )
-        return -1;
-    if ( pC0->Area > pC1->Area + 0.0001 )
-        return 1;
-    if ( pC0->AveRefs > pC1->AveRefs )
-        return -1;
-    if ( pC0->AveRefs < pC1->AveRefs )
-        return 1;
-    if ( pC0->nLeaves < pC1->nLeaves )
-        return -1;
-    if ( pC0->nLeaves > pC1->nLeaves )
-        return 1;
-    if ( pC0->Delay < pC1->Delay - 0.0001 )
-        return -1;
-    if ( pC0->Delay > pC1->Delay + 0.0001 )
-        return 1;
-    return 0;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Sorts the cuts.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void If_ManSortCuts( If_Man_t * p, int Mode )
-{
-/*
-    // sort the cuts
-    if ( Mode || p->pPars->fArea ) // area
-        qsort( p->ppCuts, p->nCuts, sizeof(If_Cut_t *), (int (*)(const void *, const void *))If_CutCompareArea );
-    else if ( p->pPars->fFancy )
-        qsort( p->ppCuts, p->nCuts, sizeof(If_Cut_t *), (int (*)(const void *, const void *))If_CutCompareDelayOld );
-    else
-        qsort( p->ppCuts, p->nCuts, sizeof(If_Cut_t *), (int (*)(const void *, const void *))If_CutCompareDelay );
-*/
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Comparison function for two cuts.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-static inline int If_ManSortCompare( If_Man_t * p, If_Cut_t * pC0, If_Cut_t * pC1 )
-{
-    if ( p->SortMode == 1 ) // area
-    {
-        if ( pC0->Area < pC1->Area - 0.0001 )
-            return -1;
-        if ( pC0->Area > pC1->Area + 0.0001 )
-            return 1;
-        if ( pC0->AveRefs > pC1->AveRefs )
-            return -1;
-        if ( pC0->AveRefs < pC1->AveRefs )
-            return 1;
-        if ( pC0->nLeaves < pC1->nLeaves )
-            return -1;
-        if ( pC0->nLeaves > pC1->nLeaves )
-            return 1;
-        if ( pC0->Delay < pC1->Delay - 0.0001 )
-            return -1;
-        if ( pC0->Delay > pC1->Delay + 0.0001 )
-            return 1;
-        return 0;
-    }
-    if ( p->SortMode == 0 ) // delay
-    {
-        if ( pC0->Delay < pC1->Delay - 0.0001 )
-            return -1;
-        if ( pC0->Delay > pC1->Delay + 0.0001 )
-            return 1;
-        if ( pC0->nLeaves < pC1->nLeaves )
-            return -1;
-        if ( pC0->nLeaves > pC1->nLeaves )
-            return 1;
-        if ( pC0->Area < pC1->Area - 0.0001 )
-            return -1;
-        if ( pC0->Area > pC1->Area + 0.0001 )
-            return 1;
-        return 0;
-    }
-    assert( p->SortMode == 2 ); // delay old
-    if ( pC0->Delay < pC1->Delay - 0.0001 )
-        return -1;
-    if ( pC0->Delay > pC1->Delay + 0.0001 )
-        return 1;
-    if ( pC0->Area < pC1->Area - 0.0001 )
-        return -1;
-    if ( pC0->Area > pC1->Area + 0.0001 )
-        return 1;
-    if ( pC0->nLeaves < pC1->nLeaves )
-        return -1;
-    if ( pC0->nLeaves > pC1->nLeaves )
-        return 1;
-    return 0;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Performs incremental sorting of cuts.]
-
-  Description [Currently only the trivial sorting is implemented.]
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void If_CutSort( If_Man_t * p, If_Set_t * pCutSet, If_Cut_t * pCut )
-{
-//    int Counter = 0;
-    int i;
-
-    // the new cut is the last one
-    assert( pCutSet->ppCuts[pCutSet->nCuts] == pCut );
-    assert( pCutSet->nCuts <= pCutSet->nCutsMax );
-
-    // cut structure is empty
-    if ( pCutSet->nCuts == 0 )
-    {
-        pCutSet->nCuts++;
-        return;
-    }
-
-    // the cut will be added - find its place
-    for ( i = pCutSet->nCuts-1; i >= 0; i-- )
-    {
-//        Counter++;
-        if ( If_ManSortCompare( p, pCutSet->ppCuts[i], pCut ) <= 0 )
-            break;
-        pCutSet->ppCuts[i+1] = pCutSet->ppCuts[i];
-        pCutSet->ppCuts[i] = pCut;
-    }
-//    printf( "%d ", Counter );
-
-    // update the number of cuts
-    if ( pCutSet->nCuts < pCutSet->nCutsMax )
-        pCutSet->nCuts++;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Computes area flow.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-float If_CutFlow( If_Man_t * p, If_Cut_t * pCut )
-{
-    If_Obj_t * pLeaf;
-    float Flow;
-    int i;
-    assert( p->pPars->fSeqMap || pCut->nLeaves > 1 );
-    Flow = If_CutLutArea(p, pCut);
-    If_CutForEachLeaf( p, pCut, pLeaf, i )
-    {
-        if ( pLeaf->nRefs == 0 )
-            Flow += If_ObjCutBest(pLeaf)->Area;
-        else if ( p->pPars->fSeqMap ) // seq
-            Flow += If_ObjCutBest(pLeaf)->Area / pLeaf->nRefs;
-        else 
-        {
-            assert( pLeaf->EstRefs > p->fEpsilon );
-            Flow += If_ObjCutBest(pLeaf)->Area / pLeaf->EstRefs;
-        }
-    }
-    return Flow;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Average number of references of the leaves.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-float If_CutAverageRefs( If_Man_t * p, If_Cut_t * pCut )
-{
-    If_Obj_t * pLeaf;
-    int nRefsTotal, i;
-    assert( p->pPars->fSeqMap || pCut->nLeaves > 1 );
-    nRefsTotal = 0;
-    If_CutForEachLeaf( p, pCut, pLeaf, i )
-        nRefsTotal += pLeaf->nRefs;
-    return ((float)nRefsTotal)/pCut->nLeaves;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Computes area of the first level.]
-
-  Description [The cut need to be derefed.]
-               
-  SideEffects []
-
-  SeeAlso     []
- 
-***********************************************************************/
-float If_CutDeref( If_Man_t * p, If_Cut_t * pCut, int nLevels )
-{
-    If_Obj_t * pLeaf;
-    float Area;
-    int i;
-    Area = If_CutLutArea(p, pCut);
-    If_CutForEachLeaf( p, pCut, pLeaf, i )
-    {
-        assert( pLeaf->nRefs > 0 );
-        if ( --pLeaf->nRefs > 0 || !If_ObjIsAnd(pLeaf) || nLevels == 1 )
-            continue;
-        Area += If_CutDeref( p, If_ObjCutBest(pLeaf), nLevels - 1 );
-    }
-    return Area;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Computes area of the first level.]
-
-  Description [The cut need to be derefed.]
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-float If_CutRef( If_Man_t * p, If_Cut_t * pCut, int nLevels )
-{
-    If_Obj_t * pLeaf;
-    float Area;
-    int i;
-    Area = If_CutLutArea(p, pCut);
-    If_CutForEachLeaf( p, pCut, pLeaf, i )
-    {
-        assert( pLeaf->nRefs >= 0 );
-        if ( pLeaf->nRefs++ > 0 || !If_ObjIsAnd(pLeaf) || nLevels == 1 )
-            continue;
-        Area += If_CutRef( p, If_ObjCutBest(pLeaf), nLevels - 1 );
-    }
-    return Area;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Prints one cut.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void If_CutPrint( If_Man_t * p, If_Cut_t * pCut )
-{
-    unsigned i;
-    printf( "{" );
-    for ( i = 0; i < pCut->nLeaves; i++ )
-        printf( " %d", pCut->pLeaves[i] );
-    printf( " }\n" );
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Prints one cut.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void If_CutPrintTiming( If_Man_t * p, If_Cut_t * pCut )
-{
-    If_Obj_t * pLeaf;
-    unsigned i;
-    printf( "{" );
-    If_CutForEachLeaf( p, pCut, pLeaf, i )
-        printf( " %d(%.2f/%.2f)", pLeaf->Id, If_ObjCutBest(pLeaf)->Delay, pLeaf->Required );
-    printf( " }\n" );
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Computes area of the first level.]
-
-  Description [The cut need to be derefed.]
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-float If_CutAreaDerefed( If_Man_t * p, If_Cut_t * pCut, int nLevels )
-{
-    float aResult, aResult2;
-    assert( p->pPars->fSeqMap || pCut->nLeaves > 1 );
-    aResult2 = If_CutRef( p, pCut, nLevels );
-    aResult  = If_CutDeref( p, pCut, nLevels );
-    assert( aResult > aResult2 - p->fEpsilon );
-    assert( aResult < aResult2 + p->fEpsilon );
-    return aResult;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Computes area of the first level.]
-
-  Description [The cut need to be derefed.]
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-float If_CutAreaRefed( If_Man_t * p, If_Cut_t * pCut, int nLevels )
-{
-    float aResult, aResult2;
-    assert( p->pPars->fSeqMap || pCut->nLeaves > 1 );
-    aResult2 = If_CutDeref( p, pCut, nLevels );
-    aResult  = If_CutRef( p, pCut, nLevels );
-    assert( aResult > aResult2 - p->fEpsilon );
-    assert( aResult < aResult2 + p->fEpsilon );
-    return aResult;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Moves the cut over the latch.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void If_CutLift( If_Cut_t * pCut )
-{
-    unsigned i;
-    for ( i = 0; i < pCut->nLeaves; i++ )
-    {
-        assert( (pCut->pLeaves[i] & 255) < 255 );
-        pCut->pLeaves[i]++;
-    }
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Computes area of the first level.]
-
-  Description [The cut need to be derefed.]
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void If_CutCopy( If_Man_t * p, If_Cut_t * pCutDest, If_Cut_t * pCutSrc )
-{
-    int * pLeaves;
-    char * pPerm;
-    unsigned * pTruth;
-    // save old arrays
-    pLeaves = pCutDest->pLeaves;
-    pPerm   = pCutDest->pPerm;
-    pTruth  = pCutDest->pTruth;
-    // copy the cut info
-    memcpy( pCutDest, pCutSrc, p->nCutBytes );
-    // restore the arrays
-    pCutDest->pLeaves = pLeaves;
-    pCutDest->pPerm   = pPerm;
-    pCutDest->pTruth  = pTruth;
-}
-
-////////////////////////////////////////////////////////////////////////
-///                       END OF FILE                                ///
-////////////////////////////////////////////////////////////////////////
-
-
diff --git a/abc70930/src/map/if/ifMan.c b/abc70930/src/map/if/ifMan.c
deleted file mode 100644
index b713d80d..00000000
--- a/abc70930/src/map/if/ifMan.c
+++ /dev/null
@@ -1,570 +0,0 @@
-/**CFile****************************************************************
-
-  FileName    [ifMan.c]
-
-  SystemName  [ABC: Logic synthesis and verification system.]
-
-  PackageName [FPGA mapping based on priority cuts.]
-
-  Synopsis    [Mapping manager.]
-
-  Author      [Alan Mishchenko]
-  
-  Affiliation [UC Berkeley]
-
-  Date        [Ver. 1.0. Started - November 21, 2006.]
-
-  Revision    [$Id: ifMan.c,v 1.00 2006/11/21 00:00:00 alanmi Exp $]
-
-***********************************************************************/
-
-#include "if.h"
-
-////////////////////////////////////////////////////////////////////////
-///                        DECLARATIONS                              ///
-////////////////////////////////////////////////////////////////////////
-
-static If_Obj_t * If_ManSetupObj( If_Man_t * p );
-
-static void       If_ManCutSetRecycle( If_Man_t * p, If_Set_t * pSet ) { pSet->pNext = p->pFreeList; p->pFreeList = pSet;                            }
-static If_Set_t * If_ManCutSetFetch( If_Man_t * p )                    { If_Set_t * pTemp = p->pFreeList; p->pFreeList = p->pFreeList->pNext; return pTemp; }
-
-////////////////////////////////////////////////////////////////////////
-///                     FUNCTION DEFINITIONS                         ///
-////////////////////////////////////////////////////////////////////////
-
-/**Function*************************************************************
-
-  Synopsis    [Starts the AIG manager.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-If_Man_t * If_ManStart( If_Par_t * pPars )
-{
-    If_Man_t * p;
-    // start the manager
-    p = ALLOC( If_Man_t, 1 );
-    memset( p, 0, sizeof(If_Man_t) );
-    p->pPars = pPars;
-    p->fEpsilon = (float)0.001;
-    // allocate arrays for nodes
-    p->vCis    = Vec_PtrAlloc( 100 );
-    p->vCos    = Vec_PtrAlloc( 100 );
-    p->vObjs   = Vec_PtrAlloc( 100 );
-    p->vMapped = Vec_PtrAlloc( 100 );
-    p->vTemp   = Vec_PtrAlloc( 100 );
-    // prepare the memory manager
-    p->nTruthWords = p->pPars->fTruth? If_CutTruthWords( p->pPars->nLutSize ) : 0;
-    p->nPermWords  = p->pPars->fUsePerm? If_CutPermWords( p->pPars->nLutSize ) : 0;
-    p->nObjBytes   = sizeof(If_Obj_t) + sizeof(int) * (p->pPars->nLutSize + p->nPermWords + p->nTruthWords);
-    p->nCutBytes   = sizeof(If_Cut_t) + sizeof(int) * (p->pPars->nLutSize + p->nPermWords + p->nTruthWords);
-    p->nSetBytes   = sizeof(If_Set_t) + (sizeof(If_Cut_t *) + p->nCutBytes) * (p->pPars->nCutsMax + 1);
-    p->pMemObj     = Mem_FixedStart( p->nObjBytes );
-//    p->pMemSet     = Mem_FixedStart( p->nSetBytes );
-    // report expected memory usage
-    if ( p->pPars->fVerbose )
-        printf( "Memory (bytes): Truth = %4d. Cut = %4d. Obj = %4d. Set = %4d.\n", 
-            4 * p->nTruthWords, p->nCutBytes, p->nObjBytes, p->nSetBytes );
-    // room for temporary truth tables
-    p->puTemp[0] = p->pPars->fTruth? ALLOC( unsigned, 4 * p->nTruthWords ) : NULL;
-    p->puTemp[1] = p->puTemp[0] + p->nTruthWords;
-    p->puTemp[2] = p->puTemp[1] + p->nTruthWords;
-    p->puTemp[3] = p->puTemp[2] + p->nTruthWords;
-    // create the constant node
-    p->pConst1 = If_ManSetupObj( p );
-    p->pConst1->Type = IF_CONST1;
-    p->pConst1->fPhase = 1;
-    p->nObjs[IF_CONST1]++;
-    return p;
-}
-
-/**Function*************************************************************
-
-  Synopsis    []
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void If_ManRestart( If_Man_t * p )
-{
-    FREE( p->pMemCi );
-    Vec_PtrClear( p->vCis );
-    Vec_PtrClear( p->vCos );
-    Vec_PtrClear( p->vObjs );
-    Vec_PtrClear( p->vMapped );
-    Vec_PtrClear( p->vTemp );
-    Mem_FixedRestart( p->pMemObj );
-    // create the constant node
-    p->pConst1 = If_ManSetupObj( p );
-    p->pConst1->Type = IF_CONST1;
-    p->pConst1->fPhase = 1;
-    // reset the counter of other nodes
-    p->nObjs[IF_CI] = p->nObjs[IF_CO] = p->nObjs[IF_AND] = 0;
-}
-
-/**Function*************************************************************
-
-  Synopsis    []
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void If_ManStop( If_Man_t * p )
-{
-    Vec_PtrFree( p->vCis );
-    Vec_PtrFree( p->vCos );
-    Vec_PtrFree( p->vObjs );
-    Vec_PtrFree( p->vMapped );
-    Vec_PtrFree( p->vTemp );
-    if ( p->vLatchOrder ) Vec_PtrFree( p->vLatchOrder );
-    if ( p->vLags ) Vec_IntFree( p->vLags );
-    Mem_FixedStop( p->pMemObj, 0 );
-    FREE( p->pMemCi );
-    FREE( p->pMemAnd );
-    FREE( p->puTemp[0] );
-    // free pars memory
-    if ( p->pPars->pTimesArr )
-        FREE( p->pPars->pTimesArr );
-    if ( p->pPars->pTimesReq )
-        FREE( p->pPars->pTimesReq );
-    free( p );
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Creates primary input.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-If_Obj_t * If_ManCreateCi( If_Man_t * p )
-{
-    If_Obj_t * pObj;
-    pObj = If_ManSetupObj( p );
-    pObj->Type = IF_CI;
-    Vec_PtrPush( p->vCis, pObj );
-    p->nObjs[IF_CI]++;
-    return pObj;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Creates primary output with the given driver.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-If_Obj_t * If_ManCreateCo( If_Man_t * p, If_Obj_t * pDriver )
-{
-    If_Obj_t * pObj;
-    pObj = If_ManSetupObj( p );
-    Vec_PtrPush( p->vCos, pObj );
-    pObj->Type = IF_CO;
-    pObj->fCompl0 = If_IsComplement(pDriver); pDriver = If_Regular(pDriver);
-    pObj->pFanin0 = pDriver; pDriver->nRefs++; 
-    p->nObjs[IF_CO]++;
-    return pObj;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Create the new node assuming it does not exist.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-If_Obj_t * If_ManCreateAnd( If_Man_t * p, If_Obj_t * pFan0, If_Obj_t * pFan1 )
-{
-    If_Obj_t * pObj;
-    // perform constant propagation
-    if ( pFan0 == pFan1 )
-        return pFan0;
-    if ( pFan0 == If_Not(pFan1) )
-        return If_Not(p->pConst1);
-    if ( If_Regular(pFan0) == p->pConst1 )
-        return pFan0 == p->pConst1 ? pFan1 : If_Not(p->pConst1);
-    if ( If_Regular(pFan1) == p->pConst1 )
-        return pFan1 == p->pConst1 ? pFan0 : If_Not(p->pConst1);
-    // get memory for the new object
-    pObj = If_ManSetupObj( p );
-    pObj->Type    = IF_AND;
-    pObj->fCompl0 = If_IsComplement(pFan0); pFan0 = If_Regular(pFan0);
-    pObj->fCompl1 = If_IsComplement(pFan1); pFan1 = If_Regular(pFan1);
-    pObj->pFanin0 = pFan0; pFan0->nRefs++; pFan0->nVisits++; pFan0->nVisitsCopy++;
-    pObj->pFanin1 = pFan1; pFan1->nRefs++; pFan1->nVisits++; pFan1->nVisitsCopy++;
-    pObj->fPhase  = (pObj->fCompl0 ^ pFan0->fPhase) & (pObj->fCompl1 ^ pFan1->fPhase);
-    pObj->Level   = 1 + IF_MAX( pFan0->Level, pFan1->Level );
-    if ( p->nLevelMax < (int)pObj->Level )
-        p->nLevelMax = (int)pObj->Level;
-    p->nObjs[IF_AND]++;
-    return pObj;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Create the new node assuming it does not exist.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-If_Obj_t * If_ManCreateXor( If_Man_t * p, If_Obj_t * pFan0, If_Obj_t * pFan1 )
-{
-    If_Obj_t * pRes1, * pRes2;
-    pRes1 = If_ManCreateAnd( p, If_Not(pFan0), pFan1 );
-    pRes2 = If_ManCreateAnd( p, pFan0, If_Not(pFan1) );
-    return If_Not( If_ManCreateAnd( p, If_Not(pRes1), If_Not(pRes2) ) );
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Create the new node assuming it does not exist.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-If_Obj_t * If_ManCreateMux( If_Man_t * p, If_Obj_t * pFan0, If_Obj_t * pFan1, If_Obj_t * pCtrl )
-{
-    If_Obj_t * pRes1, * pRes2;
-    pRes1 = If_ManCreateAnd( p, pFan0, If_Not(pCtrl) );
-    pRes2 = If_ManCreateAnd( p, pFan1, pCtrl );
-    return If_Not( If_ManCreateAnd( p, If_Not(pRes1), If_Not(pRes2) ) );
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Creates the choice node.]
-
-  Description [Should be called after the equivalence class nodes are linked.]
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void If_ManCreateChoice( If_Man_t * p, If_Obj_t * pObj )
-{
-    If_Obj_t * pTemp;
-    // mark the node as a representative if its class
-    assert( pObj->fRepr == 0 );
-    pObj->fRepr = 1;
-    // update the level of this node (needed for correct required time computation)
-    for ( pTemp = pObj; pTemp; pTemp = pTemp->pEquiv )
-    {
-        pObj->Level = IF_MAX( pObj->Level, pTemp->Level );
-        pTemp->nVisits++; pTemp->nVisitsCopy++;
-    }
-    // mark the largest level
-    if ( p->nLevelMax < (int)pObj->Level )
-        p->nLevelMax = (int)pObj->Level;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Prepares memory for one cut.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void If_ManSetupCut( If_Man_t * p, If_Cut_t * pCut )
-{
-    memset( pCut, 0, sizeof(If_Cut_t) );
-    pCut->nLimit  = p->pPars->nLutSize;
-    pCut->pLeaves = (int *)(pCut + 1);
-    if ( p->pPars->fUsePerm )
-        pCut->pPerm  = (char *)(pCut->pLeaves + p->pPars->nLutSize);
-    if ( p->pPars->fTruth )
-        pCut->pTruth = pCut->pLeaves + p->pPars->nLutSize + p->nPermWords;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Prepares memory for one cutset.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void If_ManSetupSet( If_Man_t * p, If_Set_t * pSet )
-{
-    char * pArray;
-    int i;
-    pSet->nCuts = 0;
-    pSet->nCutsMax = p->pPars->nCutsMax;
-    pSet->ppCuts = (If_Cut_t **)(pSet + 1);
-    pArray = (char *)pSet->ppCuts + sizeof(If_Cut_t *) * (pSet->nCutsMax+1);
-    for ( i = 0; i <= pSet->nCutsMax; i++ )
-    {
-        pSet->ppCuts[i] = (If_Cut_t *)(pArray + i * p->nCutBytes); 
-        If_ManSetupCut( p, pSet->ppCuts[i] );
-    }
-//    pArray += (pSet->nCutsMax + 1) * p->nCutBytes;
-//    assert( ((char *)pArray) - ((char *)pSet) == p->nSetBytes );
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Prepares memory for one cut.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void If_ManSetupCutTriv( If_Man_t * p, If_Cut_t * pCut, int ObjId )
-{
-    pCut->fCompl     = 0;
-    pCut->nLimit     = p->pPars->nLutSize;
-    pCut->nLeaves    = 1;
-    pCut->pLeaves[0] = p->pPars->fLiftLeaves? (ObjId << 8) : ObjId;
-    pCut->uSign      = If_ObjCutSign( pCut->pLeaves[0] );
-    // set up elementary truth table of the unit cut
-    if ( p->pPars->fTruth )
-    {
-        int i, nTruthWords;
-        nTruthWords = pCut->nLimit <= 5 ? 1 : (1 << (pCut->nLimit - 5));
-        for ( i = 0; i < nTruthWords; i++ )
-            If_CutTruth(pCut)[i] = 0xAAAAAAAA;
-    }
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Prepares memory for the node with cuts.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-If_Obj_t * If_ManSetupObj( If_Man_t * p )
-{
-    If_Obj_t * pObj;
-    // get memory for the object
-    pObj = (If_Obj_t *)Mem_FixedEntryFetch( p->pMemObj );
-    memset( pObj, 0, sizeof(If_Obj_t) );
-    If_ManSetupCut( p, &pObj->CutBest );
-    // assign ID and save 
-    pObj->Id = Vec_PtrSize(p->vObjs);
-    Vec_PtrPush( p->vObjs, pObj );
-    // set the required times
-    pObj->Required = IF_FLOAT_LARGE;
-    return pObj;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Prepares memory for one cut.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void If_ManSetupCiCutSets( If_Man_t * p )
-{
-    If_Obj_t * pObj;
-    int i;
-    assert( p->pMemCi == NULL );
-    // create elementary cuts for the CIs
-    If_ManForEachCi( p, pObj, i )
-        If_ManSetupCutTriv( p, &pObj->CutBest, pObj->Id );
-    // create elementary cutsets for the CIs
-    p->pMemCi = (If_Set_t *)malloc( If_ManCiNum(p) * (sizeof(If_Set_t) + sizeof(void *)) );
-    If_ManForEachCi( p, pObj, i )
-    {
-        pObj->pCutSet = (If_Set_t *)((char *)p->pMemCi + i * (sizeof(If_Set_t) + sizeof(void *)));
-        pObj->pCutSet->nCuts = 1;
-        pObj->pCutSet->nCutsMax = p->pPars->nCutsMax;
-        pObj->pCutSet->ppCuts = (If_Cut_t **)(pObj->pCutSet + 1);
-        pObj->pCutSet->ppCuts[0] = &pObj->CutBest;
-    }
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Prepares cutset of the node.]
-
-  Description [Elementary cutset will be added last.]
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-If_Set_t * If_ManSetupNodeCutSet( If_Man_t * p, If_Obj_t * pObj )
-{
-    assert( If_ObjIsAnd(pObj) );
-    assert( pObj->pCutSet == NULL );
-//    pObj->pCutSet = (If_Set_t *)Mem_FixedEntryFetch( p->pMemSet );
-//    If_ManSetupSet( p, pObj->pCutSet );
-
-    pObj->pCutSet = If_ManCutSetFetch( p );
-    pObj->pCutSet->nCuts = 0;
-    pObj->pCutSet->nCutsMax = p->pPars->nCutsMax;
-
-    return pObj->pCutSet;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Dereferences cutset of the node.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void If_ManDerefNodeCutSet( If_Man_t * p, If_Obj_t * pObj )
-{
-    If_Obj_t * pFanin;
-    assert( If_ObjIsAnd(pObj) );
-    // consider the node
-    assert( pObj->nVisits >= 0 );
-    if ( pObj->nVisits == 0 )
-    {
-//        Mem_FixedEntryRecycle( p->pMemSet, (char *)pObj->pCutSet );
-        If_ManCutSetRecycle( p, pObj->pCutSet );
-        pObj->pCutSet = NULL;
-    }
-    // consider the first fanin
-    pFanin = If_ObjFanin0(pObj);
-    assert( pFanin->nVisits > 0 );
-    if ( !If_ObjIsCi(pFanin) && --pFanin->nVisits == 0 )
-    {
-//        Mem_FixedEntryRecycle( p->pMemSet, (char *)pFanin->pCutSet );
-        If_ManCutSetRecycle( p, pFanin->pCutSet );
-        pFanin->pCutSet = NULL;
-    }
-    // consider the second fanin
-    pFanin = If_ObjFanin1(pObj);
-    assert( pFanin->nVisits > 0 );
-    if ( !If_ObjIsCi(pFanin) && --pFanin->nVisits == 0 )
-    {
-//        Mem_FixedEntryRecycle( p->pMemSet, (char *)pFanin->pCutSet );
-        If_ManCutSetRecycle( p, pFanin->pCutSet );
-        pFanin->pCutSet = NULL;
-    }
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Dereferences cutset of the node.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void If_ManDerefChoiceCutSet( If_Man_t * p, If_Obj_t * pObj )
-{
-    If_Obj_t * pTemp;
-    assert( If_ObjIsAnd(pObj) );
-    assert( pObj->fRepr );
-    assert( pObj->nVisits > 0 );
-    // consider the nodes in the choice class
-    for ( pTemp = pObj; pTemp; pTemp = pTemp->pEquiv )
-    {
-        assert( pTemp == pObj || pTemp->nVisits == 1 );
-        if ( --pTemp->nVisits == 0 )
-        {
-//            Mem_FixedEntryRecycle( p->pMemSet, (char *)pTemp->pCutSet );
-            If_ManCutSetRecycle( p, pTemp->pCutSet );
-            pTemp->pCutSet = NULL;
-        }
-    }
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Dereferences cutset of the node.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void If_ManSetupSetAll( If_Man_t * p, int nCrossCut )
-{
-    If_Set_t * pCutSet;
-    int i, nCutSets;
-    nCutSets = 128 + nCrossCut;
-    p->pFreeList = p->pMemAnd = pCutSet = (If_Set_t *)malloc( nCutSets * p->nSetBytes );
-    for ( i = 0; i < nCutSets; i++ )
-    {
-        If_ManSetupSet( p, pCutSet );
-        if ( i == nCutSets - 1 )
-            pCutSet->pNext = NULL;
-        else
-            pCutSet->pNext = (If_Set_t *)( (char *)pCutSet + p->nSetBytes );
-        pCutSet = pCutSet->pNext;
-    }
-    assert( pCutSet == NULL );
-
-    if ( p->pPars->fVerbose )
-    {
-        printf( "Node = %7d.  Ch = %5d.  Total mem = %7.2f Mb. Peak cut mem = %7.2f Mb.\n", 
-            If_ManAndNum(p), p->nChoices,
-            1.0 * (p->nObjBytes + 2*sizeof(void *)) * If_ManObjNum(p) / (1<<20), 
-            1.0 * p->nSetBytes * nCrossCut / (1<<20) );
-    }
-//    printf( "Cross cut = %d.\n", nCrossCut );
-
-}
-
-////////////////////////////////////////////////////////////////////////
-///                       END OF FILE                                ///
-////////////////////////////////////////////////////////////////////////
-
-
diff --git a/abc70930/src/map/if/ifMap.c b/abc70930/src/map/if/ifMap.c
deleted file mode 100644
index 06ed4d1e..00000000
--- a/abc70930/src/map/if/ifMap.c
+++ /dev/null
@@ -1,300 +0,0 @@
-/**CFile****************************************************************
-
-  FileName    [ifMap.c]
-
-  SystemName  [ABC: Logic synthesis and verification system.]
-
-  PackageName [FPGA mapping based on priority cuts.]
-
-  Synopsis    [Mapping procedures.]
-
-  Author      [Alan Mishchenko]
-  
-  Affiliation [UC Berkeley]
-
-  Date        [Ver. 1.0. Started - November 21, 2006.]
-
-  Revision    [$Id: ifMap.c,v 1.00 2006/11/21 00:00:00 alanmi Exp $]
-
-***********************************************************************/
-
-#include "if.h"
-
-////////////////////////////////////////////////////////////////////////
-///                        DECLARATIONS                              ///
-////////////////////////////////////////////////////////////////////////
-
-////////////////////////////////////////////////////////////////////////
-///                     FUNCTION DEFINITIONS                         ///
-////////////////////////////////////////////////////////////////////////
-
-/**Function*************************************************************
-
-  Synopsis    [Counts the number of 1s in the signature.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-static inline int If_WordCountOnes( unsigned uWord )
-{
-    uWord = (uWord & 0x55555555) + ((uWord>>1) & 0x55555555);
-    uWord = (uWord & 0x33333333) + ((uWord>>2) & 0x33333333);
-    uWord = (uWord & 0x0F0F0F0F) + ((uWord>>4) & 0x0F0F0F0F);
-    uWord = (uWord & 0x00FF00FF) + ((uWord>>8) & 0x00FF00FF);
-    return  (uWord & 0x0000FFFF) + (uWord>>16);
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Finds the best cut for the given node.]
-
-  Description [Mapping modes: delay (0), area flow (1), area (2).]
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void If_ObjPerformMappingAnd( If_Man_t * p, If_Obj_t * pObj, int Mode, int fPreprocess )
-{
-    If_Set_t * pCutSet;
-    If_Cut_t * pCut0, * pCut1, * pCut;
-    int i, k;
-
-    assert( p->pPars->fSeqMap || !If_ObjIsAnd(pObj->pFanin0) || pObj->pFanin0->pCutSet->nCuts > 1 );
-    assert( p->pPars->fSeqMap || !If_ObjIsAnd(pObj->pFanin1) || pObj->pFanin1->pCutSet->nCuts > 1 );
-
-    // prepare
-    if ( !p->pPars->fSeqMap )
-    {
-        if ( Mode == 0 )
-            pObj->EstRefs = (float)pObj->nRefs;
-        else if ( Mode == 1 )
-            pObj->EstRefs = (float)((2.0 * pObj->EstRefs + pObj->nRefs) / 3.0);
-    }
-    if ( Mode && pObj->nRefs > 0 )
-        If_CutDeref( p, If_ObjCutBest(pObj), IF_INFINITY );
-
-    // prepare the cutset
-    pCutSet = If_ManSetupNodeCutSet( p, pObj );
-
-    // get the current assigned best cut
-    pCut = If_ObjCutBest(pObj);
-    if ( pCut->nLeaves > 0 )
-    {
-        // recompute the parameters of the best cut
-        pCut->Delay = If_CutDelay( p, pCut );
-        assert( pCut->Delay <= pObj->Required + p->fEpsilon );
-        pCut->Area = (Mode == 2)? If_CutAreaDerefed( p, pCut, IF_INFINITY ) : If_CutFlow( p, pCut );
-        // save the best cut from the previous iteration
-        if ( !fPreprocess )
-            If_CutCopy( p, pCutSet->ppCuts[pCutSet->nCuts++], pCut );
-    }
-
-    // generate cuts
-    If_ObjForEachCut( pObj->pFanin0, pCut0, i )
-    If_ObjForEachCut( pObj->pFanin1, pCut1, k )
-    {
-        // get the next free cut
-        assert( pCutSet->nCuts <= pCutSet->nCutsMax );
-        pCut = pCutSet->ppCuts[pCutSet->nCuts];
-        // make sure K-feasible cut exists
-        if ( If_WordCountOnes(pCut0->uSign | pCut1->uSign) > p->pPars->nLutSize )
-            continue;
-        // merge the nodes
-        if ( !If_CutMerge( pCut0, pCut1, pCut ) )
-            continue;
-        assert( p->pPars->fSeqMap || pCut->nLeaves > 1 );
-        p->nCutsMerged++;
-        // check if this cut is contained in any of the available cuts
-//        if ( p->pPars->pFuncCost == NULL && If_CutFilter( p, pCut ) ) // do not filter functionality cuts
-        if ( If_CutFilter( pCutSet, pCut ) )
-            continue;
-        // compute the truth table
-        pCut->fCompl = 0;
-        if ( p->pPars->fTruth )
-            If_CutComputeTruth( p, pCut, pCut0, pCut1, pObj->fCompl0, pObj->fCompl1 );
-        // compute the application-specific cost and depth
-        pCut->fUser = (p->pPars->pFuncCost != NULL);
-        pCut->Cost = p->pPars->pFuncCost? p->pPars->pFuncCost(pCut) : 0;
-        if ( pCut->Cost == IF_COST_MAX )
-            continue;
-        // check if the cut satisfies the required times
-        pCut->Delay = If_CutDelay( p, pCut );
-//        printf( "%.2f ", pCut->Delay );
-        if ( Mode && pCut->Delay > pObj->Required + p->fEpsilon )
-            continue;
-        // compute area of the cut (this area may depend on the application specific cost)
-        pCut->Area = (Mode == 2)? If_CutAreaDerefed( p, pCut, IF_INFINITY ) : If_CutFlow( p, pCut );
-        pCut->AveRefs = (Mode == 0)? (float)0.0 : If_CutAverageRefs( p, pCut );
-        // insert the cut into storage
-        If_CutSort( p, pCutSet, pCut );
-    } 
-    assert( pCutSet->nCuts > 0 );
-
-    // add the trivial cut to the set
-    If_ManSetupCutTriv( p, pCutSet->ppCuts[pCutSet->nCuts++], pObj->Id );
-    assert( pCutSet->nCuts <= pCutSet->nCutsMax+1 );
-
-    // update the best cut
-    if ( !fPreprocess || pCutSet->ppCuts[0]->Delay <= pObj->Required + p->fEpsilon )
-        If_CutCopy( p, If_ObjCutBest(pObj), pCutSet->ppCuts[0] );
-    assert( p->pPars->fSeqMap || If_ObjCutBest(pObj)->nLeaves > 1 );
-
-    // ref the selected cut
-    if ( Mode && pObj->nRefs > 0 )
-        If_CutRef( p, If_ObjCutBest(pObj), IF_INFINITY );
-
-    // call the user specified function for each cut
-    if ( p->pPars->pFuncUser )
-        If_ObjForEachCut( pObj, pCut, i )
-            p->pPars->pFuncUser( p, pObj, pCut );
-
-    // free the cuts
-    If_ManDerefNodeCutSet( p, pObj );
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Finds the best cut for the choice node.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void If_ObjPerformMappingChoice( If_Man_t * p, If_Obj_t * pObj, int Mode, int fPreprocess )
-{
-    If_Set_t * pCutSet;
-    If_Obj_t * pTemp;
-    If_Cut_t * pCutTemp, * pCut;
-    int i;
-    assert( pObj->pEquiv != NULL );
-
-    // prepare
-    if ( Mode && pObj->nRefs > 0 )
-        If_CutDeref( p, If_ObjCutBest(pObj), IF_INFINITY );
-
-    // remove elementary cuts
-    for ( pTemp = pObj; pTemp; pTemp = pTemp->pEquiv )
-        pTemp->pCutSet->nCuts--;
-
-    // update the cutset of the node
-    pCutSet = pObj->pCutSet;
-
-    // generate cuts
-    for ( pTemp = pObj->pEquiv; pTemp; pTemp = pTemp->pEquiv )
-    {
-        assert( pTemp->nRefs == 0 );
-        assert( p->pPars->fSeqMap || pTemp->pCutSet->nCuts > 0 );
-        // go through the cuts of this node
-        If_ObjForEachCut( pTemp, pCutTemp, i )
-        {
-            assert( p->pPars->fSeqMap || pCutTemp->nLeaves > 1 );
-            // get the next free cut
-            assert( pCutSet->nCuts <= pCutSet->nCutsMax );
-            pCut = pCutSet->ppCuts[pCutSet->nCuts];
-            // copy the cut into storage
-            If_CutCopy( p, pCut, pCutTemp );
-            // check if this cut is contained in any of the available cuts
-            if ( If_CutFilter( pCutSet, pCut ) )
-                continue;
-            // check if the cut satisfies the required times
-            assert( pCut->Delay == If_CutDelay( p, pCut ) );
-            if ( Mode && pCut->Delay > pObj->Required + p->fEpsilon )
-                continue;
-            // set the phase attribute
-            assert( pCut->fCompl == 0 );
-            pCut->fCompl ^= (pObj->fPhase ^ pTemp->fPhase); // why ^= ?
-            // compute area of the cut (this area may depend on the application specific cost)
-            pCut->Area = (Mode == 2)? If_CutAreaDerefed( p, pCut, IF_INFINITY ) : If_CutFlow( p, pCut );
-            pCut->AveRefs = (Mode == 0)? (float)0.0 : If_CutAverageRefs( p, pCut );
-            // insert the cut into storage
-            If_CutSort( p, pCutSet, pCut );
-        }
-    }
-    assert( pCutSet->nCuts > 0 );
-
-    // add the trivial cut to the set
-    If_ManSetupCutTriv( p, pCutSet->ppCuts[pCutSet->nCuts++], pObj->Id );
-    assert( pCutSet->nCuts <= pCutSet->nCutsMax+1 );
-
-    // update the best cut
-    if ( !fPreprocess || pCutSet->ppCuts[0]->Delay <= pObj->Required + p->fEpsilon )
-        If_CutCopy( p, If_ObjCutBest(pObj), pCutSet->ppCuts[0] );
-    assert( p->pPars->fSeqMap || If_ObjCutBest(pObj)->nLeaves > 1 );
-
-    // ref the selected cut
-    if ( Mode && pObj->nRefs > 0 )
-        If_CutRef( p, If_ObjCutBest(pObj), IF_INFINITY );
-
-    // free the cuts
-    If_ManDerefChoiceCutSet( p, pObj );
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Performs one mapping pass over all nodes.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int If_ManPerformMappingRound( If_Man_t * p, int nCutsUsed, int Mode, int fPreprocess, char * pLabel )
-{
-//    ProgressBar * pProgress;
-    If_Obj_t * pObj;
-    int i, clk = clock();
-    assert( Mode >= 0 && Mode <= 2 );
-    // set the sorting function
-    if ( Mode || p->pPars->fArea ) // area
-        p->SortMode = 1;
-    else if ( p->pPars->fFancy )
-        p->SortMode = 2;
-    else
-        p->SortMode = 0;
-    // set the cut number
-    p->nCutsUsed   = nCutsUsed;
-    p->nCutsMerged = 0;
-    // map the internal nodes
-//    pProgress = Extra_ProgressBarStart( stdout, If_ManObjNum(p) );
-    If_ManForEachNode( p, pObj, i )
-    {
-//        Extra_ProgressBarUpdate( pProgress, i, pLabel );
-        If_ObjPerformMappingAnd( p, pObj, Mode, fPreprocess );
-        if ( pObj->fRepr )
-            If_ObjPerformMappingChoice( p, pObj, Mode, fPreprocess );
-    }
-//    Extra_ProgressBarStop( pProgress );
-    // make sure the visit counters are all zero
-    If_ManForEachNode( p, pObj, i )
-        assert( pObj->nVisits == 0 );
-    // compute required times and stats
-    If_ManComputeRequired( p );
-    if ( p->pPars->fVerbose )
-    {
-        char Symb = fPreprocess? 'P' : ((Mode == 0)? 'D' : ((Mode == 1)? 'F' : 'A'));
-        printf( "%c: Del = %7.2f. Ar = %9.1f. Edge = %8d. Cut = %8d. ", 
-            Symb, p->RequiredGlo, p->AreaGlo, p->nNets, p->nCutsMerged );
-        PRT( "T", clock() - clk );
-//    printf( "Max number of cuts = %d. Average number of cuts = %5.2f.\n", 
-//        p->nCutsMax, 1.0 * p->nCutsMerged / If_ManAndNum(p) );
-    }
-    return 1;
-}
-
-
-////////////////////////////////////////////////////////////////////////
-///                       END OF FILE                                ///
-////////////////////////////////////////////////////////////////////////
-
-
diff --git a/abc70930/src/map/if/ifReduce.c b/abc70930/src/map/if/ifReduce.c
deleted file mode 100644
index 5dfda661..00000000
--- a/abc70930/src/map/if/ifReduce.c
+++ /dev/null
@@ -1,574 +0,0 @@
-/**CFile****************************************************************
-
-  FileName    [ifExpand.c]
-
-  SystemName  [ABC: Logic synthesis and verification system.]
-
-  PackageName [FPGA mapping based on priority cuts.]
-
-  Synopsis    [Incremental improvement of current mapping.]
-
-  Author      [Alan Mishchenko]
-  
-  Affiliation [UC Berkeley]
-
-  Date        [Ver. 1.0. Started - November 21, 2006.]
-
-  Revision    [$Id: ifExpand.c,v 1.00 2006/11/21 00:00:00 alanmi Exp $]
-
-***********************************************************************/
-
-#include "if.h"
-
-////////////////////////////////////////////////////////////////////////
-///                        DECLARATIONS                              ///
-////////////////////////////////////////////////////////////////////////
-
-static void If_ManImproveReduce( If_Man_t * p, int nLimit );
-static void If_ManImproveExpand( If_Man_t * p, int nLimit );
-static void If_ManImproveNodeExpand( If_Man_t * p, If_Obj_t * pObj, int nLimit, Vec_Ptr_t * vFront, Vec_Ptr_t * vFrontOld, Vec_Ptr_t * vVisited );
-static void If_ManImproveNodePrepare( If_Man_t * p, If_Obj_t * pObj, int nLimit, Vec_Ptr_t * vFront, Vec_Ptr_t * vFrontOld, Vec_Ptr_t * vVisited );
-static void If_ManImproveNodeUpdate( If_Man_t * p, If_Obj_t * pObj, Vec_Ptr_t * vFront );
-static void If_ManImproveNodeFaninCompact( If_Man_t * p, If_Obj_t * pObj, int nLimit, Vec_Ptr_t * vFront, Vec_Ptr_t * vVisited );
-
-////////////////////////////////////////////////////////////////////////
-///                     FUNCTION DEFINITIONS                         ///
-////////////////////////////////////////////////////////////////////////
-
-/**Function*************************************************************
-
-  Synopsis    [Improves current mapping using expand/Expand of one cut.]
-
-  Description [Assumes current mapping assigned and required times computed.]
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void If_ManImproveMapping( If_Man_t * p )
-{
-    int clk;
-
-    clk = clock();
-    If_ManImproveExpand( p, p->pPars->nLutSize );
-    If_ManComputeRequired( p );
-    if ( p->pPars->fVerbose )
-    {
-        printf( "E: Del = %7.2f. Ar = %9.1f. Edge = %8d. Cut = %8d. ", 
-            p->RequiredGlo, p->AreaGlo, p->nNets, p->nCutsMerged );
-        PRT( "T", clock() - clk );
-    }
- 
-/*
-    clk = clock();
-    If_ManImproveReduce( p, p->pPars->nLutSize );
-    If_ManComputeRequired( p, 0 );
-    if ( p->pPars->fVerbose )
-    {
-        printf( "R:  Del = %6.2f. Area = %8.2f. Nets = %6d. Cuts = %8d. Lim = %2d. Ave = %5.2f. ", 
-            p->RequiredGlo, p->AreaGlo, p->nNets, p->nCutsMerged, p->nCutsUsed, 1.0 * p->nCutsMerged / If_ManAndNum(p) );
-        PRT( "T", clock() - clk );
-    }
-*/
-/*
-    clk = clock();
-    If_ManImproveExpand( p, p->pPars->nLutSize );
-    If_ManComputeRequired( p, 0 );
-    if ( p->pPars->fVerbose )
-    {
-        printf( "E:  Del = %6.2f. Area = %8.2f. Nets = %6d. Cuts = %8d. Lim = %2d. Ave = %5.2f. ", 
-            p->RequiredGlo, p->AreaGlo, p->nNets, p->nCutsMerged, p->nCutsUsed, 1.0 * p->nCutsMerged / If_ManAndNum(p) );
-        PRT( "T", clock() - clk );
-    }
-*/
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Performs area recovery for each node.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void If_ManImproveExpand( If_Man_t * p, int nLimit )
-{
-    Vec_Ptr_t * vFront, * vFrontOld, * vVisited;
-    If_Obj_t * pObj;
-    int i;
-    vFront    = Vec_PtrAlloc( nLimit );
-    vFrontOld = Vec_PtrAlloc( nLimit );
-    vVisited  = Vec_PtrAlloc( 100 );
-    // iterate through all nodes in the topological order
-    If_ManForEachNode( p, pObj, i )
-        If_ManImproveNodeExpand( p, pObj, nLimit, vFront, vFrontOld, vVisited );
-    Vec_PtrFree( vFront );
-    Vec_PtrFree( vFrontOld );
-    Vec_PtrFree( vVisited );
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Counts the number of nodes with no external fanout.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int If_ManImproveCutCost( If_Man_t * p, Vec_Ptr_t * vFront )
-{
-    If_Obj_t * pFanin;
-    int i, Counter = 0;
-    Vec_PtrForEachEntry( vFront, pFanin, i )
-        if ( pFanin->nRefs == 0 )
-            Counter++;
-    return Counter;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Performs area recovery for each node.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void If_ManImproveNodeExpand( If_Man_t * p, If_Obj_t * pObj, int nLimit, Vec_Ptr_t * vFront, Vec_Ptr_t * vFrontOld, Vec_Ptr_t * vVisited )
-{
-    If_Obj_t * pFanin;
-    If_Cut_t * pCut;
-    int CostBef, CostAft, i;
-    float DelayOld, AreaBef, AreaAft;
-    pCut = If_ObjCutBest(pObj);
-    assert( pCut->Delay <= pObj->Required + p->fEpsilon );
-    if ( pObj->nRefs == 0 )
-        return;
-    // get the delay
-    DelayOld = pCut->Delay;
-    // get the area
-    AreaBef = If_CutAreaRefed( p, pCut, IF_INFINITY );
-//    if ( AreaBef == 1 )
-//        return;
-    // the cut is non-trivial
-    If_ManImproveNodePrepare( p, pObj, nLimit, vFront, vFrontOld, vVisited );
-    // iteratively modify the cut
-    If_CutDeref( p, pCut, IF_INFINITY );
-    CostBef = If_ManImproveCutCost( p, vFront );
-    If_ManImproveNodeFaninCompact( p, pObj, nLimit, vFront, vVisited );
-    CostAft = If_ManImproveCutCost( p, vFront );
-    If_CutRef( p, pCut, IF_INFINITY );
-    assert( CostBef >= CostAft );
-    // clean up
-    Vec_PtrForEachEntry( vVisited, pFanin, i )
-        pFanin->fMark = 0;
-    // update the node
-    If_ManImproveNodeUpdate( p, pObj, vFront );
-    pCut->Delay = If_CutDelay( p, pCut );
-    // get the new area
-    AreaAft = If_CutAreaRefed( p, pCut, IF_INFINITY );
-    if ( AreaAft > AreaBef || pCut->Delay > pObj->Required + p->fEpsilon )
-    {
-        If_ManImproveNodeUpdate( p, pObj, vFrontOld );
-        AreaAft = If_CutAreaRefed( p, pCut, IF_INFINITY );
-        assert( AreaAft == AreaBef );
-        pCut->Delay = DelayOld;
-    }
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Performs area recovery for each node.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void If_ManImproveMark_rec( If_Man_t * p, If_Obj_t * pObj, Vec_Ptr_t * vVisited )
-{
-    if ( pObj->fMark )
-        return;
-    assert( If_ObjIsAnd(pObj) );
-    If_ManImproveMark_rec( p, If_ObjFanin0(pObj), vVisited );
-    If_ManImproveMark_rec( p, If_ObjFanin1(pObj), vVisited );
-    Vec_PtrPush( vVisited, pObj );
-    pObj->fMark = 1;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Prepares node mapping.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void If_ManImproveNodePrepare( If_Man_t * p, If_Obj_t * pObj, int nLimit, Vec_Ptr_t * vFront, Vec_Ptr_t * vFrontOld, Vec_Ptr_t * vVisited )
-{
-    If_Cut_t * pCut;
-    If_Obj_t * pLeaf;
-    int i;
-    Vec_PtrClear( vFront );
-    Vec_PtrClear( vFrontOld );
-    Vec_PtrClear( vVisited );
-    // expand the cut downwards from the given place
-    pCut = If_ObjCutBest(pObj);
-    If_CutForEachLeaf( p, pCut, pLeaf, i )
-    {
-        Vec_PtrPush( vFront, pLeaf );
-        Vec_PtrPush( vFrontOld, pLeaf );
-        Vec_PtrPush( vVisited, pLeaf );
-        pLeaf->fMark = 1;
-    }
-    // mark the nodes in the cone
-    If_ManImproveMark_rec( p, pObj, vVisited );
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Updates the frontier.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void If_ManImproveNodeUpdate( If_Man_t * p, If_Obj_t * pObj, Vec_Ptr_t * vFront )
-{
-    If_Cut_t * pCut;
-    If_Obj_t * pFanin;
-    int i;
-    pCut = If_ObjCutBest(pObj);
-    // deref node's cut
-    If_CutDeref( p, pCut, IF_INFINITY );
-    // update the node's cut
-    pCut->nLeaves = Vec_PtrSize(vFront);
-    Vec_PtrForEachEntry( vFront, pFanin, i )
-        pCut->pLeaves[i] = pFanin->Id;
-    // ref the new cut
-    If_CutRef( p, pCut, IF_INFINITY );
-}
-
-
-/**Function*************************************************************
-
-  Synopsis    [Returns 1 if the number of fanins will grow.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int If_ManImproveNodeWillGrow( If_Man_t * p, If_Obj_t * pObj )
-{
-    If_Obj_t * pFanin0, * pFanin1;
-    assert( If_ObjIsAnd(pObj) );
-    pFanin0 = If_ObjFanin0(pObj);
-    pFanin1 = If_ObjFanin1(pObj);
-    return !pFanin0->fMark && !pFanin1->fMark;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Returns the increase in the number of fanins with no external refs.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int If_ManImproveNodeFaninCost( If_Man_t * p, If_Obj_t * pObj )
-{
-    int Counter = 0;
-    assert( If_ObjIsAnd(pObj) );
-    // check if the node has external refs
-    if ( pObj->nRefs == 0 )
-        Counter--;
-    // increment the number of fanins without external refs
-    if ( !If_ObjFanin0(pObj)->fMark && If_ObjFanin0(pObj)->nRefs == 0 )
-        Counter++;
-    // increment the number of fanins without external refs
-    if ( !If_ObjFanin1(pObj)->fMark && If_ObjFanin1(pObj)->nRefs == 0 )
-        Counter++;
-    return Counter;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Updates the frontier.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void If_ManImproveNodeFaninUpdate( If_Man_t * p, If_Obj_t * pObj, Vec_Ptr_t * vFront, Vec_Ptr_t * vVisited )
-{
-    If_Obj_t * pFanin;
-    assert( If_ObjIsAnd(pObj) );
-    Vec_PtrRemove( vFront, pObj );
-    pFanin = If_ObjFanin0(pObj);
-    if ( !pFanin->fMark )
-    {
-        Vec_PtrPush( vFront, pFanin );
-        Vec_PtrPush( vVisited, pFanin );
-        pFanin->fMark = 1;
-    }
-    pFanin = If_ObjFanin1(pObj);
-    if ( !pFanin->fMark )
-    {
-        Vec_PtrPush( vFront, pFanin );
-        Vec_PtrPush( vVisited, pFanin );
-        pFanin->fMark = 1;
-    }
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Compacts the number of external refs.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int If_ManImproveNodeFaninCompact0( If_Man_t * p, If_Obj_t * pObj, int nLimit, Vec_Ptr_t * vFront, Vec_Ptr_t * vVisited )
-{
-    If_Obj_t * pFanin;
-    int i;
-    Vec_PtrForEachEntry( vFront, pFanin, i )
-    {
-        if ( If_ObjIsCi(pFanin) )
-            continue;
-        if ( If_ManImproveNodeWillGrow(p, pFanin) )
-            continue;
-        if ( If_ManImproveNodeFaninCost(p, pFanin) <= 0 )
-        {
-            If_ManImproveNodeFaninUpdate( p, pFanin, vFront, vVisited );
-            return 1;
-        }
-    }
-    return 0;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Compacts the number of external refs.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int If_ManImproveNodeFaninCompact1( If_Man_t * p, If_Obj_t * pObj, int nLimit, Vec_Ptr_t * vFront, Vec_Ptr_t * vVisited )
-{
-    If_Obj_t * pFanin;
-    int i;
-    Vec_PtrForEachEntry( vFront, pFanin, i )
-    {
-        if ( If_ObjIsCi(pFanin) )
-            continue;
-        if ( If_ManImproveNodeFaninCost(p, pFanin) < 0 )
-        {
-            If_ManImproveNodeFaninUpdate( p, pFanin, vFront, vVisited );
-            return 1;
-        }
-    }
-    return 0;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Compacts the number of external refs.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int If_ManImproveNodeFaninCompact2( If_Man_t * p, If_Obj_t * pObj, int nLimit, Vec_Ptr_t * vFront, Vec_Ptr_t * vVisited )
-{
-    If_Obj_t * pFanin;
-    int i;
-    Vec_PtrForEachEntry( vFront, pFanin, i )
-    {
-        if ( If_ObjIsCi(pFanin) )
-            continue;
-        if ( If_ManImproveNodeFaninCost(p, pFanin) <= 0 )
-        {
-            If_ManImproveNodeFaninUpdate( p, pFanin, vFront, vVisited );
-            return 1;
-        }
-    }
-    return 0;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Compacts the number of external refs.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int If_ManImproveNodeFaninCompact_int( If_Man_t * p, If_Obj_t * pObj, int nLimit, Vec_Ptr_t * vFront, Vec_Ptr_t * vVisited )
-{
-    if ( If_ManImproveNodeFaninCompact0(p, pObj, nLimit, vFront, vVisited) )
-        return 1;
-    if (  Vec_PtrSize(vFront) < nLimit && If_ManImproveNodeFaninCompact1(p, pObj, nLimit, vFront, vVisited) )
-        return 1;
-    if ( Vec_PtrSize(vFront) < nLimit && If_ManImproveNodeFaninCompact2(p, pObj, nLimit, vFront, vVisited) )
-        return 1;
-    assert( Vec_PtrSize(vFront) <= nLimit );
-    return 0;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Compacts the number of external refs.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void If_ManImproveNodeFaninCompact( If_Man_t * p, If_Obj_t * pObj, int nLimit, Vec_Ptr_t * vFront, Vec_Ptr_t * vVisited )
-{
-    while ( If_ManImproveNodeFaninCompact_int( p, pObj, nLimit, vFront, vVisited ) );
-}
-
-
-
-
-
-/**Function*************************************************************
-
-  Synopsis    [Performs fast mapping for one node.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void If_ManImproveNodeReduce( If_Man_t * p, If_Obj_t * pObj, int nLimit )
-{
-/*
-    If_Cut_t * pCut, * pCut0, * pCut1, * pCutR;
-    If_Obj_t * pFanin0, * pFanin1;
-    float AreaBef, AreaAft;
-    int RetValue;
-
-    assert( nLimit <= 32 );
-    assert( If_ObjIsAnd(pObj) );
-    // get the fanins
-    pFanin0 = If_ObjFanin0(pObj);
-    pFanin1 = If_ObjFanin1(pObj);
-    // get the cuts
-    pCut  = If_ObjCutBest(pObj);
-    pCut0 = If_ObjIsCi(pFanin0) ? If_ObjCutTriv(pFanin0) : If_ObjCutBest(pFanin0);
-    pCut1 = If_ObjIsCi(pFanin1) ? If_ObjCutTriv(pFanin1) : If_ObjCutBest(pFanin1);
-    assert( pCut->Delay <= pObj->Required + p->fEpsilon );
-
-    // deref the cut if the node is refed
-    if ( pObj->nRefs > 0 )
-        If_CutDeref( p, pCut, IF_INFINITY );
-    // get the area
-    AreaBef = If_CutAreaDerefed( p, pCut, IF_INFINITY );
-    // get the fanin support
-    if ( pFanin0->nRefs > 2 && pCut0->Delay < pObj->Required + p->fEpsilon )
-//    if ( pSupp0->nRefs > 0 && pSupp0->Delay < pSupp->DelayR ) // this leads to 2% worse results
-    {
-        pCut0 = If_ObjCutTriv(pFanin0);
-    }
-    // get the fanin support
-    if ( pFanin1->nRefs > 2 && pCut1->Delay < pObj->Required + p->fEpsilon )
-//    if ( pSupp1->nRefs > 0 && pSupp1->Delay < pSupp->DelayR )
-    {
-        pCut1 = If_ObjCutTriv(pFanin1);
-    }
-
-    // merge the cuts
-    pCutR = p->ppCuts[0];
-    RetValue = If_CutMerge( pCut0, pCut1, pCutR );
-    // try very simple cut
-    if ( !RetValue )
-    {
-        RetValue = If_CutMerge( If_ObjCutTriv(pFanin0), If_ObjCutTriv(pFanin1), pCutR );
-        assert( RetValue == 1 );
-    }
-    if ( RetValue )
-    {
-        pCutR->Delay = If_CutDelay( p, pCutR );
-        AreaAft = If_CutAreaDerefed( p, pCutR, IF_INFINITY );
-        // update the best cut
-        if ( AreaAft < AreaBef - p->fEpsilon && pCutR->Delay < pObj->Required + p->fEpsilon )
-            If_CutCopy( p, pCut, pCutR );
-    }
-    // recompute the delay of the best cut
-    pCut->Delay = If_CutDelay( p, pCut );
-    // ref the cut if the node is refed
-    if ( pObj->nRefs > 0 )
-        If_CutRef( p, pCut, IF_INFINITY );
-*/
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Performs area recovery for each node.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void If_ManImproveReduce( If_Man_t * p, int nLimit )
-{
-    If_Obj_t * pObj;
-    int i;
-    If_ManForEachNode( p, pObj, i )
-        If_ManImproveNodeReduce( p, pObj, nLimit );
-}
-
-////////////////////////////////////////////////////////////////////////
-///                       END OF FILE                                ///
-////////////////////////////////////////////////////////////////////////
-
-
diff --git a/abc70930/src/map/if/ifSeq.c b/abc70930/src/map/if/ifSeq.c
deleted file mode 100644
index 8d1de8c1..00000000
--- a/abc70930/src/map/if/ifSeq.c
+++ /dev/null
@@ -1,405 +0,0 @@
-/**CFile****************************************************************
-
-  FileName    [ifSeq.c]
-
-  SystemName  [ABC: Logic synthesis and verification system.]
-
-  PackageName [FPGA mapping based on priority cuts.]
-
-  Synopsis    [Sequential mapping.]
-
-  Author      [Alan Mishchenko]
-  
-  Affiliation [UC Berkeley]
-
-  Date        [Ver. 1.0. Started - November 21, 2006.]
-
-  Revision    [$Id: ifSeq.c,v 1.00 2006/11/21 00:00:00 alanmi Exp $]
-
-***********************************************************************/
-
-#include "if.h"
-
-////////////////////////////////////////////////////////////////////////
-///                        DECLARATIONS                              ///
-////////////////////////////////////////////////////////////////////////
-
-extern int s_MappingTime;
-
-////////////////////////////////////////////////////////////////////////
-///                     FUNCTION DEFINITIONS                         ///
-////////////////////////////////////////////////////////////////////////
-
-/**Function*************************************************************
-
-  Synopsis    [Prepares for sequential mapping by linking the latches.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void If_ManPrepareMappingSeq( If_Man_t * p )
-{
-    If_Obj_t * pObjLi, * pObjLo;
-    int i;
-
-    // link the latch outputs (CIs) directly to the drivers of latch inputs (COs)
-    for ( i = 0; i < p->pPars->nLatches; i++ )
-    {
-        pObjLi = If_ManLi( p, i );
-        pObjLo = If_ManLo( p, i );
-        pObjLo->pFanin0 = If_ObjFanin0( pObjLi );
-        pObjLo->fCompl0 = If_ObjFaninC0( pObjLi );
-    }
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Collects latches in the topological order.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
- 
-***********************************************************************/
-void If_ManCollectLatches_rec( If_Obj_t * pObj, Vec_Ptr_t * vLatches )
-{
-    if ( !If_ObjIsLatch(pObj) )
-        return;
-    if ( pObj->fMark )
-        return;
-    pObj->fMark = 1;
-    If_ManCollectLatches_rec( pObj->pFanin0, vLatches );
-    Vec_PtrPush( vLatches, pObj );
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Collects latches in the topological order.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-Vec_Ptr_t * If_ManCollectLatches( If_Man_t * p )
-{
-    Vec_Ptr_t * vLatches;
-    If_Obj_t * pObj;
-    int i;
-    // collect latches 
-    vLatches = Vec_PtrAlloc( p->pPars->nLatches );
-    If_ManForEachLatchOutput( p, pObj, i )
-        If_ManCollectLatches_rec( pObj, vLatches );
-    // clean marks
-    Vec_PtrForEachEntry( vLatches, pObj, i )
-        pObj->fMark = 0;
-    assert( Vec_PtrSize(vLatches) == p->pPars->nLatches );
-    return vLatches;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Performs one pass of l-value computation over all nodes.]
-
-  Description [Experimentally it was found that checking POs changes
-  is not enough to detect the convergence of l-values in the network.]
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int If_ManPerformMappingRoundSeq( If_Man_t * p, int nIter )
-{
-    If_Obj_t * pObj;
-    int i, clk = clock();
-    int fVeryVerbose = 0;
-    int fChange = 0;
-
-    // map the internal nodes
-    p->nCutsMerged = 0;
-    If_ManForEachNode( p, pObj, i )
-    {
-        If_ObjPerformMappingAnd( p, pObj, 0, 0 );
-        if ( pObj->fRepr )
-            If_ObjPerformMappingChoice( p, pObj, 0, 0 );
-    }
-
-    // postprocess the mapping
-//printf( "Itereation %d: \n", nIter );
-    If_ManForEachNode( p, pObj, i )
-    {
-        // update the LValues stored separately
-        if ( If_ObjLValue(pObj) < If_ObjCutBest(pObj)->Delay - p->fEpsilon )
-        {
-            If_ObjSetLValue( pObj, If_ObjCutBest(pObj)->Delay );
-            fChange = 1;
-        }
-//printf( "%d ", (int)If_ObjLValue(pObj) );
-        // reset the visit counters
-        assert( pObj->nVisits == 0 );
-        pObj->nVisits = pObj->nVisitsCopy;
-    }
-//printf( "\n" );
-
-    // propagate LValues over the registers
-    Vec_PtrForEachEntry( p->vLatchOrder, pObj, i )
-    {
-        If_ObjSetLValue( pObj, If_ObjLValue(If_ObjFanin0(pObj)) - p->Period );
-        If_ObjSetArrTime( pObj, If_ObjLValue(pObj) );
-    }
-
-    // compute area and delay
-    if ( fVeryVerbose )
-    {
-        p->RequiredGlo = If_ManDelayMax( p, 1 );
-        p->AreaGlo = If_ManScanMapping(p);
-        printf( "S%d:  Fi = %6.2f. Del = %6.2f. Area = %8.2f. Cuts = %8d. ", 
-             nIter, (float)p->Period, p->RequiredGlo, p->AreaGlo, p->nCutsMerged );
-        PRT( "T", clock() - clk );
-    }
-    return fChange;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Returns 1 if retiming with this clock period is feasible.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int If_ManBinarySearchPeriod( If_Man_t * p )
-{
-    If_Obj_t * pObj;
-    int i, c, fConverged;
-    int fResetRefs = 0;
-
-    p->nAttempts++;
-
-    // reset initial LValues (PIs to 0; others to -inf)
-    If_ManForEachObj( p, pObj, i )
-    {
-        if ( If_ObjIsPi(pObj) || If_ObjIsConst1(pObj) )
-        {
-            If_ObjSetLValue( pObj, (float)0.0 );
-            If_ObjSetArrTime( pObj, (float)0.0 );
-        }
-        else
-        {
-            If_ObjSetLValue( pObj, (float)-IF_INFINITY );
-            If_ObjSetArrTime( pObj, (float)-IF_INFINITY );
-        }
-        // undo any previous mapping, except for CIs
-        if ( If_ObjIsAnd(pObj) )
-            If_ObjCutBest(pObj)->nLeaves = 0;
-    }
-
-    // update all values iteratively
-    fConverged = 0;
-    for ( c = 1; c <= p->nMaxIters; c++ )
-    {
-        if ( !If_ManPerformMappingRoundSeq( p, c ) )
-        {
-            p->RequiredGlo = If_ManDelayMax( p, 1 );
-            fConverged = 1;
-            break;
-        }
-        p->RequiredGlo = If_ManDelayMax( p, 1 );
-//printf( "Global = %d \n", (int)p->RequiredGlo );
-        if ( p->RequiredGlo > p->Period + p->fEpsilon )
-            break; 
-    }
-
-    // report the results
-    if ( p->pPars->fVerbose )
-    {
-        p->AreaGlo = If_ManScanMapping(p);
-        printf( "Attempt = %2d.  Iters = %3d.  Area = %10.2f.  Fi = %6.2f.  ", p->nAttempts, c, p->AreaGlo, (float)p->Period );
-        if ( fConverged )
-            printf( "  Feasible" );
-        else if ( c > p->nMaxIters )
-            printf( "Infeasible (timeout)" );
-        else
-            printf( "Infeasible" );
-        printf( "\n" );
-    }
-    return fConverged;
-}
-
-
-/**Function*************************************************************
-
-  Synopsis    [Performs binary search for the optimal clock period.]
-
-  Description [Assumes that FiMin is infeasible while FiMax is feasible.]
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int If_ManBinarySearch_rec( If_Man_t * p, int FiMin, int FiMax )
-{
-    assert( FiMin < FiMax );
-    if ( FiMin + 1 == FiMax )
-        return FiMax;
-    // compute the median
-    p->Period = FiMin + (FiMax - FiMin)/2;
-    if ( If_ManBinarySearchPeriod( p ) )
-        return If_ManBinarySearch_rec( p, FiMin, p->Period ); // Median is feasible
-    else 
-        return If_ManBinarySearch_rec( p, p->Period, FiMax ); // Median is infeasible
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Performs sequential mapping.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void If_ManPerformMappingSeqPost( If_Man_t * p )
-{
-    If_Obj_t * pObjLi, * pObjLo, * pObj;
-    int i;
-
-    // link the latch outputs (CIs) directly to the drivers of latch inputs (COs)
-    for ( i = 0; i < p->pPars->nLatches; i++ )
-    {
-        pObjLi = If_ManLi( p, i );
-        pObjLo = If_ManLo( p, i );
-//        printf( "%3d : %2d -> %2d   \n", i, 
-//            (int)If_ObjLValue(If_ObjFanin0(pObjLo)), (int)If_ObjLValue(pObjLo) );
-    }
-
-    // set arrival times
-    assert( p->pPars->pTimesArr != NULL );
-    If_ManForEachLatchOutput( p, pObjLo, i )
-        p->pPars->pTimesArr[i] = If_ObjLValue(pObjLo);
-
-    // set the required times
-    assert( p->pPars->pTimesReq == NULL );
-    p->pPars->pTimesReq = ALLOC( float, If_ManCoNum(p) );
-    If_ManForEachPo( p, pObj, i )
-    {
-        p->pPars->pTimesReq[i] = p->RequiredGlo2;
-//        printf( "Out %3d : %2d   \n", i, (int)p->pPars->pTimesReq[i] );
-    }
-    If_ManForEachLatchInput( p, pObjLi, i )
-    {
-        p->pPars->pTimesReq[i] = If_ObjLValue(If_ObjFanin0(pObjLi));
-//        printf( "Out %3d : %2d   \n", i, (int)p->pPars->pTimesReq[i] );
-    }
-
-    // undo previous mapping
-    If_ManForEachObj( p, pObj, i )
-        if ( If_ObjIsAnd(pObj) )
-            If_ObjCutBest(pObj)->nLeaves = 0;
-
-    // map again combinationally
-    p->pPars->fSeqMap = 0;
-    If_ManPerformMappingComb( p );
-    p->pPars->fSeqMap = 1;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Performs sequential mapping.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int If_ManPerformMappingSeq( If_Man_t * p )
-{
-    int clkTotal = clock();
-    int PeriodBest;
-
-    p->SortMode = 0;
-
-    // perform combinational mapping to get the upper bound on the clock period
-    If_ManPerformMappingRound( p, 1, 0, 0, NULL );
-    p->RequiredGlo = If_ManDelayMax( p, 0 );
-    p->RequiredGlo2 = p->RequiredGlo;
-
-    // set direct linking of latches with their inputs
-    If_ManPrepareMappingSeq( p );
-
-    // collect latches
-    p->vLatchOrder = If_ManCollectLatches( p );
-
-    // set parameters
-    p->nCutsUsed = p->pPars->nCutsMax;
-    p->nAttempts = 0;
-    p->nMaxIters = 50;
-    p->Period    = (int)p->RequiredGlo;
-
-    // make sure the clock period works
-    if ( !If_ManBinarySearchPeriod( p ) )
-    {
-        printf( "If_ManPerformMappingSeq(): The upper bound on the clock period cannot be computed.\n" );
-        return 0;
-    }
-
-    // perform binary search
-    PeriodBest = If_ManBinarySearch_rec( p, 0, p->Period );
-
-    // recompute the best l-values
-    if ( p->Period != PeriodBest )
-    {
-        p->Period = PeriodBest;
-        if ( !If_ManBinarySearchPeriod( p ) )
-        {
-            printf( "If_ManPerformMappingSeq(): The final clock period cannot be confirmed.\n" );
-            return 0;
-        }
-    }
-    if ( p->pPars->fVerbose )
-    {
-/*
-        {
-            FILE * pTable;
-            pTable = fopen( "iscas/stats_new.txt", "a+" );
-//            fprintf( pTable, "%s ",  pNtk->pName );
-            fprintf( pTable, "%d ", p->Period );
-    //        fprintf( pTable, "%.2f ", (float)(s_MappingMem)/(float)(1<<20) );
-//            fprintf( pTable, "%.2f", (float)(s_MappingTime)/(float)(CLOCKS_PER_SEC) );
-//            fprintf( pTable, "\n" );
-            fclose( pTable );
-        }
-*/
-        printf( "The best clock period is %3d.  ", p->Period );
-        PRT( "Sequential time", clock() - clkTotal );
-    }
-    p->RequiredGlo = (float)PeriodBest;
-
-    // postprocess it using combinational mapping
-    If_ManPerformMappingSeqPost( p );
-    s_MappingTime = clock() - clkTotal;
-    return 1;
-}
-
-////////////////////////////////////////////////////////////////////////
-///                       END OF FILE                                ///
-////////////////////////////////////////////////////////////////////////
-
-
diff --git a/abc70930/src/map/if/ifTime.c b/abc70930/src/map/if/ifTime.c
deleted file mode 100644
index 60417c67..00000000
--- a/abc70930/src/map/if/ifTime.c
+++ /dev/null
@@ -1,221 +0,0 @@
-/**CFile****************************************************************
-
-  FileName    [ifTime.c]
-
-  SystemName  [ABC: Logic synthesis and verification system.]
-
-  PackageName [FPGA mapping based on priority cuts.]
-
-  Synopsis    [Computation of delay paramters depending on the library.]
-
-  Author      [Alan Mishchenko]
-  
-  Affiliation [UC Berkeley]
-
-  Date        [Ver. 1.0. Started - November 21, 2006.]
-
-  Revision    [$Id: ifTime.c,v 1.00 2006/11/21 00:00:00 alanmi Exp $]
-
-***********************************************************************/
-
-#include "if.h"
-
-////////////////////////////////////////////////////////////////////////
-///                        DECLARATIONS                              ///
-////////////////////////////////////////////////////////////////////////
-
-static void If_CutSortInputPins( If_Man_t * p, If_Cut_t * pCut, int * pPinPerm, float * pPinDelays );
-
-////////////////////////////////////////////////////////////////////////
-///                     FUNCTION DEFINITIONS                         ///
-////////////////////////////////////////////////////////////////////////
-
-/**Function*************************************************************
-
-  Synopsis    [Computes delay.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-float If_CutDelay( If_Man_t * p, If_Cut_t * pCut )
-{
-    static int pPinPerm[IF_MAX_LUTSIZE];
-    static float pPinDelays[IF_MAX_LUTSIZE];
-    If_Obj_t * pLeaf;
-    float Delay, DelayCur;
-    float * pLutDelays;
-    int i, Shift;
-    assert( p->pPars->fSeqMap || pCut->nLeaves > 1 );
-    Delay = -IF_FLOAT_LARGE;
-    if ( p->pPars->pLutLib )
-    {
-        assert( !p->pPars->fLiftLeaves );
-        pLutDelays = p->pPars->pLutLib->pLutDelays[pCut->nLeaves];
-        if ( p->pPars->pLutLib->fVarPinDelays )
-        {
-            // compute the delay using sorted pins
-            If_CutSortInputPins( p, pCut, pPinPerm, pPinDelays );
-            for ( i = 0; i < (int)pCut->nLeaves; i++ )
-            {
-                DelayCur = pPinDelays[pPinPerm[i]] + pLutDelays[i];
-                Delay = IF_MAX( Delay, DelayCur );
-            }
-        }
-        else
-        {
-            If_CutForEachLeaf( p, pCut, pLeaf, i )
-            {
-                DelayCur = If_ObjCutBest(pLeaf)->Delay + pLutDelays[0];
-                Delay = IF_MAX( Delay, DelayCur );
-            }
-        }
-    }
-    else
-    {
-        if ( pCut->fUser )
-        {
-            assert( !p->pPars->fLiftLeaves );
-            If_CutForEachLeaf( p, pCut, pLeaf, i )
-            {
-                DelayCur = If_ObjCutBest(pLeaf)->Delay + (float)pCut->pPerm[i];
-                Delay = IF_MAX( Delay, DelayCur );
-            }
-        }
-        else
-        {
-            if ( p->pPars->fLiftLeaves )
-            {
-                If_CutForEachLeafSeq( p, pCut, pLeaf, Shift, i )
-                {
-                    DelayCur = If_ObjCutBest(pLeaf)->Delay - Shift * p->Period;
-                    Delay = IF_MAX( Delay, DelayCur );
-                }
-            }
-            else
-            {
-                If_CutForEachLeaf( p, pCut, pLeaf, i )
-                {
-                    DelayCur = If_ObjCutBest(pLeaf)->Delay;
-                    Delay = IF_MAX( Delay, DelayCur );
-                }
-            }
-            Delay += 1.0;
-        }
-    }
-    return Delay;
-}
-
-/**Function*************************************************************
-
-  Synopsis    []
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void If_CutPropagateRequired( If_Man_t * p, If_Cut_t * pCut, float ObjRequired )
-{
-    static int pPinPerm[IF_MAX_LUTSIZE];
-    static float pPinDelays[IF_MAX_LUTSIZE];
-    If_Obj_t * pLeaf;
-    float * pLutDelays;
-    float Required;
-    int i;
-    assert( !p->pPars->fLiftLeaves );
-    // compute the pins
-    if ( p->pPars->pLutLib )
-    {
-        pLutDelays = p->pPars->pLutLib->pLutDelays[pCut->nLeaves];
-        if ( p->pPars->pLutLib->fVarPinDelays )
-        {
-            // compute the delay using sorted pins
-            If_CutSortInputPins( p, pCut, pPinPerm, pPinDelays );
-            for ( i = 0; i < (int)pCut->nLeaves; i++ )
-            {
-                Required = ObjRequired - pLutDelays[i];
-                pLeaf = If_ManObj( p, pCut->pLeaves[pPinPerm[i]] );
-                pLeaf->Required = IF_MIN( pLeaf->Required, Required );
-            }
-        }
-        else
-        {
-            Required = ObjRequired - pLutDelays[0];
-            If_CutForEachLeaf( p, pCut, pLeaf, i )
-                pLeaf->Required = IF_MIN( pLeaf->Required, Required );
-        }
-    }
-    else
-    {
-        if ( pCut->fUser )
-        {
-            If_CutForEachLeaf( p, pCut, pLeaf, i )
-            {
-                Required = ObjRequired - (float)pCut->pPerm[i];
-                pLeaf->Required = IF_MIN( pLeaf->Required, Required );
-            }
-        }
-        else
-        {
-            Required = ObjRequired - (float)1.0;
-            If_CutForEachLeaf( p, pCut, pLeaf, i )
-                pLeaf->Required = IF_MIN( pLeaf->Required, Required );
-        }
-    }
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Sorts the pins in the decreasing order of delays.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void If_CutSortInputPins( If_Man_t * p, If_Cut_t * pCut, int * pPinPerm, float * pPinDelays )
-{
-    If_Obj_t * pLeaf;
-    int i, j, best_i, temp;
-    // start the trivial permutation and collect pin delays
-    If_CutForEachLeaf( p, pCut, pLeaf, i )
-    {
-        pPinPerm[i] = i;
-        pPinDelays[i] = If_ObjCutBest(pLeaf)->Delay;
-    }
-    // selection sort the pins in the decreasible order of delays
-    // this order will match the increasing order of LUT input pins
-    for ( i = 0; i < (int)pCut->nLeaves-1; i++ )
-    {
-        best_i = i;
-        for ( j = i+1; j < (int)pCut->nLeaves; j++ )
-            if ( pPinDelays[pPinPerm[j]] > pPinDelays[pPinPerm[best_i]] )
-                best_i = j;
-        if ( best_i == i )
-            continue;
-        temp = pPinPerm[i]; 
-        pPinPerm[i] = pPinPerm[best_i]; 
-        pPinPerm[best_i] = temp;
-    }
-    // verify
-    assert( pPinPerm[0] < (int)pCut->nLeaves );
-    for ( i = 1; i < (int)pCut->nLeaves; i++ )
-    {
-        assert( pPinPerm[i] < (int)pCut->nLeaves );
-        assert( pPinDelays[pPinPerm[i-1]] >= pPinDelays[pPinPerm[i]] );
-    }
-}
-
-////////////////////////////////////////////////////////////////////////
-///                       END OF FILE                                ///
-////////////////////////////////////////////////////////////////////////
-
-
diff --git a/abc70930/src/map/if/ifTruth.c b/abc70930/src/map/if/ifTruth.c
deleted file mode 100644
index 5587e3ff..00000000
--- a/abc70930/src/map/if/ifTruth.c
+++ /dev/null
@@ -1,230 +0,0 @@
-/**CFile****************************************************************
-
-  FileName    [ifTruth.c]
-
-  SystemName  [ABC: Logic synthesis and verification system.]
-
-  PackageName [FPGA mapping based on priority cuts.]
-
-  Synopsis    [Computation of truth tables of the cuts.]
-
-  Author      [Alan Mishchenko]
-  
-  Affiliation [UC Berkeley]
-
-  Date        [Ver. 1.0. Started - November 21, 2006.]
-
-  Revision    [$Id: ifTruth.c,v 1.00 2006/11/21 00:00:00 alanmi Exp $]
-
-***********************************************************************/
-
-#include "if.h"
-
-////////////////////////////////////////////////////////////////////////
-///                        DECLARATIONS                              ///
-////////////////////////////////////////////////////////////////////////
-
-////////////////////////////////////////////////////////////////////////
-///                     FUNCTION DEFINITIONS                         ///
-////////////////////////////////////////////////////////////////////////
-
-/**Function*************************************************************
-
-  Synopsis    [Several simple procedures working with truth tables.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-static inline int  If_TruthWordNum( int nVars )  { return nVars <= 5 ? 1 : (1 << (nVars - 5)); }
-static inline void If_TruthNot( unsigned * pOut, unsigned * pIn, int nVars )
-{
-    int w;
-    for ( w = If_TruthWordNum(nVars)-1; w >= 0; w-- )
-        pOut[w] = ~pIn[w];
-}
-static inline void If_TruthCopy( unsigned * pOut, unsigned * pIn, int nVars )
-{
-    int w;
-    for ( w = If_TruthWordNum(nVars)-1; w >= 0; w-- )
-        pOut[w] = pIn[w];
-}
-static inline void If_TruthNand( unsigned * pOut, unsigned * pIn0, unsigned * pIn1, int nVars )
-{
-    int w;
-    for ( w = If_TruthWordNum(nVars)-1; w >= 0; w-- )
-        pOut[w] = ~(pIn0[w] & pIn1[w]);
-}
-static inline void If_TruthAnd( unsigned * pOut, unsigned * pIn0, unsigned * pIn1, int nVars )
-{
-    int w;
-    for ( w = If_TruthWordNum(nVars)-1; w >= 0; w-- )
-        pOut[w] = pIn0[w] & pIn1[w];
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Swaps two adjacent variables in the truth table.]
-
-  Description [Swaps var number Start and var number Start+1 (0-based numbers).
-  The input truth table is pIn. The output truth table is pOut.]
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void If_TruthSwapAdjacentVars( unsigned * pOut, unsigned * pIn, int nVars, int iVar )
-{
-    static unsigned PMasks[4][3] = {
-        { 0x99999999, 0x22222222, 0x44444444 },
-        { 0xC3C3C3C3, 0x0C0C0C0C, 0x30303030 },
-        { 0xF00FF00F, 0x00F000F0, 0x0F000F00 },
-        { 0xFF0000FF, 0x0000FF00, 0x00FF0000 }
-    };
-    int nWords = If_TruthWordNum( nVars );
-    int i, k, Step, Shift;
-
-    assert( iVar < nVars - 1 );
-    if ( iVar < 4 )
-    {
-        Shift = (1 << iVar);
-        for ( i = 0; i < nWords; i++ )
-            pOut[i] = (pIn[i] & PMasks[iVar][0]) | ((pIn[i] & PMasks[iVar][1]) << Shift) | ((pIn[i] & PMasks[iVar][2]) >> Shift);
-    }
-    else if ( iVar > 4 )
-    {
-        Step = (1 << (iVar - 5));
-        for ( k = 0; k < nWords; k += 4*Step )
-        {
-            for ( i = 0; i < Step; i++ )
-                pOut[i] = pIn[i];
-            for ( i = 0; i < Step; i++ )
-                pOut[Step+i] = pIn[2*Step+i];
-            for ( i = 0; i < Step; i++ )
-                pOut[2*Step+i] = pIn[Step+i];
-            for ( i = 0; i < Step; i++ )
-                pOut[3*Step+i] = pIn[3*Step+i];
-            pIn  += 4*Step;
-            pOut += 4*Step;
-        }
-    }
-    else // if ( iVar == 4 )
-    {
-        for ( i = 0; i < nWords; i += 2 )
-        {
-            pOut[i]   = (pIn[i]   & 0x0000FFFF) | ((pIn[i+1] & 0x0000FFFF) << 16);
-            pOut[i+1] = (pIn[i+1] & 0xFFFF0000) | ((pIn[i]   & 0xFFFF0000) >> 16);
-        }
-    }
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Expands the truth table according to the phase.]
-
-  Description [The input and output truth tables are in pIn/pOut. The current number
-  of variables is nVars. The total number of variables in nVarsAll. The last argument
-  (Phase) contains shows where the variables should go.]
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void If_TruthStretch( unsigned * pOut, unsigned * pIn, int nVars, int nVarsAll, unsigned Phase )
-{
-    unsigned * pTemp;
-    int i, k, Var = nVars - 1, Counter = 0;
-    for ( i = nVarsAll - 1; i >= 0; i-- )
-        if ( Phase & (1 << i) )
-        {
-            for ( k = Var; k < i; k++ )
-            {
-                If_TruthSwapAdjacentVars( pOut, pIn, nVarsAll, k );
-                pTemp = pIn; pIn = pOut; pOut = pTemp;
-                Counter++;
-            }
-            Var--;
-        }
-    assert( Var == -1 );
-    // swap if it was moved an even number of times
-    if ( !(Counter & 1) )
-        If_TruthCopy( pOut, pIn, nVarsAll );
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Computes the stretching phase of the cut w.r.t. the merged cut.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-static inline unsigned If_CutTruthPhase( If_Cut_t * pCut, If_Cut_t * pCut1 )
-{
-    unsigned uPhase = 0;
-    int i, k;
-    for ( i = k = 0; i < (int)pCut->nLeaves; i++ )
-    {
-        if ( k == (int)pCut1->nLeaves )
-            break;
-        if ( pCut->pLeaves[i] < pCut1->pLeaves[k] )
-            continue;
-        assert( pCut->pLeaves[i] == pCut1->pLeaves[k] );
-        uPhase |= (1 << i);
-        k++;
-    }
-    return uPhase;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Performs truth table computation.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void If_CutComputeTruth( If_Man_t * p, If_Cut_t * pCut, If_Cut_t * pCut0, If_Cut_t * pCut1, int fCompl0, int fCompl1 )
-{
-    extern void Kit_FactorTest( unsigned * pTruth, int nVars );
-
-    // permute the first table
-    if ( fCompl0 ^ pCut0->fCompl ) 
-        If_TruthNot( p->puTemp[0], If_CutTruth(pCut0), pCut->nLimit );
-    else
-        If_TruthCopy( p->puTemp[0], If_CutTruth(pCut0), pCut->nLimit );
-    If_TruthStretch( p->puTemp[2], p->puTemp[0], pCut0->nLeaves, pCut->nLimit, If_CutTruthPhase(pCut, pCut0) );
-    // permute the second table
-    if ( fCompl1 ^ pCut1->fCompl ) 
-        If_TruthNot( p->puTemp[1], If_CutTruth(pCut1), pCut->nLimit );
-    else
-        If_TruthCopy( p->puTemp[1], If_CutTruth(pCut1), pCut->nLimit );
-    If_TruthStretch( p->puTemp[3], p->puTemp[1], pCut1->nLeaves, pCut->nLimit, If_CutTruthPhase(pCut, pCut1) );
-    // produce the resulting table
-    assert( pCut->fCompl == 0 );
-    if ( pCut->fCompl )
-        If_TruthNand( If_CutTruth(pCut), p->puTemp[2], p->puTemp[3], pCut->nLimit );
-    else
-        If_TruthAnd( If_CutTruth(pCut), p->puTemp[2], p->puTemp[3], pCut->nLimit );
-
-    // perform 
-//    Kit_FactorTest( If_CutTruth(pCut), pCut->nLimit );
-//    printf( "%d ", If_CutLeaveNum(pCut) - Kit_TruthSupportSize(If_CutTruth(pCut), If_CutLeaveNum(pCut)) );
-}
-
-////////////////////////////////////////////////////////////////////////
-///                       END OF FILE                                ///
-////////////////////////////////////////////////////////////////////////
-
-
diff --git a/abc70930/src/map/if/ifUtil.c b/abc70930/src/map/if/ifUtil.c
deleted file mode 100644
index f3fa049e..00000000
--- a/abc70930/src/map/if/ifUtil.c
+++ /dev/null
@@ -1,454 +0,0 @@
-/**CFile****************************************************************
-
-  FileName    [ifUtil.c]
-
-  SystemName  [ABC: Logic synthesis and verification system.]
-
-  PackageName [FPGA mapping based on priority cuts.]
-
-  Synopsis    [Various utilities.]
-
-  Author      [Alan Mishchenko]
-  
-  Affiliation [UC Berkeley]
-
-  Date        [Ver. 1.0. Started - November 21, 2006.]
-
-  Revision    [$Id: ifUtil.c,v 1.00 2006/11/21 00:00:00 alanmi Exp $]
-
-***********************************************************************/
-
-#include "if.h"
-
-////////////////////////////////////////////////////////////////////////
-///                        DECLARATIONS                              ///
-////////////////////////////////////////////////////////////////////////
-
-////////////////////////////////////////////////////////////////////////
-///                     FUNCTION DEFINITIONS                         ///
-////////////////////////////////////////////////////////////////////////
-
-/**Function*************************************************************
-
-  Synopsis    [Sets all the node copy to NULL.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void If_ManCleanNodeCopy( If_Man_t * p )
-{
-    If_Obj_t * pObj;
-    int i;
-    If_ManForEachObj( p, pObj, i )
-        If_ObjSetCopy( pObj, NULL );
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Sets all the cut data to NULL.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void If_ManCleanCutData( If_Man_t * p )
-{
-    If_Obj_t * pObj;
-    int i;
-    If_ManForEachObj( p, pObj, i )
-        If_CutSetData( If_ObjCutBest(pObj), NULL );
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Sets all visited marks to 0.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void If_ManCleanMarkV( If_Man_t * p )
-{
-    If_Obj_t * pObj;
-    int i;
-    If_ManForEachObj( p, pObj, i )
-        pObj->fVisit = 0;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Returns the max delay of the POs.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-float If_ManDelayMax( If_Man_t * p, int fSeq )
-{
-    If_Obj_t * pObj;
-    float DelayBest;
-    int i;
-    if ( p->pPars->fLatchPaths && p->pPars->nLatches == 0 )
-    {
-        printf( "Delay optimization of latch path is not performed because there is no latches.\n" );
-        p->pPars->fLatchPaths = 0;
-    }
-    DelayBest = -IF_FLOAT_LARGE;
-    if ( fSeq )
-    {
-        assert( p->pPars->nLatches > 0 );
-        If_ManForEachPo( p, pObj, i )
-            if ( DelayBest < If_ObjArrTime(If_ObjFanin0(pObj)) )
-                 DelayBest = If_ObjArrTime(If_ObjFanin0(pObj));
-    }
-    else if ( p->pPars->fLatchPaths )
-    {
-        If_ManForEachLatchInput( p, pObj, i )
-            if ( DelayBest < If_ObjArrTime(If_ObjFanin0(pObj)) )
-                 DelayBest = If_ObjArrTime(If_ObjFanin0(pObj));
-    }
-    else 
-    {
-        If_ManForEachCo( p, pObj, i )
-            if ( DelayBest < If_ObjArrTime(If_ObjFanin0(pObj)) )
-                 DelayBest = If_ObjArrTime(If_ObjFanin0(pObj));
-    }
-    return DelayBest;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Computes the required times of all nodes.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void If_ManComputeRequired( If_Man_t * p )
-{
-    If_Obj_t * pObj;
-    int i, Counter;
-
-    // compute area, clean required times, collect nodes used in the mapping
-    p->nNets = 0;
-    p->AreaGlo = If_ManScanMapping( p );
-
-    // consider the case when the required times are given
-    if ( p->pPars->pTimesReq )
-    {
-        assert( !p->pPars->fAreaOnly );
-        // make sure that the required time hold
-        Counter = 0;
-        If_ManForEachCo( p, pObj, i )
-        {
-            if ( If_ObjArrTime(If_ObjFanin0(pObj)) > p->pPars->pTimesReq[i] + p->fEpsilon )
-            {
-                Counter++;
-//                printf( "Required times are violated for output %d (arr = %d; req = %d).\n", 
-//                    i, (int)If_ObjArrTime(If_ObjFanin0(pObj)), (int)p->pPars->pTimesReq[i] );
-            }
-            If_ObjFanin0(pObj)->Required = p->pPars->pTimesReq[i];
-        }
-        if ( Counter )
-            printf( "Required times are violated for %d outputs.\n", Counter );
-    }
-    else
-    {
-        // get the global required times
-        p->RequiredGlo = If_ManDelayMax( p, 0 );
-        // update the required times according to the target
-        if ( p->pPars->DelayTarget != -1 )
-        {
-            if ( p->RequiredGlo > p->pPars->DelayTarget + p->fEpsilon )
-            {
-                if ( p->fNextRound == 0 )
-                {
-                    p->fNextRound = 1;
-                    printf( "Cannot meet the target required times (%4.2f). Mapping continues anyway.\n", p->pPars->DelayTarget );
-                }
-            }
-            else if ( p->RequiredGlo < p->pPars->DelayTarget - p->fEpsilon )
-            {
-                if ( p->fNextRound == 0 )
-                {
-                    p->fNextRound = 1;
-                    printf( "Relaxing the required times from (%4.2f) to the target (%4.2f).\n", p->RequiredGlo, p->pPars->DelayTarget );
-                }
-                p->RequiredGlo = p->pPars->DelayTarget;
-            }
-        }
-        // do not propagate required times if area minimization is requested
-        if ( p->pPars->fAreaOnly ) 
-            return;
-        // set the required times for the POs
-        if ( p->pPars->fLatchPaths )
-        {
-            If_ManForEachLatchInput( p, pObj, i )
-                If_ObjFanin0(pObj)->Required = p->RequiredGlo;
-        }
-        else 
-        {
-            If_ManForEachCo( p, pObj, i )
-                If_ObjFanin0(pObj)->Required = p->RequiredGlo;
-        }
-    }
-    // go through the nodes in the reverse topological order
-    Vec_PtrForEachEntry( p->vMapped, pObj, i )
-        If_CutPropagateRequired( p, If_ObjCutBest(pObj), pObj->Required );
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Computes area, references, and nodes used in the mapping.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-float If_ManScanMapping_rec( If_Man_t * p, If_Obj_t * pObj, If_Obj_t ** ppStore )
-{
-    If_Obj_t * pLeaf;
-    If_Cut_t * pCutBest;
-    float aArea;
-    int i;
-    if ( pObj->nRefs++ || If_ObjIsCi(pObj) || If_ObjIsConst1(pObj) )
-        return 0.0;
-    // store the node in the structure by level
-    assert( If_ObjIsAnd(pObj) );
-    pObj->pCopy = (char *)ppStore[pObj->Level]; 
-    ppStore[pObj->Level] = pObj;
-    // visit the transitive fanin of the selected cut
-    pCutBest = If_ObjCutBest(pObj);
-    p->nNets += pCutBest->nLeaves;
-    aArea = If_CutLutArea( p, pCutBest );
-    If_CutForEachLeaf( p, pCutBest, pLeaf, i )
-        aArea += If_ManScanMapping_rec( p, pLeaf, ppStore );
-    return aArea;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Computes area, references, and nodes used in the mapping.]
-
-  Description [Collects the nodes in reverse topological order in array 
-  p->vMapping.]
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-float If_ManScanMapping( If_Man_t * p )
-{
-    If_Obj_t * pObj, ** ppStore;
-    float aArea;
-    int i;
-    assert( !p->pPars->fLiftLeaves );
-    // clean all references
-    If_ManForEachObj( p, pObj, i )
-    {
-        pObj->Required = IF_FLOAT_LARGE;
-        pObj->nVisits  = pObj->nVisitsCopy;
-        pObj->nRefs    = 0;
-    }
-    // allocate place to store the nodes
-    ppStore = ALLOC( If_Obj_t *, p->nLevelMax + 1 );
-    memset( ppStore, 0, sizeof(If_Obj_t *) * (p->nLevelMax + 1) );
-    // collect nodes reachable from POs in the DFS order through the best cuts
-    aArea = 0;
-    If_ManForEachCo( p, pObj, i )
-        aArea += If_ManScanMapping_rec( p, If_ObjFanin0(pObj), ppStore );
-    // reconnect the nodes in reverse topological order
-    Vec_PtrClear( p->vMapped );
-    for ( i = p->nLevelMax; i >= 0; i-- )
-        for ( pObj = ppStore[i]; pObj; pObj = pObj->pCopy )
-            Vec_PtrPush( p->vMapped, pObj );
-    free( ppStore );
-    return aArea;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Computes area, references, and nodes used in the mapping.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-float If_ManScanMappingSeq_rec( If_Man_t * p, If_Obj_t * pObj, Vec_Ptr_t * vMapped )
-{
-    If_Obj_t * pLeaf;
-    If_Cut_t * pCutBest;
-    float aArea;
-    int i, Shift;
-    // treat latches transparently
-    if ( If_ObjIsLatch(pObj) )
-        return If_ManScanMappingSeq_rec( p, If_ObjFanin0(pObj), vMapped );
-    // consider trivial cases
-    if ( pObj->nRefs++ || If_ObjIsPi(pObj) || If_ObjIsConst1(pObj) )
-        return 0.0;
-    // store the node in the structure by level
-    assert( If_ObjIsAnd(pObj) );
-    // visit the transitive fanin of the selected cut
-    pCutBest = If_ObjCutBest(pObj);
-    aArea = If_ObjIsAnd(pObj)? If_CutLutArea(p, pCutBest) : (float)0.0;
-    If_CutForEachLeafSeq( p, pCutBest, pLeaf, Shift, i )
-        aArea += If_ManScanMappingSeq_rec( p, pLeaf, vMapped );
-    // add the node
-    Vec_PtrPush( vMapped, pObj );
-    return aArea;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Computes area, references, and nodes used in the mapping.]
-
-  Description [Collects the nodes in reverse topological order in array 
-  p->vMapping.]
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-float If_ManScanMappingSeq( If_Man_t * p )
-{
-    If_Obj_t * pObj;
-    float aArea;
-    int i;
-    assert( p->pPars->fLiftLeaves );
-    // clean all references
-    If_ManForEachObj( p, pObj, i )
-        pObj->nRefs = 0;
-    // collect nodes reachable from POs in the DFS order through the best cuts
-    aArea = 0;
-    Vec_PtrClear( p->vMapped );
-    If_ManForEachPo( p, pObj, i )
-        aArea += If_ManScanMappingSeq_rec( p, If_ObjFanin0(pObj), p->vMapped );
-    return aArea;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Computes area, references, and nodes used in the mapping.]
-
-  Description [Collects the nodes in reverse topological order in array 
-  p->vMapping.]
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void If_ManResetOriginalRefs( If_Man_t * p )
-{
-    If_Obj_t * pObj;
-    int i;
-    If_ManForEachObj( p, pObj, i )
-        pObj->nRefs = 0;
-    If_ManForEachObj( p, pObj, i )
-    {
-        if ( If_ObjIsAnd(pObj) )
-        {
-            pObj->pFanin0->nRefs++;
-            pObj->pFanin1->nRefs++;
-        }
-        else if ( If_ObjIsCo(pObj) )
-            pObj->pFanin0->nRefs++;
-    }
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Computes cross-cut of the circuit.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int If_ManCrossCut( If_Man_t * p )
-{
-    If_Obj_t * pObj, * pFanin;
-    int i, nCutSize = 0, nCutSizeMax = 0;
-    If_ManForEachObj( p, pObj, i )
-    {
-        if ( !If_ObjIsAnd(pObj) )
-            continue;
-        // consider the node
-        if ( nCutSizeMax < ++nCutSize )
-            nCutSizeMax = nCutSize;
-        if ( pObj->nVisits == 0 )
-            nCutSize--;
-        // consider the fanins
-        pFanin = If_ObjFanin0(pObj);
-        if ( !If_ObjIsCi(pFanin) && --pFanin->nVisits == 0 )
-            nCutSize--;
-        pFanin = If_ObjFanin1(pObj);
-        if ( !If_ObjIsCi(pFanin) && --pFanin->nVisits == 0 )
-            nCutSize--;
-        // consider the choice class
-        if ( pObj->fRepr )
-            for ( pFanin = pObj; pFanin; pFanin = pFanin->pEquiv )
-                if ( !If_ObjIsCi(pFanin) && --pFanin->nVisits == 0 )
-                    nCutSize--;
-    }
-    If_ManForEachObj( p, pObj, i )
-    {
-        assert( If_ObjIsCi(pObj) || pObj->fVisit == 0 );
-        pObj->nVisits = pObj->nVisitsCopy;
-    }
-    assert( nCutSize == 0 );
-//    printf( "Max cross cut size = %6d.\n", nCutSizeMax );
-    return nCutSizeMax;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Computes cross-cut of the circuit.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int If_ManCountTrueArea( If_Man_t * p )
-{
-    If_Obj_t * pObj;
-    int i, Area = 0;
-    Vec_PtrForEachEntry( p->vMapped, pObj, i )
-        Area += 1 + (If_ObjCutBest(pObj)->nLeaves > (unsigned)p->pPars->nLutSize / 2);
-    return Area;
-}
-
-////////////////////////////////////////////////////////////////////////
-///                       END OF FILE                                ///
-////////////////////////////////////////////////////////////////////////
-
-
diff --git a/abc70930/src/map/if/if_.c b/abc70930/src/map/if/if_.c
deleted file mode 100644
index d2960077..00000000
--- a/abc70930/src/map/if/if_.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/**CFile****************************************************************
-
-  FileName    [if_.c]
-
-  SystemName  [ABC: Logic synthesis and verification system.]
-
-  PackageName [FPGA mapping based on priority cuts.]
-
-  Synopsis    []
-
-  Author      [Alan Mishchenko]
-  
-  Affiliation [UC Berkeley]
-
-  Date        [Ver. 1.0. Started - November 21, 2006.]
-
-  Revision    [$Id: if_.c,v 1.00 2006/11/21 00:00:00 alanmi Exp $]
-
-***********************************************************************/
-
-#include "if.h"
-
-////////////////////////////////////////////////////////////////////////
-///                        DECLARATIONS                              ///
-////////////////////////////////////////////////////////////////////////
-
-////////////////////////////////////////////////////////////////////////
-///                     FUNCTION DEFINITIONS                         ///
-////////////////////////////////////////////////////////////////////////
-
-/**Function*************************************************************
-
-  Synopsis    []
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-
-////////////////////////////////////////////////////////////////////////
-///                       END OF FILE                                ///
-////////////////////////////////////////////////////////////////////////
-
-
diff --git a/abc70930/src/map/if/module.make b/abc70930/src/map/if/module.make
deleted file mode 100644
index f3d189be..00000000
--- a/abc70930/src/map/if/module.make
+++ /dev/null
@@ -1,9 +0,0 @@
-SRC +=  src/map/if/ifCore.c \
-    src/map/if/ifCut.c \
-    src/map/if/ifMan.c \
-    src/map/if/ifMap.c \
-    src/map/if/ifReduce.c \
-    src/map/if/ifSeq.c \
-    src/map/if/ifTime.c \
-    src/map/if/ifTruth.c \
-    src/map/if/ifUtil.c 
diff --git a/abc70930/src/map/mapper/mapper.c b/abc70930/src/map/mapper/mapper.c
deleted file mode 100644
index b18b68c0..00000000
--- a/abc70930/src/map/mapper/mapper.c
+++ /dev/null
@@ -1,176 +0,0 @@
-/**CFile****************************************************************
-
-  FileName    [mapper.c]
-
-  PackageName [MVSIS 1.3: Multi-valued logic synthesis system.]
-
-  Synopsis    [Command file for the mapper package.]
-
-  Author      [MVSIS Group]
-  
-  Affiliation [UC Berkeley]
-
-  Date        [Ver. 2.0. Started - June 1, 2004.]
-
-  Revision    [$Id: mapper.c,v 1.7 2005/01/23 06:59:42 alanmi Exp $]
-
-***********************************************************************/
-
-#include "abc.h"
-#include "mainInt.h"
-#include "mio.h"
-#include "mapperInt.h"
-
-////////////////////////////////////////////////////////////////////////
-///                        DECLARATIONS                              ///
-////////////////////////////////////////////////////////////////////////
-
-static int Map_CommandReadLibrary ( Abc_Frame_t * pAbc, int argc, char **argv );
-
-////////////////////////////////////////////////////////////////////////
-///                     FUNCTION DEFINITIONS                         ///
-////////////////////////////////////////////////////////////////////////
-
-/**Function*************************************************************
-
-  Synopsis    []
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Map_Init( Abc_Frame_t * pAbc )
-{
-    Cmd_CommandAdd( pAbc, "SC mapping", "read_super",  Map_CommandReadLibrary, 0 ); 
-}
-
-/**Function*************************************************************
-
-  Synopsis    []
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Map_End()
-{
-//    Map_SuperLibFree( s_pSuperLib );
-     Map_SuperLibFree( Abc_FrameReadLibSuper() );
-}
-
-
-/**Function*************************************************************
-
-  Synopsis    []
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Map_CommandReadLibrary( Abc_Frame_t * pAbc, int argc, char **argv )
-{
-    FILE * pFile;
-    FILE * pOut, * pErr;
-    Map_SuperLib_t * pLib;
-    Abc_Ntk_t * pNet;
-    char * FileName, * ExcludeFile;
-    int fVerbose;
-    int fAlgorithm;
-    int c;
-
-    pNet = Abc_FrameReadNtk(pAbc);
-    pOut = Abc_FrameReadOut(pAbc);
-    pErr = Abc_FrameReadErr(pAbc);
-
-    // set the defaults
-    fVerbose = 1;
-    fAlgorithm = 1;
-    ExcludeFile = 0;
-    Extra_UtilGetoptReset();
-    while ( (c = Extra_UtilGetopt(argc, argv, "eovh")) != EOF ) 
-    {
-        switch (c) 
-        {
-            case 'e':
-                ExcludeFile = argv[globalUtilOptind];
-                if ( ExcludeFile == 0 )
-                    goto usage;
-                globalUtilOptind++;
-                break;
-            case 'o':
-                fAlgorithm ^= 1;
-                break;
-            case 'v':
-                fVerbose ^= 1;
-                break;
-            case 'h':
-                goto usage;
-                break;
-            default:
-                goto usage;
-        }
-    }
-
-
-    if ( argc != globalUtilOptind + 1 )
-    {
-        goto usage;
-    }
-
-    // get the input file name
-    FileName = argv[globalUtilOptind];
-    if ( (pFile = Io_FileOpen( FileName, "open_path", "r", 0 )) == NULL )
-//    if ( (pFile = fopen( FileName, "r" )) == NULL )
-    {
-        fprintf( pErr, "Cannot open input file \"%s\". ", FileName );
-        if ( FileName = Extra_FileGetSimilarName( FileName, ".genlib", ".lib", ".gen", ".g", NULL ) )
-            fprintf( pErr, "Did you mean \"%s\"?", FileName );
-        fprintf( pErr, "\n" );
-        return 1;
-    }
-    fclose( pFile );
-
-    // set the new network
-    pLib = Map_SuperLibCreate( FileName, ExcludeFile, fAlgorithm, fVerbose );
-    if ( pLib == NULL )
-    {
-        fprintf( pErr, "Reading supergate library has failed.\n" );
-        goto usage;
-    }
-    // replace the current library
-//    Map_SuperLibFree( s_pSuperLib );
-//    s_pSuperLib = pLib;
-    Map_SuperLibFree( Abc_FrameReadLibSuper() );
-    Abc_FrameSetLibSuper( pLib );
-    // replace the current genlib library
-//    if ( s_pLib ) Mio_LibraryDelete( s_pLib );
-//    s_pLib = s_pSuperLib->pGenlib;
-    Mio_LibraryDelete( Abc_FrameReadLibGen() );
-    Abc_FrameSetLibGen( pLib->pGenlib );
-    return 0;
-
-usage:
-    fprintf( pErr, "\nusage: read_super [-ovh]\n");
-    fprintf( pErr, "\t         read the supergate library from the file\n" );  
-    fprintf( pErr, "\t-e file : file contains list of genlib gates to exclude\n" );
-    fprintf( pErr, "\t-o      : toggles the use of old file format [default = %s]\n", (fAlgorithm? "new" : "old") );
-    fprintf( pErr, "\t-v      : toggles enabling of verbose output [default = %s]\n", (fVerbose? "yes" : "no") );
-    fprintf( pErr, "\t-h      : print the command usage\n");
-    return 1;       /* error exit */
-}
-
-
-////////////////////////////////////////////////////////////////////////
-///                       END OF FILE                                ///
-////////////////////////////////////////////////////////////////////////
-
-
diff --git a/abc70930/src/map/mapper/mapper.h b/abc70930/src/map/mapper/mapper.h
deleted file mode 100644
index 8eade761..00000000
--- a/abc70930/src/map/mapper/mapper.h
+++ /dev/null
@@ -1,195 +0,0 @@
-/**CFile****************************************************************
-
-  FileName    [mapper.h]
- 
-  PackageName [MVSIS 2.0: Multi-valued logic synthesis system.]
-
-  Synopsis    [Generic technology mapping engine.]
-
-  Author      [MVSIS Group]
-  
-  Affiliation [UC Berkeley]
-
-  Date        [Ver. 2.0. Started - June 1, 2004.]
-
-  Revision    [$Id: mapper.h,v 1.11 2005/02/28 05:34:26 alanmi Exp $]
-
-***********************************************************************/
-
-#ifndef __MAPPER_H__
-#define __MAPPER_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-////////////////////////////////////////////////////////////////////////
-///                          INCLUDES                                ///
-////////////////////////////////////////////////////////////////////////
-
-
-////////////////////////////////////////////////////////////////////////
-///                         PARAMETERS                               ///
-////////////////////////////////////////////////////////////////////////
-
-////////////////////////////////////////////////////////////////////////
-///                    STRUCTURE DEFINITIONS                         ///
-////////////////////////////////////////////////////////////////////////
-
-typedef struct Map_ManStruct_t_         Map_Man_t;
-typedef struct Map_NodeStruct_t_        Map_Node_t;
-typedef struct Map_NodeVecStruct_t_     Map_NodeVec_t;
-typedef struct Map_CutStruct_t_         Map_Cut_t;
-typedef struct Map_MatchStruct_t_       Map_Match_t;
-typedef struct Map_SuperStruct_t_       Map_Super_t;
-typedef struct Map_SuperLibStruct_t_    Map_SuperLib_t;
-typedef struct Map_HashTableStruct_t_   Map_HashTable_t;
-typedef struct Map_HashEntryStruct_t_   Map_HashEntry_t;
-typedef struct Map_TimeStruct_t_        Map_Time_t;
-
-// the pair of rise/fall time parameters
-struct Map_TimeStruct_t_
-{
-    float              Rise;
-    float              Fall;
-    float              Worst;
-};
-
-////////////////////////////////////////////////////////////////////////
-///                       GLOBAL VARIABLES                           ///
-////////////////////////////////////////////////////////////////////////
-
-////////////////////////////////////////////////////////////////////////
-///                       MACRO DEFINITIONS                          ///
-////////////////////////////////////////////////////////////////////////
- 
-#define Map_IsComplement(p)    (((int)((unsigned long) (p) & 01)))
-#define Map_Regular(p)         ((Map_Node_t *)((unsigned long)(p) & ~01)) 
-#define Map_Not(p)             ((Map_Node_t *)((unsigned long)(p) ^ 01)) 
-#define Map_NotCond(p,c)       ((Map_Node_t *)((unsigned long)(p) ^ (c)))
-
-////////////////////////////////////////////////////////////////////////
-///                     FUNCTION DEFINITIONS                         ///
-////////////////////////////////////////////////////////////////////////
-
-/*=== mapperCreate.c =============================================================*/
-extern Map_Man_t *     Map_ManCreate( int nInputs, int nOutputs, int fVerbose );
-extern Map_Node_t *    Map_NodeCreate( Map_Man_t * p, Map_Node_t * p1, Map_Node_t * p2 );
-extern void            Map_ManFree( Map_Man_t * pMan );
-extern void            Map_ManPrintTimeStats( Map_Man_t * p );
-extern void            Map_ManPrintStatsToFile( char * pName, float Area, float Delay, int Time );
-extern int             Map_ManReadInputNum( Map_Man_t * p );
-extern int             Map_ManReadOutputNum( Map_Man_t * p );
-extern Map_Node_t **   Map_ManReadInputs ( Map_Man_t * p );
-extern Map_Node_t **   Map_ManReadOutputs( Map_Man_t * p );
-extern Map_Node_t *    Map_ManReadConst1 ( Map_Man_t * p );
-extern Map_Time_t *    Map_ManReadInputArrivals( Map_Man_t * p );
-extern Mio_Library_t * Map_ManReadGenLib ( Map_Man_t * p );
-extern bool            Map_ManReadVerbose( Map_Man_t * p );
-extern float           Map_ManReadAreaFinal( Map_Man_t * p );
-extern float           Map_ManReadRequiredGlo( Map_Man_t * p );
-extern void            Map_ManSetTimeToMap( Map_Man_t * p, int Time );
-extern void            Map_ManSetTimeToNet( Map_Man_t * p, int Time );
-extern void            Map_ManSetTimeSweep( Map_Man_t * p, int Time );
-extern void            Map_ManSetTimeTotal( Map_Man_t * p, int Time );
-extern void            Map_ManSetOutputNames( Map_Man_t * p, char ** ppNames );
-extern void            Map_ManSetAreaRecovery( Map_Man_t * p, int fAreaRecovery );
-extern void            Map_ManSetDelayTarget( Map_Man_t * p, float DelayTarget );
-extern void            Map_ManSetInputArrivals( Map_Man_t * p, Map_Time_t * pArrivals );
-extern void            Map_ManSetObeyFanoutLimits( Map_Man_t * p, bool fObeyFanoutLimits );              
-extern void            Map_ManSetNumIterations( Map_Man_t * p, int nNumIterations );
-extern int             Map_ManReadPass( Map_Man_t * p );
-extern void            Map_ManSetPass( Map_Man_t * p, int nPass );
-extern int             Map_ManReadFanoutViolations( Map_Man_t * p );
-extern void            Map_ManSetFanoutViolations( Map_Man_t * p, int nVio );
-extern void            Map_ManSetChoiceNodeNum( Map_Man_t * p, int nChoiceNodes );
-extern void            Map_ManSetChoiceNum( Map_Man_t * p, int nChoices );
-extern void            Map_ManSetVerbose( Map_Man_t * p, int fVerbose );
-extern void            Map_ManSetSwitching( Map_Man_t * p, int fSwitching );
-
-extern Map_Man_t *     Map_NodeReadMan( Map_Node_t * p );
-extern char *          Map_NodeReadData( Map_Node_t * p, int fPhase );
-extern int             Map_NodeReadNum( Map_Node_t * p );
-extern int             Map_NodeReadLevel( Map_Node_t * p );
-extern Map_Cut_t *     Map_NodeReadCuts( Map_Node_t * p );
-extern Map_Cut_t *     Map_NodeReadCutBest( Map_Node_t * p, int fPhase );
-extern Map_Node_t *    Map_NodeReadOne( Map_Node_t * p );
-extern Map_Node_t *    Map_NodeReadTwo( Map_Node_t * p );
-extern void            Map_NodeSetData( Map_Node_t * p, int fPhase, char * pData );
-extern void            Map_NodeSetNextE( Map_Node_t * p, Map_Node_t * pNextE );
-extern void            Map_NodeSetRepr( Map_Node_t * p, Map_Node_t * pRepr );
-extern void            Map_NodeSetSwitching( Map_Node_t * p, float Switching );
-
-extern int             Map_NodeIsConst( Map_Node_t * p );
-extern int             Map_NodeIsVar( Map_Node_t * p );
-extern int             Map_NodeIsAnd( Map_Node_t * p );
-extern int             Map_NodeComparePhase( Map_Node_t * p1, Map_Node_t * p2 );
-
-extern Map_Super_t *   Map_CutReadSuperBest( Map_Cut_t * p, int fPhase );
-extern Map_Super_t *   Map_CutReadSuper0( Map_Cut_t * p );
-extern Map_Super_t *   Map_CutReadSuper1( Map_Cut_t * p );
-extern int             Map_CutReadLeavesNum( Map_Cut_t * p );
-extern Map_Node_t **   Map_CutReadLeaves( Map_Cut_t * p );
-extern unsigned        Map_CutReadPhaseBest( Map_Cut_t * p, int fPhase );
-extern unsigned        Map_CutReadPhase0( Map_Cut_t * p );
-extern unsigned        Map_CutReadPhase1( Map_Cut_t * p );
-extern Map_Cut_t *     Map_CutReadNext( Map_Cut_t * p );
-
-extern char *          Map_SuperReadFormula( Map_Super_t * p );
-extern Mio_Gate_t *    Map_SuperReadRoot( Map_Super_t * p );
-extern int             Map_SuperReadNum( Map_Super_t * p );
-extern Map_Super_t **  Map_SuperReadFanins( Map_Super_t * p );
-extern int             Map_SuperReadFaninNum( Map_Super_t * p );
-extern Map_Super_t *   Map_SuperReadNext( Map_Super_t * p );
-extern int             Map_SuperReadNumPhases( Map_Super_t * p );
-extern unsigned char * Map_SuperReadPhases( Map_Super_t * p );
-extern int             Map_SuperReadFanoutLimit( Map_Super_t * p );
-
-extern Mio_Library_t * Map_SuperLibReadGenLib( Map_SuperLib_t * p );
-extern float           Map_SuperLibReadAreaInv( Map_SuperLib_t * p );
-extern Map_Time_t      Map_SuperLibReadDelayInv( Map_SuperLib_t * p );
-extern int             Map_SuperLibReadVarsMax( Map_SuperLib_t * p );
-
-extern Map_Node_t *    Map_NodeAnd( Map_Man_t * p, Map_Node_t * p1, Map_Node_t * p2 );
-extern Map_Node_t *    Map_NodeOr( Map_Man_t * p, Map_Node_t * p1, Map_Node_t * p2 );
-extern Map_Node_t *    Map_NodeExor( Map_Man_t * p, Map_Node_t * p1, Map_Node_t * p2 );
-extern Map_Node_t *    Map_NodeMux( Map_Man_t * p, Map_Node_t * pNode, Map_Node_t * pNodeT, Map_Node_t * pNodeE );
-extern void            Map_NodeSetChoice( Map_Man_t * pMan, Map_Node_t * pNodeOld, Map_Node_t * pNodeNew );
-
-/*=== resmCanon.c =============================================================*/
-extern int             Map_CanonComputeSlow( unsigned uTruths[][2], int nVarsMax, int nVarsReal, unsigned uTruth[], unsigned char * puPhases, unsigned uTruthRes[] );
-extern int             Map_CanonComputeFast( Map_Man_t * p, int nVarsMax, int nVarsReal, unsigned uTruth[], unsigned char * puPhases, unsigned uTruthRes[] );
-/*=== mapperCut.c =============================================================*/
-extern Map_Cut_t *     Map_CutAlloc( Map_Man_t * p );
-/*=== mapperCutUtils.c =============================================================*/
-extern void            Map_CutCreateFromNode( Map_Man_t * p, Map_Super_t * pSuper, int iRoot, unsigned uPhaseRoot, 
-                           int * pLeaves, int nLeaves, unsigned uPhaseLeaves );
-/*=== mapperCore.c =============================================================*/
-extern int             Map_Mapping( Map_Man_t * p );
-/*=== mapperLib.c =============================================================*/
-extern int             Map_SuperLibDeriveFromGenlib( Mio_Library_t * pLib );
-/*=== mapperMntk.c =============================================================*/
-//extern Mntk_Man_t *    Map_ConvertMappingToMntk( Map_Man_t * pMan );
-/*=== mapperSuper.c =============================================================*/
-extern char *          Map_LibraryReadFormulaStep( char * pFormula, char * pStrings[], int * pnStrings );
-/*=== mapperSweep.c =============================================================*/
-extern void            Map_NetworkSweep( Abc_Ntk_t * pNet );
-/*=== mapperTable.c =============================================================*/
-extern Map_Super_t *   Map_SuperTableLookupC( Map_SuperLib_t * pLib, unsigned uTruth[] );
-/*=== mapperTime.c =============================================================*/
-/*=== mapperUtil.c =============================================================*/
-extern int             Map_ManCheckConsistency( Map_Man_t * p );
-extern st_table *      Map_CreateTableGate2Super( Map_Man_t * p );
-extern void            Map_ManCleanData( Map_Man_t * p );
-extern void            Map_MappingSetupTruthTables( unsigned uTruths[][2] );
-extern void            Map_MappingSetupTruthTablesLarge( unsigned uTruths[][32] );
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-////////////////////////////////////////////////////////////////////////
-///                       END OF FILE                                ///
-////////////////////////////////////////////////////////////////////////
diff --git a/abc70930/src/map/mapper/mapperCanon.c b/abc70930/src/map/mapper/mapperCanon.c
deleted file mode 100644
index 203c9142..00000000
--- a/abc70930/src/map/mapper/mapperCanon.c
+++ /dev/null
@@ -1,271 +0,0 @@
-/**CFile****************************************************************
-
-  FileName    [mapperCanon.c]
-
-  PackageName [MVSIS 1.3: Multi-valued logic synthesis system.]
-
-  Synopsis    [Generic technology mapping engine.]
-
-  Author      [MVSIS Group]
-  
-  Affiliation [UC Berkeley]
-
-  Date        [Ver. 2.0. Started - June 1, 2004.]
-
-  Revision    [$Id: mapperCanon.c,v 1.2 2005/01/23 06:59:42 alanmi Exp $]
-
-***********************************************************************/
-
-#include "mapperInt.h"
-
-////////////////////////////////////////////////////////////////////////
-///                        DECLARATIONS                              ///
-////////////////////////////////////////////////////////////////////////
-
-static unsigned Map_CanonComputePhase( unsigned uTruths[][2], int nVars, unsigned uTruth, unsigned uPhase );
-static void     Map_CanonComputePhase6( unsigned uTruths[][2], int nVars, unsigned uTruth[], unsigned uPhase, unsigned uTruthRes[] );
-
-////////////////////////////////////////////////////////////////////////
-///                     FUNCTION DEFINITIONS                         ///
-////////////////////////////////////////////////////////////////////////
-
-/**Function*************************************************************
-
-  Synopsis    [Computes the N-canonical form of the Boolean function.]
-
-  Description [The N-canonical form is defined as the truth table with 
-  the minimum integer value. This function exhaustively enumerates 
-  through the complete set of 2^N phase assignments.]
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Map_CanonComputeSlow( unsigned uTruths[][2], int nVarsMax, int nVarsReal, unsigned uTruth[], unsigned char * puPhases, unsigned uTruthRes[] )
-{
-    unsigned  uTruthPerm[2];
-    int nMints, nPhases, m;
-
-    nPhases = 0;
-    nMints = (1 << nVarsReal);
-    if ( nVarsMax < 6 )
-    {
-        uTruthRes[0] = MAP_MASK(32);
-        for ( m = 0; m < nMints; m++ )
-        {
-            uTruthPerm[0] = Map_CanonComputePhase( uTruths, nVarsMax, uTruth[0], m );
-            if ( uTruthRes[0] > uTruthPerm[0] )
-            {
-                uTruthRes[0] = uTruthPerm[0];
-                nPhases      = 0;
-                puPhases[nPhases++] = (unsigned char)m;
-            }
-            else if ( uTruthRes[0] == uTruthPerm[0] )
-            {
-                if ( nPhases < 4 ) // the max number of phases in Map_Super_t
-                    puPhases[nPhases++] = (unsigned char)m;
-            }
-        }
-        uTruthRes[1] = uTruthRes[0];
-    }
-    else
-    {
-        uTruthRes[0] = MAP_MASK(32);
-        uTruthRes[1] = MAP_MASK(32);
-        for ( m = 0; m < nMints; m++ )
-        {
-            Map_CanonComputePhase6( uTruths, nVarsMax, uTruth, m, uTruthPerm );
-            if ( uTruthRes[1] > uTruthPerm[1] || uTruthRes[1] == uTruthPerm[1] && uTruthRes[0] > uTruthPerm[0] )
-            {
-                uTruthRes[0] = uTruthPerm[0];
-                uTruthRes[1] = uTruthPerm[1];
-                nPhases      = 0;
-                puPhases[nPhases++] = (unsigned char)m;
-            }
-            else if ( uTruthRes[1] == uTruthPerm[1] && uTruthRes[0] == uTruthPerm[0] )
-            {
-                if ( nPhases < 4 ) // the max number of phases in Map_Super_t
-                    puPhases[nPhases++] = (unsigned char)m;
-            }
-        }
-    }
-    assert( nPhases > 0 );
-//    printf( "%d ", nPhases );
-    return nPhases;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Performs phase transformation for one function of less than 6 variables.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-unsigned Map_CanonComputePhase( unsigned uTruths[][2], int nVars, unsigned uTruth, unsigned uPhase )
-{
-    int v, Shift;
-    for ( v = 0, Shift = 1; v < nVars; v++, Shift <<= 1 )
-        if ( uPhase & Shift )
-            uTruth = (((uTruth & ~uTruths[v][0]) << Shift) | ((uTruth & uTruths[v][0]) >> Shift));
-    return uTruth;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Performs phase transformation for one function of 6 variables.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Map_CanonComputePhase6( unsigned uTruths[][2], int nVars, unsigned uTruth[], unsigned uPhase, unsigned uTruthRes[] )
-{
-    unsigned uTemp;
-    int v, Shift;
-
-    // initialize the result
-    uTruthRes[0] = uTruth[0];
-    uTruthRes[1] = uTruth[1];
-    if ( uPhase == 0 )
-        return;
-    // compute the phase 
-    for ( v = 0, Shift = 1; v < nVars; v++, Shift <<= 1 )
-        if ( uPhase & Shift )
-        {
-            if ( Shift < 32 )
-            {
-                uTruthRes[0] = (((uTruthRes[0] & ~uTruths[v][0]) << Shift) | ((uTruthRes[0] & uTruths[v][0]) >> Shift));
-                uTruthRes[1] = (((uTruthRes[1] & ~uTruths[v][1]) << Shift) | ((uTruthRes[1] & uTruths[v][1]) >> Shift));
-            }
-            else
-            {
-                uTemp        = uTruthRes[0];
-                uTruthRes[0] = uTruthRes[1];
-                uTruthRes[1] = uTemp;
-            }
-        }
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Computes the N-canonical form of the Boolean function.]
-
-  Description [The N-canonical form is defined as the truth table with 
-  the minimum integer value. This function exhaustively enumerates 
-  through the complete set of 2^N phase assignments.]
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Map_CanonComputeFast( Map_Man_t * p, int nVarsMax, int nVarsReal, unsigned uTruth[], unsigned char * puPhases, unsigned uTruthRes[] )
-{
-    unsigned uTruth0, uTruth1;
-    unsigned uCanon0, uCanon1, uCanonBest, uPhaseBest;
-    int i, Limit;
-
-    if ( nVarsMax == 6 )
-        return Map_CanonComputeSlow( p->uTruths, nVarsMax, nVarsReal, uTruth, puPhases, uTruthRes );
-
-    if ( nVarsReal < 5 )
-    {
-//        return Map_CanonComputeSlow( p->uTruths, nVarsMax, nVarsReal, uTruth, puPhases, uTruthRes );
-
-        uTruth0 = uTruth[0] & 0xFFFF;
-        assert( p->pCounters[uTruth0] > 0 );
-        uTruthRes[0] = (p->uCanons[uTruth0] << 16) | p->uCanons[uTruth0];
-        uTruthRes[1] = uTruthRes[0];
-        puPhases[0] = p->uPhases[uTruth0][0];
-        return 1;
-    }
-
-    assert( nVarsMax == 5 );
-    assert( nVarsReal == 5 );
-    uTruth0 = uTruth[0] & 0xFFFF;
-    uTruth1 = (uTruth[0] >> 16);
-    if ( uTruth1 == 0 )
-    {
-        uTruthRes[0] = p->uCanons[uTruth0];
-        uTruthRes[1] = uTruthRes[0];
-        Limit = (p->pCounters[uTruth0] > 4)? 4 : p->pCounters[uTruth0];
-        for ( i = 0; i < Limit; i++ )
-            puPhases[i] = p->uPhases[uTruth0][i];
-        return Limit;
-    }
-    else if ( uTruth0 == 0 )
-    {
-        uTruthRes[0] = p->uCanons[uTruth1];
-        uTruthRes[1] = uTruthRes[0];
-        Limit = (p->pCounters[uTruth1] > 4)? 4 : p->pCounters[uTruth1];
-        for ( i = 0; i < Limit; i++ )
-        {
-            puPhases[i] = p->uPhases[uTruth1][i];
-            puPhases[i] |= (1 << 4);
-        }
-        return Limit;
-    }
-    uCanon0 = p->uCanons[uTruth0];
-    uCanon1 = p->uCanons[uTruth1];
-    if ( uCanon0 >= uCanon1 ) // using nCanon1 as the main one
-    {
-        assert( p->pCounters[uTruth1] > 0 );
-        uCanonBest = 0xFFFFFFFF;
-        for ( i = 0; i < p->pCounters[uTruth1]; i++ )
-        {
-            uCanon0 = Extra_TruthPolarize( uTruth0, p->uPhases[uTruth1][i], 4 );
-            if ( uCanonBest > uCanon0 )
-            {
-                uCanonBest = uCanon0;
-                uPhaseBest = p->uPhases[uTruth1][i];
-                assert( uPhaseBest < 16 );
-            }
-        }
-        uTruthRes[0] = (uCanon1 << 16) | uCanonBest;
-        uTruthRes[1] = uTruthRes[0];
-        puPhases[0] = uPhaseBest;
-        return 1;
-    }
-    else if ( uCanon0 < uCanon1 )
-    {
-        assert( p->pCounters[uTruth0] > 0 );
-        uCanonBest = 0xFFFFFFFF;
-        for ( i = 0; i < p->pCounters[uTruth0]; i++ )
-        {
-            uCanon1 = Extra_TruthPolarize( uTruth1, p->uPhases[uTruth0][i], 4 );
-            if ( uCanonBest > uCanon1 )
-            {
-                uCanonBest = uCanon1;
-                uPhaseBest = p->uPhases[uTruth0][i];
-                assert( uPhaseBest < 16 );
-            }
-        }
-        uTruthRes[0] = (uCanon0 << 16) | uCanonBest;
-        uTruthRes[1] = uTruthRes[0];
-        puPhases[0] = uPhaseBest | (1 << 4);
-        return 1;
-    }
-    else
-    {
-        assert( 0 );
-        return Map_CanonComputeSlow( p->uTruths, nVarsMax, nVarsReal, uTruth, puPhases, uTruthRes );
-    }
-}
-
-
-
-
-
-////////////////////////////////////////////////////////////////////////
-///                       END OF FILE                                ///
-////////////////////////////////////////////////////////////////////////
-
-
diff --git a/abc70930/src/map/mapper/mapperCore.c b/abc70930/src/map/mapper/mapperCore.c
deleted file mode 100644
index 5d4854e6..00000000
--- a/abc70930/src/map/mapper/mapperCore.c
+++ /dev/null
@@ -1,228 +0,0 @@
-/**CFile****************************************************************
-
-  FileName    [mapperCore.c]
-
-  PackageName [MVSIS 1.3: Multi-valued logic synthesis system.]
-
-  Synopsis    [Generic technology mapping engine.]
-
-  Author      [MVSIS Group]
-  
-  Affiliation [UC Berkeley]
-
-  Date        [Ver. 2.0. Started - June 1, 2004.]
-
-  Revision    [$Id: mapperCore.c,v 1.7 2004/10/01 23:41:04 satrajit Exp $]
-
-***********************************************************************/
-
-#include "mapperInt.h"
-//#include "resm.h"
-
-////////////////////////////////////////////////////////////////////////
-///                        DECLARATIONS                              ///
-////////////////////////////////////////////////////////////////////////
-
-////////////////////////////////////////////////////////////////////////
-///                     FUNCTION DEFINITIONS                         ///
-////////////////////////////////////////////////////////////////////////
-
-/**Function*************************************************************
-
-  Synopsis    [Performs technology mapping for the given object graph.]
-
-  Description [The object graph is stored in the mapping manager.
-  First, the AND nodes that fanout into POs are collected in the DFS order.
-  Two preprocessing steps are performed: the k-feasible cuts are computed 
-  for each node and the truth tables are computed for each cut. Next, the 
-  delay-optimal matches are assigned for each node, followed by several 
-  iterations of area recoveryd: using area flow (global optimization) 
-  and using exact area at a node (local optimization).]
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Map_Mapping( Map_Man_t * p )
-{
-    int fShowSwitching         = 1;
-    int fUseAreaFlow           = 1;
-    int fUseExactArea          = !p->fSwitching;
-    int fUseExactAreaWithPhase = !p->fSwitching;
-    int clk;
-
-    //////////////////////////////////////////////////////////////////////
-    // perform pre-mapping computations
-    // collect the nodes reachable from POs in the DFS order (including the choices)
-    p->vAnds = Map_MappingDfs( p, 1 );
-    if ( p->fVerbose )
-        Map_MappingReportChoices( p ); 
-    Map_MappingSetChoiceLevels( p ); // should always be called before mapping!
-//    return 1;
-
-    // compute the cuts of nodes in the DFS order
-    clk = clock();
-    Map_MappingCuts( p );
-    p->timeCuts = clock() - clk;
-    // derive the truth tables 
-    clk = clock();
-    Map_MappingTruths( p );
-    p->timeTruth = clock() - clk;
-    //////////////////////////////////////////////////////////////////////
-//PRT( "Truths", clock() - clk );
-
-    //////////////////////////////////////////////////////////////////////
-    // compute the minimum-delay mapping
-    clk = clock();
-    p->fMappingMode = 0;
-    if ( !Map_MappingMatches( p ) )
-        return 0;
-    p->timeMatch = clock() - clk;
-    // compute the references and collect the nodes used in the mapping
-    Map_MappingSetRefs( p );
-    p->AreaBase = Map_MappingGetArea( p, p->vMapping );
-if ( p->fVerbose )
-{
-printf( "Delay    : %s = %8.2f  Flow = %11.1f  Area = %11.1f  %4.1f %%   ", 
-                    fShowSwitching? "Switch" : "Delay", 
-                    fShowSwitching? Map_MappingGetSwitching(p,p->vMapping) : p->fRequiredGlo, 
-                    Map_MappingGetAreaFlow(p), p->AreaBase, 0.0 );
-PRT( "Time", p->timeMatch );
-}
-    //////////////////////////////////////////////////////////////////////
-
-    if ( !p->fAreaRecovery )
-    {
-        if ( p->fVerbose )
-            Map_MappingPrintOutputArrivals( p );
-        return 1;
-    }
-
-    //////////////////////////////////////////////////////////////////////
-    // perform area recovery using area flow
-    clk = clock();
-    if ( fUseAreaFlow )
-    {
-        // compute the required times
-        Map_TimeComputeRequiredGlobal( p );
-        // recover area flow
-        p->fMappingMode = 1;
-        Map_MappingMatches( p );
-        // compute the references and collect the nodes used in the mapping
-        Map_MappingSetRefs( p );
-        p->AreaFinal = Map_MappingGetArea( p, p->vMapping );
-if ( p->fVerbose )
-{
-printf( "AreaFlow : %s = %8.2f  Flow = %11.1f  Area = %11.1f  %4.1f %%   ", 
-                    fShowSwitching? "Switch" : "Delay", 
-                    fShowSwitching? Map_MappingGetSwitching(p,p->vMapping) : p->fRequiredGlo, 
-                    Map_MappingGetAreaFlow(p), p->AreaFinal, 
-                    100.0*(p->AreaBase-p->AreaFinal)/p->AreaBase );
-PRT( "Time", clock() - clk );
-}
-    }
-    p->timeArea += clock() - clk;
-    //////////////////////////////////////////////////////////////////////
-
-    //////////////////////////////////////////////////////////////////////
-    // perform area recovery using exact area
-    clk = clock();
-    if ( fUseExactArea )
-    {
-        // compute the required times
-        Map_TimeComputeRequiredGlobal( p );
-        // recover area
-        p->fMappingMode = 2;
-        Map_MappingMatches( p );
-        // compute the references and collect the nodes used in the mapping
-        Map_MappingSetRefs( p );
-        p->AreaFinal = Map_MappingGetArea( p, p->vMapping );
-if ( p->fVerbose )
-{
-printf( "Area     : %s = %8.2f  Flow = %11.1f  Area = %11.1f  %4.1f %%   ", 
-                    fShowSwitching? "Switch" : "Delay", 
-                    fShowSwitching? Map_MappingGetSwitching(p,p->vMapping) : p->fRequiredGlo, 
-                    0.0, p->AreaFinal, 
-                    100.0*(p->AreaBase-p->AreaFinal)/p->AreaBase );
-PRT( "Time", clock() - clk );
-}
-    }
-    p->timeArea += clock() - clk;
-    //////////////////////////////////////////////////////////////////////
-
-    //////////////////////////////////////////////////////////////////////
-    // perform area recovery using exact area
-    clk = clock();
-    if ( fUseExactAreaWithPhase )
-    {
-        // compute the required times
-        Map_TimeComputeRequiredGlobal( p );
-        // recover area
-        p->fMappingMode = 3;
-        Map_MappingMatches( p );
-        // compute the references and collect the nodes used in the mapping
-        Map_MappingSetRefs( p );
-        p->AreaFinal = Map_MappingGetArea( p, p->vMapping );
-if ( p->fVerbose )
-{
-printf( "Area     : %s = %8.2f  Flow = %11.1f  Area = %11.1f  %4.1f %%   ", 
-                    fShowSwitching? "Switch" : "Delay", 
-                    fShowSwitching? Map_MappingGetSwitching(p,p->vMapping) : p->fRequiredGlo, 
-                    0.0, p->AreaFinal, 
-                    100.0*(p->AreaBase-p->AreaFinal)/p->AreaBase );
-PRT( "Time", clock() - clk );
-}
-    }
-    p->timeArea += clock() - clk;
-    //////////////////////////////////////////////////////////////////////
-
-    //////////////////////////////////////////////////////////////////////
-    // perform area recovery using exact area
-    clk = clock();
-    if ( p->fSwitching )
-    {
-        // compute the required times
-        Map_TimeComputeRequiredGlobal( p );
-        // recover switching activity
-        p->fMappingMode = 4;
-        Map_MappingMatches( p );
-        // compute the references and collect the nodes used in the mapping
-        Map_MappingSetRefs( p );
-        p->AreaFinal = Map_MappingGetArea( p, p->vMapping );
-if ( p->fVerbose )
-{
-printf( "Switching: %s = %8.2f  Flow = %11.1f  Area = %11.1f  %4.1f %%   ", 
-                    fShowSwitching? "Switch" : "Delay", 
-                    fShowSwitching? Map_MappingGetSwitching(p,p->vMapping) : p->fRequiredGlo, 
-                    0.0, p->AreaFinal, 
-                    100.0*(p->AreaBase-p->AreaFinal)/p->AreaBase );
-PRT( "Time", clock() - clk );
-}
-
-        // compute the required times
-        Map_TimeComputeRequiredGlobal( p );
-        // recover switching activity
-        p->fMappingMode = 4;
-        Map_MappingMatches( p );
-        // compute the references and collect the nodes used in the mapping
-        Map_MappingSetRefs( p );
-        p->AreaFinal = Map_MappingGetArea( p, p->vMapping );
-if ( p->fVerbose )
-{
-printf( "Switching: %s = %8.2f  Flow = %11.1f  Area = %11.1f  %4.1f %%   ", 
-                    fShowSwitching? "Switch" : "Delay", 
-                    fShowSwitching? Map_MappingGetSwitching(p,p->vMapping) : p->fRequiredGlo, 
-                    0.0, p->AreaFinal, 
-                    100.0*(p->AreaBase-p->AreaFinal)/p->AreaBase );
-PRT( "Time", clock() - clk );
-}
-    }
-    p->timeArea += clock() - clk;
-    //////////////////////////////////////////////////////////////////////
-
-    // print the arrival times of the latest outputs
-    if ( p->fVerbose )
-        Map_MappingPrintOutputArrivals( p );
-    return 1;
-}
diff --git a/abc70930/src/map/mapper/mapperCreate.c b/abc70930/src/map/mapper/mapperCreate.c
deleted file mode 100644
index 157d467b..00000000
--- a/abc70930/src/map/mapper/mapperCreate.c
+++ /dev/null
@@ -1,600 +0,0 @@
-/**CFile****************************************************************
-
-  FileName    [mapperCreate.c]
-
-  PackageName [MVSIS 1.3: Multi-valued logic synthesis system.]
-
-  Synopsis    [Generic technology mapping engine.]
-
-  Author      [MVSIS Group]
-  
-  Affiliation [UC Berkeley]
-
-  Date        [Ver. 2.0. Started - June 1, 2004.]
-
-  Revision    [$Id: mapperCreate.c,v 1.15 2005/02/28 05:34:26 alanmi Exp $]
-
-***********************************************************************/
-
-#include "mapperInt.h"
-
-////////////////////////////////////////////////////////////////////////
-///                        DECLARATIONS                              ///
-////////////////////////////////////////////////////////////////////////
-
-static void            Map_TableCreate( Map_Man_t * p );
-static void            Map_TableResize( Map_Man_t * p );
-static Map_Node_t *    Map_TableLookup( Map_Man_t * p, Map_Node_t * p1, Map_Node_t * p2 );
-
-// hash key for the structural hash table
-static inline unsigned Map_HashKey2( Map_Node_t * p0, Map_Node_t * p1, int TableSize ) { return ((unsigned)(p0) + (unsigned)(p1) * 12582917) % TableSize; }
-
-////////////////////////////////////////////////////////////////////////
-///                     FUNCTION DEFINITIONS                         ///
-////////////////////////////////////////////////////////////////////////
-
-/**Function*************************************************************
-
-  Synopsis    [Reads parameters from the mapping manager.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int             Map_ManReadInputNum( Map_Man_t * p )                    { return p->nInputs;    }
-int             Map_ManReadOutputNum( Map_Man_t * p )                   { return p->nOutputs;   }
-Map_Node_t **   Map_ManReadInputs ( Map_Man_t * p )                     { return p->pInputs;    }
-Map_Node_t **   Map_ManReadOutputs( Map_Man_t * p )                     { return p->pOutputs;   }
-Map_Node_t *    Map_ManReadConst1 ( Map_Man_t * p )                     { return p->pConst1;    }
-Map_Time_t *    Map_ManReadInputArrivals( Map_Man_t * p )               { return p->pInputArrivals;}
-Mio_Library_t * Map_ManReadGenLib ( Map_Man_t * p )                     { return p->pSuperLib->pGenlib; }
-bool            Map_ManReadVerbose( Map_Man_t * p )                     { return p->fVerbose;   }
-float           Map_ManReadAreaFinal( Map_Man_t * p )                   { return p->AreaFinal;  }
-float           Map_ManReadRequiredGlo( Map_Man_t * p )                 { return p->fRequiredGlo;  }
-void            Map_ManSetTimeToMap( Map_Man_t * p, int Time )          { p->timeToMap = Time;  }
-void            Map_ManSetTimeToNet( Map_Man_t * p, int Time )          { p->timeToNet = Time;  }
-void            Map_ManSetTimeSweep( Map_Man_t * p, int Time )          { p->timeSweep = Time;  }
-void            Map_ManSetTimeTotal( Map_Man_t * p, int Time )          { p->timeTotal = Time;  }
-void            Map_ManSetOutputNames( Map_Man_t * p, char ** ppNames ) { p->ppOutputNames = ppNames; }
-void            Map_ManSetAreaRecovery( Map_Man_t * p, int fAreaRecovery ) { p->fAreaRecovery = fAreaRecovery;}
-void            Map_ManSetDelayTarget( Map_Man_t * p, float DelayTarget ) { p->DelayTarget = DelayTarget;}
-void            Map_ManSetInputArrivals( Map_Man_t * p, Map_Time_t * pArrivals ) { p->pInputArrivals = pArrivals;}
-void            Map_ManSetObeyFanoutLimits( Map_Man_t * p, bool fObeyFanoutLimits )  { p->fObeyFanoutLimits = fObeyFanoutLimits;     }
-void            Map_ManSetNumIterations( Map_Man_t * p, int nIterations )            { p->nIterations = nIterations;     }
-int             Map_ManReadFanoutViolations( Map_Man_t * p )            { return p->nFanoutViolations; }  
-void            Map_ManSetFanoutViolations( Map_Man_t * p, int nVio )   { p->nFanoutViolations = nVio; }  
-void            Map_ManSetChoiceNodeNum( Map_Man_t * p, int nChoiceNodes ) { p->nChoiceNodes = nChoiceNodes; }  
-void            Map_ManSetChoiceNum( Map_Man_t * p, int nChoices )         { p->nChoices = nChoices; }   
-void            Map_ManSetVerbose( Map_Man_t * p, int fVerbose )           { p->fVerbose = fVerbose; }   
-void            Map_ManSetSwitching( Map_Man_t * p, int fSwitching )       { p->fSwitching = fSwitching; }   
-
-/**Function*************************************************************
-
-  Synopsis    [Reads parameters from the mapping node.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-Map_Man_t *     Map_NodeReadMan( Map_Node_t * p )                     { return p->p;                  }
-char *          Map_NodeReadData( Map_Node_t * p, int fPhase )        { return fPhase? p->pData1 : p->pData0;  }
-int             Map_NodeReadNum( Map_Node_t * p )                     { return p->Num;                }
-int             Map_NodeReadLevel( Map_Node_t * p )                   { return Map_Regular(p)->Level; }
-Map_Cut_t *     Map_NodeReadCuts( Map_Node_t * p )                    { return p->pCuts;              }
-Map_Cut_t *     Map_NodeReadCutBest( Map_Node_t * p, int fPhase )     { return p->pCutBest[fPhase];   }
-Map_Node_t *    Map_NodeReadOne( Map_Node_t * p )                     { return p->p1;                 }
-Map_Node_t *    Map_NodeReadTwo( Map_Node_t * p )                     { return p->p2;                 }
-void            Map_NodeSetData( Map_Node_t * p, int fPhase, char * pData ) { if (fPhase) p->pData1 = pData; else p->pData0 = pData; }
-void            Map_NodeSetNextE( Map_Node_t * p, Map_Node_t * pNextE )     { p->pNextE = pNextE;       }
-void            Map_NodeSetRepr( Map_Node_t * p, Map_Node_t * pRepr )       { p->pRepr = pRepr;         }
-void            Map_NodeSetSwitching( Map_Node_t * p, float Switching )     { p->Switching = Switching; }
-
-/**Function*************************************************************
-
-  Synopsis    [Checks the type of the node.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int             Map_NodeIsConst( Map_Node_t * p )    {  return (Map_Regular(p))->Num == -1;    }
-int             Map_NodeIsVar( Map_Node_t * p )      {  return (Map_Regular(p))->p1 == NULL && (Map_Regular(p))->Num >= 0; }
-int             Map_NodeIsAnd( Map_Node_t * p )      {  return (Map_Regular(p))->p1 != NULL;  }
-int             Map_NodeComparePhase( Map_Node_t * p1, Map_Node_t * p2 ) { assert( !Map_IsComplement(p1) ); assert( !Map_IsComplement(p2) ); return p1->fInv ^ p2->fInv; }
-
-/**Function*************************************************************
-
-  Synopsis    [Reads parameters from the cut.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-Map_Super_t *   Map_CutReadSuperBest( Map_Cut_t * p, int fPhase ) { return p->M[fPhase].pSuperBest;}
-Map_Super_t *   Map_CutReadSuper0( Map_Cut_t * p )                { return p->M[0].pSuperBest;}
-Map_Super_t *   Map_CutReadSuper1( Map_Cut_t * p )                { return p->M[1].pSuperBest;}
-int             Map_CutReadLeavesNum( Map_Cut_t * p )             { return p->nLeaves;  }
-Map_Node_t **   Map_CutReadLeaves( Map_Cut_t * p )                { return p->ppLeaves; }
-unsigned        Map_CutReadPhaseBest( Map_Cut_t * p, int fPhase ) { return p->M[fPhase].uPhaseBest;}
-unsigned        Map_CutReadPhase0( Map_Cut_t * p )                { return p->M[0].uPhaseBest;}
-unsigned        Map_CutReadPhase1( Map_Cut_t * p )                { return p->M[1].uPhaseBest;}
-Map_Cut_t *     Map_CutReadNext( Map_Cut_t * p )                  { return p->pNext;          }
-
-/**Function*************************************************************
-
-  Synopsis    [Reads parameters from the supergate.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-char *          Map_SuperReadFormula( Map_Super_t * p )          {  return p->pFormula; }
-Mio_Gate_t *    Map_SuperReadRoot( Map_Super_t * p )             {  return p->pRoot;    }
-int             Map_SuperReadNum( Map_Super_t * p )              {  return p->Num;      }
-Map_Super_t **  Map_SuperReadFanins( Map_Super_t * p )           {  return p->pFanins;  }
-int             Map_SuperReadFaninNum( Map_Super_t * p )         {  return p->nFanins;  }
-Map_Super_t *   Map_SuperReadNext( Map_Super_t * p )             {  return p->pNext;    }
-int             Map_SuperReadNumPhases( Map_Super_t * p )        {  return p->nPhases;  }
-unsigned char * Map_SuperReadPhases( Map_Super_t * p )           {  return p->uPhases;  }
-int             Map_SuperReadFanoutLimit( Map_Super_t * p )      {  return p->nFanLimit;}
-
-Mio_Library_t * Map_SuperLibReadGenLib( Map_SuperLib_t * p )     {  return p->pGenlib;  }
-float           Map_SuperLibReadAreaInv( Map_SuperLib_t * p )    {  return p->AreaInv;  }
-Map_Time_t      Map_SuperLibReadDelayInv( Map_SuperLib_t * p )   {  return p->tDelayInv;}
-int             Map_SuperLibReadVarsMax( Map_SuperLib_t * p )    {  return p->nVarsMax; }
-
-
-/**Function*************************************************************
-
-  Synopsis    [Create the mapping manager.]
-
-  Description [The number of inputs and outputs is assumed to be
-  known is advance. It is much simpler to have them fixed upfront.
-  When it comes to representing the object graph in the form of
-  AIG, the resulting manager is similar to the regular AIG manager, 
-  except that it does not use reference counting (and therefore
-  does not have garbage collections). It does have table resizing.
-  The data structure is more flexible to represent additional 
-  information needed for mapping.]
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-Map_Man_t * Map_ManCreate( int nInputs, int nOutputs, int fVerbose )
-{
-    Map_Man_t * p;
-    int i;
-
-    // derive the supergate library
-    if ( Abc_FrameReadLibSuper() == NULL )
-    {
-        printf( "The supergate library is not specified. Use \"read_library\" or \"read_super\".\n" );
-        return NULL;
-    }
-
-    // start the manager
-    p = ALLOC( Map_Man_t, 1 );
-    memset( p, 0, sizeof(Map_Man_t) );
-    p->pSuperLib = Abc_FrameReadLibSuper();
-    p->nVarsMax  = p->pSuperLib->nVarsMax;
-    p->fVerbose  = fVerbose;
-    p->fEpsilon  = (float)0.001;
-    assert( p->nVarsMax > 0 );
-
-    if ( p->nVarsMax == 5 )
-        Extra_Truth4VarN( &p->uCanons, &p->uPhases, &p->pCounters, 8 );
-
-    // start various data structures
-    Map_TableCreate( p );
-    Map_MappingSetupTruthTables( p->uTruths );
-    Map_MappingSetupTruthTablesLarge( p->uTruthsLarge );
-//    printf( "Node = %d bytes. Cut = %d bytes. Super = %d bytes.\n", sizeof(Map_Node_t), sizeof(Map_Cut_t), sizeof(Map_Super_t) ); 
-    p->mmNodes    = Extra_MmFixedStart( sizeof(Map_Node_t) );
-    p->mmCuts     = Extra_MmFixedStart( sizeof(Map_Cut_t) );
-
-    // make sure the constant node will get index -1
-    p->nNodes = -1;
-    // create the constant node
-    p->pConst1    = Map_NodeCreate( p, NULL, NULL );
-    p->vNodesAll  = Map_NodeVecAlloc( 100 );
-    p->vNodesTemp = Map_NodeVecAlloc( 100 );
-    p->vMapping   = Map_NodeVecAlloc( 100 );
-    p->vVisited   = Map_NodeVecAlloc( 100 );
-
-    // create the PI nodes
-    p->nInputs = nInputs;
-    p->pInputs = ALLOC( Map_Node_t *, nInputs );
-    for ( i = 0; i < nInputs; i++ )
-        p->pInputs[i] = Map_NodeCreate( p, NULL, NULL );
-
-    // create the place for the output nodes
-    p->nOutputs = nOutputs;
-    p->pOutputs = ALLOC( Map_Node_t *, nOutputs );
-    memset( p->pOutputs, 0, sizeof(Map_Node_t *) * nOutputs );
-    return p;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Deallocates the mapping manager.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Map_ManFree( Map_Man_t * p )
-{
-//    int i;
-//    for ( i = 0; i < p->vNodesAll->nSize; i++ )
-//        Map_NodeVecFree( p->vNodesAll->pArray[i]->vFanouts );
-//    Map_NodeVecFree( p->pConst1->vFanouts );
-    if ( p->vAnds )    
-        Map_NodeVecFree( p->vAnds );
-    if ( p->vNodesAll )    
-        Map_NodeVecFree( p->vNodesAll );
-    if ( p->vNodesTemp )    
-        Map_NodeVecFree( p->vNodesTemp );
-    if ( p->vMapping )    
-        Map_NodeVecFree( p->vMapping );
-    if ( p->vVisited )    
-        Map_NodeVecFree( p->vVisited );
-    if ( p->uCanons )   free( p->uCanons );
-    if ( p->uPhases )   free( p->uPhases );
-    if ( p->pCounters ) free( p->pCounters );
-    Extra_MmFixedStop( p->mmNodes );
-    Extra_MmFixedStop( p->mmCuts );
-    FREE( p->pInputArrivals );
-    FREE( p->pInputs );
-    FREE( p->pOutputs );
-    FREE( p->pBins );
-    FREE( p->ppOutputNames );
-    FREE( p );
-}
-
-
-/**Function*************************************************************
-
-  Synopsis    [Deallocates the mapping manager.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Map_ManPrintTimeStats( Map_Man_t * p )
-{
-    printf( "N-canonical = %d. Matchings = %d.  Phases = %d.  ", p->nCanons, p->nMatches, p->nPhases );
-    printf( "Choice nodes = %d. Choices = %d.\n", p->nChoiceNodes, p->nChoices );
-    PRT( "ToMap", p->timeToMap );
-    PRT( "Cuts ", p->timeCuts  );
-    PRT( "Truth", p->timeTruth );
-    PRT( "Match", p->timeMatch );
-    PRT( "Area ", p->timeArea  );
-    PRT( "Sweep", p->timeSweep );
-    PRT( "ToNet", p->timeToNet );
-    PRT( "TOTAL", p->timeTotal );
-    if ( p->time1 ) { PRT( "time1", p->time1 ); }
-    if ( p->time2 ) { PRT( "time2", p->time2 ); }
-    if ( p->time3 ) { PRT( "time3", p->time3 ); }
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Prints the mapping stats.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Map_ManPrintStatsToFile( char * pName, float Area, float Delay, int Time )
-{
-    FILE * pTable;
-    pTable = fopen( "map_stats.txt", "a+" );
-    fprintf( pTable, "%s ", pName );
-    fprintf( pTable, "%4.2f ", Area );
-    fprintf( pTable, "%4.2f ", Delay );
-    fprintf( pTable, "%4.2f\n", (float)(Time)/(float)(CLOCKS_PER_SEC) );
-    fclose( pTable );
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Creates a new node.]
-
-  Description [This procedure should be called to create the constant
-  node and the PI nodes first.]
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-Map_Node_t * Map_NodeCreate( Map_Man_t * p, Map_Node_t * p1, Map_Node_t * p2 )
-{
-    Map_Node_t * pNode;
-    // create the node
-    pNode = (Map_Node_t *)Extra_MmFixedEntryFetch( p->mmNodes );
-    memset( pNode, 0, sizeof(Map_Node_t) );
-    pNode->tRequired[0].Rise = pNode->tRequired[0].Fall = pNode->tRequired[0].Worst = MAP_FLOAT_LARGE;
-    pNode->tRequired[1].Rise = pNode->tRequired[1].Fall = pNode->tRequired[1].Worst = MAP_FLOAT_LARGE;
-    pNode->p1  = p1; 
-    pNode->p2  = p2;
-    pNode->p = p;
-    // set the number of this node
-    pNode->Num = p->nNodes++;
-    // place to store the fanouts
-//    pNode->vFanouts = Map_NodeVecAlloc( 5 );
-    // store this node in the internal array
-    if ( pNode->Num >= 0 )
-        Map_NodeVecPush( p->vNodesAll, pNode );
-    else
-        pNode->fInv = 1;
-    // set the level of this node
-    if ( p1 ) 
-    {
-#ifdef MAP_ALLOCATE_FANOUT
-        // create the fanout info
-        Map_NodeAddFaninFanout( Map_Regular(p1), pNode );
-        Map_NodeAddFaninFanout( Map_Regular(p2), pNode );
-#endif
-        pNode->Level = 1 + MAP_MAX(Map_Regular(pNode->p1)->Level, Map_Regular(pNode->p2)->Level);
-        pNode->fInv  = Map_NodeIsSimComplement(p1) & Map_NodeIsSimComplement(p2);
-    }
-    // reference the inputs (will be used to compute the number of fanouts)
-    if ( p1 ) Map_NodeRef(p1);
-    if ( p2 ) Map_NodeRef(p2);
-
-    pNode->nRefEst[0] = pNode->nRefEst[1] = -1;
-    return pNode;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Create the unique table of AND gates.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Map_TableCreate( Map_Man_t * pMan )
-{
-    assert( pMan->pBins == NULL );
-    pMan->nBins = Cudd_Prime(5000);
-    pMan->pBins = ALLOC( Map_Node_t *, pMan->nBins );
-    memset( pMan->pBins, 0, sizeof(Map_Node_t *) * pMan->nBins );
-    pMan->nNodes = 0;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Looks up the AND2 node in the unique table.]
-
-  Description [This procedure implements one-level hashing. All the nodes
-  are hashed by their children. If the node with the same children was already
-  created, it is returned by the call to this procedure. If it does not exist,
-  this procedure creates a new node with these children. ]
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-Map_Node_t * Map_TableLookup( Map_Man_t * pMan, Map_Node_t * p1, Map_Node_t * p2 )
-{
-    Map_Node_t * pEnt;
-    unsigned Key;
-
-    if ( p1 == p2 )
-        return p1;
-    if ( p1 == Map_Not(p2) )
-        return Map_Not(pMan->pConst1);
-    if ( Map_NodeIsConst(p1) )
-    {
-        if ( p1 == pMan->pConst1 )
-            return p2;
-        return Map_Not(pMan->pConst1);
-    }
-    if ( Map_NodeIsConst(p2) )
-    {
-        if ( p2 == pMan->pConst1 )
-            return p1;
-        return Map_Not(pMan->pConst1);
-    }
-
-    if ( Map_Regular(p1)->Num > Map_Regular(p2)->Num )
-        pEnt = p1, p1 = p2, p2 = pEnt;
-
-    Key = Map_HashKey2( p1, p2, pMan->nBins );
-    for ( pEnt = pMan->pBins[Key]; pEnt; pEnt = pEnt->pNext )
-        if ( pEnt->p1 == p1 && pEnt->p2 == p2 )
-            return pEnt;
-    // resize the table
-    if ( pMan->nNodes >= 2 * pMan->nBins )
-    {
-        Map_TableResize( pMan );
-        Key = Map_HashKey2( p1, p2, pMan->nBins );
-    }
-    // create the new node
-    pEnt = Map_NodeCreate( pMan, p1, p2 );
-    // add the node to the corresponding linked list in the table
-    pEnt->pNext = pMan->pBins[Key];
-    pMan->pBins[Key] = pEnt;
-    return pEnt;
-}
-
-
-/**Function*************************************************************
-
-  Synopsis    [Resizes the table.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Map_TableResize( Map_Man_t * pMan )
-{
-    Map_Node_t ** pBinsNew;
-    Map_Node_t * pEnt, * pEnt2;
-    int nBinsNew, Counter, i, clk;
-    unsigned Key;
-
-clk = clock();
-    // get the new table size
-    nBinsNew = Cudd_Prime(2 * pMan->nBins); 
-    // allocate a new array
-    pBinsNew = ALLOC( Map_Node_t *, nBinsNew );
-    memset( pBinsNew, 0, sizeof(Map_Node_t *) * nBinsNew );
-    // rehash the entries from the old table
-    Counter = 0;
-    for ( i = 0; i < pMan->nBins; i++ )
-        for ( pEnt = pMan->pBins[i], pEnt2 = pEnt? pEnt->pNext: NULL; pEnt; 
-              pEnt = pEnt2, pEnt2 = pEnt? pEnt->pNext: NULL )
-        {
-            Key = Map_HashKey2( pEnt->p1, pEnt->p2, nBinsNew );
-            pEnt->pNext = pBinsNew[Key];
-            pBinsNew[Key] = pEnt;
-            Counter++;
-        }
-    assert( Counter == pMan->nNodes - pMan->nInputs );
-    if ( pMan->fVerbose )
-    {
-//        printf( "Increasing the unique table size from %6d to %6d. ", pMan->nBins, nBinsNew );
-//        PRT( "Time", clock() - clk );
-    }
-    // replace the table and the parameters
-    free( pMan->pBins );
-    pMan->pBins = pBinsNew;
-    pMan->nBins = nBinsNew;
-}
-
-
-
-/**Function*************************************************************
-
-  Synopsis    []
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-Map_Node_t * Map_NodeAnd( Map_Man_t * p, Map_Node_t * p1, Map_Node_t * p2 )
-{
-    Map_Node_t * pNode;
-    pNode = Map_TableLookup( p, p1, p2 );    
-    return pNode;
-}
-
-/**Function*************************************************************
-
-  Synopsis    []
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-Map_Node_t * Map_NodeOr( Map_Man_t * p, Map_Node_t * p1, Map_Node_t * p2 )
-{
-    Map_Node_t * pNode;
-    pNode = Map_Not( Map_TableLookup( p, Map_Not(p1), Map_Not(p2) ) ); 
-    return pNode;
-}
-
-/**Function*************************************************************
-
-  Synopsis    []
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-Map_Node_t * Map_NodeExor( Map_Man_t * p, Map_Node_t * p1, Map_Node_t * p2 )
-{
-    return Map_NodeMux( p, p1, Map_Not(p2), p2 );
-}
-
-/**Function*************************************************************
-
-  Synopsis    []
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-Map_Node_t * Map_NodeMux( Map_Man_t * p, Map_Node_t * pC, Map_Node_t * pT, Map_Node_t * pE )
-{
-    Map_Node_t * pAnd1, * pAnd2, * pRes;
-    pAnd1 = Map_TableLookup( p, pC,          pT ); 
-    pAnd2 = Map_TableLookup( p, Map_Not(pC), pE ); 
-    pRes  = Map_NodeOr( p, pAnd1, pAnd2 );                 
-    return pRes;
-}
-
-
-/**Function*************************************************************
-
-  Synopsis    [Sets the node to be equivalent to the given one.]
-
-  Description [This procedure is a work-around for the equivalence check.
-  Does not verify the equivalence. Use at the user's risk.]
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Map_NodeSetChoice( Map_Man_t * pMan, Map_Node_t * pNodeOld, Map_Node_t * pNodeNew )
-{
-    pNodeNew->pNextE = pNodeOld->pNextE;
-    pNodeOld->pNextE = pNodeNew;
-    pNodeNew->pRepr  = pNodeOld;
-}
-
-
-
-////////////////////////////////////////////////////////////////////////
-///                       END OF FILE                                ///
-////////////////////////////////////////////////////////////////////////
-
diff --git a/abc70930/src/map/mapper/mapperCut.c b/abc70930/src/map/mapper/mapperCut.c
deleted file mode 100644
index b05e9d0c..00000000
--- a/abc70930/src/map/mapper/mapperCut.c
+++ /dev/null
@@ -1,1168 +0,0 @@
-/**CFile****************************************************************
-
-  FileName    [mapperCut.c]
-
-  PackageName [MVSIS 1.3: Multi-valued logic synthesis system.]
-
-  Synopsis    [Generic technology mapping engine.]
-
-  Author      [MVSIS Group]
-  
-  Affiliation [UC Berkeley]
-
-  Date        [Ver. 2.0. Started - June 1, 2004.]
-
-  Revision    [$Id: mapperCut.c,v 1.12 2005/02/28 05:34:27 alanmi Exp $]
-
-***********************************************************************/
-
-#include "mapperInt.h"
-
-////////////////////////////////////////////////////////////////////////
-///                        DECLARATIONS                              ///
-////////////////////////////////////////////////////////////////////////
-
-// the largest number of cuts considered
-#define  MAP_CUTS_MAX_COMPUTE   1000
-// the largest number of cuts used
-#define  MAP_CUTS_MAX_USE       250
-
-// temporary hash table to store the cuts
-typedef struct Map_CutTableStrutct_t Map_CutTable_t;
-struct Map_CutTableStrutct_t
-{
-    Map_Cut_t ** pBins;        // the table used for linear probing
-    int          nBins;        // the size of the table
-    int *        pCuts;        // the array of cuts currently stored 
-    int          nCuts;        // the number of cuts currently stored 
-    Map_Cut_t ** pArray;       // the temporary array of cuts
-    Map_Cut_t ** pCuts1;       // the temporary array of cuts
-    Map_Cut_t ** pCuts2;       // the temporary array of cuts
-};
-
-// primes used to compute the hash key
-static int s_HashPrimes[10] = { 109, 499, 557, 619, 631, 709, 797, 881, 907, 991 };
-
-static Map_Cut_t *      Map_CutCompute( Map_Man_t * p, Map_CutTable_t * pTable, Map_Node_t * pNode );
-static void             Map_CutFilter( Map_Man_t * p, Map_Node_t * pNode );
-static Map_Cut_t *      Map_CutMergeLists( Map_Man_t * p, Map_CutTable_t * pTable, Map_Cut_t * pList1, Map_Cut_t * pList2, int fComp1, int fComp2 );
-static int              Map_CutMergeTwo( Map_Cut_t * pCut1, Map_Cut_t * pCut2, Map_Node_t * ppNodes[], int nNodesMax );
-static Map_Cut_t *      Map_CutUnionLists( Map_Cut_t * pList1, Map_Cut_t * pList2 );
-static int              Map_CutBelongsToList( Map_Cut_t * pList, Map_Node_t * ppNodes[], int nNodes );
-
-static void             Map_CutListPrint( Map_Man_t * pMan, Map_Node_t * pRoot );
-static void             Map_CutListPrint2( Map_Man_t * pMan, Map_Node_t * pRoot );
-static void             Map_CutPrint_( Map_Man_t * pMan, Map_Cut_t * pCut, Map_Node_t * pRoot );
-
-static Map_CutTable_t * Map_CutTableStart( Map_Man_t * pMan );
-static void             Map_CutTableStop( Map_CutTable_t * p );
-static unsigned         Map_CutTableHash( Map_Node_t * ppNodes[], int nNodes );
-static int              Map_CutTableLookup( Map_CutTable_t * p, Map_Node_t * ppNodes[], int nNodes );
-static Map_Cut_t *      Map_CutTableConsider( Map_Man_t * pMan, Map_CutTable_t * p, Map_Node_t * ppNodes[], int nNodes );
-static void             Map_CutTableRestart( Map_CutTable_t * p );
-
-static Map_Cut_t *      Map_CutSortCuts( Map_Man_t * pMan, Map_CutTable_t * p, Map_Cut_t * pList );
-static int              Map_CutList2Array( Map_Cut_t ** pArray, Map_Cut_t * pList );
-static Map_Cut_t *      Map_CutArray2List( Map_Cut_t ** pArray, int nCuts );
-
-static unsigned         Map_CutComputeTruth( Map_Man_t * p, Map_Cut_t * pCut, Map_Cut_t * pTemp0, Map_Cut_t * pTemp1, int fComp0, int fComp1 );
-
-// iterator through all the cuts of the list
-#define Map_ListForEachCut( pList, pCut )                 \
-    for ( pCut = pList;                                   \
-          pCut;                                           \
-          pCut = pCut->pNext )
-#define Map_ListForEachCutSafe( pList, pCut, pCut2 )      \
-    for ( pCut = pList,                                   \
-          pCut2 = pCut? pCut->pNext: NULL;                \
-          pCut;                                           \
-          pCut = pCut2,                                   \
-          pCut2 = pCut? pCut->pNext: NULL )
-
-////////////////////////////////////////////////////////////////////////
-///                     FUNCTION DEFINITIONS                         ///
-////////////////////////////////////////////////////////////////////////
-
-/**Function*************************************************************
-
-  Synopsis    [Computes the cuts for each node in the object graph.]
-
-  Description [The cuts are computed in one sweep over the mapping graph. 
-  First, the elementary cuts, which include the node itself, are assigned 
-  to the PI nodes. The internal nodes are considered in the DFS order.
-  Each node is two-input AND-gate. So to compute the cuts at a node, we
-  need to merge the sets of cuts of its two predecessors. The merged set
-  contains only unique cuts with the number of inputs equal to k or less.
-  Finally, the elementary cut, composed of the node itself, is added to
-  the set of cuts for the node.
-  
-  This procedure is pretty fast for 5-feasible cuts, but it dramatically
-  slows down on some "dense" networks when computing 6-feasible cuts.
-  The problem is that there are too many cuts in this case. We should
-  think how to heuristically trim the number of cuts in such cases, 
-  to have reasonable runtime.]
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Map_MappingCuts( Map_Man_t * p )
-{
-    ProgressBar * pProgress;
-    Map_CutTable_t * pTable;
-    Map_Node_t * pNode;
-    Map_Cut_t * pCut;
-    int nCuts, nNodes, i;
-    int clk = clock();
-    // set the elementary cuts for the PI variables
-    assert( p->nVarsMax > 1 && p->nVarsMax < 7 );
-    for ( i = 0; i < p->nInputs; i++ )
-    {
-        pCut = Map_CutAlloc( p );
-        pCut->nLeaves = 1;
-        pCut->ppLeaves[0] = p->pInputs[i];
-        p->pInputs[i]->pCuts   = pCut;
-        p->pInputs[i]->pCutBest[0] = NULL; // negative polarity is not mapped
-        p->pInputs[i]->pCutBest[1] = pCut; // positive polarity is a trivial cut
-        pCut->uTruth = 0xAAAAAAAA;         // the first variable "10101010"
-        pCut->M[0].AreaFlow = 0.0;
-        pCut->M[1].AreaFlow = 0.0;
-    }
-
-    // compute the cuts for the internal nodes
-    nNodes = p->vAnds->nSize;
-    pProgress = Extra_ProgressBarStart( stdout, nNodes );
-    pTable = Map_CutTableStart( p );
-    for ( i = 0; i < nNodes; i++ )
-    {
-        pNode = p->vAnds->pArray[i];
-        if ( !Map_NodeIsAnd( pNode ) )
-            continue;
-        Map_CutCompute( p, pTable, pNode );
-        Extra_ProgressBarUpdate( pProgress, i, "Cuts ..." );
-    }
-    Extra_ProgressBarStop( pProgress );
-    Map_CutTableStop( pTable );
-
-    // report the stats
-    if ( p->fVerbose )
-    {
-        nCuts = Map_MappingCountAllCuts(p);
-        printf( "Nodes = %6d.  Total %d-feasible cuts = %10d.  Per node = %.1f. ", 
-               p->nNodes, p->nVarsMax, nCuts, ((float)nCuts)/p->nNodes );
-        PRT( "Time", clock() - clk );
-    }
-
-    // print the cuts for the first primary output
-//    Map_CutListPrint( p, Map_Regular(p->pOutputs[0]) );
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Computes the cuts for one node.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-Map_Cut_t * Map_CutCompute( Map_Man_t * p, Map_CutTable_t * pTable, Map_Node_t * pNode )
-{
-    Map_Node_t * pTemp;
-    Map_Cut_t * pList, * pList1, * pList2;
-    Map_Cut_t * pCut;
-
-    // if the cuts are computed return them
-    if ( pNode->pCuts )
-        return pNode->pCuts;
-
-    // compute the cuts for the children
-    pList1 = Map_Regular(pNode->p1)->pCuts;
-    pList2 = Map_Regular(pNode->p2)->pCuts;
-    // merge the lists
-    pList = Map_CutMergeLists( p, pTable, pList1, pList2, 
-        Map_IsComplement(pNode->p1), Map_IsComplement(pNode->p2) );
-    // if there are functionally equivalent nodes, union them with this list
-    assert( pList );
-    // only add to the list of cuts if the node is a representative one
-    if ( pNode->pRepr == NULL )
-    {
-        for ( pTemp = pNode->pNextE; pTemp; pTemp = pTemp->pNextE )
-        {
-            assert( pTemp->pCuts );
-            pList = Map_CutUnionLists( pList, pTemp->pCuts );
-            assert( pTemp->pCuts );
-            pList = Map_CutSortCuts( p, pTable, pList );
-        }
-    }
-    // add the new cut
-    pCut = Map_CutAlloc( p );
-    pCut->nLeaves = 1;
-    pCut->ppLeaves[0] = pNode;
-    pCut->uTruth = 0xAAAAAAAA;
-    // append (it is important that the elementary cut is appended first)
-    pCut->pNext = pList;
-    // set at the node
-    pNode->pCuts = pCut;
-    // remove the dominated cuts
-    Map_CutFilter( p, pNode );
-    // set the phase correctly
-    if ( pNode->pRepr && Map_NodeComparePhase(pNode, pNode->pRepr) )
-    {
-        Map_ListForEachCut( pNode->pCuts, pCut )
-            pCut->Phase = 1;
-    }
-/*
-    { 
-        int i, Counter = 0;;
-        for ( pCut = pNode->pCuts->pNext; pCut; pCut = pCut->pNext )
-            for ( i = 0; i < pCut->nLeaves; i++ )
-                Counter += (pCut->ppLeaves[i]->Level >= pNode->Level);
-//        if ( Counter )
-//            printf( " %d", Counter );
-    }
-*/
-    return pCut;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Filter the cuts using dominance.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Map_CutFilter( Map_Man_t * p, Map_Node_t * pNode )
-{ 
-    Map_Cut_t * pTemp, * pPrev, * pCut, * pCut2;
-    int i, k, Counter;
-
-    Counter = 0;
-    pPrev = pNode->pCuts;
-    Map_ListForEachCutSafe( pNode->pCuts->pNext, pCut, pCut2 )
-    {
-        // go through all the previous cuts up to pCut
-        for ( pTemp = pNode->pCuts->pNext; pTemp != pCut; pTemp = pTemp->pNext )
-        {
-            // check if every node in pTemp is contained in pCut
-            for ( i = 0; i < pTemp->nLeaves; i++ )
-            {
-                for ( k = 0; k < pCut->nLeaves; k++ )
-                    if ( pTemp->ppLeaves[i] == pCut->ppLeaves[k] )
-                        break;
-                if ( k == pCut->nLeaves ) // node i in pTemp is not contained in pCut
-                    break;
-            }
-            if ( i == pTemp->nLeaves ) // every node in pTemp is contained in pCut
-            {
-                Counter++;
-                break;
-            }
-        }
-        if ( pTemp != pCut ) // pTemp contain pCut
-        {
-            pPrev->pNext = pCut->pNext;  // skip pCut
-            // recycle pCut
-            Map_CutFree( p, pCut );
-        }
-        else 
-            pPrev = pCut; 
-    }
-//  printf( "Dominated = %3d. \n", Counter );
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Merges two lists of cuts.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-Map_Cut_t * Map_CutMergeLists( Map_Man_t * p, Map_CutTable_t * pTable, 
-    Map_Cut_t * pList1, Map_Cut_t * pList2, int fComp1, int fComp2 )
-{
-    Map_Node_t * ppNodes[6];
-    Map_Cut_t * pListNew, ** ppListNew, * pLists[7] = { NULL };
-    Map_Cut_t * pCut, * pPrev, * pTemp1, * pTemp2;
-    int nNodes, Counter, i;
-    Map_Cut_t ** ppArray1, ** ppArray2, ** ppArray3;
-    int nCuts1, nCuts2, nCuts3, k, fComp3;
-
-    ppArray1 = pTable->pCuts1;
-    ppArray2 = pTable->pCuts2;
-    nCuts1 = Map_CutList2Array( ppArray1, pList1 );
-    nCuts2 = Map_CutList2Array( ppArray2, pList2 );
-    // swap the lists based on their length
-    if ( nCuts1 > nCuts2 )
-    {
-         ppArray3 = ppArray1;
-         ppArray1 = ppArray2;
-         ppArray2 = ppArray3;
-
-         nCuts3 = nCuts1;
-         nCuts1 = nCuts2;
-         nCuts2 = nCuts3;
-
-         fComp3 = fComp1;
-         fComp1 = fComp2;
-         fComp2 = fComp3;
-    }
-    // pList1 is shorter or equal length compared to pList2
- 
-    // prepare the manager for the cut computation
-    Map_CutTableRestart( pTable );
-    // go through the cut pairs
-    Counter = 0;
-//    for ( pTemp1 = pList1; pTemp1; pTemp1 = fPivot1? NULL: pTemp1->pNext )
-//        for ( pTemp2 = pList2; pTemp2; pTemp2 = fPivot2? NULL: pTemp2->pNext )
-    for ( i = 0; i < nCuts1; i++ )
-    {
-        for ( k = 0; k <= i; k++ )
-        {
-            pTemp1 = ppArray1[i];
-            pTemp2 = ppArray2[k];
-
-            if ( pTemp1->nLeaves == p->nVarsMax && pTemp2->nLeaves == p->nVarsMax )
-            {
-                if ( pTemp1->ppLeaves[0] != pTemp2->ppLeaves[0] )
-                    continue;
-                if ( pTemp1->ppLeaves[1] != pTemp2->ppLeaves[1] )
-                    continue;
-            }
-
-            // check if k-feasible cut exists
-            nNodes = Map_CutMergeTwo( pTemp1, pTemp2, ppNodes, p->nVarsMax );
-            if ( nNodes == 0 )
-                continue;
-            // consider the cut for possible addition to the set of new cuts
-            pCut = Map_CutTableConsider( p, pTable, ppNodes, nNodes );
-            if ( pCut == NULL )
-                continue;
-            // add data to the cut
-            pCut->pOne = Map_CutNotCond( pTemp1, fComp1 );
-            pCut->pTwo = Map_CutNotCond( pTemp2, fComp2 );
-//            if ( p->nVarsMax == 5 )
-//            pCut->uTruth = Map_CutComputeTruth( p, pCut, pTemp1, pTemp2, fComp1, fComp2 );
-            // add it to the corresponding list
-            pCut->pNext = pLists[pCut->nLeaves];
-            pLists[pCut->nLeaves] = pCut;
-            // count this cut and quit if limit is reached
-            Counter++;
-            if ( Counter == MAP_CUTS_MAX_COMPUTE )
-                goto QUITS;
-        }
-        for ( k = 0; k < i; k++ )
-        {
-            pTemp1 = ppArray1[k];
-            pTemp2 = ppArray2[i];
-
-            if ( pTemp1->nLeaves == p->nVarsMax && pTemp2->nLeaves == p->nVarsMax )
-            {
-                if ( pTemp1->ppLeaves[0] != pTemp2->ppLeaves[0] )
-                    continue;
-                if ( pTemp1->ppLeaves[1] != pTemp2->ppLeaves[1] )
-                    continue;
-            }
-
-            // check if k-feasible cut exists
-            nNodes = Map_CutMergeTwo( pTemp1, pTemp2, ppNodes, p->nVarsMax );
-            if ( nNodes == 0 )
-                continue;
-            // consider the cut for possible addition to the set of new cuts
-            pCut = Map_CutTableConsider( p, pTable, ppNodes, nNodes );
-            if ( pCut == NULL )
-                continue;
-            // add data to the cut
-            pCut->pOne = Map_CutNotCond( pTemp1, fComp1 );
-            pCut->pTwo = Map_CutNotCond( pTemp2, fComp2 );
-//            if ( p->nVarsMax == 5 )
-//            pCut->uTruth = Map_CutComputeTruth( p, pCut, pTemp1, pTemp2, fComp1, fComp2 );
-            // add it to the corresponding list
-            pCut->pNext = pLists[pCut->nLeaves];
-            pLists[pCut->nLeaves] = pCut;
-            // count this cut and quit if limit is reached
-            Counter++;
-            if ( Counter == MAP_CUTS_MAX_COMPUTE )
-                goto QUITS;
-        }
-    }
-    // consider the rest of them
-    for ( i = nCuts1; i < nCuts2; i++ )
-        for ( k = 0; k < nCuts1; k++ )
-        {
-            pTemp1 = ppArray1[k];
-            pTemp2 = ppArray2[i];
-
-            if ( pTemp1->nLeaves == p->nVarsMax && pTemp2->nLeaves == p->nVarsMax )
-            {
-                if ( pTemp1->ppLeaves[0] != pTemp2->ppLeaves[0] )
-                    continue;
-                if ( pTemp1->ppLeaves[1] != pTemp2->ppLeaves[1] )
-                    continue;
-            }
-
-            // check if k-feasible cut exists
-            nNodes = Map_CutMergeTwo( pTemp1, pTemp2, ppNodes, p->nVarsMax );
-            if ( nNodes == 0 )
-                continue;
-            // consider the cut for possible addition to the set of new cuts
-            pCut = Map_CutTableConsider( p, pTable, ppNodes, nNodes );
-            if ( pCut == NULL )
-                continue;
-            // add data to the cut
-            pCut->pOne = Map_CutNotCond( pTemp1, fComp1 );
-            pCut->pTwo = Map_CutNotCond( pTemp2, fComp2 );
-//            if ( p->nVarsMax == 5 )
-//            pCut->uTruth = Map_CutComputeTruth( p, pCut, pTemp1, pTemp2, fComp1, fComp2 );
-            // add it to the corresponding list
-            pCut->pNext = pLists[pCut->nLeaves];
-            pLists[pCut->nLeaves] = pCut;
-            // count this cut and quit if limit is reached
-            Counter++;
-            if ( Counter == MAP_CUTS_MAX_COMPUTE )
-                goto QUITS;
-        }
-QUITS :
-    // combine all the lists into one
-    pListNew  = NULL;
-    ppListNew = &pListNew;
-    for ( i = 1; i <= p->nVarsMax; i++ )
-    {
-        if ( pLists[i] == NULL )
-            continue;
-        // find the last entry
-        for ( pPrev = pLists[i], pCut = pPrev->pNext; pCut; 
-            pPrev = pCut, pCut = pCut->pNext );
-        // connect these lists
-        *ppListNew = pLists[i];
-        ppListNew  = &pPrev->pNext;
-    }
-    *ppListNew = NULL;
-    // soft the cuts by arrival times and use only the first MAP_CUTS_MAX_USE
-    pListNew = Map_CutSortCuts( p, pTable, pListNew );
-    return pListNew;
-}
-
-
-/**Function*************************************************************
-
-  Synopsis    [Merges two lists of cuts.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-Map_Cut_t * Map_CutMergeLists2( Map_Man_t * p, Map_CutTable_t * pTable, 
-    Map_Cut_t * pList1, Map_Cut_t * pList2, int fComp1, int fComp2 )
-{
-    Map_Node_t * ppNodes[6];
-    Map_Cut_t * pListNew, ** ppListNew, * pLists[7] = { NULL };
-    Map_Cut_t * pCut, * pPrev, * pTemp1, * pTemp2;
-    int nNodes, Counter, i;
-
-    // prepare the manager for the cut computation
-    Map_CutTableRestart( pTable );
-    // go through the cut pairs
-    Counter = 0;
-    for ( pTemp1 = pList1; pTemp1; pTemp1 = pTemp1->pNext )
-        for ( pTemp2 = pList2; pTemp2; pTemp2 = pTemp2->pNext )
-        {
-            // check if k-feasible cut exists
-            nNodes = Map_CutMergeTwo( pTemp1, pTemp2, ppNodes, p->nVarsMax );
-            if ( nNodes == 0 )
-                continue;
-            // consider the cut for possible addition to the set of new cuts
-            pCut = Map_CutTableConsider( p, pTable, ppNodes, nNodes );
-            if ( pCut == NULL )
-                continue;
-            // add data to the cut
-            pCut->pOne = Map_CutNotCond( pTemp1, fComp1 );
-            pCut->pTwo = Map_CutNotCond( pTemp2, fComp2 );
-            // add it to the corresponding list
-            pCut->pNext = pLists[pCut->nLeaves];
-            pLists[pCut->nLeaves] = pCut;
-            // count this cut and quit if limit is reached
-            Counter++;
-            if ( Counter == MAP_CUTS_MAX_COMPUTE )
-                goto QUITS;
-        }
-QUITS :
-    // combine all the lists into one
-    pListNew  = NULL;
-    ppListNew = &pListNew;
-    for ( i = 1; i <= p->nVarsMax; i++ )
-    {
-        if ( pLists[i] == NULL )
-            continue;
-        // find the last entry
-        for ( pPrev = pLists[i], pCut = pPrev->pNext; pCut; 
-            pPrev = pCut, pCut = pCut->pNext );
-        // connect these lists
-        *ppListNew = pLists[i];
-        ppListNew  = &pPrev->pNext;
-    }
-    *ppListNew = NULL;
-    // soft the cuts by arrival times and use only the first MAP_CUTS_MAX_USE
-    pListNew = Map_CutSortCuts( p, pTable, pListNew );
-    return pListNew;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Merges two cuts.]
-
-  Description [Returns the number of nodes in the resulting cut, or 0 if the
-  cut is infeasible. Returns the resulting nodes in the array ppNodes[].]
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Map_CutMergeTwo( Map_Cut_t * pCut1, Map_Cut_t * pCut2, Map_Node_t * ppNodes[], int nNodesMax )
-{
-    Map_Node_t * pNodeTemp;
-    int nTotal, i, k, min, fMismatch;
-
-    // check the special case when at least of the cuts is the largest
-    if ( pCut1->nLeaves == nNodesMax )
-    {
-        if ( pCut2->nLeaves == nNodesMax )
-        {
-            // return 0 if the cuts are different
-            for ( i = 0; i < nNodesMax; i++ )
-                if ( pCut1->ppLeaves[i] != pCut2->ppLeaves[i] )
-                    return 0;
-            // return nNodesMax if they are the same
-            for ( i = 0; i < nNodesMax; i++ )
-                ppNodes[i] = pCut1->ppLeaves[i];
-            return nNodesMax;
-        }
-        else if ( pCut2->nLeaves == nNodesMax - 1 ) 
-        {
-            // return 0 if the cuts are different
-            fMismatch = 0;
-            for ( i = 0; i < nNodesMax; i++ )
-                if ( pCut1->ppLeaves[i] != pCut2->ppLeaves[i - fMismatch] )
-                {
-                    if ( fMismatch == 1 )
-                        return 0;
-                    fMismatch = 1;
-                }
-            // return nNodesMax if they are the same
-            for ( i = 0; i < nNodesMax; i++ )
-                ppNodes[i] = pCut1->ppLeaves[i];
-            return nNodesMax;
-        }
-    }
-    else if ( pCut1->nLeaves == nNodesMax - 1 && pCut2->nLeaves == nNodesMax )
-    {
-        // return 0 if the cuts are different
-        fMismatch = 0;
-        for ( i = 0; i < nNodesMax; i++ )
-            if ( pCut1->ppLeaves[i - fMismatch] != pCut2->ppLeaves[i] )
-            {
-                if ( fMismatch == 1 )
-                    return 0;
-                fMismatch = 1;
-            }
-        // return nNodesMax if they are the same
-        for ( i = 0; i < nNodesMax; i++ )
-            ppNodes[i] = pCut2->ppLeaves[i];
-        return nNodesMax;
-    }
-
-    // count the number of unique entries in pCut2
-    nTotal = pCut1->nLeaves;
-    for ( i = 0; i < pCut2->nLeaves; i++ )
-    {
-        // try to find this entry among the leaves of pCut1
-        for ( k = 0; k < pCut1->nLeaves; k++ )
-            if ( pCut2->ppLeaves[i] == pCut1->ppLeaves[k] )
-                break;
-        if ( k < pCut1->nLeaves ) // found
-            continue;
-        // we found a new entry to add
-        if ( nTotal == nNodesMax )
-            return 0;
-        ppNodes[nTotal++] = pCut2->ppLeaves[i];
-    }
-    // we know that the feasible cut exists
-
-    // add the starting entries
-    for ( k = 0; k < pCut1->nLeaves; k++ )
-        ppNodes[k] = pCut1->ppLeaves[k];
-
-    // selection-sort the entries
-    for ( i = 0; i < nTotal - 1; i++ )
-    {
-        min = i;
-        for ( k = i+1; k < nTotal; k++ )
-//            if ( ppNodes[k] < ppNodes[min] ) // reported bug fix (non-determinism!)
-            if ( ppNodes[k]->Num < ppNodes[min]->Num )
-                min = k;
-        pNodeTemp    = ppNodes[i];
-        ppNodes[i]   = ppNodes[min];
-        ppNodes[min] = pNodeTemp;
-    }
-
-    return nTotal;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Computes the union of the two lists of cuts.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-Map_Cut_t * Map_CutUnionLists( Map_Cut_t * pList1, Map_Cut_t * pList2 )
-{
-    Map_Cut_t * pTemp, * pRoot;
-    // find the last cut in the first list
-    pRoot = pList1;
-    Map_ListForEachCut( pList1, pTemp )
-        pRoot = pTemp;
-    // attach the non-trival part of the second cut to the end of the first
-    assert( pRoot->pNext == NULL );
-    pRoot->pNext = pList2->pNext;   
-    pList2->pNext = NULL;
-    return pList1;
-}
-
-
-/**Function*************************************************************
-
-  Synopsis    [Checks whether the given cut belongs to the list.]
-
-  Description [This procedure takes most of the runtime in the cut 
-  computation.]
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Map_CutBelongsToList( Map_Cut_t * pList, Map_Node_t * ppNodes[], int nNodes )
-{
-    Map_Cut_t * pTemp;
-    int i;
-    for ( pTemp = pList; pTemp; pTemp = pTemp->pNext )
-    {
-        for ( i = 0; i < nNodes; i++ )
-            if ( pTemp->ppLeaves[i] != ppNodes[i] )
-                break;
-        if ( i == nNodes )
-            return 1;
-    }
-    return 0;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Counts all the cuts.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Map_MappingCountAllCuts( Map_Man_t * pMan )
-{
-    Map_Node_t * pNode;
-    Map_Cut_t * pCut;
-    int i, nCuts;
-//    int nCuts55 = 0, nCuts5x = 0, nCuts4x = 0, nCuts3x = 0;
-//    int pCounts[7] = {0};
-    nCuts = 0;
-    for ( i = 0; i < pMan->nBins; i++ )
-        for ( pNode = pMan->pBins[i]; pNode; pNode = pNode->pNext )
-            for ( pCut = pNode->pCuts; pCut; pCut = pCut->pNext )
-                if ( pCut->nLeaves > 1 ) // skip the elementary cuts
-                {
-                    nCuts++;
-/*
-                    if ( Map_CutRegular(pCut->pOne)->nLeaves == 5 && Map_CutRegular(pCut->pTwo)->nLeaves == 5 )
-                        nCuts55++;
-                    if ( Map_CutRegular(pCut->pOne)->nLeaves == 5 || Map_CutRegular(pCut->pTwo)->nLeaves == 5 )
-                        nCuts5x++;
-                    else if ( Map_CutRegular(pCut->pOne)->nLeaves == 4 || Map_CutRegular(pCut->pTwo)->nLeaves == 4 )
-                        nCuts4x++;
-                    else if ( Map_CutRegular(pCut->pOne)->nLeaves == 3 || Map_CutRegular(pCut->pTwo)->nLeaves == 3 )
-                        nCuts3x++;
-*/                  
-//                    pCounts[ Map_CutRegular(pCut->pOne)->nLeaves ]++;
-//                    pCounts[ Map_CutRegular(pCut->pTwo)->nLeaves ]++;
-                }
-//    printf( "Total cuts = %6d. 55 = %6d. 5x = %6d. 4x = %6d. 3x = %6d.\n", nCuts, nCuts55, nCuts5x, nCuts4x, nCuts3x );
-
-//    printf( "Total cuts = %6d. 6= %6d. 5= %6d. 4= %6d. 3= %6d. 2= %6d. 1= %6d.\n", 
-//        nCuts, pCounts[6], pCounts[5], pCounts[4], pCounts[3], pCounts[2], pCounts[1] );
-    return nCuts;
-}
-
-
-/**Function*************************************************************
-
-  Synopsis    [Prints the cuts in the list.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Map_CutListPrint( Map_Man_t * pMan, Map_Node_t * pRoot )
-{
-    Map_Cut_t * pTemp;
-    int Counter;
-    for ( Counter = 0, pTemp = pRoot->pCuts; pTemp; pTemp = pTemp->pNext, Counter++ )
-    {
-        printf( "%2d : ", Counter + 1 );
-        Map_CutPrint_( pMan, pTemp, pRoot );
-    }
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Prints the cuts in the list.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Map_CutListPrint2( Map_Man_t * pMan, Map_Node_t * pRoot )
-{
-    Map_Cut_t * pTemp;
-    int Counter;
-    for ( Counter = 0, pTemp = pRoot->pCuts; pTemp; pTemp = pTemp->pNext, Counter++ )
-    {
-        printf( "%2d : ", Counter + 1 );
-        Map_CutPrint_( pMan, pTemp, pRoot );
-    }
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Prints the cut.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Map_CutPrint_( Map_Man_t * pMan, Map_Cut_t * pCut, Map_Node_t * pRoot )
-{
-    int i;
-    printf( "(%3d)  {", pRoot->Num );
-    for ( i = 0; i < pMan->nVarsMax; i++ )
-        if ( pCut->ppLeaves[i] )
-            printf( " %3d", pCut->ppLeaves[i]->Num );
-    printf( " }\n" );
-}
-
-
-
-
-
-
-
-
-/**Function*************************************************************
-
-  Synopsis    [Starts the hash table to canonicize cuts.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-Map_CutTable_t * Map_CutTableStart( Map_Man_t * pMan )
-{
-    Map_CutTable_t * p;
-    // allocate the table
-    p = ALLOC( Map_CutTable_t, 1 );
-    memset( p, 0, sizeof(Map_CutTable_t) );
-    p->nBins = Cudd_Prime( 10 * MAP_CUTS_MAX_COMPUTE );
-    p->pBins = ALLOC( Map_Cut_t *, p->nBins );
-    memset( p->pBins, 0, sizeof(Map_Cut_t *) * p->nBins );
-    p->pCuts = ALLOC( int, 2 * MAP_CUTS_MAX_COMPUTE );
-    p->pArray = ALLOC( Map_Cut_t *, 2 * MAP_CUTS_MAX_COMPUTE );
-    p->pCuts1 = ALLOC( Map_Cut_t *, 2 * MAP_CUTS_MAX_COMPUTE );
-    p->pCuts2 = ALLOC( Map_Cut_t *, 2 * MAP_CUTS_MAX_COMPUTE );
-    return p;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Stops the hash table.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Map_CutTableStop( Map_CutTable_t * p )
-{
-    free( p->pCuts1 );
-    free( p->pCuts2 );
-    free( p->pArray );
-    free( p->pBins );
-    free( p->pCuts );
-    free( p );
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Computes the hash value of the cut.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-unsigned Map_CutTableHash( Map_Node_t * ppNodes[], int nNodes )
-{
-    unsigned uRes;
-    int i;
-    uRes = 0;
-    for ( i = 0; i < nNodes; i++ )
-        uRes += s_HashPrimes[i] * ppNodes[i]->Num;
-    return uRes;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Looks up the table for the available cut.]
-
-  Description [Returns -1 if the same cut is found. Returns the index
-  of the cell where the cut should be added, if it does not exist.]
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Map_CutTableLookup( Map_CutTable_t * p, Map_Node_t * ppNodes[], int nNodes )
-{
-    Map_Cut_t * pCut;
-    unsigned Key;
-    int b, i;
-
-    Key = Map_CutTableHash(ppNodes, nNodes) % p->nBins; 
-    for ( b = Key; p->pBins[b]; b = (b+1) % p->nBins )
-    {
-        pCut = p->pBins[b];
-        if ( pCut->nLeaves != nNodes )
-            continue;
-        for ( i = 0; i < nNodes; i++ )
-            if ( pCut->ppLeaves[i] != ppNodes[i] )
-                break;
-        if ( i == nNodes )
-            return -1;
-    }
-    return b;
-}
-
-
-/**Function*************************************************************
-
-  Synopsis    [Starts the hash table to canonicize cuts.]
-
-  Description [Considers addition of the cut to the hash table.]
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-Map_Cut_t * Map_CutTableConsider( Map_Man_t * pMan, Map_CutTable_t * p, Map_Node_t * ppNodes[], int nNodes )
-{
-    Map_Cut_t * pCut;
-    int Place, i;
-//    int clk;
-    // check the cut
-    Place = Map_CutTableLookup( p, ppNodes, nNodes );
-    if ( Place == -1 )
-        return NULL;
-    assert( nNodes > 0 );
-    // create the new cut
-//clk = clock();
-    pCut = Map_CutAlloc( pMan );
-//pMan->time1 += clock() - clk;
-    pCut->nLeaves = nNodes;
-    for ( i = 0; i < nNodes; i++ )
-        pCut->ppLeaves[i] = ppNodes[i];
-    // add the cut to the table
-    assert( p->pBins[Place] == NULL );
-    p->pBins[Place] = pCut;
-    // add the cut to the new list
-    p->pCuts[ p->nCuts++ ] = Place;
-    return pCut;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Prepares the table to be used with other cuts.]
-
-  Description [Restarts the table by cleaning the info about cuts stored
-  when the previous node was considered.]
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Map_CutTableRestart( Map_CutTable_t * p )
-{
-    int i;
-    for ( i = 0; i < p->nCuts; i++ )
-    {
-        assert( p->pBins[ p->pCuts[i] ] );
-        p->pBins[ p->pCuts[i] ] = NULL;
-    }
-    p->nCuts = 0;
-}
-
-
-
-/**Function*************************************************************
-
-  Synopsis    [Compares the cuts by the number of leaves and then by delay.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Map_CutSortCutsCompare( Map_Cut_t ** pC1, Map_Cut_t ** pC2 )
-{
-    if ( (*pC1)->nLeaves < (*pC2)->nLeaves )
-        return -1;
-    if ( (*pC1)->nLeaves > (*pC2)->nLeaves )
-        return 1;
-    return 0;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Sorts the cuts by average arrival time.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-Map_Cut_t * Map_CutSortCuts( Map_Man_t * pMan, Map_CutTable_t * p, Map_Cut_t * pList )
-{
-    Map_Cut_t * pListNew;
-    int nCuts, i;
-//    int clk;
-    // move the cuts from the list into the array
-    nCuts = Map_CutList2Array( p->pCuts1, pList );
-    assert( nCuts <= MAP_CUTS_MAX_COMPUTE );
-    // sort the cuts
-//clk = clock();
-    qsort( (void *)p->pCuts1, nCuts, sizeof(Map_Cut_t *), 
-            (int (*)(const void *, const void *)) Map_CutSortCutsCompare );
-//pMan->time2 += clock() - clk;
-    // move them back into the list
-    if ( nCuts > MAP_CUTS_MAX_USE - 1 )
-    {
-        // free the remaining cuts
-        for ( i = MAP_CUTS_MAX_USE - 1; i < nCuts; i++ )
-            Extra_MmFixedEntryRecycle( pMan->mmCuts, (char *)p->pCuts1[i] );
-        // update the number of cuts
-        nCuts = MAP_CUTS_MAX_USE - 1;
-    }
-    pListNew = Map_CutArray2List( p->pCuts1, nCuts );
-    return pListNew;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Moves the nodes from the list into the array.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Map_CutList2Array( Map_Cut_t ** pArray, Map_Cut_t * pList )
-{
-    int i;
-    for ( i = 0; pList; pList = pList->pNext, i++ )
-        pArray[i] = pList;
-    return i;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Moves the nodes from the array into the list.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-Map_Cut_t * Map_CutArray2List( Map_Cut_t ** pArray, int nCuts )
-{
-    Map_Cut_t * pListNew, ** ppListNew;
-    int i;
-    pListNew  = NULL;
-    ppListNew = &pListNew;
-    for ( i = 0; i < nCuts; i++ )
-    {
-        // connect these lists
-        *ppListNew = pArray[i];
-        ppListNew  = &pArray[i]->pNext;
-    }
-//printf( "\n" );
-
-    *ppListNew = NULL;
-    return pListNew;
-}
-
-
-/**Function*************************************************************
-
-  Synopsis    [Computes the truth table of the 5-input cut.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-unsigned Map_CutComputeTruth( Map_Man_t * p, Map_Cut_t * pCut, Map_Cut_t * pTemp0, Map_Cut_t * pTemp1, int fComp0, int fComp1 )
-{
-    static unsigned ** pPerms53 = NULL;
-    static unsigned ** pPerms54 = NULL;
-
-    unsigned uPhase, uTruth, uTruth0, uTruth1;
-    int i, k;
-
-    if ( pPerms53 == NULL )
-    {
-        pPerms53 = (unsigned **)Extra_TruthPerm53();
-        pPerms54 = (unsigned **)Extra_TruthPerm54();
-    }
-
-    // find the mapping from the old nodes to the new
-    if ( pTemp0->nLeaves == pCut->nLeaves )
-        uTruth0 = pTemp0->uTruth;
-    else
-    {
-        assert( pTemp0->nLeaves < pCut->nLeaves );
-        uPhase = 0;
-        for ( i = 0; i < (int)pTemp0->nLeaves; i++ )
-        {
-            for ( k = 0; k < pCut->nLeaves; k++ )
-                if ( pTemp0->ppLeaves[i] == pCut->ppLeaves[k] )
-                    break;
-            uPhase |= (1 << k);
-        }
-        assert( uPhase < 32 );
-        if ( pTemp0->nLeaves == 4 )
-        {
-            if ( uPhase == 31-16 ) // 01111
-                uTruth0 = pTemp0->uTruth;
-            else if ( uPhase == 31-8 ) // 10111
-                uTruth0 = pPerms54[pTemp0->uTruth & 0xFFFF][0];
-            else if ( uPhase == 31-4 ) // 11011
-                uTruth0 = pPerms54[pTemp0->uTruth & 0xFFFF][1];
-            else if ( uPhase == 31-2 ) // 11101
-                uTruth0 = pPerms54[pTemp0->uTruth & 0xFFFF][2];
-            else if ( uPhase == 31-1 ) // 11110
-                uTruth0 = pPerms54[pTemp0->uTruth & 0xFFFF][3];
-            else
-                assert( 0 );
-        }
-        else
-            uTruth0 = pPerms53[pTemp0->uTruth & 0xFF][uPhase];
-    }
-    uTruth0 = fComp0? ~uTruth0: uTruth0;
-
-    // find the mapping from the old nodes to the new
-    if ( pTemp1->nLeaves == pCut->nLeaves )
-        uTruth1 = pTemp1->uTruth;
-    else
-    {
-        assert( pTemp1->nLeaves < pCut->nLeaves );
-        uPhase = 0;
-        for ( i = 0; i < (int)pTemp1->nLeaves; i++ )
-        {
-            for ( k = 0; k < pCut->nLeaves; k++ )
-                if ( pTemp1->ppLeaves[i] == pCut->ppLeaves[k] )
-                    break;
-            uPhase |= (1 << k);
-        }
-        assert( uPhase < 32 );
-        if ( pTemp1->nLeaves == 4 )
-        {
-            if ( uPhase == 31-16 ) // 01111
-                uTruth1 = pTemp1->uTruth;
-            else if ( uPhase == 31-8 ) // 10111
-                uTruth1 = pPerms54[pTemp1->uTruth & 0xFFFF][0];
-            else if ( uPhase == 31-4 ) // 11011
-                uTruth1 = pPerms54[pTemp1->uTruth & 0xFFFF][1];
-            else if ( uPhase == 31-2 ) // 11101
-                uTruth1 = pPerms54[pTemp1->uTruth & 0xFFFF][2];
-            else if ( uPhase == 31-1 ) // 11110
-                uTruth1 = pPerms54[pTemp1->uTruth & 0xFFFF][3];
-            else
-                assert( 0 );
-        }
-        else
-            uTruth1 = pPerms53[pTemp1->uTruth & 0xFF][uPhase];
-    }
-    uTruth1 = fComp1? ~uTruth1: uTruth1;
-    uTruth  = uTruth0 & uTruth1;
-    return uTruth;
-}
-
-////////////////////////////////////////////////////////////////////////
-///                       END OF FILE                                ///
-////////////////////////////////////////////////////////////////////////
-
diff --git a/abc70930/src/map/mapper/mapperCutUtils.c b/abc70930/src/map/mapper/mapperCutUtils.c
deleted file mode 100644
index 4450cb04..00000000
--- a/abc70930/src/map/mapper/mapperCutUtils.c
+++ /dev/null
@@ -1,273 +0,0 @@
-/**CFile****************************************************************
-
-  FileName    [mapperCutUtils.c]
-
-  PackageName [MVSIS 1.3: Multi-valued logic synthesis system.]
-
-  Synopsis    [Generic technology mapping engine.]
-
-  Author      [MVSIS Group]
-  
-  Affiliation [UC Berkeley]
-
-  Date        [Ver. 2.0. Started - June 1, 2004.]
-
-  Revision    [$Id: mapperCutUtils.h,v 1.0 2003/09/08 00:00:00 alanmi Exp $]
-
-***********************************************************************/
-
-#include "mapperInt.h"
-
-////////////////////////////////////////////////////////////////////////
-///                        DECLARATIONS                              ///
-////////////////////////////////////////////////////////////////////////
-
-////////////////////////////////////////////////////////////////////////
-///                     FUNCTION DEFINITIONS                         ///
-////////////////////////////////////////////////////////////////////////
-
-/**Function*************************************************************
-
-  Synopsis    [Allocates the cut.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-Map_Cut_t * Map_CutAlloc( Map_Man_t * p )
-{
-    Map_Cut_t * pCut;
-    Map_Match_t * pMatch;
-    pCut = (Map_Cut_t *)Extra_MmFixedEntryFetch( p->mmCuts );
-    memset( pCut, 0, sizeof(Map_Cut_t) );
-
-    pMatch = pCut->M;
-    pMatch->AreaFlow       = MAP_FLOAT_LARGE; // unassigned
-    pMatch->tArrive.Rise   = MAP_FLOAT_LARGE; // unassigned
-    pMatch->tArrive.Fall   = MAP_FLOAT_LARGE; // unassigned
-    pMatch->tArrive.Worst  = MAP_FLOAT_LARGE; // unassigned
-
-    pMatch = pCut->M + 1;
-    pMatch->AreaFlow       = MAP_FLOAT_LARGE; // unassigned
-    pMatch->tArrive.Rise   = MAP_FLOAT_LARGE; // unassigned
-    pMatch->tArrive.Fall   = MAP_FLOAT_LARGE; // unassigned
-    pMatch->tArrive.Worst  = MAP_FLOAT_LARGE; // unassigned
-    return pCut;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Deallocates the cut.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Map_CutFree( Map_Man_t * p, Map_Cut_t * pCut )
-{
-    if ( pCut )
-    Extra_MmFixedEntryRecycle( p->mmCuts, (char *)pCut );
-}
-
-/**Function*************************************************************
-
-  Synopsis    []
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Map_CutPrint( Map_Man_t * p, Map_Node_t * pRoot, Map_Cut_t * pCut, int fPhase )
-{
-    int i;
-    printf( "CUT:  Delay = (%4.2f, %4.2f). Area = %4.2f. Nodes = %d -> {", 
-        pCut->M[fPhase].tArrive.Rise, pCut->M[fPhase].tArrive.Fall, pCut->M[fPhase].AreaFlow, pRoot->Num );
-    for ( i = 0; i < pCut->nLeaves; i++ )
-        printf( " %d", pCut->ppLeaves[i]->Num );
-    printf( " } \n" );
-}
-
-
-/**function*************************************************************
-
-  synopsis    [Computes the exact area associated with the cut.]
-
-  description []
-               
-  sideeffects []
-
-  seealso     []
-
-***********************************************************************/
-float Map_CutGetRootArea( Map_Cut_t * pCut, int fPhase )
-{
-    assert( pCut->M[fPhase].pSuperBest );
-    return pCut->M[fPhase].pSuperBest->Area;
-}
-
-/**function*************************************************************
-
-  synopsis    [Computes the exact area associated with the cut.]
-
-  description []
-               
-  sideeffects []
-
-  seealso     []
-
-***********************************************************************/
-int Map_CutGetLeafPhase( Map_Cut_t * pCut, int fPhase, int iLeaf )
-{
-    assert( pCut->M[fPhase].pSuperBest );
-    return (( pCut->M[fPhase].uPhaseBest & (1<<iLeaf) ) == 0);
-}
-
-/**function*************************************************************
-
-  synopsis    [Computes the exact area associated with the cut.]
-
-  description []
-               
-  sideeffects []
-
-  seealso     []
-
-***********************************************************************/
-int Map_NodeGetLeafPhase( Map_Node_t * pNode, int fPhase, int iLeaf )
-{
-    assert( pNode->pCutBest[fPhase]->M[fPhase].pSuperBest );
-    return (( pNode->pCutBest[fPhase]->M[fPhase].uPhaseBest & (1<<iLeaf) ) == 0);
-}
-
-/**Function*************************************************************
-
-  Synopsis    []
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-Map_Cut_t * Map_CutListAppend( Map_Cut_t * pSetAll, Map_Cut_t * pSets )
-{
-    Map_Cut_t * pPrev, * pTemp;
-    if ( pSetAll == NULL )
-        return pSets;
-    if ( pSets == NULL )
-        return pSetAll;
-    // find the last one
-    for ( pTemp = pSets; pTemp; pTemp = pTemp->pNext )
-        pPrev = pTemp;
-    // append all the end of the current set
-    assert( pPrev->pNext == NULL );
-    pPrev->pNext = pSetAll;
-    return pSets;
-}
-
-/**Function*************************************************************
-
-  Synopsis    []
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Map_CutListRecycle( Map_Man_t * p, Map_Cut_t * pSetList, Map_Cut_t * pSave )
-{
-    Map_Cut_t * pNext, * pTemp;
-    for ( pTemp = pSetList, pNext = pTemp? pTemp->pNext : NULL; 
-          pTemp; 
-          pTemp = pNext, pNext = pNext? pNext->pNext : NULL )
-        if ( pTemp != pSave )
-            Extra_MmFixedEntryRecycle( p->mmCuts, (char *)pTemp );
-}
-
-/**Function*************************************************************
-
-  Synopsis    []
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Map_CutListCount( Map_Cut_t * pSets )
-{
-    Map_Cut_t * pTemp;
-    int i;
-    for ( i = 0, pTemp = pSets; pTemp; pTemp = pTemp->pNext, i++ );
-    return i;
-}
-
-#if 0
-
-/**function*************************************************************
-
-  synopsis    [Removes the fanouts of the cut.]
-
-  description []
-               
-  sideeffects []
-
-  seealso     []
-
-***********************************************************************/
-void Map_CutRemoveFanouts( Map_Node_t * pNode, Map_Cut_t * pCut, int fPhase )
-{
-    Map_NodeVec_t * vFanouts;
-    int i, k;
-    for ( i = 0; i < pCut->nLeaves; i++ )
-    {
-        vFanouts = pCut->ppLeaves[i]->vFanouts;
-        for ( k = 0; k < vFanouts->nSize; k++ )
-            if ( vFanouts->pArray[k] == pNode )
-                break;
-        assert( k != vFanouts->nSize );
-        for ( k++; k < vFanouts->nSize; k++ )
-            vFanouts->pArray[k-1] = vFanouts->pArray[k];
-        vFanouts->nSize--;
-    }
-}
-
-/**function*************************************************************
-
-  synopsis    [Removes the fanouts of the cut.]
-
-  description []
-               
-  sideeffects []
-
-  seealso     []
-
-***********************************************************************/
-void Map_CutInsertFanouts( Map_Node_t * pNode, Map_Cut_t * pCut, int fPhase )
-{
-    int i;
-    for ( i = 0; i < pCut->nLeaves; i++ )
-        Map_NodeVecPush( pCut->ppLeaves[i]->vFanouts, pNode );
-}
-
-#endif
-
-
-////////////////////////////////////////////////////////////////////////
-///                       END OF FILE                                ///
-////////////////////////////////////////////////////////////////////////
-
-
diff --git a/abc70930/src/map/mapper/mapperFanout.c b/abc70930/src/map/mapper/mapperFanout.c
deleted file mode 100644
index 63cdbd2a..00000000
--- a/abc70930/src/map/mapper/mapperFanout.c
+++ /dev/null
@@ -1,141 +0,0 @@
-/**CFile****************************************************************
-
-  FileName    [mapperFanout.c]
-
-  PackageName [FRAIG: Functionally reduced AND-INV graphs.]
-
-  Synopsis    [Procedures to manipulate fanouts of the FRAIG nodes.]
-
-  Author      [Alan Mishchenko <alanmi@eecs.berkeley.edu>]
-  
-  Affiliation [UC Berkeley]
-
-  Date        [Ver. 2.0. Started - June 1, 2004.]
-
-  Revision    [$Id: mapperFanout.c,v 1.5 2005/01/23 06:59:43 alanmi Exp $]
-
-***********************************************************************/
-
-#include "mapperInt.h"
-
-#ifdef MAP_ALLOCATE_FANOUT
-
-////////////////////////////////////////////////////////////////////////
-///                        DECLARATIONS                              ///
-////////////////////////////////////////////////////////////////////////
-
-////////////////////////////////////////////////////////////////////////
-///                     FUNCTION DEFINITIONS                         ///
-////////////////////////////////////////////////////////////////////////
-
-/**Function*************************************************************
-
-  Synopsis    [Add the fanout to the node.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Map_NodeAddFaninFanout( Map_Node_t * pFanin, Map_Node_t * pFanout )
-{
-    Map_Node_t * pPivot;
-
-    // pFanins is a fanin of pFanout
-    assert( !Map_IsComplement(pFanin) );
-    assert( !Map_IsComplement(pFanout) );
-    assert( Map_Regular(pFanout->p1) == pFanin || Map_Regular(pFanout->p2) == pFanin );
-
-    pPivot = pFanin->pFanPivot;
-    if ( pPivot == NULL )
-    {
-        pFanin->pFanPivot = pFanout;
-        return;
-    }
-
-    if ( Map_Regular(pPivot->p1) == pFanin )
-    {
-        if ( Map_Regular(pFanout->p1) == pFanin )
-        {
-            pFanout->pFanFanin1 = pPivot->pFanFanin1;
-            pPivot->pFanFanin1  = pFanout;
-        }
-        else // if ( Map_Regular(pFanout->p2) == pFanin )
-        {
-            pFanout->pFanFanin2 = pPivot->pFanFanin1;
-            pPivot->pFanFanin1  = pFanout;
-        }
-    }
-    else // if ( Map_Regular(pPivot->p2) == pFanin )
-    {
-        assert( Map_Regular(pPivot->p2) == pFanin );
-        if ( Map_Regular(pFanout->p1) == pFanin )
-        {
-            pFanout->pFanFanin1 = pPivot->pFanFanin2;
-            pPivot->pFanFanin2  = pFanout;
-        }
-        else // if ( Map_Regular(pFanout->p2) == pFanin )
-        {
-            pFanout->pFanFanin2 = pPivot->pFanFanin2;
-            pPivot->pFanFanin2  = pFanout;
-        }
-    }
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Add the fanout to the node.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Map_NodeRemoveFaninFanout( Map_Node_t * pFanin, Map_Node_t * pFanoutToRemove )
-{
-    Map_Node_t * pFanout, * pFanout2, ** ppFanList;
-    // start the linked list of fanouts
-    ppFanList = &pFanin->pFanPivot; 
-    // go through the fanouts
-    Map_NodeForEachFanoutSafe( pFanin, pFanout, pFanout2 )
-    {
-        // skip the fanout-to-remove
-        if ( pFanout == pFanoutToRemove )
-            continue;
-        // add useful fanouts to the list
-        *ppFanList = pFanout;
-        ppFanList = Map_NodeReadNextFanoutPlace( pFanin, pFanout );
-    }
-    *ppFanList = NULL;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Returns the number of fanouts of a node.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Map_NodeGetFanoutNum( Map_Node_t * pNode )
-{
-    Map_Node_t * pFanout;
-    int Counter = 0;
-    Map_NodeForEachFanout( pNode, pFanout )
-        Counter++;
-    return Counter;
-}
-
-////////////////////////////////////////////////////////////////////////
-///                       END OF FILE                                ///
-////////////////////////////////////////////////////////////////////////
-
-#endif
-
diff --git a/abc70930/src/map/mapper/mapperGENERIC.c b/abc70930/src/map/mapper/mapperGENERIC.c
deleted file mode 100644
index 823eb4f2..00000000
--- a/abc70930/src/map/mapper/mapperGENERIC.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/**CFile****************************************************************
-
-  FileName    [mapper__.c]
-
-  PackageName [MVSIS 1.3: Multi-valued logic synthesis system.]
-
-  Synopsis    [Generic technology mapping engine.]
-
-  Author      [MVSIS Group]
-  
-  Affiliation [UC Berkeley]
-
-  Date        [Ver. 1.0. Started - September 8, 2003.]
-
-  Revision    [$Id: mapper__.h,v 1.0 2003/09/08 00:00:00 alanmi Exp $]
-
-***********************************************************************/
-
-#include "mapperInt.h"
-
-////////////////////////////////////////////////////////////////////////
-///                        DECLARATIONS                              ///
-////////////////////////////////////////////////////////////////////////
-
-////////////////////////////////////////////////////////////////////////
-///                     FUNCTION DEFINITIONS                         ///
-////////////////////////////////////////////////////////////////////////
-
-/**Function*************************************************************
-
-  Synopsis    []
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-
-
-////////////////////////////////////////////////////////////////////////
-///                       END OF FILE                                ///
-////////////////////////////////////////////////////////////////////////
-
-
diff --git a/abc70930/src/map/mapper/mapperInt.h b/abc70930/src/map/mapper/mapperInt.h
deleted file mode 100644
index 37cca3d3..00000000
--- a/abc70930/src/map/mapper/mapperInt.h
+++ /dev/null
@@ -1,477 +0,0 @@
-/**CFile****************************************************************
-
-  FileName    [mapperInt.h]
-
-  PackageName [MVSIS 2.0: Multi-valued logic synthesis system.]
-
-  Synopsis    [Generic technology mapping engine.]
-
-  Author      [MVSIS Group]
-  
-  Affiliation [UC Berkeley]
-
-  Date        [Ver. 2.0. Started - June 1, 2004.]
-
-  Revision    [$Id: mapperInt.h,v 1.8 2004/09/30 21:18:10 satrajit Exp $]
-
-***********************************************************************/
-
-#ifndef __MAPPER_INT_H__
-#define __MAPPER_INT_H__
-
-////////////////////////////////////////////////////////////////////////
-///                          INCLUDES                                ///
-////////////////////////////////////////////////////////////////////////
- 
-//#include "leaks.h"       
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <float.h>
-#include "cuddInt.h"
-#include "main.h"
-#include "mio.h"
-#include "mapper.h"
-
-////////////////////////////////////////////////////////////////////////
-///                         PARAMETERS                               ///
-////////////////////////////////////////////////////////////////////////
-
-// uncomment to have fanouts represented in the mapping graph
-//#define MAP_ALLOCATE_FANOUT  1
-
-////////////////////////////////////////////////////////////////////////
-///                       MACRO DEFINITIONS                          ///
-////////////////////////////////////////////////////////////////////////
-
-// the bit masks
-#define MAP_MASK(n)             ((~((unsigned)0)) >> (32-(n)))
-#define MAP_FULL                 (~((unsigned)0))
-#define MAP_NO_VAR               (-9999.0)
-
-// maximum/minimum operators
-#define MAP_MIN(a,b)             (((a) < (b))? (a) : (b))
-#define MAP_MAX(a,b)             (((a) > (b))? (a) : (b))
-
-// the small and large numbers (min/max float are 1.17e-38/3.40e+38)
-#define MAP_FLOAT_LARGE          ((float)(FLT_MAX/10))
-#define MAP_FLOAT_SMALL          ((float)1.0e-03)
-
-// generating random unsigned (#define RAND_MAX 0x7fff)
-#define MAP_RANDOM_UNSIGNED   ((((unsigned)rand()) << 24) ^ (((unsigned)rand()) << 12) ^ ((unsigned)rand()))
-
-// internal macros to work with cuts
-#define Map_CutIsComplement(p)  (((int)((unsigned long) (p) & 01)))
-#define Map_CutRegular(p)       ((Map_Cut_t *)((unsigned long)(p) & ~01)) 
-#define Map_CutNot(p)           ((Map_Cut_t *)((unsigned long)(p) ^ 01)) 
-#define Map_CutNotCond(p,c)     ((Map_Cut_t *)((unsigned long)(p) ^ (c)))
-
-// internal macros for referencing of nodes
-#define Map_NodeReadRef(p)      ((Map_Regular(p))->nRefs)
-#define Map_NodeRef(p)          ((Map_Regular(p))->nRefs++)
-
-// macros to get hold of the bits in the support info
-#define Map_InfoSetVar(p,i)     (p[(i)>>5] |=  (1<<((i) & 31)))
-#define Map_InfoRemVar(p,i)     (p[(i)>>5] &= ~(1<<((i) & 31)))
-#define Map_InfoFlipVar(p,i)    (p[(i)>>5] ^=  (1<<((i) & 31)))
-#define Map_InfoReadVar(p,i)   ((p[(i)>>5]  &  (1<<((i) & 31))) > 0)
-
-// returns the complemented attribute of the node
-#define Map_NodeIsSimComplement(p) (Map_IsComplement(p)? !(Map_Regular(p)->fInv) : (p)->fInv)
-
-////////////////////////////////////////////////////////////////////////
-///                    STRUCTURE DEFINITIONS                         ///
-////////////////////////////////////////////////////////////////////////
-
-// the mapping manager
-struct Map_ManStruct_t_
-{
-    // the mapping graph
-    Map_Node_t **       pBins;         // the table of nodes hashed by their children
-    int                 nBins;         // the size of the table
-    Map_Node_t **       pInputs;       // the array of inputs
-    int                 nInputs;       // the number of inputs
-    Map_Node_t **       pOutputs;      // the array of outputs
-    int                 nOutputs;      // the number of outputs
-    int                 nNodes;        // the total number of nodes
-    Map_Node_t *        pConst1;       // the constant 1 node
-    Map_NodeVec_t *     vAnds;         // the array of nodes in the DFS order
-    Map_NodeVec_t *     vNodesAll;     // the array of all nodes
-    Map_NodeVec_t *     vNodesTemp;    // the array of all nodes
-    Map_NodeVec_t *     vMapping;      // the array of internal nodes used in the mapping
-
-    // info about the original circuit
-    char **             ppOutputNames; // the primary output names
-    Map_Time_t *        pInputArrivals;// the PI arrival times
-
-    // mapping parameters
-    int                 nVarsMax;      // the max number of variables
-    int                 fAreaRecovery; // the flag to enable area recovery
-    int                 fVerbose;      // the verbosiness flag
-    int                 fMappingMode;  // set to 1 when doing area
-    float               fRequiredGlo;  // the global required times
-    float               fEpsilon;      // the epsilon used to compare floats
-    float               AreaBase;      // the area after delay-oriented mapping
-    float               AreaFinal;     // the area after delay-oriented mapping
-    int                 nIterations;   // How many matching passes to do
-    bool                fObeyFanoutLimits;// Should mapper try to obey fanout limits or not
-    float               DelayTarget;   // the required times set by the user
-    int                 nTravIds;      // the traversal counter
-    bool                fSwitching;    // Should mapper try to obey fanout limits or not
-
-    // the supergate library
-    Map_SuperLib_t *    pSuperLib;     // the current supergate library
-    unsigned            uTruths[6][2]; // the elementary truth tables
-    unsigned            uTruthsLarge[10][32]; // the elementary truth tables
-    int                 nCounts[32];   // the counter of minterms
-    int                 nCountsBest[32];// the counter of minterms
-    Map_NodeVec_t *     vVisited;      // the visited cuts during cut computation
-
-    // the memory managers
-    Extra_MmFixed_t *   mmNodes;       // the memory manager for nodes
-    Extra_MmFixed_t *   mmCuts;        // the memory manager for cuts
-
-    // precomputed N-canonical forms
-    unsigned short *    uCanons;       // N-canonical forms
-    char **             uPhases;       // N-canonical phases
-    char *              pCounters;     // counters of phases
-
-    // various statistical variables
-    int                 nChoiceNodes;  // the number of choice nodes
-    int                 nChoices;      // the number of all choices
-    int                 nCanons;       // the number of times N-canonical form was computed
-    int                 nMatches;      // the number of times supergate matching was performed
-    int                 nPhases;       // the number of phases considered during matching
-    int                 nFanoutViolations;  // the number of nodes in mapped circuit violating fanout
-
-    // runtime statistics
-    int                 timeToMap;     // time to transfer to the mapping structure
-    int                 timeCuts;      // time to compute k-feasible cuts
-    int                 timeTruth;     // time to compute the truth table for each cut
-    int                 timeMatch;     // time to perform matching for each node
-    int                 timeArea;      // time to recover area after delay oriented mapping
-    int                 timeSweep;     // time to perform technology dependent sweep
-    int                 timeToNet;     // time to transfer back to the network
-    int                 timeTotal;     // the total mapping time
-    int                 time1;         // time to transfer to the mapping structure
-    int                 time2;         // time to transfer to the mapping structure
-    int                 time3;         // time to transfer to the mapping structure
-};
-
-// the supergate library
-struct Map_SuperLibStruct_t_
-{
-    // general info
-    char *              pName;         // the name of the supergate library
-    Mio_Library_t *     pGenlib;       // the generic library
-
-    // other info
-    int                 nVarsMax;      // the max number of variables
-    int                 nSupersAll;    // the total number of supergates
-    int                 nSupersReal;   // the total number of supergates
-    int                 nLines;        // the total number of lines in the supergate file
-    bool                fVerbose;      // the verbosity flag
-
-    // hash tables
-    Map_Super_t **      ppSupers;      // the array of supergates
-    Map_HashTable_t *   tTableC;       // the table mapping N-canonical forms into supergates
-    Map_HashTable_t *   tTable;        // the table mapping truth tables into supergates
-
-    // data structures for N-canonical form computation
-    unsigned            uTruths[6][2]; // the elementary truth tables
-    unsigned            uMask[2];      // the mask for the truth table
-
-    // the invertor
-    Mio_Gate_t *        pGateInv;      // the pointer to the intertor gate
-    Map_Time_t          tDelayInv;     // the delay of the inverter
-    float               AreaInv;       // the area of the inverter
-    float               AreaBuf;       // the area of the buffer
-    Map_Super_t *       pSuperInv;     // the supergate representing the inverter
-
-    // the memory manager for the internal table
-    Extra_MmFixed_t *   mmSupers;      // the mamory manager for supergates
-    Extra_MmFixed_t *   mmEntries;     // the memory manager for the entries
-    Extra_MmFlex_t *    mmForms;       // the memory manager for formulas
-};
-
-// the mapping node
-struct Map_NodeStruct_t_ 
-{
-    // general information about the node
-    Map_Man_t *         p;             // the mapping manager
-    Map_Node_t *        pNext;         // the next node in the hash table
-    int                 Num;           // the unique number of this node
-    int                 TravId;        // the traversal ID (use to avoid cleaning marks)
-    int                 nRefs;         // the number of references (fanouts) of the given node
-    unsigned            fMark0 : 1;    // the mark used for traversals
-    unsigned            fMark1 : 1;    // the mark used for traversals
-    unsigned            fUsed  : 1;    // the mark to mark the node or its fanins
-    unsigned            fInv   : 1;    // the complemented attribute for the equivalent nodes
-    unsigned            fInvert: 1;    // the flag to denote the use of interter
-    unsigned            Level  :16;    // the level of the given node
-    unsigned            NumTemp:10;    // the level of the given node
-    int                 nRefAct[3];    // estimated fanout for current covering phase, neg and pos and sum
-    float               nRefEst[3];    // actual fanout for previous covering phase, neg and pos and sum
-    float               Switching;     // the probability of switching
-
-    // connectivity
-    Map_Node_t *        p1;            // the first child
-    Map_Node_t *        p2;            // the second child
-    Map_Node_t *        pNextE;        // the next functionally equivalent node
-    Map_Node_t *        pRepr;         // the representative of the functionally equivalent class
-
-#ifdef MAP_ALLOCATE_FANOUT
-    // representation of node's fanouts
-    Map_Node_t *        pFanPivot;     // the first fanout of this node
-    Map_Node_t *        pFanFanin1;    // the next fanout of p1
-    Map_Node_t *        pFanFanin2;    // the next fanout of p2
-//    Map_NodeVec_t *     vFanouts;      // the array of fanouts of the gate
-#endif
-
-    // the delay information
-    Map_Time_t          tArrival[2];   // the best arrival time of the neg (0) and pos (1) phases
-    Map_Time_t          tRequired[2];  // the required time of the neg (0) and pos (1) phases
-
-    // misc information  
-    Map_Cut_t *         pCutBest[2];   // the best mapping for neg and pos phase
-    Map_Cut_t *         pCuts;         // mapping choices for the node (elementary comes first)
-    char *              pData0;        // temporary storage for the corresponding network node
-    char *              pData1;        // temporary storage for the corresponding network node
-}; 
-
-// the match of the cut
-struct Map_MatchStruct_t_  
-{
-    // information used for matching
-    Map_Super_t *       pSupers;     
-    unsigned            uPhase;  
-    // information about the best selected match
-    unsigned            uPhaseBest;    // the best phase (the EXOR of match's phase and gate's phase)
-    Map_Super_t *       pSuperBest;    // the best supergate matched
-    // the parameters of the match
-    Map_Time_t          tArrive;       // the arrival time of this match
-    float               AreaFlow;      // the area flow or area of this match
-};
-  
-// the cuts used for matching
-struct Map_CutStruct_t_  
-{
-    Map_Cut_t *         pNext;         // the pointer to the next cut in the list
-    Map_Cut_t *         pOne;          // the father of this cut
-    Map_Cut_t *         pTwo;          // the mother of this cut
-    Map_Node_t *        ppLeaves[6];   // the leaves of this cut
-    unsigned            uTruth;        // truth table for five-input cuts
-    char                nLeaves;       // the number of leaves
-    char                nVolume;       // the volume of this cut
-    char                fMark;         // the mark to denote visited cut
-    char                Phase;         // the mark to denote complemented cut
-    Map_Match_t         M[2];          // the matches for positive/negative phase
-};
-
-// the supergate internally represented
-struct Map_SuperStruct_t_  
-{
-    int                 Num;           // the ID of the supergate
-    unsigned            fSuper  :  1;  // the flag to distinquish a real super from a fake one
-    unsigned            fExclude:  1;  // the flag if set causes gate to be excluded from being used for mapping
-    unsigned            nFanins :  3;  // the number of inputs
-    unsigned            nGates  :  3;  // the number of gates inside this supergate
-    unsigned            nFanLimit: 4;  // the max number of fanout count
-    unsigned            nSupers : 16;  // the number of supergates in the list
-    unsigned            nPhases :  4;  // the number of phases for matching with canonical form
-    unsigned char       uPhases[4];    // the maximum of 4 phases for matching with canonical form
-    int                 nUsed;         // the number of times the supergate is used
-    Map_Super_t *       pFanins[6];    // the fanins of the gate
-    Mio_Gate_t *        pRoot;         // the root gate
-    unsigned            uTruth[2];     // the truth table
-    Map_Time_t          tDelaysR[6];   // the pin-to-pin delay constraints for the rise of the output
-    Map_Time_t          tDelaysF[6];   // the pin-to-pin delay constraints for the rise of the output
-    Map_Time_t          tDelayMax;     // the maximum delay
-    float               Area;          // the area
-    char *              pFormula;      // the symbolic formula
-    Map_Super_t *       pNext;         // the pointer to the next super in the list
-};
-
-// the vector of nodes
-struct Map_NodeVecStruct_t_
-{
-    Map_Node_t **       pArray;        // the array of nodes
-    int                 nSize;         // the number of entries in the array
-    int                 nCap;          // the number of allocated entries
-};
-
-// the hash table 
-struct Map_HashTableStruct_t_
-{
-    Map_HashEntry_t **  pBins;         // the table bins
-    int                 nBins;         // the size of the table
-    int                 nEntries;      // the total number of entries in the table
-    Extra_MmFixed_t *   mmMan;         // the memory manager for entries
-};
-
-// the entry in the hash table
-struct Map_HashEntryStruct_t_
-{
-    unsigned            uTruth[2];     // the truth table for 6-var function
-    unsigned            uPhase;        // the phase to tranform it into the canonical form
-    Map_Super_t *       pGates;        // the linked list of matching supergates
-    Map_HashEntry_t *   pNext;         // the next entry in the hash table
-};
-
-// getting hold of the next fanout of the node
-#define Map_NodeReadNextFanout( pNode, pFanout )                \
-    ( ( pFanout == NULL )? NULL :                               \
-        ((Map_Regular((pFanout)->p1) == (pNode))?               \
-             (pFanout)->pFanFanin1 : (pFanout)->pFanFanin2) )
-
-// getting hold of the place where the next fanout will be attached
-#define Map_NodeReadNextFanoutPlace( pNode, pFanout )           \
-    ( (Map_Regular((pFanout)->p1) == (pNode))?                  \
-         &(pFanout)->pFanFanin1 : &(pFanout)->pFanFanin2 )
-
-// iterator through the fanouts of the node
-#define Map_NodeForEachFanout( pNode, pFanout )                 \
-    for ( pFanout = (pNode)->pFanPivot; pFanout;                \
-          pFanout = Map_NodeReadNextFanout(pNode, pFanout) )
-
-// safe iterator through the fanouts of the node
-#define Map_NodeForEachFanoutSafe( pNode, pFanout, pFanout2 )   \
-    for ( pFanout  = (pNode)->pFanPivot,                        \
-          pFanout2 = Map_NodeReadNextFanout(pNode, pFanout);    \
-          pFanout;                                              \
-          pFanout  = pFanout2,                                  \
-          pFanout2 = Map_NodeReadNextFanout(pNode, pFanout) )
-
-////////////////////////////////////////////////////////////////////////
-///                       GLOBAL VARIABLES                           ///
-////////////////////////////////////////////////////////////////////////
-
-////////////////////////////////////////////////////////////////////////
-///                     FUNCTION DEFINITIONS                         ///
-////////////////////////////////////////////////////////////////////////
-
-/*=== mapperCanon.c =============================================================*/
-/*=== mapperCut.c ===============================================================*/
-extern void              Map_MappingCuts( Map_Man_t * p );
-extern int               Map_MappingCountAllCuts( Map_Man_t * p );
-/*=== mapperCutDcs.c ===============================================================*/
-extern void              Map_ComputeDcs( Map_Man_t * p );
-extern unsigned          Map_ComputeIsop_rec( Map_Man_t * p, unsigned uF, unsigned uFD, int iVar, int nVars, int fDir );
-/*=== mapperCutUtils.c ===============================================================*/
-extern Map_Cut_t *       Map_CutAlloc( Map_Man_t * p );
-extern void              Map_CutFree( Map_Man_t * p, Map_Cut_t * pCut );
-extern void              Map_CutPrint( Map_Man_t * p, Map_Node_t * pRoot, Map_Cut_t * pCut, int fPhase );
-extern float             Map_CutGetRootArea( Map_Cut_t * pCut, int fPhase );
-extern int               Map_CutGetLeafPhase( Map_Cut_t * pCut, int fPhase, int iLeaf );
-extern int               Map_NodeGetLeafPhase( Map_Node_t * pNode, int fPhase, int iLeaf );
-extern Map_Cut_t *       Map_CutListAppend( Map_Cut_t * pSetAll, Map_Cut_t * pSets );
-extern void              Map_CutListRecycle( Map_Man_t * p, Map_Cut_t * pSetList, Map_Cut_t * pSave );
-extern int               Map_CutListCount( Map_Cut_t * pSets );
-extern void              Map_CutRemoveFanouts( Map_Node_t * pNode, Map_Cut_t * pCut, int fPhase );
-extern void              Map_CutInsertFanouts( Map_Node_t * pNode, Map_Cut_t * pCut, int fPhase );
-/*=== mapperFanout.c =============================================================*/
-extern void              Map_NodeAddFaninFanout( Map_Node_t * pFanin, Map_Node_t * pFanout );
-extern void              Map_NodeRemoveFaninFanout( Map_Node_t * pFanin, Map_Node_t * pFanoutToRemove );
-extern int               Map_NodeGetFanoutNum( Map_Node_t * pNode );
-/*=== mapperLib.c ============================================================*/
-extern Map_SuperLib_t *  Map_SuperLibCreate( char * pFileName, char * pExcludeFile, bool fAlgorithm, bool fVerbose );
-extern void              Map_SuperLibFree( Map_SuperLib_t * p );
-/*=== mapperMatch.c ===============================================================*/
-extern int               Map_MappingMatches( Map_Man_t * p );
-extern float             Map_MappingCombinePhases( Map_Man_t * p );
-extern void              Map_MatchClean( Map_Match_t * pMatch );
-extern int               Map_MatchCompare( Map_Man_t * pMan, Map_Match_t * pM1, Map_Match_t * pM2, int fDoingArea );
-/*=== mapperPower.c =============================================================*/
-extern float             Map_SwitchCutGetDerefed( Map_Node_t * pNode, Map_Cut_t * pCut, int fPhase );
-extern float             Map_SwitchCutRef( Map_Node_t * pNode, Map_Cut_t * pCut, int fPhase );
-extern float             Map_SwitchCutDeref( Map_Node_t * pNode, Map_Cut_t * pCut, int fPhase );
-extern float             Map_MappingGetSwitching( Map_Man_t * pMan, Map_NodeVec_t * vMapping );
-/*=== mapperRefs.c =============================================================*/
-extern int               Map_NodeReadRefPhaseAct( Map_Node_t * pNode, int fPhase );
-extern float             Map_NodeReadRefPhaseEst( Map_Node_t * pNode, int fPhase );
-extern void              Map_MappingEstimateRefsInit( Map_Man_t * p );
-extern void              Map_MappingEstimateRefs( Map_Man_t * p );
-extern float             Map_CutGetAreaFlow( Map_Cut_t * pCut, int fPhase );
-extern float             Map_CutGetAreaRefed( Map_Cut_t * pCut, int fPhase );
-extern float             Map_CutGetAreaDerefed( Map_Cut_t * pCut, int fPhase );
-extern float             Map_CutRef( Map_Cut_t * pCut, int fPhase );
-extern float             Map_CutDeref( Map_Cut_t * pCut, int fPhase );
-extern void              Map_MappingSetRefs( Map_Man_t * pMan );
-extern float             Map_MappingGetArea( Map_Man_t * pMan, Map_NodeVec_t * vMapping );
-/*=== mapperShow.c =============================================================*/
-extern void              Map_MappingShow( Map_Man_t * pMan, char * pFileName );
-/*=== mapperTree.c ===============================================================*/
-extern int               Map_LibraryReadTree( Map_SuperLib_t * pLib, char * pFileName, char * pExcludeFile );
-extern void              Map_LibraryPrintTree( Map_SuperLib_t * pLib );
-/*=== mapperSuper.c ===============================================================*/
-extern int               Map_LibraryRead( Map_SuperLib_t * p, char * pFileName );
-extern void              Map_LibraryPrintSupergate( Map_Super_t * pGate );
-/*=== mapperTable.c ============================================================*/
-extern Map_HashTable_t * Map_SuperTableCreate( Map_SuperLib_t * pLib );
-extern void              Map_SuperTableFree( Map_HashTable_t * p );
-extern int               Map_SuperTableInsertC( Map_HashTable_t * pLib, unsigned uTruthC[], Map_Super_t * pGate );
-extern int               Map_SuperTableInsert( Map_HashTable_t * pLib, unsigned uTruth[], Map_Super_t * pGate, unsigned uPhase );
-extern Map_Super_t *     Map_SuperTableLookup( Map_HashTable_t * p, unsigned uTruth[], unsigned * puPhase );
-extern void              Map_SuperTableSortSupergates( Map_HashTable_t * p, int nSupersMax );
-extern void              Map_SuperTableSortSupergatesByDelay( Map_HashTable_t * p, int nSupersMax );
-/*=== mapperTime.c =============================================================*/
-extern float             Map_TimeCutComputeArrival( Map_Node_t * pNode, Map_Cut_t * pCut, int fPhase, float tWorstCaseLimit );
-extern void              Map_TimeCutComputeArrival_rec( Map_Cut_t * pCut, int fPhase );
-extern float             Map_TimeComputeArrivalMax( Map_Man_t * p );
-extern void              Map_TimeComputeRequiredGlobal( Map_Man_t * p );
-extern void              Map_TimeComputeRequired( Map_Man_t * p, float fRequired );
-extern float             Map_TimeNodeFanoutDelay( Map_Node_t * pNode, int fPhase );
-extern float             Map_TimeCutFanoutDelay( Map_Node_t * pNode, Map_Cut_t * pCut, int fPhase );
-extern float             Map_TimeMatchWithInverter( Map_Man_t * p, Map_Match_t * pMatch );
-/*=== mapperTruth.c ===============================================================*/
-extern void              Map_MappingTruths( Map_Man_t * pMan );
-extern int               Map_TruthsCutDontCare( Map_Man_t * pMan, Map_Cut_t * pCut, unsigned * uTruthDc );
-extern int               Map_TruthCountOnes( unsigned * uTruth, int nLeaves );
-extern int               Map_TruthDetectTwoFirst( unsigned * uTruth, int nLeaves );
-/*=== mapperUtils.c ===============================================================*/
-extern Map_NodeVec_t *   Map_MappingDfs( Map_Man_t * pMan, int fCollectEquiv );
-extern Map_NodeVec_t *   Map_MappingDfsNodes( Map_Man_t * pMan, Map_Node_t ** ppNodes, int nNodes, int fEquiv );
-
-extern void              Map_MappingDfsMarked1_rec( Map_Node_t * pNode, Map_NodeVec_t * vNodes, int fFirst );
-extern void              Map_MappingDfsMarked2_rec( Map_Node_t * pNode, Map_NodeVec_t * vNodes, Map_NodeVec_t * vBoundary, int fFirst );
-
-extern int               Map_MappingCountLevels( Map_Man_t * pMan );
-extern void              Map_MappingUnmark( Map_Man_t * pMan );
-extern void              Map_MappingMark_rec( Map_Node_t * pNode );
-extern void              Map_MappingUnmark_rec( Map_Node_t * pNode );
-extern void              Map_MappingPrintOutputArrivals( Map_Man_t * p );
-extern void              Map_MappingSetupMask( unsigned uMask[], int nVarsMax );
-extern int               Map_MappingNodeIsViolator( Map_Node_t * pNode, Map_Cut_t * pCut, int fPosPol );
-extern float             Map_MappingGetAreaFlow( Map_Man_t * p );
-extern void              Map_MappingSortByLevel( Map_Man_t * pMan, Map_NodeVec_t * vNodes );
-extern int               Map_MappingCountDoubles( Map_Man_t * pMan, Map_NodeVec_t * vNodes );
-extern void              Map_MappingExpandTruth( unsigned uTruth[2], int nVars );
-extern float             Map_MappingPrintSwitching( Map_Man_t * pMan );
-extern void              Map_MappingSetPlacementInfo( Map_Man_t * p );
-extern float             Map_MappingPrintWirelength( Map_Man_t * p );
-extern void              Map_MappingWireReport( Map_Man_t * p );
-extern float             Map_MappingComputeDelayWithFanouts( Map_Man_t * p );
-extern int               Map_MappingGetMaxLevel( Map_Man_t * pMan );
-extern void              Map_MappingSetChoiceLevels( Map_Man_t * pMan );
-extern void              Map_MappingReportChoices( Map_Man_t * pMan );
-/*=== mapperVec.c =============================================================*/
-extern Map_NodeVec_t *   Map_NodeVecAlloc( int nCap );
-extern void              Map_NodeVecFree( Map_NodeVec_t * p );
-extern Map_Node_t **     Map_NodeVecReadArray( Map_NodeVec_t * p );
-extern int               Map_NodeVecReadSize( Map_NodeVec_t * p );
-extern void              Map_NodeVecGrow( Map_NodeVec_t * p, int nCapMin );
-extern void              Map_NodeVecShrink( Map_NodeVec_t * p, int nSizeNew );
-extern void              Map_NodeVecClear( Map_NodeVec_t * p );
-extern void              Map_NodeVecPush( Map_NodeVec_t * p, Map_Node_t * Entry );
-extern int               Map_NodeVecPushUnique( Map_NodeVec_t * p, Map_Node_t * Entry );
-extern Map_Node_t *      Map_NodeVecPop( Map_NodeVec_t * p );
-extern void              Map_NodeVecRemove( Map_NodeVec_t * p, Map_Node_t * Entry );
-extern void              Map_NodeVecWriteEntry( Map_NodeVec_t * p, int i, Map_Node_t * Entry );
-extern Map_Node_t *      Map_NodeVecReadEntry( Map_NodeVec_t * p, int i );
-extern void              Map_NodeVecSortByLevel( Map_NodeVec_t * p );
-
-#endif
-
-////////////////////////////////////////////////////////////////////////
-///                       END OF FILE                                ///
-////////////////////////////////////////////////////////////////////////
diff --git a/abc70930/src/map/mapper/mapperLib.c b/abc70930/src/map/mapper/mapperLib.c
deleted file mode 100644
index d916487e..00000000
--- a/abc70930/src/map/mapper/mapperLib.c
+++ /dev/null
@@ -1,231 +0,0 @@
-/**CFile****************************************************************
-
-  FileName    [mapperLib.c]
-
-  PackageName [MVSIS 1.3: Multi-valued logic synthesis system.]
-
-  Synopsis    [Generic technology mapping engine.]
-
-  Author      [MVSIS Group]
-  
-  Affiliation [UC Berkeley]
-
-  Date        [Ver. 2.0. Started - June 1, 2004.]
-
-  Revision    [$Id: mapperLib.c,v 1.6 2005/01/23 06:59:44 alanmi Exp $]
-
-***********************************************************************/
-
-#include "mapperInt.h"
-
-////////////////////////////////////////////////////////////////////////
-///                        DECLARATIONS                              ///
-////////////////////////////////////////////////////////////////////////
-
-////////////////////////////////////////////////////////////////////////
-///                     FUNCTION DEFINITIONS                         ///
-////////////////////////////////////////////////////////////////////////
-
-/**Function*************************************************************
-
-  Synopsis    [Reads in the supergate library and prepares it for use.]
-
-  Description [The supergates library comes in a .super file. This file
-  contains descriptions of supergates along with some relevant information.
-  This procedure reads the supergate file, canonicizes the supergates,
-  and constructs an additional lookup table, which can be used to map
-  truth tables of the cuts into the pair (phase, supergate). The phase
-  indicates how the current truth table should be phase assigned to 
-  match the canonical form of the supergate. The resulting phase is the
-  bitwise EXOR of the phase needed to canonicize the supergate and the
-  phase needed to transform the truth table into its canonical form.]
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-Map_SuperLib_t * Map_SuperLibCreate( char * pFileName, char * pExcludeFile, bool fAlgorithm, bool fVerbose )
-{
-    Map_SuperLib_t * p;
-    int clk;
-
-    // start the supergate library
-    p = ALLOC( Map_SuperLib_t, 1 );
-    memset( p, 0, sizeof(Map_SuperLib_t) );
-    p->pName     = pFileName;
-    p->fVerbose  = fVerbose;
-    p->mmSupers  = Extra_MmFixedStart( sizeof(Map_Super_t) );
-    p->mmEntries = Extra_MmFixedStart( sizeof(Map_HashEntry_t) );
-    p->mmForms   = Extra_MmFlexStart();
-    Map_MappingSetupTruthTables( p->uTruths );
-
-    // start the hash table
-    p->tTableC = Map_SuperTableCreate( p );
-    p->tTable  = Map_SuperTableCreate( p );
-
-    // read the supergate library from file
-clk = clock();
-    if ( fAlgorithm )
-    {
-        if ( !Map_LibraryReadTree( p, pFileName, pExcludeFile ) )
-        {
-            Map_SuperLibFree( p );
-            return NULL;
-        }
-    }
-    else
-    {
-        if ( pExcludeFile != 0 )
-        {
-            printf ("Error: Exclude file support not present for old format. Stop.\n");
-            return NULL;
-        }
-        if ( !Map_LibraryRead( p, pFileName ) )
-        {
-            Map_SuperLibFree( p );
-            return NULL;
-        }
-    }
-    assert( p->nVarsMax > 0 );
-
-    // report the stats
-if ( fVerbose ) {
-    printf( "Loaded %d unique %d-input supergates from \"%s\".  ", 
-        p->nSupersReal, p->nVarsMax, pFileName );
-    PRT( "Time", clock() - clk );
-}
-
-    // assign the interver parameters
-    p->pGateInv        = Mio_LibraryReadInv( p->pGenlib );
-    p->tDelayInv.Rise  = Mio_LibraryReadDelayInvRise( p->pGenlib );
-    p->tDelayInv.Fall  = Mio_LibraryReadDelayInvFall( p->pGenlib );
-    p->tDelayInv.Worst = MAP_MAX( p->tDelayInv.Rise, p->tDelayInv.Fall );
-    p->AreaInv         = Mio_LibraryReadAreaInv( p->pGenlib );
-    p->AreaBuf         = Mio_LibraryReadAreaBuf( p->pGenlib );
-
-    // assign the interver supergate
-    p->pSuperInv = (Map_Super_t *)Extra_MmFixedEntryFetch( p->mmSupers );
-    memset( p->pSuperInv, 0, sizeof(Map_Super_t) );
-    p->pSuperInv->Num         = -1;
-    p->pSuperInv->nGates      =  1;
-    p->pSuperInv->nFanins     =  1;
-    p->pSuperInv->nFanLimit   = 10;
-    p->pSuperInv->pFanins[0]  = p->ppSupers[0];
-    p->pSuperInv->pRoot       = p->pGateInv;
-    p->pSuperInv->Area        = p->AreaInv;
-    p->pSuperInv->tDelayMax   = p->tDelayInv;
-    p->pSuperInv->tDelaysR[0].Rise = MAP_NO_VAR;
-    p->pSuperInv->tDelaysR[0].Fall = p->tDelayInv.Rise;
-    p->pSuperInv->tDelaysF[0].Rise = p->tDelayInv.Fall;
-    p->pSuperInv->tDelaysF[0].Fall = MAP_NO_VAR;
-    return p;
-}
-
-
-/**Function*************************************************************
-
-  Synopsis    [Deallocates the supergate library.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Map_SuperLibFree( Map_SuperLib_t * p )
-{
-    if ( p == NULL ) return;
-    if ( p->pGenlib )
-    {
-        assert( p->pGenlib == Abc_FrameReadLibGen() );
-        Mio_LibraryDelete( p->pGenlib );
-        Abc_FrameSetLibGen( NULL );
-    }
-    if ( p->tTableC )
-        Map_SuperTableFree( p->tTableC );
-    if ( p->tTable )
-        Map_SuperTableFree( p->tTable );
-    Extra_MmFixedStop( p->mmSupers );
-    Extra_MmFixedStop( p->mmEntries );
-    Extra_MmFlexStop( p->mmForms );
-    FREE( p->ppSupers );
-    FREE( p );
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Derives the library from the genlib library.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Map_SuperLibDeriveFromGenlib( Mio_Library_t * pLib )
-{
-    Abc_Frame_t * pAbc = Abc_FrameGetGlobalFrame();
-    char * pNameGeneric;
-    char FileNameGenlib[100];
-    char FileNameSuper[100];
-    char CommandSuper[500];
-    char CommandRead[500];
-    FILE * pFile;
-
-    if ( pLib == NULL )
-        return 0;
-
-    // write the current library into the file
-    sprintf( FileNameGenlib, "%s_temp", Mio_LibraryReadName(pLib) );
-    pFile = fopen( FileNameGenlib, "w" );
-    Mio_WriteLibrary( pFile, pLib, 0 );
-    fclose( pFile );
-
-    // get the file name with the library
-    pNameGeneric = Extra_FileNameGeneric( Mio_LibraryReadName(pLib) );
-    sprintf( FileNameSuper, "%s.super", pNameGeneric );
-    free( pNameGeneric );
-
-    sprintf( CommandSuper,  "super -l 1 -i 5 -d 10000000 -a 10000000 -t 100 %s", FileNameGenlib ); 
-    if ( Cmd_CommandExecute( pAbc, CommandSuper ) )
-    {
-        fprintf( stdout, "Cannot execute command \"%s\".\n", CommandSuper );
-        return 0;
-    }
-//#ifdef WIN32
-//        _unlink( FileNameGenlib );
-//#else
-//        unlink( FileNameGenlib );
-//#endif
-
-    sprintf( CommandRead,  "read_super %s", FileNameSuper ); 
-    if ( Cmd_CommandExecute( pAbc, CommandRead ) )
-    {
-#ifdef WIN32
-        _unlink( FileNameSuper );
-#else
-        unlink( FileNameSuper );
-#endif
-        fprintf( stdout, "Cannot execute command \"%s\".\n", CommandRead );
-        return 0;
-    }
-
-/* // don't remove the intermediate file
-#ifdef WIN32
-    _unlink( FileNameSuper );
-#else
-    unlink( FileNameSuper );
-#endif
-*/
-     return 1;
-}
-
-
-////////////////////////////////////////////////////////////////////////
-///                       END OF FILE                                ///
-////////////////////////////////////////////////////////////////////////
-
-
diff --git a/abc70930/src/map/mapper/mapperMatch.c b/abc70930/src/map/mapper/mapperMatch.c
deleted file mode 100644
index bfa72601..00000000
--- a/abc70930/src/map/mapper/mapperMatch.c
+++ /dev/null
@@ -1,596 +0,0 @@
-/**CFile****************************************************************
-
-  FileName    [mapperMatch.c]
-
-  PackageName [MVSIS 1.3: Multi-valued logic synthesis system.]
-
-  Synopsis    [Generic technology mapping engine.]
-
-  Author      [MVSIS Group]
-  
-  Affiliation [UC Berkeley]
-
-  Date        [Ver. 2.0. Started - June 1, 2004.]
-
-  Revision    [$Id: mapperMatch.c,v 1.7 2004/09/30 21:18:10 satrajit Exp $]
-
-***********************************************************************/
-
-#include "mapperInt.h"
-
-/*
-    A potential improvement:
-    When an internal node is not used in the mapping, its required times 
-    are set to be +infinity. So when we recover area, we try to find the 
-    best match for area and completely disregard the delay for the nodes
-    that are not currently used in the mapping because any match whose 
-    arrival times are less than the required times (+infinity) can be used.
-    It may be possible to develop a better approach to recover area for
-    the nodes that are not currently used in the mapping...
-*/
-
-////////////////////////////////////////////////////////////////////////
-///                        DECLARATIONS                              ///
-////////////////////////////////////////////////////////////////////////
-
-static int  Map_MatchNodePhase( Map_Man_t * p, Map_Node_t * pNode, int fPhase );
-static int  Map_MatchNodeCut( Map_Man_t * p, Map_Node_t * pNode, Map_Cut_t * pCut, int fPhase, float fWorstLimit );
-
-static void Map_MappingSetPiArrivalTimes( Map_Man_t * p );
-static void Map_NodeTryDroppingOnePhase( Map_Man_t * p, Map_Node_t * pNode );
-static void Map_NodeTransferArrivalTimes( Map_Man_t * p, Map_Node_t * pNode );
-
-////////////////////////////////////////////////////////////////////////
-///                     FUNCTION DEFINITIONS                         ///
-////////////////////////////////////////////////////////////////////////
-
-/**Function*************************************************************
-
-  Synopsis    [Computes the best matches of the nodes.]
-
-  Description [Uses parameter p->fMappingMode to decide how to assign
-  the matches for both polarities of the node. While the matches are 
-  being assigned, one of them may turn out to be better than the other 
-  (in terms of delay, for example). In this case, the worse match can 
-  be permanently dropped, and the corresponding pointer set to NULL.]
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Map_MappingMatches( Map_Man_t * p )
-{
-    ProgressBar * pProgress;
-    Map_Node_t * pNode;
-    int i;
-
-    assert( p->fMappingMode >= 0 && p->fMappingMode <= 4 );
-
-    // use the externally given PI arrival times
-    if ( p->fMappingMode == 0 )
-        Map_MappingSetPiArrivalTimes( p );
-
-    // estimate the fanouts
-    if ( p->fMappingMode == 0 )
-        Map_MappingEstimateRefsInit( p );
-    else if ( p->fMappingMode == 1 )
-        Map_MappingEstimateRefs( p );
-
-    // the PI cuts are matched in the cut computation package
-    // in the loop below we match the internal nodes
-    pProgress = Extra_ProgressBarStart( stdout, p->vAnds->nSize );
-    for ( i = 0; i < p->vAnds->nSize; i++ )
-    {
-        // skip primary inputs and secondary nodes if mapping with choices
-        pNode = p->vAnds->pArray[i];
-        if ( !Map_NodeIsAnd( pNode ) || pNode->pRepr )
-            continue;
-
-        // make sure that at least one non-trival cut is present
-        if ( pNode->pCuts->pNext == NULL )
-        {
-            printf( "\nError: A node in the mapping graph does not have feasible cuts.\n" );
-            return 0;
-        }
-
-        // match negative phase
-        if ( !Map_MatchNodePhase( p, pNode, 0 ) )
-            return 0;
-        // match positive phase
-        if ( !Map_MatchNodePhase( p, pNode, 1 ) )
-            return 0;
-
-        // make sure that at least one phase is mapped
-        if ( pNode->pCutBest[0] == NULL && pNode->pCutBest[1] == NULL )
-        {
-            printf( "\nError: Could not match both phases of AIG node %d.\n", pNode->Num );
-            printf( "Please make sure that the supergate library has equivalents of AND2 or NAND2.\n" );
-            printf( "If such supergates exist in the library, report a bug.\n" );
-            return 0;
-        }
-
-        // if both phases are assigned, check if one of them can be dropped
-        Map_NodeTryDroppingOnePhase( p, pNode );
-        // set the arrival times of the node using the best cuts
-        Map_NodeTransferArrivalTimes( p, pNode );
-
-        // update the progress bar
-        Extra_ProgressBarUpdate( pProgress, i, "Matches ..." );
-    }
-    Extra_ProgressBarStop( pProgress );
-    return 1;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Find the matching of one polarity of the node.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Map_MatchNodePhase( Map_Man_t * p, Map_Node_t * pNode, int fPhase )
-{
-    Map_Match_t MatchBest, * pMatch;
-    Map_Cut_t * pCut, * pCutBest;
-    float Area1, Area2, fWorstLimit;
-
-    // skip the cuts that have been unassigned during area recovery
-    pCutBest = pNode->pCutBest[fPhase];
-    if ( p->fMappingMode != 0 && pCutBest == NULL )
-        return 1;
-
-    // recompute the arrival times of the current best match 
-    // because the arrival times of the fanins may have changed 
-    // as a result of remapping fanins in the topological order
-    if ( p->fMappingMode != 0 )
-    {
-        Map_TimeCutComputeArrival( pNode, pCutBest, fPhase, MAP_FLOAT_LARGE );
-        // make sure that the required times are met
-        assert( pCutBest->M[fPhase].tArrive.Rise < pNode->tRequired[fPhase].Rise + p->fEpsilon );
-        assert( pCutBest->M[fPhase].tArrive.Fall < pNode->tRequired[fPhase].Fall + p->fEpsilon );
-    }
-
-    // recompute the exact area of the current best match
-    // because the exact area of the fanins may have changed
-    // as a result of remapping fanins in the topological order
-    if ( p->fMappingMode == 2 || p->fMappingMode == 3 )
-    {
-        pMatch = pCutBest->M + fPhase;
-        if ( pNode->nRefAct[fPhase] > 0 || 
-            (pNode->pCutBest[!fPhase] == NULL && pNode->nRefAct[!fPhase] > 0) )
-            pMatch->AreaFlow = Area1 = Map_CutDeref( pCutBest, fPhase );
-        else
-            pMatch->AreaFlow = Area1 = Map_CutGetAreaDerefed( pCutBest, fPhase );
-    }
-    else if ( p->fMappingMode == 4 )
-    {
-        pMatch = pCutBest->M + fPhase;
-        if ( pNode->nRefAct[fPhase] > 0 || 
-            (pNode->pCutBest[!fPhase] == NULL && pNode->nRefAct[!fPhase] > 0) )
-            pMatch->AreaFlow = Area1 = Map_SwitchCutDeref( pNode, pCutBest, fPhase );
-        else
-            pMatch->AreaFlow = Area1 = Map_SwitchCutGetDerefed( pNode, pCutBest, fPhase );
-    }
-
-    // save the old mapping
-    if ( pCutBest )
-        MatchBest = pCutBest->M[fPhase];
-    else
-        Map_MatchClean( &MatchBest );
- 
-    // select the new best cut
-    fWorstLimit = pNode->tRequired[fPhase].Worst;
-    for ( pCut = pNode->pCuts->pNext; pCut; pCut = pCut->pNext )
-    {
-        pMatch = pCut->M + fPhase;
-        if ( pMatch->pSupers == NULL )
-            continue;
-
-        // find the matches for the cut
-        Map_MatchNodeCut( p, pNode, pCut, fPhase, fWorstLimit );
-        if ( pMatch->pSuperBest == NULL || pMatch->tArrive.Worst > fWorstLimit + p->fEpsilon )
-            continue;
-
-        // if the cut can be matched compare the matchings
-        if ( Map_MatchCompare( p, &MatchBest, pMatch, p->fMappingMode ) )
-        {
-            pCutBest  =  pCut;
-            MatchBest = *pMatch;
-            // if we are mapping for delay, the worst-case limit should be tightened
-            if ( p->fMappingMode == 0 )
-                fWorstLimit = MatchBest.tArrive.Worst;
-        }
-    }
-
-    if ( pCutBest == NULL )
-        return 1;
-
-    // set the new mapping
-    pNode->pCutBest[fPhase] = pCutBest;
-    pCutBest->M[fPhase]     = MatchBest;
-
-    // reference the new cut if it used
-    if ( p->fMappingMode >= 2 && 
-         (pNode->nRefAct[fPhase] > 0 || 
-         (pNode->pCutBest[!fPhase] == NULL && pNode->nRefAct[!fPhase] > 0)) )
-    {
-        if ( p->fMappingMode == 2 || p->fMappingMode == 3 )
-            Area2 = Map_CutRef( pNode->pCutBest[fPhase], fPhase );
-        else if ( p->fMappingMode == 4 )
-            Area2 = Map_SwitchCutRef( pNode, pNode->pCutBest[fPhase], fPhase );
-        else 
-            assert( 0 );
-        assert( Area2 < Area1 + p->fEpsilon );
-    }
-
-    // make sure that the requited times are met
-    assert( MatchBest.tArrive.Rise < pNode->tRequired[fPhase].Rise + p->fEpsilon );
-    assert( MatchBest.tArrive.Fall < pNode->tRequired[fPhase].Fall + p->fEpsilon );
-    return 1;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Find the best matching of the cut.]
-
-  Description [The parameters: the node (pNode), the cut (pCut), the phase to be matched 
-  (fPhase), and the upper bound on the arrival times of the cut (fWorstLimit). This 
-  procedure goes through the matching supergates up to the phase assignment, and selects the
-  best supergate, which will be used to map the cut. As a result of calling this procedure
-  the matching information is written into pMatch.]
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Map_MatchNodeCut( Map_Man_t * p, Map_Node_t * pNode, Map_Cut_t * pCut, int fPhase, float fWorstLimit )
-{
-    Map_Match_t MatchBest, * pMatch = pCut->M + fPhase;
-    Map_Super_t * pSuper;
-    int i, Counter;
-
-    // save the current match of the cut
-    MatchBest = *pMatch;
-    // go through the supergates
-    for ( pSuper = pMatch->pSupers, Counter = 0; pSuper; pSuper = pSuper->pNext, Counter++ )
-    {
-        p->nMatches++;
-        // this is an attempt to reduce the runtime of matching and area 
-        // at the cost of rare and very minor increase in delay
-        // (the supergates are sorted by increasing area)
-        if ( Counter == 30 )
-           break;
-
-        // go through different phases of the given match and supergate
-        pMatch->pSuperBest = pSuper;
-        for ( i = 0; i < (int)pSuper->nPhases; i++ )
-        {
-            p->nPhases++;
-            // find the overall phase of this match
-            pMatch->uPhaseBest = pMatch->uPhase ^ pSuper->uPhases[i];
-            if ( p->fMappingMode == 0 )
-            {
-                // get the arrival time
-                Map_TimeCutComputeArrival( pNode, pCut, fPhase, fWorstLimit );
-                // skip the cut if the arrival times exceed the required times
-                if ( pMatch->tArrive.Worst > fWorstLimit + p->fEpsilon )
-                    continue;
-                // get the area (area flow)
-                pMatch->AreaFlow = Map_CutGetAreaFlow( pCut, fPhase );
-            }
-            else
-            {
-                // get the area (area flow)
-                if ( p->fMappingMode == 2 || p->fMappingMode == 3 )
-                    pMatch->AreaFlow = Map_CutGetAreaDerefed( pCut, fPhase );
-                else if ( p->fMappingMode == 4 )
-                    pMatch->AreaFlow = Map_SwitchCutGetDerefed( pNode, pCut, fPhase );
-                else 
-                    pMatch->AreaFlow = Map_CutGetAreaFlow( pCut, fPhase );
-                // skip if the cut is too large
-                if ( pMatch->AreaFlow > MatchBest.AreaFlow + p->fEpsilon )
-                    continue;
-                // get the arrival time
-                Map_TimeCutComputeArrival( pNode, pCut, fPhase, fWorstLimit );
-                // skip the cut if the arrival times exceed the required times
-                if ( pMatch->tArrive.Worst > fWorstLimit + p->fEpsilon )
-                    continue;
-            }
-
-            // if the cut is non-trivial, compare it
-            if ( Map_MatchCompare( p, &MatchBest, pMatch, p->fMappingMode ) )
-            {
-                MatchBest = *pMatch;
-                // if we are mapping for delay, the worst-case limit should be reduced
-                if ( p->fMappingMode == 0 )
-                    fWorstLimit = MatchBest.tArrive.Worst;
-            }
-        }
-    }
-    // set the best match
-    *pMatch = MatchBest;
-
-    // recompute the arrival time and area (area flow) of this cut
-    if ( pMatch->pSuperBest )
-    {
-        Map_TimeCutComputeArrival( pNode, pCut, fPhase, MAP_FLOAT_LARGE );
-        if ( p->fMappingMode == 2 || p->fMappingMode == 3 )
-            pMatch->AreaFlow = Map_CutGetAreaDerefed( pCut, fPhase );
-        else if ( p->fMappingMode == 4 )
-            pMatch->AreaFlow = Map_SwitchCutGetDerefed( pNode, pCut, fPhase );
-        else 
-            pMatch->AreaFlow = Map_CutGetAreaFlow( pCut, fPhase );
-    }
-    return 1;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Cleans the match.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Map_MatchClean( Map_Match_t * pMatch )
-{
-    memset( pMatch, 0, sizeof(Map_Match_t) );
-    pMatch->AreaFlow          = MAP_FLOAT_LARGE; // unassigned
-    pMatch->tArrive.Rise   = MAP_FLOAT_LARGE; // unassigned
-    pMatch->tArrive.Fall   = MAP_FLOAT_LARGE; // unassigned
-    pMatch->tArrive.Worst  = MAP_FLOAT_LARGE; // unassigned
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Compares two matches.]
-
-  Description [Returns 1 if the second match is better. Otherwise returns 0.]
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Map_MatchCompare( Map_Man_t * pMan, Map_Match_t * pM1, Map_Match_t * pM2, int fDoingArea )
-{
-    if ( !fDoingArea )
-    {
-        // compare the arrival times
-        if ( pM1->tArrive.Worst < pM2->tArrive.Worst - pMan->fEpsilon )
-            return 0;
-        if ( pM1->tArrive.Worst > pM2->tArrive.Worst + pMan->fEpsilon )
-            return 1;
-        // compare the areas or area flows
-        if ( pM1->AreaFlow < pM2->AreaFlow - pMan->fEpsilon )
-            return 0;
-        if ( pM1->AreaFlow > pM2->AreaFlow + pMan->fEpsilon )
-            return 1;
-        // compare the fanout limits
-        if ( pM1->pSuperBest->nFanLimit > pM2->pSuperBest->nFanLimit )
-            return 0;
-        if ( pM1->pSuperBest->nFanLimit < pM2->pSuperBest->nFanLimit )
-            return 1;
-        // compare the number of leaves
-        if ( pM1->pSuperBest->nFanins < pM2->pSuperBest->nFanins )
-            return 0;
-        if ( pM1->pSuperBest->nFanins > pM2->pSuperBest->nFanins )
-            return 1;
-        // otherwise prefer the old cut
-        return 0;
-    }
-    else
-    {
-        // compare the areas or area flows
-        if ( pM1->AreaFlow < pM2->AreaFlow - pMan->fEpsilon )
-            return 0;
-        if ( pM1->AreaFlow > pM2->AreaFlow + pMan->fEpsilon )
-            return 1;
-        // compare the arrival times
-        if ( pM1->tArrive.Worst < pM2->tArrive.Worst - pMan->fEpsilon )
-            return 0;
-        if ( pM1->tArrive.Worst > pM2->tArrive.Worst + pMan->fEpsilon )
-            return 1;
-        // compare the fanout limits
-        if ( pM1->pSuperBest->nFanLimit > pM2->pSuperBest->nFanLimit )
-            return 0;
-        if ( pM1->pSuperBest->nFanLimit < pM2->pSuperBest->nFanLimit )
-            return 1;
-        // compare the number of leaves
-        if ( pM1->pSuperBest->nFanins < pM2->pSuperBest->nFanins )
-            return 0;
-        if ( pM1->pSuperBest->nFanins > pM2->pSuperBest->nFanins )
-            return 1;
-        // otherwise prefer the old cut
-        return 0;
-    }
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Sets the PI arrival times.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Map_MappingSetPiArrivalTimes( Map_Man_t * p )
-{
-    Map_Node_t * pNode;
-    int i;
-    for ( i = 0; i < p->nInputs; i++ )
-    {
-        pNode = p->pInputs[i];
-        // set the arrival time of the positive phase
-        pNode->tArrival[1] = p->pInputArrivals[i];
-        // set the arrival time of the negative phase
-        pNode->tArrival[0].Rise  = pNode->tArrival[1].Fall + p->pSuperLib->tDelayInv.Rise;
-        pNode->tArrival[0].Fall  = pNode->tArrival[1].Rise + p->pSuperLib->tDelayInv.Fall;
-        pNode->tArrival[0].Worst = MAP_MAX(pNode->tArrival[0].Rise, pNode->tArrival[0].Fall);
-    }
-}
-
-
-/**Function*************************************************************
-
-  Synopsis    [Attempts dropping one phase of the node.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Map_NodeTryDroppingOnePhase( Map_Man_t * p, Map_Node_t * pNode )
-{
-    Map_Match_t * pMatchBest0, * pMatchBest1;
-    float tWorst0Using1, tWorst1Using0; 
-    int fUsePhase1, fUsePhase0;
-
-    // nothing to do if one of the phases is already dropped
-    if ( pNode->pCutBest[0] == NULL || pNode->pCutBest[1] == NULL )
-        return;
-
-    // do not drop while recovering area flow
-    if ( p->fMappingMode == 1 )//|| p->fMappingMode == 2 )
-        return;
-
-    // get the pointers to the matches of the best cuts
-    pMatchBest0 = pNode->pCutBest[0]->M + 0;
-    pMatchBest1 = pNode->pCutBest[1]->M + 1;
-
-    // get the worst arrival times of each phase
-    // implemented using the other phase with inverter added
-    tWorst0Using1 = Map_TimeMatchWithInverter( p, pMatchBest1 );
-    tWorst1Using0 = Map_TimeMatchWithInverter( p, pMatchBest0 );
-
-    // consider the case of mapping for delay
-    if ( p->fMappingMode == 0 )
-    { 
-        // if the arrival time of a phase is larger than the arrival time 
-        // of the opposite phase plus the inverter, drop this phase
-        if ( pMatchBest0->tArrive.Worst > tWorst0Using1 + p->fEpsilon ) 
-            pNode->pCutBest[0] = NULL;
-        else if ( pMatchBest1->tArrive.Worst > tWorst1Using0 + p->fEpsilon ) 
-            pNode->pCutBest[1] = NULL;
-        return;
-    }
-
-    // do not perform replacement if one of the phases is unused
-    if ( pNode->nRefAct[0] == 0 || pNode->nRefAct[1] == 0 )
-        return;
- 
-    // check if replacement of each phase is possible using required times
-    fUsePhase0 = fUsePhase1 = 0;
-    if ( p->fMappingMode == 2 )
-    {
-        fUsePhase0 = (pNode->tRequired[1].Worst > tWorst1Using0 + 3*p->pSuperLib->tDelayInv.Worst + p->fEpsilon);
-        fUsePhase1 = (pNode->tRequired[0].Worst > tWorst0Using1 + 3*p->pSuperLib->tDelayInv.Worst + p->fEpsilon);
-    }
-    else if ( p->fMappingMode == 3 || p->fMappingMode == 4 )
-    {
-        fUsePhase0 = (pNode->tRequired[1].Worst > tWorst1Using0 + p->fEpsilon);
-        fUsePhase1 = (pNode->tRequired[0].Worst > tWorst0Using1 + p->fEpsilon);
-    }
-    if ( !fUsePhase0 && !fUsePhase1 )
-        return;
-
-    // if replacement is possible both ways, use the one that works better
-    if ( fUsePhase0 && fUsePhase1 )
-    {
-        if ( pMatchBest0->AreaFlow < pMatchBest1->AreaFlow )
-            fUsePhase1 = 0;
-        else
-            fUsePhase0 = 0;
-    }
-    // only one phase should be used
-    assert( fUsePhase0 ^ fUsePhase1 );
-
-    // set the corresponding cut to NULL
-    if ( fUsePhase0 )
-    {
-        // deref phase 1 cut if necessary
-        if ( p->fMappingMode >= 2 && pNode->nRefAct[1] > 0 )
-            Map_CutDeref( pNode->pCutBest[1], 1 );
-        // get rid of the cut
-        pNode->pCutBest[1] = NULL;
-        // ref phase 0 cut if necessary
-        if ( p->fMappingMode >= 2 && pNode->nRefAct[0] == 0 )
-            Map_CutRef( pNode->pCutBest[0], 0 );
-    }
-    else
-    {
-        // deref phase 0 cut if necessary
-        if ( p->fMappingMode >= 2 && pNode->nRefAct[0] > 0 )
-            Map_CutDeref( pNode->pCutBest[0], 0 );
-        // get rid of the cut
-        pNode->pCutBest[0] = NULL;
-        // ref phase 1 cut if necessary
-        if ( p->fMappingMode >= 2 && pNode->nRefAct[1] == 0 )
-            Map_CutRef( pNode->pCutBest[1], 1 );
-    }
-}
-
-
-/**Function*************************************************************
-
-  Synopsis    [Transfers the arrival times from the best cuts to the node.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Map_NodeTransferArrivalTimes( Map_Man_t * p, Map_Node_t * pNode )
-{
-    // if both phases are available, set their arrival times
-    if ( pNode->pCutBest[0] && pNode->pCutBest[1] )
-    {
-        pNode->tArrival[0] = pNode->pCutBest[0]->M[0].tArrive;
-        pNode->tArrival[1] = pNode->pCutBest[1]->M[1].tArrive;
-    }
-    // if only one phase is available, compute the arrival time of other phase
-    else if ( pNode->pCutBest[0] )
-    {
-        pNode->tArrival[0] = pNode->pCutBest[0]->M[0].tArrive;
-        pNode->tArrival[1].Rise  = pNode->tArrival[0].Fall + p->pSuperLib->tDelayInv.Rise;
-        pNode->tArrival[1].Fall  = pNode->tArrival[0].Rise + p->pSuperLib->tDelayInv.Fall;
-        pNode->tArrival[1].Worst = MAP_MAX(pNode->tArrival[1].Rise, pNode->tArrival[1].Fall);
-    }
-    else if ( pNode->pCutBest[1] )
-    {
-        pNode->tArrival[1] = pNode->pCutBest[1]->M[1].tArrive;
-        pNode->tArrival[0].Rise  = pNode->tArrival[1].Fall + p->pSuperLib->tDelayInv.Rise;
-        pNode->tArrival[0].Fall  = pNode->tArrival[1].Rise + p->pSuperLib->tDelayInv.Fall;
-        pNode->tArrival[0].Worst = MAP_MAX(pNode->tArrival[0].Rise, pNode->tArrival[0].Fall);
-    }
-    else 
-    {
-        assert( 0 );
-    }
-
-    assert( pNode->tArrival[0].Rise < pNode->tRequired[0].Rise + p->fEpsilon );
-    assert( pNode->tArrival[0].Fall < pNode->tRequired[0].Fall + p->fEpsilon );
-
-    assert( pNode->tArrival[1].Rise < pNode->tRequired[1].Rise + p->fEpsilon );
-    assert( pNode->tArrival[1].Fall < pNode->tRequired[1].Fall + p->fEpsilon );
-}
-
-////////////////////////////////////////////////////////////////////////
-///                       END OF FILE                                ///
-////////////////////////////////////////////////////////////////////////
diff --git a/abc70930/src/map/mapper/mapperRefs.c b/abc70930/src/map/mapper/mapperRefs.c
deleted file mode 100644
index a50b134a..00000000
--- a/abc70930/src/map/mapper/mapperRefs.c
+++ /dev/null
@@ -1,557 +0,0 @@
-/**CFile****************************************************************
-
-  FileName    [mapperRefs.c]
-
-  PackageName [MVSIS 1.3: Multi-valued logic synthesis system.]
-
-  Synopsis    [Generic technology mapping engine.]
-
-  Author      [MVSIS Group]
-  
-  Affiliation [UC Berkeley]
-
-  Date        [Ver. 2.0. Started - June 1, 2004.]
-
-  Revision    [$Id: mapperRefs.h,v 1.0 2003/09/08 00:00:00 alanmi Exp $]
-
-***********************************************************************/
-
-#include "mapperInt.h"
-
-////////////////////////////////////////////////////////////////////////
-///                        DECLARATIONS                              ///
-////////////////////////////////////////////////////////////////////////
-
-static int   Map_NodeIncRefPhaseAct( Map_Node_t * pNode, int fPhase );
-static int   Map_NodeDecRefPhaseAct( Map_Node_t * pNode, int fPhase );
-static float Map_CutRefDeref( Map_Cut_t * pCut, int fPhase, int fReference );
-static void  Map_MappingSetRefs_rec( Map_Man_t * pMan, Map_Node_t * pNode, Map_Node_t ** ppStore );
-
-////////////////////////////////////////////////////////////////////////
-///                     FUNCTION DEFINITIONS                         ///
-////////////////////////////////////////////////////////////////////////
-
-/**Function*************************************************************
-
-  Synopsis    [Reads the actual reference counter of a phase.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Map_NodeReadRefPhaseAct( Map_Node_t * pNode, int fPhase )
-{
-    assert( !Map_IsComplement(pNode) );
-    if ( pNode->pCutBest[0] && pNode->pCutBest[1] ) // both assigned
-        return pNode->nRefAct[fPhase];
-    assert( pNode->pCutBest[0] || pNode->pCutBest[1] ); // at least one assigned
-    return pNode->nRefAct[2];
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Reads the estimated reference counter of a phase.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-float Map_NodeReadRefPhaseEst( Map_Node_t * pNode, int fPhase )
-{
-    assert( !Map_IsComplement(pNode) );
-    if ( pNode->pCutBest[0] && pNode->pCutBest[1] ) // both assigned
-        return pNode->nRefEst[fPhase];
-    assert( pNode->pCutBest[0] || pNode->pCutBest[1] ); // at least one assigned
-//    return pNode->nRefEst[0] + pNode->nRefEst[1];
-    return pNode->nRefEst[2];
-}
-
-
-/**Function*************************************************************
-
-  Synopsis    [Increments the actual reference counter of a phase.]
-
-  Description [Returns the old reference counter.]
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Map_NodeIncRefPhaseAct( Map_Node_t * pNode, int fPhase )
-{
-    assert( !Map_IsComplement(pNode) );
-    if ( pNode->pCutBest[0] && pNode->pCutBest[1] ) // both assigned
-        return pNode->nRefAct[fPhase]++;
-    assert( pNode->pCutBest[0] || pNode->pCutBest[1] ); // at least one assigned
-    return pNode->nRefAct[2]++;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Decrements the actual reference counter of a phase.]
-
-  Description [Returns the new reference counter.]
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Map_NodeDecRefPhaseAct( Map_Node_t * pNode, int fPhase )
-{
-    assert( !Map_IsComplement(pNode) );
-    if ( pNode->pCutBest[0] && pNode->pCutBest[1] ) // both assigned
-        return --pNode->nRefAct[fPhase];
-    assert( pNode->pCutBest[0] || pNode->pCutBest[1] ); // at least one assigned
-    return --pNode->nRefAct[2];
-}
-
-
-/**Function*************************************************************
-
-  Synopsis    [Sets the estimated reference counter for the PIs.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Map_MappingEstimateRefsInit( Map_Man_t * p )
-{
-    Map_Node_t * pNode;
-    int i;
-    for ( i = 0; i < p->vAnds->nSize; i++ )
-    {
-        pNode = p->vAnds->pArray[i];
-//        pNode->nRefEst[0] = pNode->nRefEst[1] = ((float)pNode->nRefs)*(float)2.0;
-        pNode->nRefEst[0] = pNode->nRefEst[1] = pNode->nRefEst[2] = ((float)pNode->nRefs);
-    }
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Sets the estimated reference counter.]
-
-  Description [When this procedure is called for the first time,
-  the reference counter is estimated from the AIG. Otherwise, it is
-  a linear combination of reference counters in the last two iterations.]
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Map_MappingEstimateRefs( Map_Man_t * p )
-{
-    Map_Node_t * pNode;
-    int i;
-    for ( i = 0; i < p->vAnds->nSize; i++ )
-    {
-        pNode = p->vAnds->pArray[i];
-//        pNode->nRefEst[0] = (float)((2.0 * pNode->nRefEst[0] + 1.0 * pNode->nRefAct[0]) / 3.0);
-//        pNode->nRefEst[1] = (float)((2.0 * pNode->nRefEst[1] + 1.0 * pNode->nRefAct[1]) / 3.0);
-//        pNode->nRefEst[2] = (float)((2.0 * pNode->nRefEst[2] + 1.0 * pNode->nRefAct[2]) / 3.0);
-        pNode->nRefEst[0] = (float)((3.0 * pNode->nRefEst[0] + 1.0 * pNode->nRefAct[0]) / 4.0);
-        pNode->nRefEst[1] = (float)((3.0 * pNode->nRefEst[1] + 1.0 * pNode->nRefAct[1]) / 4.0);
-        pNode->nRefEst[2] = (float)((3.0 * pNode->nRefEst[2] + 1.0 * pNode->nRefAct[2]) / 4.0);
-    }
-}
-
-
-
-
-
-/**function*************************************************************
-
-  synopsis    [Computes the area flow of the cut.]
-
-  description [Computes the area flow of the cut if it is implemented using 
-  the best supergate with the best phase.]
-               
-  sideeffects []
-
-  seealso     []
-
-***********************************************************************/
-float Map_CutGetAreaFlow( Map_Cut_t * pCut, int fPhase )
-{
-    Map_Match_t * pM = pCut->M + fPhase;
-    Map_Super_t * pSuper = pM->pSuperBest;
-    unsigned uPhaseTot = pM->uPhaseBest;
-    Map_Cut_t * pCutFanin;
-    float aFlowRes, aFlowFanin, nRefs;
-    int i, fPinPhasePos;
-
-    // start the resulting area flow
-    aFlowRes = pSuper->Area;
-    // iterate through the leaves
-    for ( i = 0; i < pCut->nLeaves; i++ )
-    {
-        // get the phase of this fanin
-        fPinPhasePos = ((uPhaseTot & (1 << i)) == 0);
-        // get the cut implementing this phase of the fanin
-        pCutFanin = pCut->ppLeaves[i]->pCutBest[fPinPhasePos];
-        // if the cut is not available, we have to use the opposite phase
-        if ( pCutFanin == NULL )
-        {
-            fPinPhasePos = !fPinPhasePos;
-            pCutFanin = pCut->ppLeaves[i]->pCutBest[fPinPhasePos];
-        }
-        aFlowFanin = pCutFanin->M[fPinPhasePos].AreaFlow; // ignores the area of the interter
-        // get the fanout count of the cut in the given phase
-        nRefs = Map_NodeReadRefPhaseEst( pCut->ppLeaves[i], fPinPhasePos );
-        // if the node does no fanout, assume fanout count equal to 1
-        if ( nRefs == (float)0.0 )
-            nRefs = (float)1.0;
-        // add the area flow due to the fanin
-        aFlowRes += aFlowFanin / nRefs;
-    }
-    pM->AreaFlow = aFlowRes;
-    return aFlowRes;
-}
-
-
-
-/**function*************************************************************
-
-  synopsis    [Computes the exact area associated with the cut.]
-
-  description [Assumes that the cut is referenced.]
-               
-  sideeffects []
-
-  seealso     []
-
-***********************************************************************/
-float Map_CutGetAreaRefed( Map_Cut_t * pCut, int fPhase )
-{
-    float aResult, aResult2;
-    aResult2 = Map_CutRefDeref( pCut, fPhase, 0 ); // dereference
-    aResult  = Map_CutRefDeref( pCut, fPhase, 1 ); // reference
-//    assert( aResult == aResult2 );
-    return aResult;
-}
-
-/**function*************************************************************
-
-  synopsis    [Computes the exact area associated with the cut.]
-
-  description []
-               
-  sideeffects []
-
-  seealso     []
-
-***********************************************************************/
-float Map_CutGetAreaDerefed( Map_Cut_t * pCut, int fPhase )
-{
-    float aResult, aResult2;
-    aResult2 = Map_CutRefDeref( pCut, fPhase, 1 ); // reference
-    aResult  = Map_CutRefDeref( pCut, fPhase, 0 ); // dereference
-//    assert( aResult == aResult2 );
-    return aResult;
-}
-
-/**function*************************************************************
-
-  synopsis    [References the cut.]
-
-  description []
-               
-  sideeffects []
-
-  seealso     []
-
-***********************************************************************/
-float Map_CutRef( Map_Cut_t * pCut, int fPhase )
-{
-    return Map_CutRefDeref( pCut, fPhase, 1 ); // reference
-}
-
-/**function*************************************************************
-
-  synopsis    [Dereferences the cut.]
-
-  description []
-               
-  sideeffects []
-
-  seealso     []
-
-***********************************************************************/
-float Map_CutDeref( Map_Cut_t * pCut, int fPhase )
-{
-    return Map_CutRefDeref( pCut, fPhase, 0 ); // dereference
-}
-
-/**function*************************************************************
-
-  synopsis    [References or dereferences the cut.]
-
-  description [This reference part is similar to Cudd_NodeReclaim(). 
-  The dereference part is similar to Cudd_RecursiveDeref().]
-               
-  sideeffects []
-
-  seealso     []
-
-***********************************************************************/
-float Map_CutRefDeref( Map_Cut_t * pCut, int fPhase, int fReference )
-{
-    Map_Node_t * pNodeChild;
-    Map_Cut_t * pCutChild;
-    float aArea;
-    int i, fPhaseChild;
-//    int nRefs;
-
-    // consider the elementary variable
-    if ( pCut->nLeaves == 1 )
-        return 0;
-    // start the area of this cut
-    aArea = Map_CutGetRootArea( pCut, fPhase );
-    // go through the children
-    for ( i = 0; i < pCut->nLeaves; i++ )
-    {
-        pNodeChild  = pCut->ppLeaves[i];
-        fPhaseChild = Map_CutGetLeafPhase( pCut, fPhase, i );
-        // get the reference counter of the child
-/*
-        // this code does not take inverters into account
-        // the quality of area recovery seems to always be a little worse
-        if ( fReference )
-            nRefs = Map_NodeIncRefPhaseAct( pNodeChild, fPhaseChild );
-        else
-            nRefs = Map_NodeDecRefPhaseAct( pNodeChild, fPhaseChild );
-        assert( nRefs >= 0 );
-        // skip if the child was already reference before
-        if ( nRefs > 0 )
-            continue;
-*/
-
-        if ( fReference )
-        {
-            if ( pNodeChild->pCutBest[0] && pNodeChild->pCutBest[1] ) // both phases are present
-            {
-                // if this phase of the node is referenced, there is no recursive call
-                pNodeChild->nRefAct[2]++;
-                if ( pNodeChild->nRefAct[fPhaseChild]++ > 0 )
-                    continue;
-            }
-            else // only one phase is present
-            {
-                // inverter should be added if the phase
-                // (a) has no reference and (b) is implemented using other phase
-                if ( pNodeChild->nRefAct[fPhaseChild]++ == 0 && pNodeChild->pCutBest[fPhaseChild] == NULL )
-                    aArea += pNodeChild->p->pSuperLib->AreaInv;
-                // if the node is referenced, there is no recursive call
-                if ( pNodeChild->nRefAct[2]++ > 0 )
-                    continue;
-            }
-        }
-        else
-        {
-            if ( pNodeChild->pCutBest[0] && pNodeChild->pCutBest[1] ) // both phases are present
-            {
-                // if this phase of the node is referenced, there is no recursive call
-                --pNodeChild->nRefAct[2];
-                if ( --pNodeChild->nRefAct[fPhaseChild] > 0 )
-                    continue;
-            }
-            else // only one phase is present
-            {
-                // inverter should be added if the phase
-                // (a) has no reference and (b) is implemented using other phase
-                if ( --pNodeChild->nRefAct[fPhaseChild] == 0 && pNodeChild->pCutBest[fPhaseChild] == NULL )
-                    aArea += pNodeChild->p->pSuperLib->AreaInv;
-                // if the node is referenced, there is no recursive call
-                if ( --pNodeChild->nRefAct[2] > 0 )
-                    continue;
-            }
-            assert( pNodeChild->nRefAct[fPhaseChild] >= 0 );
-        }
-
-        // get the child cut
-        pCutChild = pNodeChild->pCutBest[fPhaseChild];
-        // if the child does not have this phase mapped, take the opposite phase
-        if ( pCutChild == NULL )
-        {
-            fPhaseChild = !fPhaseChild;
-            pCutChild   = pNodeChild->pCutBest[fPhaseChild];
-        }
-        // reference and compute area recursively
-        aArea += Map_CutRefDeref( pCutChild, fPhaseChild, fReference );
-    }
-    return aArea;
-}
-
-
-
-
-/**Function*************************************************************
-
-  Synopsis    [Computes actual reference counters.]
-
-  Description [Collects the nodes used in the mapping in array pMan->vMapping.
-  Nodes are collected in reverse topological order to facilitate the 
-  computation of required times.]
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Map_MappingSetRefs( Map_Man_t * pMan )
-{
-    Map_Node_t * pNode, ** ppStore;
-    int i, fPhase, LevelMax;
-
-    // clean all references
-    for ( i = 0; i < pMan->vNodesAll->nSize; i++ )
-    {
-        pNode = pMan->vNodesAll->pArray[i];
-        pNode->nRefAct[0] = 0;
-        pNode->nRefAct[1] = 0;
-        pNode->nRefAct[2] = 0;
-    }
-
-    // find the largest level of a node
-    LevelMax = 0;
-    for ( i = 0; i < pMan->nOutputs; i++ )
-        if ( LevelMax < (int)Map_Regular(pMan->pOutputs[i])->Level )
-            LevelMax = Map_Regular(pMan->pOutputs[i])->Level;
-
-    // allocate place to store the nodes
-    ppStore = ALLOC( Map_Node_t *, LevelMax + 1 );
-    memset( ppStore, 0, sizeof(Map_Node_t *) * (LevelMax + 1) );
-
-    // visit nodes reachable from POs in the DFS order through the best cuts
-    for ( i = 0; i < pMan->nOutputs; i++ )
-    {
-        pNode  = pMan->pOutputs[i];
-        fPhase = !Map_IsComplement(pNode);
-        if ( !Map_NodeIsConst(pNode) )
-            Map_MappingSetRefs_rec( pMan, pNode, ppStore );
-    }
-
-    // reconnect the nodes in reverse topological order
-    pMan->vMapping->nSize = 0;
-    for ( i = LevelMax; i >= 0; i-- )
-        for ( pNode = ppStore[i]; pNode; pNode = (Map_Node_t *)pNode->pData0 )
-            Map_NodeVecPush( pMan->vMapping, pNode );
-    free( ppStore );
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Recursively computes the DFS ordering of the nodes.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Map_MappingSetRefs_rec( Map_Man_t * pMan, Map_Node_t * pNode, Map_Node_t ** ppStore )
-{
-    Map_Cut_t * pCut;
-    Map_Node_t * pNodeR;
-    unsigned uPhase;
-    int i, fPhase, fInvPin;
-
-    // get the regular node and its phase
-    pNodeR = Map_Regular(pNode);
-    fPhase = !Map_IsComplement(pNode);
-
-    // add the node to the list of all visited nodes
-    if ( pNodeR->nRefAct[2]++ == 0 )
-//        Map_NodeVecPush( pMan->vMapping, pNodeR );
-        pNodeR->pData0 = (char *)ppStore[pNodeR->Level], ppStore[pNodeR->Level] = pNodeR;
-
-    // quit if the node was already visited in this phase
-    if ( pNodeR->nRefAct[fPhase]++ )
-        return;
-
-    // quit if this is a PI node
-    if ( Map_NodeIsVar(pNodeR) )
-        return;
-
-    // get the cut implementing this or opposite polarity
-    pCut = pNodeR->pCutBest[fPhase];
-    if ( pCut == NULL )
-    {
-        fPhase = !fPhase;
-        pCut   = pNodeR->pCutBest[fPhase];
-    }
-
-    // visit the transitive fanin
-    uPhase = pCut->M[fPhase].uPhaseBest;
-    for ( i = 0; i < pCut->nLeaves; i++ )
-    {
-        fInvPin = ((uPhase & (1 << i)) > 0);
-        Map_MappingSetRefs_rec( pMan, Map_NotCond(pCut->ppLeaves[i], fInvPin), ppStore );
-    }
-}
-
-
-/**Function*************************************************************
-
-  Synopsis    [Computes the array of mapping.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-float Map_MappingGetArea( Map_Man_t * pMan, Map_NodeVec_t * vMapping )
-{
-    Map_Node_t * pNode;
-    float Area;
-    int i;
-    Area = 0.0;
-    for ( i = 0; i < vMapping->nSize; i++ )
-    {
-        pNode = vMapping->pArray[i];
-        // at least one phase has the best cut assigned
-        assert( pNode->pCutBest[0] != NULL || pNode->pCutBest[1] != NULL );
-        // at least one phase is used in the mapping
-        assert( pNode->nRefAct[0] > 0 || pNode->nRefAct[1] > 0 );
-        // compute the array due to the supergate
-        if ( Map_NodeIsAnd(pNode) )
-        {
-            // count area of the negative phase
-            if ( pNode->pCutBest[0] && (pNode->nRefAct[0] > 0 || pNode->pCutBest[1] == NULL) )
-                Area += pNode->pCutBest[0]->M[0].pSuperBest->Area;
-            // count area of the positive phase
-            if ( pNode->pCutBest[1] && (pNode->nRefAct[1] > 0 || pNode->pCutBest[0] == NULL) )
-                Area += pNode->pCutBest[1]->M[1].pSuperBest->Area;
-        }
-        // count area of the interver if we need to implement one phase with another phase
-        if ( (pNode->pCutBest[0] == NULL && pNode->nRefAct[0] > 0) || 
-             (pNode->pCutBest[1] == NULL && pNode->nRefAct[1] > 0) )
-            Area += pMan->pSuperLib->AreaInv;
-    }
-    // add buffers for each CO driven by a CI
-    for ( i = 0; i < pMan->nOutputs; i++ )
-        if ( Map_NodeIsVar(pMan->pOutputs[i]) && !Map_IsComplement(pMan->pOutputs[i]) )
-            Area += pMan->pSuperLib->AreaBuf;
-    return Area;
-}
-
-
-////////////////////////////////////////////////////////////////////////
-///                       END OF FILE                                ///
-////////////////////////////////////////////////////////////////////////
-
-
diff --git a/abc70930/src/map/mapper/mapperSuper.c b/abc70930/src/map/mapper/mapperSuper.c
deleted file mode 100644
index ce6a780f..00000000
--- a/abc70930/src/map/mapper/mapperSuper.c
+++ /dev/null
@@ -1,449 +0,0 @@
-/**CFile****************************************************************
-
-  FileName    [mapperSuper.c]
-
-  PackageName [MVSIS 1.3: Multi-valued logic synthesis system.]
-
-  Synopsis    [Generic technology mapping engine.]
-
-  Author      [MVSIS Group]
-  
-  Affiliation [UC Berkeley]
-
-  Date        [Ver. 2.0. Started - June 1, 2004.]
-
-  Revision    [$Id: mapperSuper.c,v 1.6 2005/01/23 06:59:44 alanmi Exp $]
-
-***********************************************************************/
-
-#include "mapperInt.h"
-
-////////////////////////////////////////////////////////////////////////
-///                        DECLARATIONS                              ///
-////////////////////////////////////////////////////////////////////////
-
-static int           Map_LibraryReadFile( Map_SuperLib_t * pLib, FILE * pFile );
-static Map_Super_t * Map_LibraryReadGate( Map_SuperLib_t * pLib, char * pBuffer, int nVars );
-static int           Map_LibraryTruthVerify( Map_SuperLib_t * pLib, Map_Super_t * pGate );
-static void          Map_LibraryComputeTruth( Map_SuperLib_t * pLib, char * pFormula, unsigned uTruthRes[] );
-static void          Map_LibraryComputeTruth_rec( Map_SuperLib_t * pLib, char * pFormula, unsigned uTruthsIn[][2], unsigned uTruthRes[] );
-static void          Map_LibraryPrintClasses( Map_SuperLib_t * p );
-
-////////////////////////////////////////////////////////////////////////
-///                     FUNCTION DEFINITIONS                         ///
-////////////////////////////////////////////////////////////////////////
-
-/**Function*************************************************************
-
-  Synopsis    [Reads the supergate library from file.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Map_LibraryRead( Map_SuperLib_t * pLib, char * pFileName )
-{
-    FILE * pFile;
-    int Status;
-    // read the beginning of the file
-    assert( pLib->pGenlib == NULL );
-    pFile = fopen( pFileName, "r" );
-    if ( pFile == NULL )
-    {
-        printf( "Cannot open input file \"%s\".\n", pFileName );
-        return 0;
-    }
-    Status = Map_LibraryReadFile( pLib, pFile );
-    fclose( pFile );
-//    Map_LibraryPrintClasses( pLib );
-    return Status;
-}
-
-
-/**Function*************************************************************
-
-  Synopsis    [Reads the library file.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Map_LibraryReadFile( Map_SuperLib_t * pLib, FILE * pFile )
-{
-    ProgressBar * pProgress;
-    char pBuffer[2000];
-    FILE * pFileGen;
-    Map_Super_t * pGate;
-    char * pTemp, * pLibName;
-    int nCounter, nGatesTotal;
-    unsigned uCanon[2];
-
-    // skip empty and comment lines
-    while ( fgets( pBuffer, 5000, pFile ) != NULL )
-    {
-        // skip leading spaces
-        for ( pTemp = pBuffer; *pTemp == ' ' || *pTemp == '\r' || *pTemp == '\n'; pTemp++ );
-        // skip comment lines and empty lines
-        if ( *pTemp != 0 && *pTemp != '#' )
-            break;
-    }
-
-    // get the genlib file name
-    pLibName = strtok( pTemp, " \t\r\n" );
-    if ( strcmp( pLibName, "GATE" ) == 0 )
-    {
-        printf( "The input file \"%s\" looks like a GENLIB file and not a supergate library file.\n", pLib->pName );
-        return 0;
-    }
-    pFileGen = fopen( pLibName, "r" );
-    if ( pFileGen == NULL )
-    {
-        printf( "Cannot open the GENLIB file \"%s\".\n", pLibName );
-        return 0;
-    }
-    fclose( pFileGen );
-
-    // read the genlib library
-    pLib->pGenlib = Mio_LibraryRead( Abc_FrameGetGlobalFrame(), pLibName, 0, 0 );
-    if ( pLib->pGenlib == NULL )
-    {
-        printf( "Cannot read GENLIB file \"%s\".\n", pLibName );
-        return 0;
-    }
-
-    // read the number of variables
-    fscanf( pFile, "%d\n", &pLib->nVarsMax );
-    if ( pLib->nVarsMax < 2 || pLib->nVarsMax > 10 )
-    {
-        printf( "Suspicious number of variables (%d).\n", pLib->nVarsMax );
-        return 0;
-    }
-
-    // read the number of gates
-    fscanf( pFile, "%d\n", &nGatesTotal );
-    if ( nGatesTotal < 1 || nGatesTotal > 10000000 )
-    {
-        printf( "Suspicious number of gates (%d).\n", nGatesTotal );
-        return 0;
-    }
-
-    // read the lines
-    nCounter = 0;
-    pProgress = Extra_ProgressBarStart( stdout, nGatesTotal );
-    while ( fgets( pBuffer, 5000, pFile ) != NULL )
-    {
-        for ( pTemp = pBuffer; *pTemp == ' ' || *pTemp == '\r' || *pTemp == '\n'; pTemp++ );
-        if ( pTemp[0] == '\0' )
-            continue;
-        // get the gate
-        pGate = Map_LibraryReadGate( pLib, pTemp, pLib->nVarsMax );
-        assert( pGate->Num == nCounter + 1 );
-        // count the number of parantheses in the formula - this is the number of gates
-        for ( pTemp = pGate->pFormula; *pTemp; pTemp++ )
-            pGate->nGates += (*pTemp == '(');
-        // verify the truth table
-        assert( Map_LibraryTruthVerify(pLib, pGate) );
-
-        // find the N-canonical form of this supergate
-        pGate->nPhases = Map_CanonComputeSlow( pLib->uTruths, pLib->nVarsMax, pLib->nVarsMax, pGate->uTruth, pGate->uPhases, uCanon );
-        // add the supergate into the table by its N-canonical table
-        Map_SuperTableInsertC( pLib->tTableC, uCanon, pGate );
-        // update the progress bar
-        Extra_ProgressBarUpdate( pProgress, ++nCounter, NULL );
-    }
-    Extra_ProgressBarStop( pProgress );
-    pLib->nSupersAll = nCounter;
-    if ( nCounter != nGatesTotal )
-        printf( "The number of gates read (%d) is different what the file says (%d).\n", nGatesTotal, nCounter );
-    return 1;
-}
-
-/**Function*************************************************************
-
-  Synopsis    []
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-Map_Super_t * Map_LibraryReadGate( Map_SuperLib_t * pLib, char * pBuffer, int nVars )
-{
-    Map_Super_t * pGate;
-    char * pTemp;
-    int i;
-
-    // start and clean the gate
-    pGate = (Map_Super_t *)Extra_MmFixedEntryFetch( pLib->mmSupers );
-    memset( pGate, 0, sizeof(Map_Super_t) );
-
-    // read the number
-    pTemp = strtok( pBuffer, " " );
-    pGate->Num = atoi(pTemp);
-
-    // read the signature
-    pTemp = strtok( NULL, " " );
-    if ( pLib->nVarsMax < 6 )
-    {
-        pGate->uTruth[0] = Extra_ReadBinary(pTemp);
-        pGate->uTruth[1] = 0;
-    }
-    else
-    {
-        pGate->uTruth[0] = Extra_ReadBinary(pTemp+32);
-        pTemp[32] = 0;
-        pGate->uTruth[1] = Extra_ReadBinary(pTemp);
-    }
-
-    // read the max delay
-    pTemp = strtok( NULL, " " );
-    pGate->tDelayMax.Rise = (float)atof(pTemp);
-    pGate->tDelayMax.Fall = pGate->tDelayMax.Rise;
-
-    // read the pin-to-pin delay
-    for ( i = 0; i < nVars; i++ )
-    {
-        pTemp = strtok( NULL, " " );
-        pGate->tDelaysR[i].Rise = (float)atof(pTemp);
-        pGate->tDelaysF[i].Fall = pGate->tDelaysR[i].Rise;
-    }
-
-    // read the area
-    pTemp = strtok( NULL, " " );
-    pGate->Area = (float)atof(pTemp);
-
-    // the rest is the gate name
-    pTemp = strtok( NULL, " \r\n" );
-    if ( strlen(pTemp) == 0 )
-        printf( "A gate name is empty.\n" );
-
-    // save the gate name
-    pGate->pFormula = Extra_MmFlexEntryFetch( pLib->mmForms, strlen(pTemp) + 1 );
-    strcpy( pGate->pFormula, pTemp );
-
-    // the rest is the gate name
-    pTemp = strtok( NULL, " \n\0" );
-    if ( pTemp != NULL )
-        printf( "The following trailing symbols found \"%s\".\n", pTemp );
-    return pGate;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Performs one step of parsing the formula into parts.]
-
-  Description [This function will eventually be replaced when the
-  tree-supergate library representation will become standard.]
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-char * Map_LibraryReadFormulaStep( char * pFormula, char * pStrings[], int * pnStrings )
-{
-    char * pName, * pPar1, * pPar2, * pCur;
-    int nStrings, CountPars;
-
-    // skip leading spaces
-    for ( pName = pFormula; *pName && *pName == ' '; pName++ );
-    assert( *pName );
-    // find the first opening paranthesis
-    for ( pPar1 = pName; *pPar1 && *pPar1 != '('; pPar1++ );
-    if ( *pPar1 == 0 )
-    {
-        *pnStrings = 0;
-        return pName;
-    }
-    // overwrite it with space
-    assert( *pPar1 == '(' );
-    *pPar1 = 0;
-    // find the corresponding closing paranthesis
-    for ( CountPars = 1, pPar2 = pPar1 + 1; *pPar2 && CountPars; pPar2++ )
-        if ( *pPar2 == '(' )
-            CountPars++;
-        else if ( *pPar2 == ')' )
-            CountPars--;
-    pPar2--;
-    assert( CountPars == 0 );
-    // overwrite it with space
-    assert( *pPar2 == ')' );
-    *pPar2 = 0;
-    // save the intervals between the commas
-    nStrings = 0;
-    pCur = pPar1 + 1;
-    while ( 1 )
-    {
-        // save the current string
-        pStrings[ nStrings++ ] = pCur;
-        // find the beginning of the next string
-        for ( CountPars = 0; *pCur && (CountPars || *pCur != ','); pCur++ )
-            if ( *pCur == '(' )
-                CountPars++;
-            else if ( *pCur == ')' )
-                CountPars--;
-        if ( *pCur == 0 )
-            break;
-        assert( *pCur == ',' );
-        *pCur = 0;
-        pCur++;
-    }
-    // save the results and return
-    *pnStrings = nStrings;
-    return pName;
-}
-
-
-/**Function*************************************************************
-
-  Synopsis    [Verifies the truth table of the supergate.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Map_LibraryTruthVerify( Map_SuperLib_t * pLib, Map_Super_t * pGate )
-{
-    unsigned uTruthRes[2];
-    Map_LibraryComputeTruth( pLib, pGate->pFormula, uTruthRes );
-    if ( uTruthRes[0] != pGate->uTruth[0] || uTruthRes[1] != pGate->uTruth[1] )
-        return 0;
-    return 1;
-}
-
-
-/**Function*************************************************************
-
-  Synopsis    [Derives the functionality of the supergate.]
-
-  Description [This procedure is useful for verification the supergate 
-  library. The truth table derived by this procedure should be the same
-  as the one contained in the original supergate file.]
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Map_LibraryComputeTruth( Map_SuperLib_t * pLib, char * pFormula, unsigned uTruthRes[] )
-{
-    char Buffer[1000];
-    strcpy( Buffer, pFormula );
-    Map_LibraryComputeTruth_rec( pLib, Buffer, pLib->uTruths, uTruthRes );
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Derives the functionality of the supergate.]
-
-  Description [This procedure is useful for verification the supergate 
-  library. The truth table derived by this procedure should be the same
-  as the one contained in the original supergate file.]
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Map_LibraryComputeTruth_rec( Map_SuperLib_t * pLib, char * pFormula, unsigned uTruthsIn[][2], unsigned uTruthRes[] )
-{
-    Mio_Gate_t * pMioGate;
-    char * pGateName, * pStrings[6];
-    unsigned uTruthsFanins[6][2];
-    int nStrings, i;
-
-    // perform one step parsing of the formula
-    // detect the root gate name, the next-step strings, and their number
-    pGateName = Map_LibraryReadFormulaStep( pFormula, pStrings, &nStrings );
-    if ( nStrings == 0 ) // elementary variable
-    {
-        assert( pGateName[0] - 'a' < pLib->nVarsMax );
-        uTruthRes[0] = uTruthsIn[pGateName[0] - 'a'][0];
-        uTruthRes[1] = uTruthsIn[pGateName[0] - 'a'][1];
-        return;
-    }
-    // derive the functionality of the fanins
-    for ( i = 0; i < nStrings; i++ )
-        Map_LibraryComputeTruth_rec( pLib, pStrings[i], uTruthsIn, uTruthsFanins[i] );
-    // get the root supergate
-    pMioGate = Mio_LibraryReadGateByName( pLib->pGenlib, pGateName );
-    if ( pMioGate == NULL )
-        printf( "A supergate contains gate \"%s\" that is not in \"%s\".\n", pGateName, Mio_LibraryReadName(pLib->pGenlib) ); 
-    // derive the functionality of the output of the supergate
-    Mio_DeriveTruthTable( pMioGate, uTruthsFanins, nStrings, pLib->nVarsMax, uTruthRes );
-}
-
-/**Function*************************************************************
-
-  Synopsis    []
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Map_LibraryPrintSupergate( Map_Super_t * pGate )
-{
-    printf( "%5d : ",  pGate->nUsed );
-    printf( "%5d   ",  pGate->Num );
-    printf( "A = %5.2f   ",  pGate->Area );
-    printf( "D = %5.2f   ",  pGate->tDelayMax );
-    printf( "%s",    pGate->pFormula );
-    printf( "\n" );
-}
-
-
-/**Function*************************************************************
-
-  Synopsis    [Prints N-classes of supergates.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Map_LibraryPrintClasses( Map_SuperLib_t * p )
-{
-/*
-    st_generator * gen;
-    Map_Super_t * pSuper, * pSuper2;
-    unsigned Key, uTruth;
-    int Counter = 0;
-    // copy all the supergates into one array
-    st_foreach_item( p->tSuplib, gen, (char **)&Key, (char **)&pSuper )
-    {
-        for ( pSuper2 = pSuper; pSuper2; pSuper2 = pSuper2->pNext )
-        {
-            uTruth = pSuper2->Phase;
-            Extra_PrintBinary( stdout, &uTruth, 5 );
-            printf( "  %5d   ",  pSuper2->Num );
-            printf( "%s",    pSuper2->pFormula );
-            printf( "\n" );
-        }
-        printf( "\n" );
-        if ( ++ Counter == 100 )
-            break;
-    }
-*/
-}
-
-////////////////////////////////////////////////////////////////////////
-///                       END OF FILE                                ///
-////////////////////////////////////////////////////////////////////////
-
-
diff --git a/abc70930/src/map/mapper/mapperSwitch.c b/abc70930/src/map/mapper/mapperSwitch.c
deleted file mode 100644
index 9dd6e42b..00000000
--- a/abc70930/src/map/mapper/mapperSwitch.c
+++ /dev/null
@@ -1,223 +0,0 @@
-/**CFile****************************************************************
-
-  FileName    [mapperSwitch.c]
-
-  PackageName [MVSIS 1.3: Multi-valued logic synthesis system.]
-
-  Synopsis    [Generic technology mapping engine.]
-
-  Author      [MVSIS Group]
-  
-  Affiliation [UC Berkeley]
-
-  Date        [Ver. 1.0. Started - September 8, 2003.]
-
-  Revision    [$Id: mapperSwitch.h,v 1.0 2003/09/08 00:00:00 alanmi Exp $]
-
-***********************************************************************/
-
-#include "mapperInt.h"
-
-////////////////////////////////////////////////////////////////////////
-///                        DECLARATIONS                              ///
-////////////////////////////////////////////////////////////////////////
-
-static float Map_SwitchCutRefDeref( Map_Node_t * pNode, Map_Cut_t * pCut, int fPhase, int fReference );
-
-////////////////////////////////////////////////////////////////////////
-///                     FUNCTION DEFINITIONS                         ///
-////////////////////////////////////////////////////////////////////////
-
-/**function*************************************************************
-
-  synopsis    [Computes the exact area associated with the cut.]
-
-  description []
-               
-  sideeffects []
-
-  seealso     []
-
-***********************************************************************/
-float Map_SwitchCutGetDerefed( Map_Node_t * pNode, Map_Cut_t * pCut, int fPhase )
-{
-    float aResult, aResult2;
-//    assert( pNode->Switching > 0 );
-    aResult2 = Map_SwitchCutRefDeref( pNode, pCut, fPhase, 1 ); // reference
-    aResult  = Map_SwitchCutRefDeref( pNode, pCut, fPhase, 0 ); // dereference
-//    assert( aResult == aResult2 );
-    return aResult;
-}
-
-/**function*************************************************************
-
-  synopsis    [References the cut.]
-
-  description []
-               
-  sideeffects []
-
-  seealso     []
-
-***********************************************************************/
-float Map_SwitchCutRef( Map_Node_t * pNode, Map_Cut_t * pCut, int fPhase )
-{
-    return Map_SwitchCutRefDeref( pNode, pCut, fPhase, 1 ); // reference
-}
-
-/**function*************************************************************
-
-  synopsis    [References the cut.]
-
-  description []
-               
-  sideeffects []
-
-  seealso     []
-
-***********************************************************************/
-float Map_SwitchCutDeref( Map_Node_t * pNode, Map_Cut_t * pCut, int fPhase )
-{
-    return Map_SwitchCutRefDeref( pNode, pCut, fPhase, 0 ); // dereference
-}
-
-/**function*************************************************************
-
-  synopsis    [References or dereferences the cut.]
-
-  description [This reference part is similar to Cudd_NodeReclaim(). 
-  The dereference part is similar to Cudd_RecursiveDeref().]
-               
-  sideeffects []
-
-  seealso     []
-
-***********************************************************************/
-float Map_SwitchCutRefDeref( Map_Node_t * pNode, Map_Cut_t * pCut, int fPhase, int fReference )
-{
-    Map_Node_t * pNodeChild;
-    Map_Cut_t * pCutChild;
-    float aSwitchActivity;
-    int i, fPhaseChild;
-
-    // start switching activity for the node
-    aSwitchActivity = pNode->Switching;
-    // consider the elementary variable
-    if ( pCut->nLeaves == 1 )
-        return aSwitchActivity;
-
-    // go through the children
-    assert( pCut->M[fPhase].pSuperBest );
-    for ( i = 0; i < pCut->nLeaves; i++ )
-    {
-        pNodeChild  = pCut->ppLeaves[i];
-        fPhaseChild = Map_CutGetLeafPhase( pCut, fPhase, i );
-        // get the reference counter of the child
-
-        if ( fReference )
-        {
-            if ( pNodeChild->pCutBest[0] && pNodeChild->pCutBest[1] ) // both phases are present
-            {
-                // if this phase of the node is referenced, there is no recursive call
-                pNodeChild->nRefAct[2]++;
-                if ( pNodeChild->nRefAct[fPhaseChild]++ > 0 )
-                    continue;
-            }
-            else // only one phase is present
-            {
-                // inverter should be added if the phase
-                // (a) has no reference and (b) is implemented using other phase
-                if ( pNodeChild->nRefAct[fPhaseChild]++ == 0 && pNodeChild->pCutBest[fPhaseChild] == NULL )
-                    aSwitchActivity += pNodeChild->Switching; // inverter switches the same as the node
-                // if the node is referenced, there is no recursive call
-                if ( pNodeChild->nRefAct[2]++ > 0 )
-                    continue;
-            }
-        }
-        else
-        {
-            if ( pNodeChild->pCutBest[0] && pNodeChild->pCutBest[1] ) // both phases are present
-            {
-                // if this phase of the node is referenced, there is no recursive call
-                --pNodeChild->nRefAct[2];
-                if ( --pNodeChild->nRefAct[fPhaseChild] > 0 )
-                    continue;
-            }
-            else // only one phase is present
-            {
-                // inverter should be added if the phase
-                // (a) has no reference and (b) is implemented using other phase
-                if ( --pNodeChild->nRefAct[fPhaseChild] == 0 && pNodeChild->pCutBest[fPhaseChild] == NULL )
-                    aSwitchActivity += pNodeChild->Switching; // inverter switches the same as the node
-                // if the node is referenced, there is no recursive call
-                if ( --pNodeChild->nRefAct[2] > 0 )
-                    continue;
-            }
-            assert( pNodeChild->nRefAct[fPhaseChild] >= 0 );
-        }
-
-        // get the child cut
-        pCutChild = pNodeChild->pCutBest[fPhaseChild];
-        // if the child does not have this phase mapped, take the opposite phase
-        if ( pCutChild == NULL )
-        {
-            fPhaseChild = !fPhaseChild;
-            pCutChild   = pNodeChild->pCutBest[fPhaseChild];
-        }
-        // reference and compute area recursively
-        aSwitchActivity += Map_SwitchCutRefDeref( pNodeChild, pCutChild, fPhaseChild, fReference );
-    }
-    return aSwitchActivity;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Computes the array of mapping.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-float Map_MappingGetSwitching( Map_Man_t * pMan, Map_NodeVec_t * vMapping )
-{
-    Map_Node_t * pNode;
-    float Switch;
-    int i;
-    Switch = 0.0;
-    for ( i = 0; i < vMapping->nSize; i++ )
-    {
-        pNode = vMapping->pArray[i];
-        // at least one phase has the best cut assigned
-        assert( pNode->pCutBest[0] != NULL || pNode->pCutBest[1] != NULL );
-        // at least one phase is used in the mapping
-        assert( pNode->nRefAct[0] > 0 || pNode->nRefAct[1] > 0 );
-        // compute the array due to the supergate
-        if ( Map_NodeIsAnd(pNode) )
-        {
-            // count switching of the negative phase
-            if ( pNode->pCutBest[0] && (pNode->nRefAct[0] > 0 || pNode->pCutBest[1] == NULL) )
-                Switch += pNode->Switching;
-            // count switching of the positive phase
-            if ( pNode->pCutBest[1] && (pNode->nRefAct[1] > 0 || pNode->pCutBest[0] == NULL) )
-                Switch += pNode->Switching;
-        }
-        // count switching of the interver if we need to implement one phase with another phase
-        if ( (pNode->pCutBest[0] == NULL && pNode->nRefAct[0] > 0) || 
-             (pNode->pCutBest[1] == NULL && pNode->nRefAct[1] > 0) )
-            Switch += pNode->Switching; // inverter switches the same as the node
-    }
-    // add buffers for each CO driven by a CI
-    for ( i = 0; i < pMan->nOutputs; i++ )
-        if ( Map_NodeIsVar(pMan->pOutputs[i]) && !Map_IsComplement(pMan->pOutputs[i]) )
-            Switch += pMan->pOutputs[i]->Switching;
-    return Switch;
-}
-
-////////////////////////////////////////////////////////////////////////
-///                       END OF FILE                                ///
-////////////////////////////////////////////////////////////////////////
-
-
diff --git a/abc70930/src/map/mapper/mapperTable.c b/abc70930/src/map/mapper/mapperTable.c
deleted file mode 100644
index d0cb7a01..00000000
--- a/abc70930/src/map/mapper/mapperTable.c
+++ /dev/null
@@ -1,402 +0,0 @@
-/**CFile****************************************************************
-
-  FileName    [mapperTable.c]
-
-  PackageName [MVSIS 1.3: Multi-valued logic synthesis system.]
-
-  Synopsis    [Generic technology mapping engine.]
-
-  Author      [MVSIS Group]
-  
-  Affiliation [UC Berkeley]
-
-  Date        [Ver. 2.0. Started - June 1, 2004.]
-
-  Revision    [$Id: mapperTable.c,v 1.6 2005/01/23 06:59:44 alanmi Exp $]
-
-***********************************************************************/
-
-#include "mapperInt.h"
-
-////////////////////////////////////////////////////////////////////////
-///                        DECLARATIONS                              ///
-////////////////////////////////////////////////////////////////////////
-
-// the table function for the tables
-#define  MAP_TABLE_HASH(u1,u2,nSize)  (((u1) + 2003 * (u2)) % nSize)
-
-static void Map_SuperTableResize( Map_HashTable_t * pLib );
-
-////////////////////////////////////////////////////////////////////////
-///                     FUNCTION DEFINITIONS                         ///
-////////////////////////////////////////////////////////////////////////
-
-/**Function*************************************************************
-
-  Synopsis    [Creates the hash table for supergates.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-Map_HashTable_t * Map_SuperTableCreate( Map_SuperLib_t * pLib )
-{
-    Map_HashTable_t * p;
-    // allocate the table
-    p = ALLOC( Map_HashTable_t, 1 );
-    memset( p, 0, sizeof(Map_HashTable_t) );
-    p->mmMan = pLib->mmEntries;
-    // allocate and clean the bins
-    p->nBins = Cudd_Prime(20000);
-    p->pBins = ALLOC( Map_HashEntry_t *, p->nBins );
-    memset( p->pBins, 0, sizeof(Map_HashEntry_t *) * p->nBins );
-    return p;
-}
-
-
-/**Function*************************************************************
-
-  Synopsis    [Deallocates the supergate hash table.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Map_SuperTableFree( Map_HashTable_t * p )
-{
-    FREE( p->pBins );
-    FREE( p );
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Inserts a new entry into the hash table.]
-
-  Description [This function inserts the new gate (pGate), which will be
-  accessible through its canonical form (uTruthC).]
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Map_SuperTableInsertC( Map_HashTable_t * p, unsigned uTruthC[], Map_Super_t * pGate )
-{
-    Map_HashEntry_t * pEnt;
-    unsigned Key;
-    // resize the table
-    if ( p->nEntries >= 2 * p->nBins )
-        Map_SuperTableResize( p );
-    // check if another supergate with the same canonical form exists
-    Key = MAP_TABLE_HASH( uTruthC[0], uTruthC[1], p->nBins );
-    for ( pEnt = p->pBins[Key]; pEnt; pEnt = pEnt->pNext )
-        if ( pEnt->uTruth[0] == uTruthC[0] && pEnt->uTruth[1] == uTruthC[1] )
-            break;
-    // create a new entry if it does not exist
-    if ( pEnt == NULL )
-    {
-        // add the new entry to the table
-        pEnt = (Map_HashEntry_t *)Extra_MmFixedEntryFetch( p->mmMan );
-        memset( pEnt, 0, sizeof(Map_HashEntry_t) );
-        pEnt->uTruth[0] = uTruthC[0];
-        pEnt->uTruth[1] = uTruthC[1];
-        // add the hash table entry to the corresponding linked list in the table
-        pEnt->pNext   = p->pBins[Key];
-        p->pBins[Key] = pEnt;
-        p->nEntries++;
-    }
-    // add the supergate to the entry
-    pGate->pNext = pEnt->pGates;
-    pEnt->pGates = pGate;
-    return 0;
-}
-
-
-
-/**Function*************************************************************
-
-  Synopsis    [Inserts a new entry into the library.]
-
-  Description [This function inserts the new gate (pGate), which will be
-  accessible through its unfolded function (uTruth).]
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Map_SuperTableInsert( Map_HashTable_t * p, unsigned uTruth[], Map_Super_t * pGate, unsigned uPhase )
-{
-    Map_HashEntry_t * pEnt;
-    unsigned Key;
-    // resize the table
-    if ( p->nEntries >= 2 * p->nBins )
-        Map_SuperTableResize( p );
-    // check if this entry already exists
-    Key = MAP_TABLE_HASH( uTruth[0], uTruth[1], p->nBins );
-    for ( pEnt = p->pBins[Key]; pEnt; pEnt = pEnt->pNext )
-        if ( pEnt->uTruth[0] == uTruth[0] && pEnt->uTruth[1] == uTruth[1] )
-            return 1;
-    // add the new hash table entry to the table
-    pEnt = (Map_HashEntry_t *)Extra_MmFixedEntryFetch( p->mmMan );
-    memset( pEnt, 0, sizeof(Map_HashEntry_t) );
-    pEnt->uTruth[0] = uTruth[0];
-    pEnt->uTruth[1] = uTruth[1];
-    pEnt->pGates    = pGate;
-    pEnt->uPhase    = uPhase;
-    // add the hash table to the corresponding linked list in the table
-    pEnt->pNext   = p->pBins[Key];
-    p->pBins[Key] = pEnt;
-    p->nEntries++;
-/*
-printf( "Adding gate: %10u ", Key );
-Map_LibraryPrintSupergate( pGate );
-Extra_PrintBinary( stdout, uTruth, 32 );
-printf( "\n" );
-*/
-    return 0;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Looks up an entry in the library.]
-
-  Description [This function looks up the function, given by its truth table,
-  and return two things: (1) the linked list of supergates, which can implement
-  the functions of this N-class; (2) the phase, which should be applied to the
-  given function, in order to derive the canonical form of this N-class.]
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-Map_Super_t * Map_SuperTableLookupC( Map_SuperLib_t * p, unsigned uTruth[] )
-{
-    Map_HashEntry_t * pEnt;
-    unsigned Key;
-    Key = MAP_TABLE_HASH( uTruth[0], uTruth[1], p->tTableC->nBins );
-    for ( pEnt = p->tTableC->pBins[Key]; pEnt; pEnt = pEnt->pNext )
-        if ( pEnt->uTruth[0] == uTruth[0] && pEnt->uTruth[1] == uTruth[1] )
-            return pEnt->pGates;
-    return NULL;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Looks up an entry in the library.]
-
-  Description [This function looks up the function, given by its truth table,
-  and return two things: (1) the linked list of supergates, which can implement
-  the functions of this N-class; (2) the phase, which should be applied to the
-  given function, in order to derive the canonical form of this N-class.]
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-Map_Super_t * Map_SuperTableLookup( Map_HashTable_t * p, unsigned uTruth[], unsigned * puPhase )
-{
-    Map_HashEntry_t * pEnt;
-    unsigned Key;
-    Key = MAP_TABLE_HASH( uTruth[0], uTruth[1], p->nBins );
-    for ( pEnt = p->pBins[Key]; pEnt; pEnt = pEnt->pNext )
-        if ( pEnt->uTruth[0] == uTruth[0] && pEnt->uTruth[1] == uTruth[1] )
-        {
-            *puPhase = pEnt->uPhase;
-            return pEnt->pGates;
-        }
-    return NULL;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Resizes the table.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Map_SuperTableResize( Map_HashTable_t * p )
-{
-    Map_HashEntry_t ** pBinsNew;
-    Map_HashEntry_t * pEnt, * pEnt2;
-    int nBinsNew, Counter, i, clk = clock();
-    unsigned Key;
-    // get the new table size
-    nBinsNew = Cudd_Prime(2 * p->nBins); 
-    // allocate a new array
-    pBinsNew = ALLOC( Map_HashEntry_t *, nBinsNew );
-    memset( pBinsNew, 0, sizeof(Map_HashEntry_t *) * nBinsNew );
-    // rehash the entries from the old table
-    Counter = 0;
-    for ( i = 0; i < p->nBins; i++ )
-        for ( pEnt = p->pBins[i], pEnt2 = pEnt? pEnt->pNext: NULL; pEnt; 
-              pEnt = pEnt2, pEnt2 = pEnt? pEnt->pNext: NULL )
-        {
-            Key = MAP_TABLE_HASH( pEnt->uTruth[0], pEnt->uTruth[1], nBinsNew );
-            pEnt->pNext   = pBinsNew[Key];
-            pBinsNew[Key] = pEnt;
-            Counter++;
-        }
-    assert( Counter == p->nEntries );
-    // replace the table and the parameters
-    free( p->pBins );
-    p->pBins = pBinsNew;
-    p->nBins = nBinsNew;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Compares the supergates by the number of times they are used.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Map_SuperTableCompareSupergates( Map_Super_t ** ppS1, Map_Super_t ** ppS2 )
-{
-    if ( (*ppS1)->nUsed > (*ppS2)->nUsed )
-        return -1;
-    if ( (*ppS1)->nUsed < (*ppS2)->nUsed )
-        return 1;
-    return 0;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Compares the supergates by the number of times they are used.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Map_SuperTableCompareGatesInList( Map_Super_t ** ppS1, Map_Super_t ** ppS2 )
-{
-//   if ( (*ppS1)->tDelayMax.Rise > (*ppS2)->tDelayMax.Rise )
-    if ( (*ppS1)->Area > (*ppS2)->Area )
-        return -1;
-//   if ( (*ppS1)->tDelayMax.Rise < (*ppS2)->tDelayMax.Rise )
-    if ( (*ppS1)->Area < (*ppS2)->Area )
-        return 1;
-    return 0;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Sorts supergates by usefulness and prints out most useful.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Map_SuperTableSortSupergates( Map_HashTable_t * p, int nSupersMax )
-{
-    Map_HashEntry_t * pEnt;
-    Map_Super_t ** ppSupers;
-    Map_Super_t * pSuper;
-    int nSupers, i;
-
-    // copy all the supergates into one array
-    ppSupers = ALLOC( Map_Super_t *, nSupersMax );
-    nSupers = 0;
-    for ( i = 0; i < p->nBins; i++ )
-        for ( pEnt = p->pBins[i]; pEnt; pEnt = pEnt->pNext )
-            for ( pSuper = pEnt->pGates; pSuper; pSuper = pSuper->pNext )
-                ppSupers[nSupers++] = pSuper;
-
-    // sort by usage
-    qsort( (void *)ppSupers, nSupers, sizeof(Map_Super_t *), 
-            (int (*)(const void *, const void *)) Map_SuperTableCompareSupergates );
-    assert( Map_SuperTableCompareSupergates( ppSupers, ppSupers + nSupers - 1 ) <= 0 );
-
-    // print out the "top ten"
-//    for ( i = 0; i < nSupers; i++ )
-    for ( i = 0; i < 10; i++ )
-    {
-        if ( ppSupers[i]->nUsed == 0 )
-            break;
-        printf( "%5d : ",        ppSupers[i]->nUsed );
-        printf( "%5d   ",        ppSupers[i]->Num );
-        printf( "A = %5.2f   ",  ppSupers[i]->Area );
-        printf( "D = %5.2f   ",  ppSupers[i]->tDelayMax.Rise );
-        printf( "%s",            ppSupers[i]->pFormula );
-        printf( "\n" );
-    }
-    free( ppSupers );
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Sorts supergates by max delay for each truth table.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Map_SuperTableSortSupergatesByDelay( Map_HashTable_t * p, int nSupersMax )
-{
-    Map_HashEntry_t * pEnt;
-    Map_Super_t ** ppSupers;
-    Map_Super_t * pSuper;
-    int nSupers, i, k;
-
-    ppSupers = ALLOC( Map_Super_t *, nSupersMax );
-    for ( i = 0; i < p->nBins; i++ )
-        for ( pEnt = p->pBins[i]; pEnt; pEnt = pEnt->pNext )
-        {
-            // collect the gates in this entry
-            nSupers = 0;
-            for ( pSuper = pEnt->pGates; pSuper; pSuper = pSuper->pNext )
-            {
-                // skip supergates, whose root is the AND gate
-//                if ( strcmp( Mio_GateReadName(pSuper->pRoot), "and" ) == 0 )
-//                    continue;
-                ppSupers[nSupers++] = pSuper;
-            }
-            pEnt->pGates = NULL;
-            if ( nSupers == 0 )
-                continue;
-            // sort the gates by delay
-            qsort( (void *)ppSupers, nSupers, sizeof(Map_Super_t *), 
-                    (int (*)(const void *, const void *)) Map_SuperTableCompareGatesInList );
-            assert( Map_SuperTableCompareGatesInList( ppSupers, ppSupers + nSupers - 1 ) <= 0 );
-            // link them in the reverse order
-            for ( k = 0; k < nSupers; k++ )
-            {
-                ppSupers[k]->pNext = pEnt->pGates;
-                pEnt->pGates = ppSupers[k];
-            }
-            // save the number of supergates in the list
-            pEnt->pGates->nSupers = nSupers;
-        }
-    FREE( ppSupers );
-}
-
-////////////////////////////////////////////////////////////////////////
-///                       END OF FILE                                ///
-////////////////////////////////////////////////////////////////////////
-
-
diff --git a/abc70930/src/map/mapper/mapperTime.c b/abc70930/src/map/mapper/mapperTime.c
deleted file mode 100644
index cc4173cf..00000000
--- a/abc70930/src/map/mapper/mapperTime.c
+++ /dev/null
@@ -1,510 +0,0 @@
-/**CFile****************************************************************
-
-  FileName    [mapperTime.c]
-
-  PackageName [MVSIS 1.3: Multi-valued logic synthesis system.]
-
-  Synopsis    [Generic technology mapping engine.]
-
-  Author      [MVSIS Group]
-  
-  Affiliation [UC Berkeley]
-
-  Date        [Ver. 2.0. Started - June 1, 2004.]
-
-  Revision    [$Id: mapperTime.c,v 1.3 2005/03/02 02:35:54 alanmi Exp $]
-
-***********************************************************************/
-
-#include "mapperInt.h"
-
-////////////////////////////////////////////////////////////////////////
-///                        DECLARATIONS                              ///
-////////////////////////////////////////////////////////////////////////
-
-static void  Map_TimePropagateRequired( Map_Man_t * p, Map_NodeVec_t * vNodes );
-static void  Map_TimePropagateRequiredPhase( Map_Man_t * p, Map_Node_t * pNode, int fPhase );
-static float Map_MatchComputeReqTimes( Map_Cut_t * pCut, int fPhase, Map_Time_t * ptArrRes );
-
-////////////////////////////////////////////////////////////////////////
-///                     FUNCTION DEFINITIONS                         ///
-////////////////////////////////////////////////////////////////////////
-
-/**function*************************************************************
-
-  synopsis    [Computes the exact area associated with the cut.]
-
-  description []
-               
-  sideeffects []
-
-  seealso     []
-
-***********************************************************************/
-float Map_TimeMatchWithInverter( Map_Man_t * p, Map_Match_t * pMatch )
-{
-    Map_Time_t tArrInv;
-    tArrInv.Fall  = pMatch->tArrive.Rise + p->pSuperLib->tDelayInv.Fall;
-    tArrInv.Rise  = pMatch->tArrive.Fall + p->pSuperLib->tDelayInv.Rise;
-    tArrInv.Worst = MAP_MAX( tArrInv.Rise, tArrInv.Fall ); 
-    return tArrInv.Worst;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Computes the arrival times of the cut recursively.]
-
-  Description [When computing the arrival time for the previously unused 
-  cuts, their arrival time may be incorrect because their fanins have 
-  incorrect arrival time. This procedure is called to fix this problem.]
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Map_TimeCutComputeArrival_rec( Map_Cut_t * pCut, int fPhase )
-{
-    int i, fPhaseLeaf;
-    for ( i = 0; i < pCut->nLeaves; i++ )
-    {
-        fPhaseLeaf = Map_CutGetLeafPhase( pCut, fPhase, i );
-        if ( pCut->ppLeaves[i]->nRefAct[fPhaseLeaf] > 0 )
-            continue;
-        Map_TimeCutComputeArrival_rec( pCut->ppLeaves[i]->pCutBest[fPhaseLeaf], fPhaseLeaf );
-    }
-    Map_TimeCutComputeArrival( NULL, pCut, fPhase, MAP_FLOAT_LARGE );
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Computes the arrival times of the cut.]
-
-  Description [Computes the arrival times of the cut if it is implemented using 
-  the given supergate with the given phase. Uses the constraint-type specification
-  of rise/fall arrival times.]
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-float Map_TimeCutComputeArrival( Map_Node_t * pNode, Map_Cut_t * pCut, int fPhase, float tWorstLimit )
-{
-    Map_Match_t * pM = pCut->M + fPhase;
-    Map_Super_t * pSuper = pM->pSuperBest;
-    unsigned uPhaseTot = pM->uPhaseBest;
-    Map_Time_t * ptArrRes = &pM->tArrive;
-    Map_Time_t * ptArrIn;
-    bool fPinPhase;
-    float tDelay;
-    int i;
-
-    ptArrRes->Rise  = ptArrRes->Fall = 0.0;
-    ptArrRes->Worst = MAP_FLOAT_LARGE;
-    for ( i = pCut->nLeaves - 1; i >= 0; i-- )
-    {
-        // get the phase of the given pin
-        fPinPhase = ((uPhaseTot & (1 << i)) == 0);
-        ptArrIn = pCut->ppLeaves[i]->tArrival + fPinPhase;
-
-        // get the rise of the output due to rise of the inputs
-        if ( pSuper->tDelaysR[i].Rise > 0 )
-        {
-            tDelay = ptArrIn->Rise + pSuper->tDelaysR[i].Rise;
-            if ( tDelay > tWorstLimit )
-                return MAP_FLOAT_LARGE;
-            if ( ptArrRes->Rise < tDelay )
-                ptArrRes->Rise = tDelay;
-        }
-
-        // get the rise of the output due to fall of the inputs
-        if ( pSuper->tDelaysR[i].Fall > 0 )
-        {
-            tDelay = ptArrIn->Fall + pSuper->tDelaysR[i].Fall;
-            if ( tDelay > tWorstLimit )
-                return MAP_FLOAT_LARGE;
-            if ( ptArrRes->Rise < tDelay )
-                ptArrRes->Rise = tDelay;
-        }
-
-        // get the fall of the output due to rise of the inputs
-        if ( pSuper->tDelaysF[i].Rise > 0 )
-        {
-            tDelay = ptArrIn->Rise + pSuper->tDelaysF[i].Rise;
-            if ( tDelay > tWorstLimit )
-                return MAP_FLOAT_LARGE;
-            if ( ptArrRes->Fall < tDelay )
-                ptArrRes->Fall = tDelay;
-        }
-
-        // get the fall of the output due to fall of the inputs
-        if ( pSuper->tDelaysF[i].Fall > 0 )
-        {
-            tDelay = ptArrIn->Fall + pSuper->tDelaysF[i].Fall;
-            if ( tDelay > tWorstLimit )
-                return MAP_FLOAT_LARGE;
-            if ( ptArrRes->Fall < tDelay )
-                ptArrRes->Fall = tDelay;
-        }
-    }
-    // return the worst-case of rise/fall arrival times
-    ptArrRes->Worst = MAP_MAX(ptArrRes->Rise, ptArrRes->Fall);
-    return ptArrRes->Worst;
-}
-
-
-/**Function*************************************************************
-
-  Synopsis    [Computes the maximum arrival times.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-float Map_TimeComputeArrivalMax( Map_Man_t * p )
-{
-    float tReqMax, tReq;
-    int i, fPhase;
-    // get the critical PO arrival time
-    tReqMax = -MAP_FLOAT_LARGE;
-    for ( i = 0; i < p->nOutputs; i++ )
-    {
-        if ( Map_NodeIsConst(p->pOutputs[i]) )
-            continue;
-        fPhase  = !Map_IsComplement(p->pOutputs[i]);
-        tReq    = Map_Regular(p->pOutputs[i])->tArrival[fPhase].Worst;
-        tReqMax = MAP_MAX( tReqMax, tReq );
-    }
-    return tReqMax;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Computes the required times of all nodes.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Map_TimeComputeRequiredGlobal( Map_Man_t * p )
-{
-    p->fRequiredGlo = Map_TimeComputeArrivalMax( p );
-    // update the required times according to the target
-    if ( p->DelayTarget != -1 )
-    {
-        if ( p->fRequiredGlo > p->DelayTarget + p->fEpsilon )
-        {
-            if ( p->fMappingMode == 1 )
-                printf( "Cannot meet the target required times (%4.2f). Continue anyway.\n", p->DelayTarget );
-        }
-        else if ( p->fRequiredGlo < p->DelayTarget - p->fEpsilon )
-        {
-            if ( p->fMappingMode == 1 )
-                printf( "Relaxing the required times from (%4.2f) to the target (%4.2f).\n", p->fRequiredGlo, p->DelayTarget );
-            p->fRequiredGlo = p->DelayTarget;
-        }
-    }
-    Map_TimeComputeRequired( p, p->fRequiredGlo );
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Computes the required times of all nodes.]
-
-  Description [This procedure assumes that the nodes used in the mapping
-  are collected in p->vMapping.]
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Map_TimeComputeRequired( Map_Man_t * p, float fRequired )
-{
-    Map_Time_t * ptTime;
-    int fPhase, i;
-
-    // clean the required times
-    for ( i = 0; i < p->vAnds->nSize; i++ )
-    {
-        p->vAnds->pArray[i]->tRequired[0].Rise = MAP_FLOAT_LARGE;
-        p->vAnds->pArray[i]->tRequired[0].Fall = MAP_FLOAT_LARGE;
-        p->vAnds->pArray[i]->tRequired[0].Worst = MAP_FLOAT_LARGE;
-        p->vAnds->pArray[i]->tRequired[1].Rise = MAP_FLOAT_LARGE;
-        p->vAnds->pArray[i]->tRequired[1].Fall = MAP_FLOAT_LARGE;
-        p->vAnds->pArray[i]->tRequired[1].Worst = MAP_FLOAT_LARGE;
-    }
-
-    // set the required times for the POs
-    for ( i = 0; i < p->nOutputs; i++ )
-    {
-        fPhase  = !Map_IsComplement(p->pOutputs[i]);
-        ptTime  =  Map_Regular(p->pOutputs[i])->tRequired + fPhase;
-        ptTime->Rise = ptTime->Fall = ptTime->Worst = fRequired;
-    }
-
-    // sorts the nodes in the decreasing order of levels
-    // this puts the nodes in reverse topological order
-//    Map_MappingSortByLevel( p, p->vMapping );
-    // the array is already sorted by construction in Map_MappingSetRefs()
-
-    Map_TimePropagateRequired( p, p->vMapping );
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Computes the required times of the given nodes.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Map_TimePropagateRequired( Map_Man_t * p, Map_NodeVec_t * vNodes )
-{
-    Map_Node_t * pNode;
-    Map_Time_t tReqOutTest, * ptReqOutTest = &tReqOutTest;
-    Map_Time_t * ptReqIn, * ptReqOut;
-    int fPhase, k;
-
-    // go through the nodes in the reverse topological order
-    for ( k = 0; k < vNodes->nSize; k++ )
-    {
-        pNode = vNodes->pArray[k];
-
-        // this computation works for regular nodes only
-        assert( !Map_IsComplement(pNode) );
-        // at least one phase should be mapped
-        assert( pNode->pCutBest[0] != NULL || pNode->pCutBest[1] != NULL );
-        // the node should be used in the currently assigned mapping
-        assert( pNode->nRefAct[0] > 0 || pNode->nRefAct[1] > 0 );
-
-        // if one of the cuts is not given, project the required times from the other cut
-        if ( pNode->pCutBest[0] == NULL || pNode->pCutBest[1] == NULL )
-        {
-//            assert( 0 );
-            // get the missing phase 
-            fPhase = (pNode->pCutBest[1] == NULL); 
-            // check if the missing phase is needed in the mapping
-            if ( pNode->nRefAct[fPhase] > 0 )
-            {
-                // get the pointers to the required times of the missing phase
-                ptReqOut = pNode->tRequired +  fPhase;
-//                assert( ptReqOut->Fall < MAP_FLOAT_LARGE );
-                // get the pointers to the required times of the present phase
-                ptReqIn  = pNode->tRequired + !fPhase;
-                // propagate the required times from the missing phase to the present phase
-    //            tArrInv.Fall  = pMatch->tArrive.Rise + p->pSuperLib->tDelayInv.Fall;
-    //            tArrInv.Rise  = pMatch->tArrive.Fall + p->pSuperLib->tDelayInv.Rise;
-                ptReqIn->Fall = MAP_MIN( ptReqIn->Fall, ptReqOut->Rise - p->pSuperLib->tDelayInv.Rise );
-                ptReqIn->Rise = MAP_MIN( ptReqIn->Rise, ptReqOut->Fall - p->pSuperLib->tDelayInv.Fall );
-            }
-        }
-
-        // finalize the worst case computation
-        pNode->tRequired[0].Worst = MAP_MIN( pNode->tRequired[0].Fall, pNode->tRequired[0].Rise );
-        pNode->tRequired[1].Worst = MAP_MIN( pNode->tRequired[1].Fall, pNode->tRequired[1].Rise );
-
-        // skip the PIs
-        if ( !Map_NodeIsAnd(pNode) )
-            continue;
-
-        // propagate required times of different phases of the node
-        // the ordering of phases does not matter since they are mapped independently
-        if ( pNode->pCutBest[0] && pNode->tRequired[0].Worst < MAP_FLOAT_LARGE )
-            Map_TimePropagateRequiredPhase( p, pNode, 0 );
-        if ( pNode->pCutBest[1] && pNode->tRequired[1].Worst < MAP_FLOAT_LARGE )
-            Map_TimePropagateRequiredPhase( p, pNode, 1 );
-    }
-
-    // in the end, we verify the required times
-    // for this, we compute the arrival times of the outputs of each phase 
-    // of the supergates using the fanins' required times as the fanins' arrival times
-    // the resulting arrival time of the supergate should be less than the actual required time
-    for ( k = 0; k < vNodes->nSize; k++ )
-    {
-        pNode = vNodes->pArray[k];
-        if ( !Map_NodeIsAnd(pNode) )
-            continue;
-        // verify that the required times are propagated correctly
-//        if ( pNode->pCutBest[0] && (pNode->nRefAct[0] > 0 || pNode->pCutBest[1] == NULL) )
-        if ( pNode->pCutBest[0] && pNode->tRequired[0].Worst < MAP_FLOAT_LARGE )
-        {
-            Map_MatchComputeReqTimes( pNode->pCutBest[0], 0, ptReqOutTest );
-            assert( ptReqOutTest->Rise < pNode->tRequired[0].Rise + p->fEpsilon );
-            assert( ptReqOutTest->Fall < pNode->tRequired[0].Fall + p->fEpsilon );
-        }
-//        if ( pNode->pCutBest[1] && (pNode->nRefAct[1] > 0 || pNode->pCutBest[0] == NULL) )
-        if ( pNode->pCutBest[1] && pNode->tRequired[1].Worst < MAP_FLOAT_LARGE )
-        {
-            Map_MatchComputeReqTimes( pNode->pCutBest[1], 1, ptReqOutTest );
-            assert( ptReqOutTest->Rise < pNode->tRequired[1].Rise + p->fEpsilon );
-            assert( ptReqOutTest->Fall < pNode->tRequired[1].Fall + p->fEpsilon );
-        }
-    }
-
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Computes the required times of the given nodes.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Map_TimePropagateRequiredPhase( Map_Man_t * p, Map_Node_t * pNode, int fPhase )
-{
-    Map_Time_t * ptReqIn, * ptReqOut;
-    Map_Cut_t * pCut;
-    Map_Super_t * pSuper;
-    float tNewReqTime;
-    unsigned uPhase;
-    int fPinPhase, i;
-
-    // get the cut to be propagated
-    pCut = pNode->pCutBest[fPhase];
-    assert( pCut != NULL );
-    // get the supergate and its polarity
-    pSuper  = pCut->M[fPhase].pSuperBest;
-    uPhase  = pCut->M[fPhase].uPhaseBest;
-    // get the required time of the output of the supergate
-    ptReqOut = pNode->tRequired + fPhase;
-    // set the required time of the children
-    for ( i = 0; i < pCut->nLeaves; i++ )
-    {
-        // get the phase of the given pin of the supergate
-        fPinPhase = ((uPhase & (1 << i)) == 0);
-        ptReqIn = pCut->ppLeaves[i]->tRequired + fPinPhase;
-        assert( pCut->ppLeaves[i]->nRefAct[2] > 0 );
-
-        // get the rise of the output due to rise of the inputs
-//            if ( ptArrOut->Rise < ptArrIn->Rise + pSuper->tDelaysR[i].Rise )
-//                ptArrOut->Rise = ptArrIn->Rise + pSuper->tDelaysR[i].Rise;
-        if ( pSuper->tDelaysR[i].Rise > 0 )
-        {
-            tNewReqTime = ptReqOut->Rise - pSuper->tDelaysR[i].Rise;
-            ptReqIn->Rise = MAP_MIN( ptReqIn->Rise, tNewReqTime );
-        }
-
-        // get the rise of the output due to fall of the inputs
-//            if ( ptArrOut->Rise < ptArrIn->Fall + pSuper->tDelaysR[i].Fall )
-//                ptArrOut->Rise = ptArrIn->Fall + pSuper->tDelaysR[i].Fall;
-        if ( pSuper->tDelaysR[i].Fall > 0 )
-        {
-            tNewReqTime = ptReqOut->Rise - pSuper->tDelaysR[i].Fall;
-            ptReqIn->Fall = MAP_MIN( ptReqIn->Fall, tNewReqTime );
-        }
-
-        // get the fall of the output due to rise of the inputs
-//            if ( ptArrOut->Fall < ptArrIn->Rise + pSuper->tDelaysF[i].Rise )
-//                ptArrOut->Fall = ptArrIn->Rise + pSuper->tDelaysF[i].Rise;
-        if ( pSuper->tDelaysF[i].Rise > 0 )
-        {
-            tNewReqTime = ptReqOut->Fall - pSuper->tDelaysF[i].Rise;
-            ptReqIn->Rise = MAP_MIN( ptReqIn->Rise, tNewReqTime );
-        }
-
-        // get the fall of the output due to fall of the inputs
-//            if ( ptArrOut->Fall < ptArrIn->Fall + pSuper->tDelaysF[i].Fall )
-//                ptArrOut->Fall = ptArrIn->Fall + pSuper->tDelaysF[i].Fall;
-        if ( pSuper->tDelaysF[i].Fall > 0 )
-        {
-            tNewReqTime = ptReqOut->Fall - pSuper->tDelaysF[i].Fall;
-            ptReqIn->Fall = MAP_MIN( ptReqIn->Fall, tNewReqTime );
-        }
-    }
-
-    // compare the required times with the arrival times
-    assert( pNode->tArrival[fPhase].Rise < ptReqOut->Rise + p->fEpsilon );
-    assert( pNode->tArrival[fPhase].Fall < ptReqOut->Fall + p->fEpsilon );
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Computes the arrival times of the cut.]
-
-  Description [Computes the arrival times of the cut if it is implemented using 
-  the given supergate with the given phase. Uses the constraint-type specification
-  of rise/fall arrival times.]
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-float Map_MatchComputeReqTimes( Map_Cut_t * pCut, int fPhase, Map_Time_t * ptArrRes )
-{
-    Map_Time_t * ptArrIn;
-    Map_Super_t * pSuper;
-    unsigned uPhaseTot;
-    int fPinPhase, i;
-    float tDelay;
-
-    // get the supergate and the phase
-    pSuper = pCut->M[fPhase].pSuperBest;
-    uPhaseTot = pCut->M[fPhase].uPhaseBest;
-
-    // propagate the arrival times 
-    ptArrRes->Rise = ptArrRes->Fall = -MAP_FLOAT_LARGE;
-    for ( i = 0; i < pCut->nLeaves; i++ )
-    {
-        // get the phase of the given pin
-        fPinPhase = ((uPhaseTot & (1 << i)) == 0);
-        ptArrIn = pCut->ppLeaves[i]->tRequired + fPinPhase;
-//        assert( ptArrIn->Worst < MAP_FLOAT_LARGE );
-
-        // get the rise of the output due to rise of the inputs
-        if ( pSuper->tDelaysR[i].Rise > 0 )
-        {
-            tDelay = ptArrIn->Rise + pSuper->tDelaysR[i].Rise;
-            if ( ptArrRes->Rise < tDelay )
-                ptArrRes->Rise = tDelay;
-        }
-
-        // get the rise of the output due to fall of the inputs
-        if ( pSuper->tDelaysR[i].Fall > 0 )
-        {
-            tDelay = ptArrIn->Fall + pSuper->tDelaysR[i].Fall;
-            if ( ptArrRes->Rise < tDelay )
-                ptArrRes->Rise = tDelay;
-        }
-
-        // get the fall of the output due to rise of the inputs
-        if ( pSuper->tDelaysF[i].Rise > 0 )
-        {
-            tDelay = ptArrIn->Rise + pSuper->tDelaysF[i].Rise;
-            if ( ptArrRes->Fall < tDelay )
-                ptArrRes->Fall = tDelay;
-        }
-
-        // get the fall of the output due to fall of the inputs
-        if ( pSuper->tDelaysF[i].Fall > 0 )
-        {
-            tDelay = ptArrIn->Fall + pSuper->tDelaysF[i].Fall;
-            if ( ptArrRes->Fall < tDelay )
-                ptArrRes->Fall = tDelay;
-        }
-    }
-    // return the worst-case of rise/fall arrival times
-    return MAP_MAX(ptArrRes->Rise, ptArrRes->Fall);
-}
-
-
-////////////////////////////////////////////////////////////////////////
-///                       END OF FILE                                ///
-////////////////////////////////////////////////////////////////////////
-
-
diff --git a/abc70930/src/map/mapper/mapperTree.c b/abc70930/src/map/mapper/mapperTree.c
deleted file mode 100644
index ef66082d..00000000
--- a/abc70930/src/map/mapper/mapperTree.c
+++ /dev/null
@@ -1,818 +0,0 @@
-/**CFile****************************************************************
-
-  FileName    [mapperTree.c]
-
-  PackageName [MVSIS 1.3: Multi-valued logic synthesis system.]
-
-  Synopsis    [Generic technology mapping engine.]
-
-  Author      [MVSIS Group]
-  
-  Affiliation [UC Berkeley]
-
-  Date        [Ver. 2.0. Started - June 1, 2004.]
-
-  Revision    [$Id: mapperTree.c,v 1.9 2005/01/23 06:59:45 alanmi Exp $]
-
-***********************************************************************/
-
-#ifdef __linux__
-#include <libgen.h>
-#endif
-
-#include "mapperInt.h"
-
-////////////////////////////////////////////////////////////////////////
-///                        DECLARATIONS                              ///
-////////////////////////////////////////////////////////////////////////
-
-static int           Map_LibraryReadFileTree( Map_SuperLib_t * pLib, FILE * pFile, char *pFileName );
-static Map_Super_t * Map_LibraryReadGateTree( Map_SuperLib_t * pLib, char * pBuffer, int Number, int nVars );
-static int           Map_LibraryDeriveGateInfo( Map_SuperLib_t * pLib, st_table * tExcludeGate );
-static void          Map_LibraryAddFaninDelays( Map_SuperLib_t * pLib, Map_Super_t * pGate, Map_Super_t * pFanin, Mio_Pin_t * pPin );
-static int           Map_LibraryGetMaxSuperPi_rec( Map_Super_t * pGate );
-static unsigned      Map_LibraryGetGateSupp_rec( Map_Super_t * pGate );
-
-// fanout limits
-extern const int s_MapFanoutLimits[10] = { 1/*0*/, 10/*1*/, 5/*2*/, 2/*3*/, 1/*4*/, 1/*5*/, 1/*6*/ };
-
-////////////////////////////////////////////////////////////////////////
-///                     FUNCTION DEFINITIONS                         ///
-////////////////////////////////////////////////////////////////////////
-
-/**Function*************************************************************
-
-  Synopsis    [Reads the supergate library from file.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Map_LibraryReadTree( Map_SuperLib_t * pLib, char * pFileName, char * pExcludeFile )
-{
-    FILE * pFile;
-    int Status, num;
-    Abc_Frame_t * pAbc;
-    st_table * tExcludeGate = 0;
-
-    // read the beginning of the file
-    assert( pLib->pGenlib == NULL );
-    pFile = Io_FileOpen( pFileName, "open_path", "r", 1 );
-//    pFile = fopen( pFileName, "r" ); 
-    if ( pFile == NULL )
-    {
-        printf( "Cannot open input file \"%s\".\n", pFileName );
-        return 0;
-    }
-
-    if ( pExcludeFile )
-    {
-        pAbc = Abc_FrameGetGlobalFrame();
-        
-        tExcludeGate = st_init_table(strcmp, st_strhash);
-        if ( (num = Mio_LibraryReadExclude( pAbc, pExcludeFile, tExcludeGate )) == -1 )
-        {
-            st_free_table( tExcludeGate );
-            tExcludeGate = 0;
-            return 0;
-        }
-
-        fprintf ( Abc_FrameReadOut( pAbc ), "Read %d gates from exclude file\n", num );
-    }
-    
-    Status = Map_LibraryReadFileTree( pLib, pFile, pFileName );
-    fclose( pFile );
-    if ( Status == 0 )
-        return 0;
-    // prepare the info about the library
-    return Map_LibraryDeriveGateInfo( pLib, tExcludeGate );
-}
-
-
-/**Function*************************************************************
-
-  Synopsis    [Reads the library file.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Map_LibraryReadFileTree( Map_SuperLib_t * pLib, FILE * pFile, char *pFileName )
-{
-    ProgressBar * pProgress;
-    char pBuffer[5000], pLibFile[5000];
-    FILE * pFileGen;
-    Map_Super_t * pGate;
-    char * pTemp = 0, * pLibName;
-    int nCounter, k, i;
-
-    // skip empty and comment lines
-    while ( fgets( pBuffer, 5000, pFile ) != NULL )
-    {
-        // skip leading spaces
-        for ( pTemp = pBuffer; *pTemp == ' ' || *pTemp == '\r' || *pTemp == '\n'; pTemp++ );
-        // skip comment lines and empty lines
-        if ( *pTemp != 0 && *pTemp != '#' )
-            break;
-    }
-    
-    // get the genlib file name (base)
-    pLibName = strtok( pTemp, " \t\r\n" );
-    
-    if ( strcmp( pLibName, "GATE" ) == 0 )
-    {
-        printf( "The input file \"%s\" looks like a GENLIB file and not a supergate library file.\n", pLib->pName );
-        return 0;
-    }
-    
-
-    // now figure out the directory if any in the pFileName
-#ifdef __linux__
-    snprintf( pLibFile, 5000, "%s/%s", dirname(strdup(pFileName)), pLibName ); 
-#else
-    {
-        char * pStr;
-        strcpy( pLibFile, pFileName );
-        pStr = pLibFile + strlen(pBuffer) - 1;
-        while ( pStr > pLibFile && *pStr != '\\' && *pStr != '/' )
-            pStr--;
-        if ( pStr == pLibFile )
-            strcpy( pLibFile, pLibName );
-        else
-            sprintf( pStr, "/%s", pLibName );
-    }
-#endif
-    
-    pFileGen = Io_FileOpen( pLibFile, "open_path", "r", 1 );
-//    pFileGen = fopen( pLibFile, "r" ); 
-    if ( pFileGen == NULL )
-    {
-        printf( "Cannot open the GENLIB file \"%s\".\n", pLibFile );
-        return 0;
-    }
-    fclose( pFileGen );
-
-    // read the genlib library
-    pLib->pGenlib = Mio_LibraryRead( Abc_FrameGetGlobalFrame(), pLibFile, 0, 0 );
-    if ( pLib->pGenlib == NULL )
-    {
-        printf( "Cannot read GENLIB file \"%s\".\n", pLibFile );
-        return 0;
-    }
-
-    // read the number of variables
-    fscanf( pFile, "%d\n", &pLib->nVarsMax );
-    if ( pLib->nVarsMax < 2 || pLib->nVarsMax > 10 )
-    {
-        printf( "Suspicious number of variables (%d).\n", pLib->nVarsMax );
-        return 0;
-    }
-
-    // read the number of gates
-    fscanf( pFile, "%d\n", &pLib->nSupersReal );
-    if ( pLib->nSupersReal < 1 || pLib->nSupersReal > 10000000 )
-    {
-        printf( "Suspicious number of gates (%d).\n", pLib->nSupersReal );
-        return 0;
-    }
-
-    // read the number of lines
-    fscanf( pFile, "%d\n", &pLib->nLines );
-    if ( pLib->nLines < 1 || pLib->nLines > 10000000 )
-    {
-        printf( "Suspicious number of lines (%d).\n", pLib->nLines );
-        return 0;
-    }
-
-    // allocate room for supergate pointers
-    pLib->ppSupers = ALLOC( Map_Super_t *, pLib->nLines + 10000 );
-
-    // create the elementary supergates
-    for ( i = 0; i < pLib->nVarsMax; i++ )
-    {
-        // get a new gate
-        pGate = (Map_Super_t *)Extra_MmFixedEntryFetch( pLib->mmSupers );
-        memset( pGate, 0, sizeof(Map_Super_t) );
-        // assign the elementary variable, the truth table, and the delays
-        pGate->Num = i;
-        // set the truth table
-        pGate->uTruth[0] = pLib->uTruths[i][0];
-        pGate->uTruth[1] = pLib->uTruths[i][1];
-        // set the arrival times of all input to non-existent delay
-        for ( k = 0; k < pLib->nVarsMax; k++ )
-        {
-            pGate->tDelaysR[k].Rise = pGate->tDelaysR[k].Fall = MAP_NO_VAR;
-            pGate->tDelaysF[k].Rise = pGate->tDelaysF[k].Fall = MAP_NO_VAR;
-        }
-        // set an existent arrival time for rise and fall
-        pGate->tDelaysR[i].Rise = 0.0;
-        pGate->tDelaysF[i].Fall = 0.0;
-        // set the gate
-        pLib->ppSupers[i] = pGate;
-    }
-
-    // read the lines
-    nCounter = pLib->nVarsMax;
-    pProgress = Extra_ProgressBarStart( stdout, pLib->nLines );
-    while ( fgets( pBuffer, 5000, pFile ) != NULL )
-    {
-        for ( pTemp = pBuffer; *pTemp == ' ' || *pTemp == '\r' || *pTemp == '\n'; pTemp++ );
-        if ( pTemp[0] == '\0' )
-            continue;
-//        if ( pTemp[0] == 'a' || pTemp[2] == 'a' )
-//        {
-//            pLib->nLines--;
-//            continue;
-//        }
-
-        // get the gate
-        pGate = Map_LibraryReadGateTree( pLib, pTemp, nCounter, pLib->nVarsMax );
-        if ( pGate == NULL )
-        {
-            Extra_ProgressBarStop( pProgress );
-            return 0;
-        }
-        pLib->ppSupers[nCounter++] = pGate;
-        // later we will derive: truth table, delays, area, number of component gates, etc
-
-        // update the progress bar
-        Extra_ProgressBarUpdate( pProgress, nCounter, NULL );
-    }
-    Extra_ProgressBarStop( pProgress );
-    if ( nCounter != pLib->nLines )
-        printf( "The number of lines read (%d) is different what the file says (%d).\n", nCounter, pLib->nLines );
-    pLib->nSupersAll = nCounter;
-    // count the number of real supergates
-    nCounter = 0;
-    for ( k = 0; k < pLib->nLines; k++ )
-        nCounter += pLib->ppSupers[k]->fSuper;
-    if ( nCounter != pLib->nSupersReal )
-        printf( "The number of gates read (%d) is different what the file says (%d).\n", nCounter, pLib->nSupersReal );
-    pLib->nSupersReal = nCounter;
-    return 1;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Reads one gate.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-Map_Super_t * Map_LibraryReadGateTree( Map_SuperLib_t * pLib, char * pBuffer, int Number, int nVarsMax )
-{
-    Map_Super_t * pGate;
-    char * pTemp;
-    int i, Num;
-
-    // start and clean the gate
-    pGate = (Map_Super_t *)Extra_MmFixedEntryFetch( pLib->mmSupers );
-    memset( pGate, 0, sizeof(Map_Super_t) );
-
-    // set the gate number
-    pGate->Num = Number;
-
-    // read the mark
-    pTemp = strtok( pBuffer, " " );
-    if ( pTemp[0] == '*' )
-    {
-        pGate->fSuper = 1;
-        pTemp = strtok( NULL, " " );
-    }
-
-    // read the root gate
-    pGate->pRoot = Mio_LibraryReadGateByName( pLib->pGenlib, pTemp );
-    if ( pGate->pRoot == NULL )
-    {
-        printf( "Cannot read the root gate names %s.\n", pTemp );
-        return NULL;
-    }
-    // set the max number of fanouts
-    pGate->nFanLimit = s_MapFanoutLimits[ Mio_GateReadInputs(pGate->pRoot) ];
-
-    // read the pin-to-pin delay
-    for ( i = 0; ( pTemp = strtok( NULL, " \n\0" ) ); i++ )
-    {
-        if ( pTemp[0] == '#' )
-            break;
-        if ( i == nVarsMax )
-        {
-            printf( "There are too many entries on the line.\n" );
-            return NULL;
-        }
-        Num = atoi(pTemp);
-        if ( Num < 0 )
-        {
-            printf( "The number of a child supergate is negative.\n" );
-            return NULL;
-        }
-        if ( Num > pLib->nLines )
-        {
-            printf( "The number of a child supergate (%d) exceeded the number of lines (%d).\n", 
-                Num, pLib->nLines );
-            return NULL;
-        }
-        pGate->pFanins[i] = pLib->ppSupers[Num];
-    }
-    pGate->nFanins = i;
-    if ( pGate->nFanins != (unsigned)Mio_GateReadInputs(pGate->pRoot) )
-    {
-        printf( "The number of fanins of a root gate is wrong.\n" );
-        return NULL;
-    }
-
-    // save the gate name, just in case
-    if ( pTemp && pTemp[0] == '#' )
-    {
-        if ( pTemp[1] == 0 )
-            pTemp = strtok( NULL, " \n\0" );
-        else // skip spaces
-            for ( pTemp++; *pTemp == ' '; pTemp++ );
-        // save the formula
-        pGate->pFormula = Extra_MmFlexEntryFetch( pLib->mmForms, strlen(pTemp)+1 );
-        strcpy( pGate->pFormula, pTemp );
-    }
-    // check the rest of the string
-    pTemp = strtok( NULL, " \n\0" );
-    if ( pTemp != NULL )
-        printf( "The following trailing symbols found \"%s\".\n", pTemp );
-    return pGate;
-}
-
-
-/**Function*************************************************************
-
-  Synopsis    [Derives information about the library.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Map_LibraryDeriveGateInfo( Map_SuperLib_t * pLib, st_table * tExcludeGate )
-{
-    Map_Super_t * pGate, * pFanin;
-    Mio_Pin_t * pPin;
-    unsigned uCanon[2];
-    unsigned uTruths[6][2];
-    int i, k, nRealVars;
-
-    // set all the derivable info related to the supergates
-    for ( i = pLib->nVarsMax; i < (int)pLib->nLines; i++ )
-    {
-        pGate = pLib->ppSupers[i];
-
-        if ( tExcludeGate )
-        {
-            if ( st_is_member( tExcludeGate, Mio_GateReadName( pGate->pRoot ) ) )
-                pGate->fExclude = 1;
-            for ( k = 0; k < (int)pGate->nFanins; k++ )
-            {
-                pFanin = pGate->pFanins[k];
-                if ( pFanin->fExclude )
-                {
-                    pGate->fExclude = 1;
-                    continue;
-                }
-            }
-        }
-        
-        // collect the truth tables of the fanins
-        for ( k = 0; k < (int)pGate->nFanins; k++ )
-        {
-            pFanin = pGate->pFanins[k];
-            uTruths[k][0] = pFanin->uTruth[0];
-            uTruths[k][1] = pFanin->uTruth[1];
-        }
-        // derive the new truth table
-        Mio_DeriveTruthTable( pGate->pRoot, uTruths, pGate->nFanins, 6, pGate->uTruth );
-
-        // set the initial delays of the supergate
-        for ( k = 0; k < pLib->nVarsMax; k++ )
-        {
-            pGate->tDelaysR[k].Rise = pGate->tDelaysR[k].Fall = MAP_NO_VAR;
-            pGate->tDelaysF[k].Rise = pGate->tDelaysF[k].Fall = MAP_NO_VAR;
-        }
-        // get the linked list of pins for the given root gate
-        pPin = Mio_GateReadPins( pGate->pRoot );
-        // update the initial delay of the supergate using info from the corresponding pin
-        for ( k = 0; k < (int)pGate->nFanins; k++, pPin = Mio_PinReadNext(pPin) )
-        {
-            // if there is no corresponding pin, this is a bug, return fail
-            if ( pPin == NULL )
-            {
-                printf( "There are less pins than gate inputs.\n" );
-                return 0;
-            }
-            // update the delay information of k-th fanins info from the corresponding pin
-            Map_LibraryAddFaninDelays( pLib, pGate, pGate->pFanins[k], pPin );
-        }
-        // if there are some pins left, this is a bug, return fail
-        if ( pPin != NULL )
-        {
-            printf( "There are more pins than gate inputs.\n" );
-            return 0;
-        }
-        // find the max delay
-        pGate->tDelayMax.Rise = pGate->tDelayMax.Fall = MAP_NO_VAR;
-        for ( k = 0; k < pLib->nVarsMax; k++ )
-        {
-            // the rise of the output depends on the rise and fall of the output
-            if ( pGate->tDelayMax.Rise < pGate->tDelaysR[k].Rise )
-                pGate->tDelayMax.Rise = pGate->tDelaysR[k].Rise;
-            if ( pGate->tDelayMax.Rise < pGate->tDelaysR[k].Fall )
-                pGate->tDelayMax.Rise = pGate->tDelaysR[k].Fall;
-            // the fall of the output depends on the rise and fall of the output
-            if ( pGate->tDelayMax.Fall < pGate->tDelaysF[k].Rise )
-                pGate->tDelayMax.Fall = pGate->tDelaysF[k].Rise;
-            if ( pGate->tDelayMax.Fall < pGate->tDelaysF[k].Fall )
-                pGate->tDelayMax.Fall = pGate->tDelaysF[k].Fall;
-
-            pGate->tDelaysF[k].Worst = MAP_MAX( pGate->tDelaysF[k].Fall, pGate->tDelaysF[k].Rise );
-            pGate->tDelaysR[k].Worst = MAP_MAX( pGate->tDelaysR[k].Fall, pGate->tDelaysR[k].Rise );
-        }
-
-        // count gates and area of the supergate
-        pGate->nGates = 1;
-        pGate->Area   = (float)Mio_GateReadArea(pGate->pRoot);
-        for ( k = 0; k < (int)pGate->nFanins; k++ )
-        {
-            pGate->nGates += pGate->pFanins[k]->nGates;
-            pGate->Area   += pGate->pFanins[k]->Area;
-        }
-        // do not add the gate to the table, if this gate is an internal gate
-        // of some supegate and does not correspond to a supergate output
-        if ( ( !pGate->fSuper ) || pGate->fExclude )
-            continue;
-
-        // find the maximum index of a variable in the support of the supergates
-        // this is important for two reasons:
-        // (1) to limit the number of permutations considered for canonicization
-        // (2) to get rid of equivalence phases to speed-up matching
-        nRealVars = Map_LibraryGetMaxSuperPi_rec( pGate ) + 1;
-        assert( nRealVars > 0 && nRealVars <= pLib->nVarsMax );
-        // if there are some problems with this code, try this instead
-//        nRealVars = pLib->nVarsMax;
-
-        // find the N-canonical form of this supergate
-        pGate->nPhases = Map_CanonComputeSlow( pLib->uTruths, pLib->nVarsMax, nRealVars, pGate->uTruth, pGate->uPhases, uCanon );
-        // add the supergate into the table by its N-canonical table
-        Map_SuperTableInsertC( pLib->tTableC, uCanon, pGate );
-/*
-        {
-            int uCanon1, uCanon2;
-            uCanon1 = uCanon[0];
-            pGate->uTruth[0] = ~pGate->uTruth[0];
-            pGate->uTruth[1] = ~pGate->uTruth[1];
-            Map_CanonComputeSlow( pLib->uTruths, pLib->nVarsMax, nRealVars, pGate->uTruth, pGate->uPhases, uCanon );
-            uCanon2 = uCanon[0];
-Rwt_Man5ExploreCount( uCanon1 < uCanon2 ? uCanon1 : uCanon2 );
-        }
-*/
-    }
-    // sort the gates in each line
-    Map_SuperTableSortSupergatesByDelay( pLib->tTableC, pLib->nSupersAll );
-
-    // let the glory be manifest
-//    Map_LibraryPrintTree( pLib );
-    return 1;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Finds the largest PI number in the support of the supergate.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Map_LibraryGetMaxSuperPi_rec( Map_Super_t * pGate )
-{
-    int i, VarCur, VarMax = 0;
-    if ( pGate->pRoot == NULL )
-        return pGate->Num;
-    for ( i = 0; i < (int)pGate->nFanins; i++ )
-    {
-        VarCur = Map_LibraryGetMaxSuperPi_rec( pGate->pFanins[i] );
-        if ( VarMax < VarCur )
-            VarMax = VarCur;
-    }
-    return VarMax;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Finds the largest PI number in the support of the supergate.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-unsigned Map_LibraryGetGateSupp_rec( Map_Super_t * pGate )
-{
-    unsigned uSupport;
-    int i;
-    if ( pGate->pRoot == NULL )
-        return (unsigned)(1 << (pGate->Num));
-    uSupport = 0;
-    for ( i = 0; i < (int)pGate->nFanins; i++ )
-        uSupport |= Map_LibraryGetGateSupp_rec( pGate->pFanins[i] );
-    return uSupport;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Derives the pin-to-pin delay constraints for the supergate.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Map_LibraryAddFaninDelays( Map_SuperLib_t * pLib, Map_Super_t * pGate, Map_Super_t * pFanin, Mio_Pin_t * pPin )
-{
-    Mio_PinPhase_t PinPhase;
-    float tDelayBlockRise, tDelayBlockFall, tDelayPin;
-    bool fMaxDelay = 0;
-    int i;
-
-    // use this node to enable max-delay model
-    if ( fMaxDelay )
-    {
-        float tDelayBlockMax;
-        // get the maximum delay
-        tDelayBlockMax = (float)Mio_PinReadDelayBlockMax(pPin);
-        // go through the supergate inputs
-        for ( i = 0; i < pLib->nVarsMax; i++ )
-        {
-            if ( pFanin->tDelaysR[i].Rise < 0 )
-                continue;
-            tDelayPin = pFanin->tDelaysR[i].Rise + tDelayBlockMax;
-            if ( pGate->tDelaysR[i].Rise < tDelayPin )
-                pGate->tDelaysR[i].Rise = tDelayPin;
-        }
-        // go through the supergate inputs
-        for ( i = 0; i < pLib->nVarsMax; i++ )
-        {
-            if ( pFanin->tDelaysF[i].Fall < 0 )
-                continue;
-            tDelayPin = pFanin->tDelaysF[i].Fall + tDelayBlockMax;
-            if ( pGate->tDelaysF[i].Fall < tDelayPin )
-                pGate->tDelaysF[i].Fall = tDelayPin;
-        }
-        return;
-    }
-
-    // get the interesting parameters of this pin
-    PinPhase = Mio_PinReadPhase(pPin);
-    tDelayBlockRise = (float)Mio_PinReadDelayBlockRise( pPin );  
-    tDelayBlockFall = (float)Mio_PinReadDelayBlockFall( pPin );  
-
-    // update the rise and fall of the output depending on the phase of the pin 
-    if ( PinPhase != MIO_PHASE_INV )  // NONINV phase is present
-    {
-        // the rise of the gate is determined by the rise of the fanin
-        // the fall of the gate is determined by the fall of the fanin
-        for ( i = 0; i < pLib->nVarsMax; i++ )
-        {
-            ////////////////////////////////////////////////////////
-            // consider the rise of the gate
-            ////////////////////////////////////////////////////////
-            // check two types of constraints on the rise of the fanin:
-            // (1) the constraints related to the rise of the PIs
-            // (2) the constraints related to the fall of the PIs
-            if ( pFanin->tDelaysR[i].Rise >= 0 ) // case (1)
-            { // fanin's rise depends on the rise of i-th PI
-                // update the rise of the gate's output
-                if ( pGate->tDelaysR[i].Rise < pFanin->tDelaysR[i].Rise + tDelayBlockRise )
-                    pGate->tDelaysR[i].Rise = pFanin->tDelaysR[i].Rise + tDelayBlockRise;
-            }
-            if ( pFanin->tDelaysR[i].Fall >= 0 ) // case (2)
-            { // fanin's rise depends on the fall of i-th PI
-                // update the rise of the gate's output
-                if ( pGate->tDelaysR[i].Fall < pFanin->tDelaysR[i].Fall + tDelayBlockRise )
-                    pGate->tDelaysR[i].Fall = pFanin->tDelaysR[i].Fall + tDelayBlockRise;
-            }
-            ////////////////////////////////////////////////////////
-
-            ////////////////////////////////////////////////////////
-            // consider the fall of the gate (similar)
-            ////////////////////////////////////////////////////////
-            // check two types of constraints on the fall of the fanin:
-            // (1) the constraints related to the rise of the PIs
-            // (2) the constraints related to the fall of the PIs
-            if ( pFanin->tDelaysF[i].Rise >= 0 ) // case (1) 
-            { 
-                if ( pGate->tDelaysF[i].Rise < pFanin->tDelaysF[i].Rise + tDelayBlockFall )
-                    pGate->tDelaysF[i].Rise = pFanin->tDelaysF[i].Rise + tDelayBlockFall;
-            }
-            if ( pFanin->tDelaysF[i].Fall >= 0 ) // case (2) 
-            { 
-                if ( pGate->tDelaysF[i].Fall < pFanin->tDelaysF[i].Fall + tDelayBlockFall )
-                    pGate->tDelaysF[i].Fall = pFanin->tDelaysF[i].Fall + tDelayBlockFall;
-            }
-            ////////////////////////////////////////////////////////
-        }
-    }
-    if ( PinPhase != MIO_PHASE_NONINV )  // INV phase is present
-    {
-        // the rise of the gate is determined by the fall of the fanin
-        // the fall of the gate is determined by the rise of the fanin
-        for ( i = 0; i < pLib->nVarsMax; i++ )
-        {
-            ////////////////////////////////////////////////////////
-            // consider the rise of the gate's output
-            ////////////////////////////////////////////////////////
-            // check two types of constraints on the fall of the fanin:
-            // (1) the constraints related to the rise of the PIs
-            // (2) the constraints related to the fall of the PIs
-            if ( pFanin->tDelaysF[i].Rise >= 0 ) // case (1)
-            { // fanin's rise depends on the rise of i-th PI
-                // update the rise of the gate
-                if ( pGate->tDelaysR[i].Rise < pFanin->tDelaysF[i].Rise + tDelayBlockRise )
-                    pGate->tDelaysR[i].Rise = pFanin->tDelaysF[i].Rise + tDelayBlockRise;
-            }
-            if ( pFanin->tDelaysF[i].Fall >= 0 ) // case (2)
-            { // fanin's rise depends on the fall of i-th PI
-                // update the rise of the gate
-                if ( pGate->tDelaysR[i].Fall < pFanin->tDelaysF[i].Fall + tDelayBlockRise )
-                    pGate->tDelaysR[i].Fall = pFanin->tDelaysF[i].Fall + tDelayBlockRise;
-            }
-            ////////////////////////////////////////////////////////
-
-            ////////////////////////////////////////////////////////
-            // consider the fall of the gate (similar)
-            ////////////////////////////////////////////////////////
-            // check two types of constraints on the rise of the fanin:
-            // (1) the constraints related to the rise of the PIs
-            // (2) the constraints related to the fall of the PIs
-            if ( pFanin->tDelaysR[i].Rise >= 0 ) // case (1) 
-            { 
-                if ( pGate->tDelaysF[i].Rise < pFanin->tDelaysR[i].Rise + tDelayBlockFall )
-                    pGate->tDelaysF[i].Rise = pFanin->tDelaysR[i].Rise + tDelayBlockFall;
-            }
-            if ( pFanin->tDelaysR[i].Fall >= 0 ) // case (2) 
-            { 
-                if ( pGate->tDelaysF[i].Fall < pFanin->tDelaysR[i].Fall + tDelayBlockFall )
-                    pGate->tDelaysF[i].Fall = pFanin->tDelaysR[i].Fall + tDelayBlockFall;
-            }
-            ////////////////////////////////////////////////////////
-        }
-    }
-}
-
-
-/**Function*************************************************************
-
-  Synopsis    [Performs phase transformation for one function.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-unsigned Map_CalculatePhase( unsigned uTruths[][2], int nVars, unsigned uTruth, unsigned uPhase )
-{
-    int v, Shift;
-    for ( v = 0, Shift = 1; v < nVars; v++, Shift <<= 1 )
-        if ( uPhase & Shift )
-            uTruth = (((uTruth & ~uTruths[v][0]) << Shift) | ((uTruth & uTruths[v][0]) >> Shift));
-    return uTruth;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Performs phase transformation for one function.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Map_CalculatePhase6( unsigned uTruths[][2], int nVars, unsigned uTruth[], unsigned uPhase, unsigned uTruthRes[] )
-{
-    unsigned uTemp;
-    int v, Shift;
-
-    // initialize the result
-    uTruthRes[0] = uTruth[0];
-    uTruthRes[1] = uTruth[1];
-    if ( uPhase == 0 )
-        return;
-    // compute the phase 
-    for ( v = 0, Shift = 1; v < nVars; v++, Shift <<= 1 )
-        if ( uPhase & Shift )
-        {
-            if ( Shift < 32 )
-            {
-                uTruthRes[0] = (((uTruthRes[0] & ~uTruths[v][0]) << Shift) | ((uTruthRes[0] & uTruths[v][0]) >> Shift));
-                uTruthRes[1] = (((uTruthRes[1] & ~uTruths[v][1]) << Shift) | ((uTruthRes[1] & uTruths[v][1]) >> Shift));
-            }
-            else
-            {
-                uTemp        = uTruthRes[0];
-                uTruthRes[0] = uTruthRes[1];
-                uTruthRes[1] = uTemp;
-            }
-        }
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Prints the supergate library after deriving parameters.]
-
-  Description [This procedure is very useful to see the library after
-  it has been read into the mapper by "read_super" and all the information
-  about the supergates derived.]
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Map_LibraryPrintTree( Map_SuperLib_t * pLib )
-{
-    Map_Super_t * pGate;
-    int i, k;
-
-    // print all the info related to the supergates
-//    for ( i = pLib->nVarsMax; i < (int)pLib->nLines; i++ )
-    for ( i = pLib->nVarsMax; i < 20; i++ )
-    {
-        pGate = pLib->ppSupers[i];
-
-        // write the gate's fanin info and formula
-        printf( "%6d  ", pGate->Num );
-        printf( "%c ", pGate->fSuper? '*' : ' ' );
-        printf( "%6s", Mio_GateReadName(pGate->pRoot) );
-        for ( k = 0; k < (int)pGate->nFanins; k++ )
-            printf( " %6d", pGate->pFanins[k]->Num );
-        printf( "  %s", pGate->pFormula );
-        printf( "\n" );
-
-        // write the gate's derived info
-        Extra_PrintBinary( stdout, pGate->uTruth, 64 );
-        printf( "  %3d",   pGate->nGates );
-        printf( "  %6.2f", pGate->Area );
-        printf( "  (%4.2f, %4.2f)", pGate->tDelayMax.Rise, pGate->tDelayMax.Fall );
-        printf( "\n" );
-        for ( k = 0; k < pLib->nVarsMax; k++ )
-        {
-            // print the constraint on the rise of the gate in the form (D1, D2), 
-            // where D1 is the constraint related to the rise of the k-th PI
-            // where D2 is the constraint related to the fall of the k-th PI
-            if ( pGate->tDelaysR[k].Rise < 0 && pGate->tDelaysR[k].Fall < 0 )
-                printf( " (----, ----)" );
-            else if ( pGate->tDelaysR[k].Fall < 0 )
-                printf( " (%4.2f, ----)", pGate->tDelaysR[k].Rise );
-            else if ( pGate->tDelaysR[k].Rise < 0 )
-                printf( " (----, %4.2f)", pGate->tDelaysR[k].Fall );
-            else
-                printf( " (%4.2f, %4.2f)", pGate->tDelaysR[k].Rise, pGate->tDelaysR[k].Fall );
-
-            // print the constraint on the fall of the gate in the form (D1, D2), 
-            // where D1 is the constraint related to the rise of the k-th PI
-            // where D2 is the constraint related to the fall of the k-th PI
-            if ( pGate->tDelaysF[k].Rise < 0 && pGate->tDelaysF[k].Fall < 0 )
-                printf( " (----, ----)" );
-            else if ( pGate->tDelaysF[k].Fall < 0 )
-                printf( " (%4.2f, ----)", pGate->tDelaysF[k].Rise );
-            else if ( pGate->tDelaysF[k].Rise < 0 )
-                printf( " (----, %4.2f)", pGate->tDelaysF[k].Fall );
-            else
-                printf( " (%4.2f, %4.2f)", pGate->tDelaysF[k].Rise, pGate->tDelaysF[k].Fall );
-            printf( "\n" );
-        }
-        printf( "\n" );
-    }
-}
-
-////////////////////////////////////////////////////////////////////////
-///                       END OF FILE                                ///
-////////////////////////////////////////////////////////////////////////
-
-
diff --git a/abc70930/src/map/mapper/mapperTruth.c b/abc70930/src/map/mapper/mapperTruth.c
deleted file mode 100644
index 388b6dd3..00000000
--- a/abc70930/src/map/mapper/mapperTruth.c
+++ /dev/null
@@ -1,310 +0,0 @@
-/**CFile****************************************************************
-
-  FileName    [mapperTruth.c]
-
-  PackageName [MVSIS 1.3: Multi-valued logic synthesis system.]
-
-  Synopsis    [Generic technology mapping engine.]
-
-  Author      [MVSIS Group]
-  
-  Affiliation [UC Berkeley]
-
-  Date        [Ver. 2.0. Started - June 1, 2004.]
-
-  Revision    [$Id: mapperTruth.c,v 1.8 2005/01/23 06:59:45 alanmi Exp $]
-
-***********************************************************************/
-
-#include "mapperInt.h"
-
-////////////////////////////////////////////////////////////////////////
-///                        DECLARATIONS                              ///
-////////////////////////////////////////////////////////////////////////
-
-static void Map_TruthsCut( Map_Man_t * pMan, Map_Cut_t * pCut );
-extern void Map_TruthsCutOne( Map_Man_t * p, Map_Cut_t * pCut, unsigned uTruth[] );
-static void Map_CutsCollect_rec( Map_Cut_t * pCut, Map_NodeVec_t * vVisited );
-
-////////////////////////////////////////////////////////////////////////
-///                     FUNCTION DEFINITIONS                         ///
-////////////////////////////////////////////////////////////////////////
-
-/**Function*************************************************************
-
-  Synopsis    [Derives truth tables for each cut.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Map_MappingTruths( Map_Man_t * pMan )
-{
-    ProgressBar * pProgress;
-    Map_Node_t * pNode;
-    Map_Cut_t * pCut;
-    int nNodes, i;
-    // compute the cuts for the POs
-    nNodes = pMan->vAnds->nSize;
-    pProgress = Extra_ProgressBarStart( stdout, nNodes );
-    for ( i = 0; i < nNodes; i++ )
-    {
-        pNode = pMan->vAnds->pArray[i];
-        if ( !Map_NodeIsAnd( pNode ) )
-            continue;
-        assert( pNode->pCuts );
-        assert( pNode->pCuts->nLeaves == 1 );
-
-        // match the simple cut
-        pNode->pCuts->M[0].uPhase     = 0;
-        pNode->pCuts->M[0].pSupers    = pMan->pSuperLib->pSuperInv;
-        pNode->pCuts->M[0].uPhaseBest = 0;
-        pNode->pCuts->M[0].pSuperBest = pMan->pSuperLib->pSuperInv;
-
-        pNode->pCuts->M[1].uPhase     = 0;
-        pNode->pCuts->M[1].pSupers    = pMan->pSuperLib->pSuperInv;
-        pNode->pCuts->M[1].uPhaseBest = 1;
-        pNode->pCuts->M[1].pSuperBest = pMan->pSuperLib->pSuperInv;
-
-        // match the rest of the cuts
-        for ( pCut = pNode->pCuts->pNext; pCut; pCut = pCut->pNext )
-             Map_TruthsCut( pMan, pCut );
-        Extra_ProgressBarUpdate( pProgress, i, "Tables ..." );
-    }
-    Extra_ProgressBarStop( pProgress );
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Derives the truth table for one cut.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Map_TruthsCut( Map_Man_t * p, Map_Cut_t * pCut )
-{ 
-//    unsigned uCanon1, uCanon2;
-    unsigned uTruth[2], uCanon[2];
-    unsigned char uPhases[16];
-    unsigned * uCanon2;
-    char * pPhases2;
-    int fUseFast = 1;
-    int fUseSlow = 0;
-    int fUseRec = 0; // this does not work for Solaris
-
-    extern int Map_CanonCompute( int nVarsMax, int nVarsReal, unsigned * pt, unsigned ** pptRes, char ** ppfRes );
- 
-    // generally speaking, 1-input cut can be matched into a wire!
-    if ( pCut->nLeaves == 1 )
-        return;
-/*
-    if ( p->nVarsMax == 5 )
-    {
-        uTruth[0] = pCut->uTruth;
-        uTruth[1] = pCut->uTruth;
-    }
-    else
-*/
-    Map_TruthsCutOne( p, pCut, uTruth );
-
-
-    // compute the canonical form for the positive phase
-    if ( fUseFast )
-        Map_CanonComputeFast( p, p->nVarsMax, pCut->nLeaves, uTruth, uPhases, uCanon );
-    else if ( fUseSlow )
-        Map_CanonComputeSlow( p->uTruths, p->nVarsMax, pCut->nLeaves, uTruth, uPhases, uCanon );
-    else if ( fUseRec )
-    {
-//        Map_CanonComputeSlow( p->uTruths, p->nVarsMax, pCut->nLeaves, uTruth, uPhases, uCanon );
-        Extra_TruthCanonFastN( p->nVarsMax, pCut->nLeaves, uTruth, &uCanon2, &pPhases2 );
-/*
-        if ( uCanon[0] != uCanon2[0] || uPhases[0] != pPhases2[0] )
-        {
-            int k = 0;
-            Map_CanonCompute( p->nVarsMax, pCut->nLeaves, uTruth, &uCanon2, &pPhases2 );
-        }
-*/
-        uCanon[0] = uCanon2[0];
-        uCanon[1] = (p->nVarsMax == 6)? uCanon2[1] : uCanon2[0];
-        uPhases[0] = pPhases2[0];
-    }
-    else
-        Map_CanonComputeSlow( p->uTruths, p->nVarsMax, pCut->nLeaves, uTruth, uPhases, uCanon );
-    pCut->M[1].pSupers = Map_SuperTableLookupC( p->pSuperLib, uCanon );
-    pCut->M[1].uPhase  = uPhases[0];
-    p->nCanons++;
-
-//uCanon1 = uCanon[0] & 0xFFFF;
-
-    // compute the canonical form for the negative phase
-    uTruth[0] = ~uTruth[0];
-    uTruth[1] = ~uTruth[1];
-    if ( fUseFast )
-        Map_CanonComputeFast( p, p->nVarsMax, pCut->nLeaves, uTruth, uPhases, uCanon );
-    else if ( fUseSlow )
-        Map_CanonComputeSlow( p->uTruths, p->nVarsMax, pCut->nLeaves, uTruth, uPhases, uCanon );
-    else if ( fUseRec )
-    {
-//        Map_CanonComputeSlow( p->uTruths, p->nVarsMax, pCut->nLeaves, uTruth, uPhases, uCanon );
-        Extra_TruthCanonFastN( p->nVarsMax, pCut->nLeaves, uTruth, &uCanon2, &pPhases2 );
-/*
-        if ( uCanon[0] != uCanon2[0] || uPhases[0] != pPhases2[0] )
-        {
-            int k = 0;
-            Map_CanonCompute( p->nVarsMax, pCut->nLeaves, uTruth, &uCanon2, &pPhases2 );
-        }
-*/
-        uCanon[0] = uCanon2[0];
-        uCanon[1] = (p->nVarsMax == 6)? uCanon2[1] : uCanon2[0];
-        uPhases[0] = pPhases2[0];
-    }
-    else
-        Map_CanonComputeSlow( p->uTruths, p->nVarsMax, pCut->nLeaves, uTruth, uPhases, uCanon );
-    pCut->M[0].pSupers = Map_SuperTableLookupC( p->pSuperLib, uCanon );
-    pCut->M[0].uPhase  = uPhases[0];
-    p->nCanons++;
-
-//uCanon2 = uCanon[0] & 0xFFFF;
-//assert( p->nVarsMax == 4 );
-//Rwt_Man4ExploreCount( uCanon1 < uCanon2 ? uCanon1 : uCanon2 );
-
-    // restore the truth table
-    uTruth[0] = ~uTruth[0];
-    uTruth[1] = ~uTruth[1];
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Computes the truth table of one cut.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Map_TruthsCutOne( Map_Man_t * p, Map_Cut_t * pCut, unsigned uTruth[] )
-{
-    unsigned uTruth1[2], uTruth2[2];
-    Map_Cut_t * pTemp;
-    int i;
-    // mark the cut leaves
-    for ( i = 0; i < pCut->nLeaves; i++ )
-    {
-        pTemp = pCut->ppLeaves[i]->pCuts;
-        pTemp->fMark = 1;
-        pTemp->M[0].uPhaseBest = p->uTruths[i][0];
-        pTemp->M[1].uPhaseBest = p->uTruths[i][1];
-    }
-    assert( pCut->fMark == 0 );
-
-    // collect the cuts in the cut cone
-    p->vVisited->nSize = 0;
-    Map_CutsCollect_rec( pCut, p->vVisited );
-    assert( p->vVisited->nSize > 0 );
-    pCut->nVolume = p->vVisited->nSize;
-
-    // compute the tables and unmark
-    for ( i = 0; i < pCut->nLeaves; i++ )
-    {
-        pTemp = pCut->ppLeaves[i]->pCuts;
-        pTemp->fMark = 0;
-    }
-    for ( i = 0; i < p->vVisited->nSize; i++ )
-    {
-        // get the cut
-        pTemp = (Map_Cut_t *)p->vVisited->pArray[i];
-        pTemp->fMark = 0;
-        // get truth table of the first branch
-        if ( Map_CutIsComplement(pTemp->pOne) )
-        {
-            uTruth1[0] = ~Map_CutRegular(pTemp->pOne)->M[0].uPhaseBest;
-            uTruth1[1] = ~Map_CutRegular(pTemp->pOne)->M[1].uPhaseBest;
-        }
-        else
-        {
-            uTruth1[0] = Map_CutRegular(pTemp->pOne)->M[0].uPhaseBest;
-            uTruth1[1] = Map_CutRegular(pTemp->pOne)->M[1].uPhaseBest;
-        }
-        // get truth table of the second branch
-        if ( Map_CutIsComplement(pTemp->pTwo) )
-        {
-            uTruth2[0] = ~Map_CutRegular(pTemp->pTwo)->M[0].uPhaseBest;
-            uTruth2[1] = ~Map_CutRegular(pTemp->pTwo)->M[1].uPhaseBest;
-        }
-        else
-        {
-            uTruth2[0] = Map_CutRegular(pTemp->pTwo)->M[0].uPhaseBest;
-            uTruth2[1] = Map_CutRegular(pTemp->pTwo)->M[1].uPhaseBest;
-        }
-        // get the truth table of the output
-        if ( !pTemp->Phase )
-        {
-            pTemp->M[0].uPhaseBest = uTruth1[0] & uTruth2[0];
-            pTemp->M[1].uPhaseBest = uTruth1[1] & uTruth2[1];
-        }
-        else
-        {
-            pTemp->M[0].uPhaseBest = ~(uTruth1[0] & uTruth2[0]);
-            pTemp->M[1].uPhaseBest = ~(uTruth1[1] & uTruth2[1]);
-        }
-    }
-    uTruth[0] = pTemp->M[0].uPhaseBest;
-    uTruth[1] = pTemp->M[1].uPhaseBest;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Recursively collect the cuts.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Map_CutsCollect_rec( Map_Cut_t * pCut, Map_NodeVec_t * vVisited )
-{
-    if ( pCut->fMark )
-        return;
-    Map_CutsCollect_rec( Map_CutRegular(pCut->pOne), vVisited );
-    Map_CutsCollect_rec( Map_CutRegular(pCut->pTwo), vVisited );
-    assert( pCut->fMark == 0 );
-    pCut->fMark = 1;
-    Map_NodeVecPush( vVisited, (Map_Node_t *)pCut );
-}
-
-/*
-    {
-        unsigned * uCanon2;
-        char * pPhases2;
-
-        Map_CanonComputeSlow( p->uTruths, p->nVarsMax, pCut->nLeaves, uTruth, uPhases, uCanon );
-        Map_CanonCompute( p->nVarsMax, pCut->nLeaves, uTruth, &uCanon2, &pPhases2 );
-        if ( uCanon2[0] != uCanon[0] )
-        {
-            int v = 0;
-            Map_CanonCompute( p->nVarsMax, pCut->nLeaves, uTruth, &uCanon2, &pPhases2 );
-            Map_CanonComputeFast( p, p->nVarsMax, pCut->nLeaves, uTruth, uPhases, uCanon );
-        }
-//        else
-//        {
-//            printf( "Correct.\n" );
-//        }
-    }
-*/
-
-////////////////////////////////////////////////////////////////////////
-///                       END OF FILE                                ///
-////////////////////////////////////////////////////////////////////////
-
-
diff --git a/abc70930/src/map/mapper/mapperUtils.c b/abc70930/src/map/mapper/mapperUtils.c
deleted file mode 100644
index 11a3a683..00000000
--- a/abc70930/src/map/mapper/mapperUtils.c
+++ /dev/null
@@ -1,1154 +0,0 @@
-/**CFile****************************************************************
-
-  FileName    [mapperUtils.c]
-
-  PackageName [MVSIS 1.3: Multi-valued logic synthesis system.]
-
-  Synopsis    [Generic technology mapping engine.]
-
-  Author      [MVSIS Group]
-  
-  Affiliation [UC Berkeley]
-
-  Date        [Ver. 2.0. Started - June 1, 2004.]
-
-  Revision    [$Id: mapperUtils.c,v 1.8 2004/11/03 22:41:45 satrajit Exp $]
-
-***********************************************************************/
-
-#include "mapperInt.h"
-
-////////////////////////////////////////////////////////////////////////
-///                        DECLARATIONS                              ///
-////////////////////////////////////////////////////////////////////////
-
-#define MAP_CO_LIST_SIZE 5
-
-static void  Map_MappingDfs_rec( Map_Node_t * pNode, Map_NodeVec_t * vNodes, int fCollectEquiv );
-static int   Map_MappingCountLevels_rec( Map_Node_t * pNode );
-static float Map_MappingSetRefsAndArea_rec( Map_Man_t * pMan, Map_Node_t * pNode );
-static float Map_MappingSetRefsAndSwitch_rec( Map_Man_t * pMan, Map_Node_t * pNode );
-static float Map_MappingSetRefsAndWire_rec( Map_Man_t * pMan, Map_Node_t * pNode );
-static void  Map_MappingDfsCuts_rec( Map_Node_t * pNode, Map_NodeVec_t * vNodes );
-static float Map_MappingArea_rec( Map_Man_t * pMan, Map_Node_t * pNode, Map_NodeVec_t * vNodes );
-static int   Map_MappingCompareOutputDelay( Map_Node_t ** ppNode1, Map_Node_t ** ppNode2 );
-static void  Map_MappingFindLatest( Map_Man_t * p, int * pNodes, int nNodesMax );
-static unsigned Map_MappingExpandTruth_rec( unsigned uTruth, int nVars );
-static void Map_MappingGetChoiceLevels( Map_Man_t * pMan, Map_Node_t * p1, Map_Node_t * p2, int * pMin, int * pMax );
-static float Map_MappingGetChoiceVolumes( Map_Man_t * pMan, Map_Node_t * p1, Map_Node_t * p2 );
-static int Map_MappingCountUsedNodes( Map_Man_t * pMan, int fChoices );
-static Map_Man_t * s_pMan = NULL;
-
-////////////////////////////////////////////////////////////////////////
-///                     FUNCTION DEFINITIONS                         ///
-////////////////////////////////////////////////////////////////////////
-
-
-/**Function*************************************************************
-
-  Synopsis    [Computes the DFS ordering of the nodes.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-Map_NodeVec_t * Map_MappingDfs( Map_Man_t * pMan, int fCollectEquiv )
-{
-    Map_NodeVec_t * vNodes;
-    int i;
-    // perform the traversal
-    vNodes = Map_NodeVecAlloc( 100 );
-    for ( i = 0; i < pMan->nOutputs; i++ )
-        Map_MappingDfs_rec( Map_Regular(pMan->pOutputs[i]), vNodes, fCollectEquiv );
-    for ( i = 0; i < vNodes->nSize; i++ )
-        vNodes->pArray[i]->fMark0 = 0;
-//    for ( i = 0; i < pMan->nOutputs; i++ )
-//        Map_MappingUnmark_rec( Map_Regular(pMan->pOutputs[i]) );
-    return vNodes;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Computes the DFS ordering of the nodes.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-Map_NodeVec_t * Map_MappingDfsNodes( Map_Man_t * pMan, Map_Node_t ** ppCuts, int nNodes, int fEquiv )
-{
-    Map_NodeVec_t * vNodes;
-    int i;
-    // perform the traversal
-    vNodes = Map_NodeVecAlloc( 200 );
-    for ( i = 0; i < nNodes; i++ )
-        Map_MappingDfs_rec( ppCuts[i], vNodes, fEquiv );
-    for ( i = 0; i < vNodes->nSize; i++ )
-        vNodes->pArray[i]->fMark0 = 0;
-    return vNodes;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Recursively computes the DFS ordering of the nodes.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Map_MappingDfs_rec( Map_Node_t * pNode, Map_NodeVec_t * vNodes, int fCollectEquiv )
-{
-    assert( !Map_IsComplement(pNode) );
-    if ( pNode->fMark0 )
-        return;
-    // visit the transitive fanin
-    if ( Map_NodeIsAnd(pNode) )
-    {
-        Map_MappingDfs_rec( Map_Regular(pNode->p1), vNodes, fCollectEquiv );
-        Map_MappingDfs_rec( Map_Regular(pNode->p2), vNodes, fCollectEquiv );
-    }
-    // visit the equivalent nodes
-    if ( fCollectEquiv && pNode->pNextE )
-        Map_MappingDfs_rec( pNode->pNextE, vNodes, fCollectEquiv );
-    // make sure the node is not visited through the equivalent nodes
-    assert( pNode->fMark0 == 0 );
-    // mark the node as visited
-    pNode->fMark0 = 1;
-    // add the node to the list
-    Map_NodeVecPush( vNodes, pNode );
-}
-
-
-
-/**Function*************************************************************
-
-  Synopsis    [Recursively computes the DFS ordering of the nodes.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Map_MappingDfsMarked1_rec( Map_Node_t * pNode, Map_NodeVec_t * vNodes, int fFirst )
-{
-    assert( !Map_IsComplement(pNode) );
-    if ( pNode->fMark0 )
-        return;
-    // visit the transitive fanin
-    if ( Map_NodeIsAnd(pNode) )
-    {
-        Map_MappingDfsMarked1_rec( Map_Regular(pNode->p1), vNodes, 0 );
-        Map_MappingDfsMarked1_rec( Map_Regular(pNode->p2), vNodes, 0 );
-    }
-    // visit the equivalent nodes
-    if ( !fFirst && pNode->pNextE )
-        Map_MappingDfsMarked1_rec( pNode->pNextE, vNodes, 0 );
-    // make sure the node is not visited through the equivalent nodes
-    assert( pNode->fMark0 == 0 );
-    // mark the node as visited
-    pNode->fMark0 = 1;
-    // add the node to the list
-    Map_NodeVecPush( vNodes, pNode );
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Recursively computes the DFS ordering of the nodes.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Map_MappingDfsMarked2_rec( Map_Node_t * pNode, Map_NodeVec_t * vNodes, Map_NodeVec_t * vBoundary, int fFirst )
-{
-    assert( !Map_IsComplement(pNode) );
-    if ( pNode->fMark1 )
-        return;
-    if ( pNode->fMark0 || Map_NodeIsVar(pNode) )
-    {
-        pNode->fMark1 = 1;
-        Map_NodeVecPush(vBoundary, pNode);
-        return;
-    }
-    // visit the transitive fanin
-    if ( Map_NodeIsAnd(pNode) )
-    {
-        Map_MappingDfsMarked2_rec( Map_Regular(pNode->p1), vNodes, vBoundary, 0 );
-        Map_MappingDfsMarked2_rec( Map_Regular(pNode->p2), vNodes, vBoundary, 0 );
-    }
-    // visit the equivalent nodes
-    if ( !fFirst && pNode->pNextE )
-        Map_MappingDfsMarked2_rec( pNode->pNextE, vNodes, vBoundary, 0 );
-    // make sure the node is not visited through the equivalent nodes
-    assert( pNode->fMark1 == 0 );
-    // mark the node as visited
-    pNode->fMark1 = 1;
-    // add the node to the list
-    Map_NodeVecPush( vNodes, pNode );
-}
-
-
-/**Function*************************************************************
-
-  Synopsis    [Recursively computes the DFS ordering of the nodes.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Map_MappingDfsMarked3_rec( Map_Node_t * pNode, Map_NodeVec_t * vNodes )
-{
-    assert( !Map_IsComplement(pNode) );
-    if ( pNode->fMark0 )
-        return;
-    // visit the transitive fanin
-    if ( Map_NodeIsAnd(pNode) )
-    {
-        Map_MappingDfsMarked3_rec( Map_Regular(pNode->p1), vNodes );
-        Map_MappingDfsMarked3_rec( Map_Regular(pNode->p2), vNodes );
-    }
-    // make sure the node is not visited through the equivalent nodes
-    assert( pNode->fMark0 == 0 );
-    // mark the node as visited
-    pNode->fMark0 = 1;
-    // add the node to the list
-    Map_NodeVecPush( vNodes, pNode );
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Recursively computes the DFS ordering of the nodes.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Map_MappingDfsMarked4_rec( Map_Node_t * pNode, Map_NodeVec_t * vNodes )
-{
-    assert( !Map_IsComplement(pNode) );
-    if ( pNode->fMark1 )
-        return;
-    // visit the transitive fanin
-    if ( Map_NodeIsAnd(pNode) )
-    {
-        Map_MappingDfsMarked4_rec( Map_Regular(pNode->p1), vNodes );
-        Map_MappingDfsMarked4_rec( Map_Regular(pNode->p2), vNodes );
-    }
-    // make sure the node is not visited through the equivalent nodes
-    assert( pNode->fMark1 == 0 );
-    // mark the node as visited
-    pNode->fMark1 = 1;
-    // add the node to the list
-    Map_NodeVecPush( vNodes, pNode );
-}
-
-
-
-/**Function*************************************************************
-
-  Synopsis    [Computes the number of logic levels not counting PIs/POs.]
-
-  Description []
-               
-  SideEffects [Note that this procedure will reassign the levels assigned
-  originally by NodeCreate() because it counts the number of levels with 
-  choices differently!]
-
-  SeeAlso     []
-
-***********************************************************************/
-int Map_MappingCountLevels( Map_Man_t * pMan )
-{
-    int i, LevelsMax, LevelsCur;
-    // perform the traversal
-    LevelsMax = -1;
-    for ( i = 0; i < pMan->nOutputs; i++ )
-    {
-        LevelsCur = Map_MappingCountLevels_rec( Map_Regular(pMan->pOutputs[i]) );
-        if ( LevelsMax < LevelsCur )
-            LevelsMax = LevelsCur;
-    }
-    for ( i = 0; i < pMan->nOutputs; i++ )
-        Map_MappingUnmark_rec( Map_Regular(pMan->pOutputs[i]) );
-    return LevelsMax;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Recursively computes the number of logic levels.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Map_MappingCountLevels_rec( Map_Node_t * pNode )
-{
-    int Level1, Level2;
-    assert( !Map_IsComplement(pNode) );
-    if ( !Map_NodeIsAnd(pNode) )
-    {
-        pNode->Level = 0;
-        return 0;
-    }
-    if ( pNode->fMark0 )
-        return pNode->Level;
-    pNode->fMark0 = 1;
-    // visit the transitive fanin
-    Level1 = Map_MappingCountLevels_rec( Map_Regular(pNode->p1) );
-    Level2 = Map_MappingCountLevels_rec( Map_Regular(pNode->p2) );
-    // set the number of levels
-    pNode->Level = 1 + ((Level1>Level2)? Level1: Level2);
-    return pNode->Level;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Unmarks the nodes.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Map_MappingUnmark( Map_Man_t * pMan )
-{
-    int i;
-    for ( i = 0; i < pMan->nOutputs; i++ )
-        Map_MappingUnmark_rec( Map_Regular(pMan->pOutputs[i]) );
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Recursively unmarks the nodes.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Map_MappingUnmark_rec( Map_Node_t * pNode )
-{
-    assert( !Map_IsComplement(pNode) );
-    if ( pNode->fMark0 == 0 )
-        return;
-    pNode->fMark0 = 0;
-    if ( !Map_NodeIsAnd(pNode) )
-        return;
-    Map_MappingUnmark_rec( Map_Regular(pNode->p1) );
-    Map_MappingUnmark_rec( Map_Regular(pNode->p2) );
-    // visit the equivalent nodes
-    if ( pNode->pNextE )
-        Map_MappingUnmark_rec( pNode->pNextE );
-}
-
-/**Function*************************************************************
-
-  Synopsis    []
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Map_MappingMark_rec( Map_Node_t * pNode )
-{
-    assert( !Map_IsComplement(pNode) );
-    if ( pNode->fMark0 == 1 )
-        return;
-    pNode->fMark0 = 1;
-    if ( !Map_NodeIsAnd(pNode) )
-        return;
-    // visit the transitive fanin of the selected cut
-    Map_MappingMark_rec( Map_Regular(pNode->p1) );
-    Map_MappingMark_rec( Map_Regular(pNode->p2) );
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Compares the outputs by their arrival times.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Map_MappingCompareOutputDelay( Map_Node_t ** ppNode1, Map_Node_t ** ppNode2 )
-{
-    Map_Node_t * pNode1 = Map_Regular(*ppNode1);
-    Map_Node_t * pNode2 = Map_Regular(*ppNode2);
-    int fPhase1 = !Map_IsComplement(*ppNode1);
-    int fPhase2 = !Map_IsComplement(*ppNode2);
-    float Arrival1 = pNode1->tArrival[fPhase1].Worst;
-    float Arrival2 = pNode2->tArrival[fPhase2].Worst;
-    if ( Arrival1 < Arrival2 )
-        return -1;
-    if ( Arrival1 > Arrival2 )
-        return 1;
-    return 0;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Finds given number of latest arriving COs.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Map_MappingFindLatest( Map_Man_t * p, int * pNodes, int nNodesMax )
-{
-    int nNodes, i, k, v;
-    assert( p->nOutputs >= nNodesMax );
-    pNodes[0] = 0;
-    nNodes = 1;
-    for ( i = 1; i < p->nOutputs; i++ )
-    {
-        for ( k = nNodes - 1; k >= 0; k-- )
-            if ( Map_MappingCompareOutputDelay( &p->pOutputs[pNodes[k]], &p->pOutputs[i] ) >= 0 )
-                break;
-        if ( k == nNodesMax - 1 )
-            continue;
-        if ( nNodes < nNodesMax )
-            nNodes++;
-        for ( v = nNodes - 1; v > k+1; v-- )
-            pNodes[v] = pNodes[v-1];
-        pNodes[k+1] = i;
-    }
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Prints a bunch of latest arriving outputs.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Map_MappingPrintOutputArrivals( Map_Man_t * p )
-{
-    int pSorted[MAP_CO_LIST_SIZE];
-    Map_Time_t * pTimes;
-    Map_Node_t * pNode;
-    int fPhase, Limit, i;
-    int MaxNameSize;
-
-    // determine the number of nodes to print
-    Limit = (p->nOutputs > MAP_CO_LIST_SIZE)? MAP_CO_LIST_SIZE : p->nOutputs;
-
-    // determine the order
-    Map_MappingFindLatest( p, pSorted, Limit );
-
-    // determine max size of the node's name
-    MaxNameSize = 0;
-    for ( i = 0; i < Limit; i++ )
-        if ( MaxNameSize < (int)strlen(p->ppOutputNames[pSorted[i]]) )
-            MaxNameSize = strlen(p->ppOutputNames[pSorted[i]]);
-
-    // print the latest outputs
-    for ( i = 0; i < Limit; i++ )
-    {
-        // get the i-th latest output
-        pNode  = Map_Regular(p->pOutputs[pSorted[i]]);
-        fPhase =!Map_IsComplement(p->pOutputs[pSorted[i]]);
-        pTimes = pNode->tArrival + fPhase;
-        // print out the best arrival time
-        printf( "Output  %-*s : ", MaxNameSize + 3, p->ppOutputNames[pSorted[i]] );
-        printf( "Delay = (%5.2f, %5.2f)  ", (double)pTimes->Rise, (double)pTimes->Fall );
-        printf( "%s", fPhase? "POS" : "NEG" );
-        printf( "\n" );
-    }
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Sets up the truth tables.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Map_MappingSetupTruthTables( unsigned uTruths[][2] )
-{
-    int m, v;
-    // set up the truth tables
-    for ( m = 0; m < 32; m++ )
-        for ( v = 0; v < 5; v++ )
-            if ( m & (1 << v) )
-                uTruths[v][0] |= (1 << m);
-    // make adjustments for the case of 6 variables
-    for ( v = 0; v < 5; v++ )
-        uTruths[v][1] = uTruths[v][0];
-    uTruths[5][0] = 0;
-    uTruths[5][1] = MAP_FULL;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Sets up the truth tables.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Map_MappingSetupTruthTablesLarge( unsigned uTruths[][32] )
-{
-    int m, v;
-    // clean everything
-    for ( m = 0; m < 32; m++ )
-        for ( v = 0; v < 10; v++ )
-            uTruths[v][m] = 0;
-    // set up the truth tables
-    for ( m = 0; m < 32; m++ )
-        for ( v = 0; v < 5; v++ )
-            if ( m & (1 << v) )
-            {
-                uTruths[v][0] |= (1 << m);
-                uTruths[v+5][m] = MAP_FULL;
-            }
-    // extend this info for the rest of the first 5 variables
-    for ( m = 0; m < 32; m++ )
-        for ( v = 0; v < 5; v++ )
-            uTruths[v][m] = uTruths[v][0];
-/*
-    // verify
-    for ( m = 0; m < 1024; m++, printf("\n") )
-        for ( v = 0; v < 10; v++ )
-            if ( Map_InfoReadVar( uTruths[v], m ) )
-                printf( "1" );
-            else
-                printf( "0" );
-*/
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Sets up the mask.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Map_MappingSetupMask( unsigned uMask[], int nVarsMax )
-{
-    if ( nVarsMax == 6 )
-        uMask[0] = uMask[1] = MAP_FULL;
-    else
-    {
-        uMask[0] = MAP_MASK(1 << nVarsMax);
-        uMask[1] = 0;
-    }
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Verify one useful property.]
-
-  Description [This procedure verifies one useful property. After 
-  the FRAIG construction with choice nodes is over, each primary node 
-  should have fanins that are primary nodes. The primary nodes is the 
-  one that does not have pNode->pRepr set to point to another node.]
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Map_ManCheckConsistency( Map_Man_t * p )
-{
-    Map_Node_t * pNode;
-    Map_NodeVec_t * pVec;
-    int i;
-    pVec = Map_MappingDfs( p, 0 );
-    for ( i = 0; i < pVec->nSize; i++ )
-    {
-        pNode = pVec->pArray[i];
-        if ( Map_NodeIsVar(pNode) )
-        {
-            if ( pNode->pRepr )
-                printf( "Primary input %d is a secondary node.\n", pNode->Num );
-        }
-        else if ( Map_NodeIsConst(pNode) )
-        {
-            if ( pNode->pRepr )
-                printf( "Constant 1 %d is a secondary node.\n", pNode->Num );
-        }
-        else
-        {
-            if ( pNode->pRepr )
-                printf( "Internal node %d is a secondary node.\n", pNode->Num );
-            if ( Map_Regular(pNode->p1)->pRepr )
-                printf( "Internal node %d has first fanin that is a secondary node.\n", pNode->Num );
-            if ( Map_Regular(pNode->p2)->pRepr )
-                printf( "Internal node %d has second fanin that is a secondary node.\n", pNode->Num );
-        }
-    }
-    Map_NodeVecFree( pVec );
-    return 1;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Returns 1 if current mapping of the node violates fanout limits.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Map_MappingNodeIsViolator( Map_Node_t * pNode, Map_Cut_t * pCut, int fPosPol )
-{
-    return pNode->nRefAct[fPosPol] > (int)pCut->M[fPosPol].pSuperBest->nFanLimit;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Computes the total are flow of the network.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-float Map_MappingGetAreaFlow( Map_Man_t * p )
-{
-    Map_Node_t * pNode;
-    Map_Cut_t * pCut;
-    float aFlowFlowTotal = 0;
-    int fPosPol, i;
-    for ( i = 0; i < p->nOutputs; i++ )
-    {
-        pNode = Map_Regular(p->pOutputs[i]);
-        if ( !Map_NodeIsAnd(pNode) )
-            continue;
-        fPosPol = !Map_IsComplement(p->pOutputs[i]);
-        pCut = pNode->pCutBest[fPosPol];
-        if ( pCut == NULL )
-        {
-            fPosPol = !fPosPol;
-            pCut = pNode->pCutBest[fPosPol];
-        }
-        aFlowFlowTotal += pNode->pCutBest[fPosPol]->M[fPosPol].AreaFlow;
-    }
-    return aFlowFlowTotal;
-}
-
-
-/**Function*************************************************************
-
-  Synopsis    [Compares the supergates by their level.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Map_CompareNodesByLevel( Map_Node_t ** ppS1, Map_Node_t ** ppS2 )
-{
-    Map_Node_t * pN1 = Map_Regular(*ppS1);
-    Map_Node_t * pN2 = Map_Regular(*ppS2);
-    if ( pN1->Level > pN2->Level )
-        return -1;
-    if ( pN1->Level < pN2->Level )
-        return 1;
-    return 0;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Orders the nodes in the decreasing order of levels.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Map_MappingSortByLevel( Map_Man_t * pMan, Map_NodeVec_t * vNodes )
-{
-    qsort( (void *)vNodes->pArray, vNodes->nSize, sizeof(Map_Node_t *), 
-            (int (*)(const void *, const void *)) Map_CompareNodesByLevel );
-//    assert( Map_CompareNodesByLevel( vNodes->pArray, vNodes->pArray + vNodes->nSize - 1 ) <= 0 );
-}
-
-
-/**Function*************************************************************
-
-  Synopsis    [Compares the supergates by their pointer.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Map_CompareNodesByPointer( Map_Node_t ** ppS1, Map_Node_t ** ppS2 )
-{
-    if ( *ppS1 < *ppS2 )
-        return -1;
-    if ( *ppS1 > *ppS2 )
-        return 1;
-    return 0;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Counts how many AIG nodes are mapped in both polarities.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Map_MappingCountDoubles( Map_Man_t * pMan, Map_NodeVec_t * vNodes )
-{
-    Map_Node_t * pNode;
-    int Counter, i;
-    // count the number of equal adjacent nodes
-    Counter = 0;
-    for ( i = 0; i < vNodes->nSize; i++ )
-    {
-        pNode = vNodes->pArray[i];
-        if ( !Map_NodeIsAnd(pNode) )
-            continue;
-        if ( (pNode->nRefAct[0] && pNode->pCutBest[0]) && 
-             (pNode->nRefAct[1] && pNode->pCutBest[1]) )
-            Counter++;
-    }
-    return Counter;
-}
-
-
-/**Function*************************************************************
-
-  Synopsis    []
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-st_table * Map_CreateTableGate2Super( Map_Man_t * pMan )
-{
-    Map_Super_t * pSuper;
-    st_table * tTable;
-    int i, nInputs, v;
-    tTable = st_init_table(strcmp, st_strhash);
-    for ( i = 0; i < pMan->pSuperLib->nSupersAll; i++ )
-    {
-        pSuper = pMan->pSuperLib->ppSupers[i];
-        if ( pSuper->nGates == 1 )
-        {
-            // skip different versions of the same root gate
-            nInputs = Mio_GateReadInputs(pSuper->pRoot);
-            for ( v = 0; v < nInputs; v++ )
-                if ( pSuper->pFanins[v]->Num != nInputs - 1 - v )
-                    break;
-            if ( v != nInputs )
-                continue;
-//            printf( "%s\n", Mio_GateReadName(pSuper->pRoot) );
-            if ( st_insert( tTable, (char *)pSuper->pRoot, (char *)pSuper ) )
-            {
-                assert( 0 );
-            }
-        }
-    }
-    return tTable;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Get the FRAIG node with phase.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Map_ManCleanData( Map_Man_t * p )
-{
-    int i;
-    for ( i = 0; i < p->vNodesAll->nSize; i++ )
-        p->vNodesAll->pArray[i]->pData0 = p->vNodesAll->pArray[i]->pData1 = 0;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Expand the truth table]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Map_MappingExpandTruth( unsigned uTruth[2], int nVars )
-{
-    assert( nVars < 7 );
-    if ( nVars == 6 )
-        return;
-    if ( nVars < 5 )
-    {
-        uTruth[0] &= MAP_MASK( (1<<nVars) );
-        uTruth[0]  = Map_MappingExpandTruth_rec( uTruth[0], nVars );
-    }
-    uTruth[1] = uTruth[0];
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Expand the truth table]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-unsigned Map_MappingExpandTruth_rec( unsigned uTruth, int nVars )
-{
-    assert( nVars < 6 );
-    if ( nVars == 5 )
-        return uTruth;
-    return Map_MappingExpandTruth_rec( uTruth | (uTruth << (1 << nVars)), nVars + 1 );    
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Compute the arrival times.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-float Map_MappingComputeDelayWithFanouts( Map_Man_t * p )
-{
-    Map_Node_t * pNode;
-    float Result;
-    int i;
-    for ( i = 0; i < p->vAnds->nSize; i++ )
-    {
-        // skip primary inputs
-        pNode = p->vAnds->pArray[i];
-        if ( !Map_NodeIsAnd( pNode ) )
-            continue;
-        // skip a secondary node
-        if ( pNode->pRepr )
-            continue;
-        // count the switching nodes
-        if ( pNode->nRefAct[0] > 0 )
-            Map_TimeCutComputeArrival( pNode, pNode->pCutBest[0], 0, MAP_FLOAT_LARGE );
-        if ( pNode->nRefAct[1] > 0 )
-            Map_TimeCutComputeArrival( pNode, pNode->pCutBest[1], 1, MAP_FLOAT_LARGE );
-    }
-    Result = Map_TimeComputeArrivalMax(p);
-    printf( "Max arrival times with fanouts = %10.2f.\n", Result );
-    return Result;
-}
-
-
-/**Function*************************************************************
-
-  Synopsis    [Sets up the mask.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Map_MappingGetMaxLevel( Map_Man_t * pMan )
-{
-    int nLevelMax, i;
-    nLevelMax = 0;
-    for ( i = 0; i < pMan->nOutputs; i++ )
-        nLevelMax = ((unsigned)nLevelMax) > Map_Regular(pMan->pOutputs[i])->Level? 
-                nLevelMax : Map_Regular(pMan->pOutputs[i])->Level;
-    return nLevelMax;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Analyses choice nodes.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Map_MappingUpdateLevel_rec( Map_Man_t * pMan, Map_Node_t * pNode, int fMaximum )
-{
-    Map_Node_t * pTemp;
-    int Level1, Level2, LevelE;
-    assert( !Map_IsComplement(pNode) );
-    if ( !Map_NodeIsAnd(pNode) )
-        return pNode->Level;
-    // skip the visited node
-    if ( pNode->TravId == pMan->nTravIds )
-        return pNode->Level;
-    pNode->TravId = pMan->nTravIds;
-    // compute levels of the children nodes
-    Level1 = Map_MappingUpdateLevel_rec( pMan, Map_Regular(pNode->p1), fMaximum );
-    Level2 = Map_MappingUpdateLevel_rec( pMan, Map_Regular(pNode->p2), fMaximum );
-    pNode->Level = 1 + MAP_MAX( Level1, Level2 );
-    if ( pNode->pNextE )
-    {
-        LevelE = Map_MappingUpdateLevel_rec( pMan, pNode->pNextE, fMaximum );
-        if ( fMaximum )
-        {
-            if ( pNode->Level < (unsigned)LevelE )
-                pNode->Level = LevelE;
-        }
-        else
-        {
-            if ( pNode->Level > (unsigned)LevelE )
-                pNode->Level = LevelE;
-        }
-        // set the level of all equivalent nodes to be the same minimum
-        if ( pNode->pRepr == NULL ) // the primary node
-            for ( pTemp = pNode->pNextE; pTemp; pTemp = pTemp->pNextE )
-                pTemp->Level = pNode->Level;
-    }
-    return pNode->Level;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Resets the levels of the nodes in the choice graph.]
-
-  Description [Makes the level of the choice nodes to be equal to the
-  maximum of the level of the nodes in the equivalence class. This way
-  sorting by level leads to the reverse topological order, which is
-  needed for the required time computation.]
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Map_MappingSetChoiceLevels( Map_Man_t * pMan )
-{
-    int i;
-    pMan->nTravIds++;
-    for ( i = 0; i < pMan->nOutputs; i++ )
-        Map_MappingUpdateLevel_rec( pMan, Map_Regular(pMan->pOutputs[i]), 1 );
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Reports statistics on choice nodes.]
-
-  Description [The number of choice nodes is the number of primary nodes,
-  which has pNextE set to a pointer. The number of choices is the number
-  of entries in the equivalent-node lists of the primary nodes.]
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Map_MappingReportChoices( Map_Man_t * pMan )
-{
-    Map_Node_t * pNode, * pTemp;
-    int nChoiceNodes, nChoices;
-    int i, LevelMax1, LevelMax2;
-
-    // report the number of levels
-    LevelMax1 = Map_MappingGetMaxLevel( pMan );
-    pMan->nTravIds++;
-    for ( i = 0; i < pMan->nOutputs; i++ )
-        Map_MappingUpdateLevel_rec( pMan, Map_Regular(pMan->pOutputs[i]), 0 );
-    LevelMax2 = Map_MappingGetMaxLevel( pMan );
-
-    // report statistics about choices
-    nChoiceNodes = nChoices = 0;
-    for ( i = 0; i < pMan->vAnds->nSize; i++ )
-    {
-        pNode = pMan->vAnds->pArray[i];
-        if ( pNode->pRepr == NULL && pNode->pNextE != NULL )
-        { // this is a choice node = the primary node that has equivalent nodes
-            nChoiceNodes++;
-            for ( pTemp = pNode; pTemp; pTemp = pTemp->pNextE )
-                nChoices++;
-        }
-    }
-    printf( "Maximum level: Original = %d. Reduced due to choices = %d.\n", LevelMax1, LevelMax2 );
-    printf( "Choice stats:  Choice nodes = %d. Total choices = %d.\n", nChoiceNodes, nChoices );
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Computes the maximum and minimum levels of the choice nodes.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Map_MappingGetChoiceLevels( Map_Man_t * pMan, Map_Node_t * p1, Map_Node_t * p2, int * pMin, int * pMax )
-{
-    Map_NodeVec_t * vNodes;
-    Map_NodeVec_t * vBoundary;
-    Map_Node_t * pNode;
-    int i, Min, Max;
-
-    vNodes    = Map_NodeVecAlloc( 100 );
-    vBoundary = Map_NodeVecAlloc( 100 );
-    Map_MappingDfsMarked1_rec( p1, vNodes, 1 );
-    Map_MappingDfsMarked2_rec( p2, vNodes, vBoundary, 1 );
-    // clean the marks
-    Min =  100000;
-    Max = -100000;
-    for ( i = 0; i < vBoundary->nSize; i++ )
-    {
-        pNode = vBoundary->pArray[i];
-        if ( Min > (int)pNode->Level )
-            Min = pNode->Level;
-        if ( Max < (int)pNode->Level )
-            Max = pNode->Level;
-    }
-    Map_NodeVecFree( vBoundary );
-    for ( i = 0; i < vNodes->nSize; i++ )
-    {
-        pNode = vNodes->pArray[i];
-        pNode->fMark0 = pNode->fMark1 = 0;
-    }
-    Map_NodeVecFree( vNodes );
-    *pMin = Min;
-    *pMax = Max;
-}
-
-
-/**Function*************************************************************
-
-  Synopsis    []
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-float Map_MappingGetChoiceVolumes( Map_Man_t * pMan, Map_Node_t * p1, Map_Node_t * p2 )
-{
-    Map_NodeVec_t * vNodes;
-    Map_Node_t * pNode;
-    int i, nVolumeTotal, nVolumeUnique;
-
-    vNodes    = Map_NodeVecAlloc( 100 );
-    Map_MappingDfsMarked3_rec( p1, vNodes );
-    Map_MappingDfsMarked4_rec( p2, vNodes );
-    // clean the marks
-    nVolumeTotal = nVolumeUnique = 0;
-    for ( i = 0; i < vNodes->nSize; i++ )
-    {
-        pNode = vNodes->pArray[i];
-        if ( !Map_NodeIsAnd(pNode) )
-            continue;
-        nVolumeTotal++;
-        if ( pNode->fMark0 ^ pNode->fMark1 )
-            nVolumeUnique++;
-        pNode->fMark0 = pNode->fMark1 = 0;
-    }
-    Map_NodeVecFree( vNodes );
-//    return ((float)nVolumeUnique)/nVolumeTotal;
-    return (float)nVolumeUnique;
-}
-
-
-/**Function*************************************************************
-
-  Synopsis    [Computes the maximum and minimum levels of the choice nodes.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Map_MappingCountUsedNodes( Map_Man_t * pMan, int fChoices )
-{
-    Map_NodeVec_t * vNodes;
-    int Result;
-    vNodes = Map_MappingDfs( pMan, fChoices );
-    Result = vNodes->nSize;
-    Map_NodeVecFree( vNodes );
-    return Result;    
-}
-
-////////////////////////////////////////////////////////////////////////
-///                       END OF FILE                                ///
-////////////////////////////////////////////////////////////////////////
-
-
diff --git a/abc70930/src/map/mapper/mapperVec.c b/abc70930/src/map/mapper/mapperVec.c
deleted file mode 100644
index f75138fb..00000000
--- a/abc70930/src/map/mapper/mapperVec.c
+++ /dev/null
@@ -1,318 +0,0 @@
-/**CFile****************************************************************
-
-  FileName    [mapperVec.c]
-
-  PackageName [MVSIS 1.3: Multi-valued logic synthesis system.]
-
-  Synopsis    [Generic technology mapping engine.]
-
-  Author      [MVSIS Group]
-  
-  Affiliation [UC Berkeley]
-
-  Date        [Ver. 2.0. Started - June 1, 2004.]
-
-  Revision    [$Id: mapperVec.c,v 1.3 2005/01/23 06:59:45 alanmi Exp $]
-
-***********************************************************************/
-
-#include "mapperInt.h"
-
-////////////////////////////////////////////////////////////////////////
-///                        DECLARATIONS                              ///
-////////////////////////////////////////////////////////////////////////
-
-static int Map_NodeVecCompareLevels( Map_Node_t ** pp1, Map_Node_t ** pp2 );
-
-////////////////////////////////////////////////////////////////////////
-///                     FUNCTION DEFINITIONS                         ///
-////////////////////////////////////////////////////////////////////////
-
-/**Function*************************************************************
-
-  Synopsis    [Allocates a vector with the given capacity.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-Map_NodeVec_t * Map_NodeVecAlloc( int nCap )
-{
-    Map_NodeVec_t * p;
-    p = ALLOC( Map_NodeVec_t, 1 );
-    if ( nCap > 0 && nCap < 16 )
-        nCap = 16;
-    p->nSize  = 0;
-    p->nCap   = nCap;
-    p->pArray = p->nCap? ALLOC( Map_Node_t *, p->nCap ) : NULL;
-    return p;
-}
-
-/**Function*************************************************************
-
-  Synopsis    []
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Map_NodeVecFree( Map_NodeVec_t * p )
-{
-    FREE( p->pArray );
-    FREE( p );
-}
-
-/**Function*************************************************************
-
-  Synopsis    []
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-Map_Node_t ** Map_NodeVecReadArray( Map_NodeVec_t * p )
-{
-    return p->pArray;
-}
-
-/**Function*************************************************************
-
-  Synopsis    []
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Map_NodeVecReadSize( Map_NodeVec_t * p )
-{
-    return p->nSize;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Resizes the vector to the given capacity.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Map_NodeVecGrow( Map_NodeVec_t * p, int nCapMin )
-{
-    if ( p->nCap >= nCapMin )
-        return;
-    p->pArray = REALLOC( Map_Node_t *, p->pArray, nCapMin ); 
-    p->nCap   = nCapMin;
-}
-
-/**Function*************************************************************
-
-  Synopsis    []
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Map_NodeVecShrink( Map_NodeVec_t * p, int nSizeNew )
-{
-    assert( p->nSize >= nSizeNew );
-    p->nSize = nSizeNew;
-}
-
-/**Function*************************************************************
-
-  Synopsis    []
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Map_NodeVecClear( Map_NodeVec_t * p )
-{
-    p->nSize = 0;
-}
-
-/**Function*************************************************************
-
-  Synopsis    []
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Map_NodeVecPush( Map_NodeVec_t * p, Map_Node_t * Entry )
-{
-    if ( p->nSize == p->nCap )
-    {
-        if ( p->nCap < 16 )
-            Map_NodeVecGrow( p, 16 );
-        else
-            Map_NodeVecGrow( p, 2 * p->nCap );
-    }
-    p->pArray[p->nSize++] = Entry;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Add the element while ensuring uniqueness.]
-
-  Description [Returns 1 if the element was found, and 0 if it was new. ]
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Map_NodeVecPushUnique( Map_NodeVec_t * p, Map_Node_t * Entry )
-{
-    int i;
-    for ( i = 0; i < p->nSize; i++ )
-        if ( p->pArray[i] == Entry )
-            return 1;
-    Map_NodeVecPush( p, Entry );
-    return 0;
-}
-
-/**Function*************************************************************
-
-  Synopsis    []
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-Map_Node_t * Map_NodeVecPop( Map_NodeVec_t * p )
-{
-    return p->pArray[--p->nSize];
-}
-
-/**Function*************************************************************
-
-  Synopsis    []
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Map_NodeVecRemove( Map_NodeVec_t * p, Map_Node_t * Entry )
-{
-    int i;
-    for ( i = 0; i < p->nSize; i++ )
-        if ( p->pArray[i] == Entry )
-            break;
-    assert( i < p->nSize );
-    for ( i++; i < p->nSize; i++ )
-        p->pArray[i-1] = p->pArray[i];
-    p->nSize--;
-}
-
-/**Function*************************************************************
-
-  Synopsis    []
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Map_NodeVecWriteEntry( Map_NodeVec_t * p, int i, Map_Node_t * Entry )
-{
-    assert( i >= 0 && i < p->nSize );
-    p->pArray[i] = Entry;
-}
-
-/**Function*************************************************************
-
-  Synopsis    []
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-Map_Node_t * Map_NodeVecReadEntry( Map_NodeVec_t * p, int i )
-{
-    assert( i >= 0 && i < p->nSize );
-    return p->pArray[i];
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Sorting the entries by their integer value.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Map_NodeVecSortByLevel( Map_NodeVec_t * p )
-{
-    qsort( (void *)p->pArray, p->nSize, sizeof(Map_Node_t *), 
-            (int (*)(const void *, const void *)) Map_NodeVecCompareLevels );
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Comparison procedure for two clauses.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Map_NodeVecCompareLevels( Map_Node_t ** pp1, Map_Node_t ** pp2 )
-{
-    int Level1 = Map_Regular(*pp1)->Level;
-    int Level2 = Map_Regular(*pp2)->Level;
-    if ( Level1 < Level2 )
-        return -1;
-    if ( Level1 > Level2 )
-        return 1;
-    if ( Map_Regular(*pp1)->Num < Map_Regular(*pp2)->Num )
-        return -1;
-    if ( Map_Regular(*pp1)->Num > Map_Regular(*pp2)->Num )
-        return 1;
-    return 0; 
-}
-
-////////////////////////////////////////////////////////////////////////
-///                       END OF FILE                                ///
-////////////////////////////////////////////////////////////////////////
-
diff --git a/abc70930/src/map/mapper/module.make b/abc70930/src/map/mapper/module.make
deleted file mode 100644
index bd6447d8..00000000
--- a/abc70930/src/map/mapper/module.make
+++ /dev/null
@@ -1,18 +0,0 @@
-SRC +=  src/map/mapper/mapper.c \
-    src/map/mapper/mapperCanon.c \
-    src/map/mapper/mapperCore.c \
-    src/map/mapper/mapperCreate.c \
-    src/map/mapper/mapperCut.c \
-    src/map/mapper/mapperCutUtils.c \
-    src/map/mapper/mapperFanout.c \
-    src/map/mapper/mapperLib.c \
-    src/map/mapper/mapperMatch.c \
-    src/map/mapper/mapperRefs.c \
-    src/map/mapper/mapperSuper.c \
-    src/map/mapper/mapperSwitch.c \
-    src/map/mapper/mapperTable.c \
-    src/map/mapper/mapperTime.c \
-    src/map/mapper/mapperTree.c \
-    src/map/mapper/mapperTruth.c \
-    src/map/mapper/mapperUtils.c \
-    src/map/mapper/mapperVec.c
diff --git a/abc70930/src/map/mio/mio.c b/abc70930/src/map/mio/mio.c
deleted file mode 100644
index 10a5af9d..00000000
--- a/abc70930/src/map/mio/mio.c
+++ /dev/null
@@ -1,269 +0,0 @@
-/**CFile****************************************************************
-
-  FileName    [mio.c]
-
-  PackageName [MVSIS 1.3: Multi-valued logic synthesis system.]
-
-  Synopsis    [File reading/writing for technology mapping.]
-
-  Author      [MVSIS Group]
-  
-  Affiliation [UC Berkeley]
-
-  Date        [Ver. 1.0. Started - August 18, 2003.]
-
-  Revision    [$Id: mio.c,v 1.4 2004/08/05 18:34:51 satrajit Exp $]
-
-***********************************************************************/
-
-#include "abc.h"
-#include "mvc.h"
-#include "mainInt.h"
-#include "mioInt.h"
-#include "mapper.h"
-
-////////////////////////////////////////////////////////////////////////
-///                        DECLARATIONS                              ///
-////////////////////////////////////////////////////////////////////////
-
-static int Mio_CommandReadLibrary( Abc_Frame_t * pAbc, int argc, char **argv );
-static int Mio_CommandPrintLibrary( Abc_Frame_t * pAbc, int argc, char **argv );
-
-// internal version of GENLIB library
-static char * pMcncGenlib[25] = {
-    "GATE inv1    1   O=!a;             PIN * INV     1 999 0.9 0.0 0.9 0.0\n",
-    "GATE inv2    2   O=!a;             PIN * INV     2 999 1.0 0.0 1.0 0.0\n",
-    "GATE inv3    3   O=!a;             PIN * INV     3 999 1.1 0.0 1.1 0.0\n",
-    "GATE inv4    4   O=!a;             PIN * INV     4 999 1.2 0.0 1.2 0.0\n",
-    "GATE nand2   2   O=!(a*b);         PIN * INV     1 999 1.0 0.0 1.0 0.0\n",
-    "GATE nand3   3   O=!(a*b*c);       PIN * INV     1 999 1.1 0.0 1.1 0.0\n",
-    "GATE nand4   4   O=!(a*b*c*d);     PIN * INV     1 999 1.4 0.0 1.4 0.0\n",
-    "GATE nor2    2   O=!(a+b);         PIN * INV     1 999 1.4 0.0 1.4 0.0\n",
-    "GATE nor3    3   O=!(a+b+c);       PIN * INV     1 999 2.4 0.0 2.4 0.0\n",
-    "GATE nor4    4   O=!(a+b+c+d);     PIN * INV     1 999 3.8 0.0 3.8 0.0\n",
-    "GATE xora    5   O=a*!b+!a*b;      PIN * UNKNOWN 2 999 1.9 0.0 1.9 0.0\n",
-    "GATE xorb    5   O=!(a*b+!a*!b);   PIN * UNKNOWN 2 999 1.9 0.0 1.9 0.0\n",
-    "GATE xnora   5   O=a*b+!a*!b;      PIN * UNKNOWN 2 999 2.1 0.0 2.1 0.0\n",
-    "GATE xnorb   5   O=!(!a*b+a*!b);   PIN * UNKNOWN 2 999 2.1 0.0 2.1 0.0\n",
-    "GATE aoi21   3   O=!(a*b+c);       PIN * INV     1 999 1.6 0.0 1.6 0.0\n",
-    "GATE aoi22   4   O=!(a*b+c*d);     PIN * INV     1 999 2.0 0.0 2.0 0.0\n",
-    "GATE oai21   3   O=!((a+b)*c);     PIN * INV     1 999 1.6 0.0 1.6 0.0\n",
-    "GATE oai22   4   O=!((a+b)*(c+d)); PIN * INV     1 999 2.0 0.0 2.0 0.0\n",
-    "GATE buf     1   O=a;              PIN * NONINV  1 999 1.0 0.0 1.0 0.0\n",
-    "GATE zero    0   O=CONST0;\n",
-    "GATE one     0   O=CONST1;\n"
-};
-
-////////////////////////////////////////////////////////////////////////
-///                     FUNCTION DEFINITIONS                         ///
-////////////////////////////////////////////////////////////////////////
-
-/**Function*************************************************************
-
-  Synopsis    []
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Mio_Init( Abc_Frame_t * pAbc )
-{
-    char * pFileTemp = "mcnc_temp.genlib";
-    Mio_Library_t * pLibGen;
-    FILE * pFile;
-    int i;
-
-    // write genlib into file
-    pFile = fopen( pFileTemp, "w" );
-    for ( i = 0; pMcncGenlib[i]; i++ )
-        fputs( pMcncGenlib[i], pFile );
-    fclose( pFile );
-    // read genlib from file
-    pLibGen = Mio_LibraryRead( pAbc, pFileTemp, NULL, 0 );
-    Abc_FrameSetLibGen( pLibGen );
-#ifdef WIN32
-        _unlink( pFileTemp );
-#else
-        unlink( pFileTemp );
-#endif
-
-    Cmd_CommandAdd( pAbc, "SC mapping", "read_library",   Mio_CommandReadLibrary,  0 ); 
-    Cmd_CommandAdd( pAbc, "SC mapping", "print_library",  Mio_CommandPrintLibrary, 0 ); 
-}
-
-/**Function*************************************************************
-
-  Synopsis    []
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Mio_End()
-{
-//    Mio_LibraryDelete( s_pLib );
-    Mio_LibraryDelete( Abc_FrameReadLibGen() );
-}
-
-
-/**Function*************************************************************
-
-  Synopsis    []
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Mio_CommandReadLibrary( Abc_Frame_t * pAbc, int argc, char **argv )
-{
-    FILE * pFile;
-    FILE * pOut, * pErr;
-    Mio_Library_t * pLib;
-    Abc_Ntk_t * pNet;
-    char * FileName;
-    int fVerbose;
-    int c;
-
-    pNet = Abc_FrameReadNtk(pAbc);
-    pOut = Abc_FrameReadOut(pAbc);
-    pErr = Abc_FrameReadErr(pAbc);
-
-    // set the defaults
-    fVerbose = 1;
-    Extra_UtilGetoptReset();
-    while ( (c = Extra_UtilGetopt(argc, argv, "vh")) != EOF ) 
-    {
-        switch (c) 
-        {
-            case 'v':
-                fVerbose ^= 1;
-                break;
-            case 'h':
-                goto usage;
-                break;
-            default:
-                goto usage;
-        }
-    }
-
-
-    if ( argc != globalUtilOptind + 1 )
-    {
-        goto usage;
-    }
-
-    // get the input file name
-    FileName = argv[globalUtilOptind];
-    if ( (pFile = Io_FileOpen( FileName, "open_path", "r", 0 )) == NULL )
-    {
-        fprintf( pErr, "Cannot open input file \"%s\". ", FileName );
-        if ( (FileName = Extra_FileGetSimilarName( FileName, ".genlib", ".lib", ".gen", ".g", NULL )) )
-            fprintf( pErr, "Did you mean \"%s\"?", FileName );
-        fprintf( pErr, "\n" );
-        return 1;
-    }
-    fclose( pFile );
-
-    // set the new network
-    pLib = Mio_LibraryRead( pAbc, FileName, 0, fVerbose );  
-    if ( pLib == NULL )
-    {
-        fprintf( pErr, "Reading GENLIB library has failed.\n" );
-        return 1;
-    }
-    // free the current superlib because it depends on the old Mio library
-    if ( Abc_FrameReadLibSuper() )
-    {
-        extern void Map_SuperLibFree( Map_SuperLib_t * p );
-//        Map_SuperLibFree( s_pSuperLib );
-//        s_pSuperLib = NULL;
-        Map_SuperLibFree( Abc_FrameReadLibSuper() );
-        Abc_FrameSetLibSuper( NULL );
-    }
-
-    // replace the current library
-//    Mio_LibraryDelete( s_pLib );
-//    s_pLib = pLib;
-    Mio_LibraryDelete( Abc_FrameReadLibGen() );
-    Abc_FrameSetLibGen( pLib );
-    return 0;
-
-usage:
-    fprintf( pErr, "usage: read_library [-vh]\n");
-    fprintf( pErr, "\t         read the library from a genlib file\n" );  
-    fprintf( pErr, "\t-h     : enable verbose output\n");
-    return 1;       /* error exit */
-}
-
-
-/**Function*************************************************************
-
-  Synopsis    [Command procedure to read LUT libraries.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Mio_CommandPrintLibrary( Abc_Frame_t * pAbc, int argc, char **argv )
-{
-    FILE * pOut, * pErr;
-    Abc_Ntk_t * pNet;
-    int fVerbose;
-    int c;
-
-    pNet = Abc_FrameReadNtk(pAbc);
-    pOut = Abc_FrameReadOut(pAbc);
-    pErr = Abc_FrameReadErr(pAbc);
-
-    // set the defaults
-    fVerbose = 1;
-    Extra_UtilGetoptReset();
-    while ( (c = Extra_UtilGetopt(argc, argv, "vh")) != EOF ) 
-    {
-        switch (c) 
-        {
-            case 'v':
-                fVerbose ^= 1;
-                break;
-            case 'h':
-                goto usage;
-                break;
-            default:
-                goto usage;
-        }
-    }
-
-
-    if ( argc != globalUtilOptind )
-    {
-        goto usage;
-    }
-
-    // set the new network
-    Mio_WriteLibrary( stdout, Abc_FrameReadLibGen(), 0 );
-    return 0;
-
-usage:
-    fprintf( pErr, "\nusage: print_library [-vh]\n");
-    fprintf( pErr, "\t          print the current genlib library\n" );  
-    fprintf( pErr, "\t-v      : toggles enabling of verbose output [default = %s]\n", (fVerbose? "yes" : "no") );
-    fprintf( pErr, "\t-h      : print the command usage\n");
-    return 1;       /* error exit */
-}
-////////////////////////////////////////////////////////////////////////
-///                       END OF FILE                                ///
-////////////////////////////////////////////////////////////////////////
-
-
diff --git a/abc70930/src/map/mio/mio.h b/abc70930/src/map/mio/mio.h
deleted file mode 100644
index dbe2420b..00000000
--- a/abc70930/src/map/mio/mio.h
+++ /dev/null
@@ -1,150 +0,0 @@
-/**CFile****************************************************************
-
-  FileName    [mio.h]
-
-  PackageName [MVSIS 2.0: Multi-valued logic synthesis system.]
-
-  Synopsis    [File reading/writing for technology mapping.]
-
-  Author      [MVSIS Group]
-  
-  Affiliation [UC Berkeley]
-
-  Date        [Ver. 1.0. Started - September 8, 2003.]
-
-  Revision    [$Id: mio.h,v 1.6 2004/08/09 22:16:31 satrajit Exp $]
-
-***********************************************************************/
-
-#ifndef __MIO_H__
-#define __MIO_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-////////////////////////////////////////////////////////////////////////
-///                          INCLUDES                                ///
-////////////////////////////////////////////////////////////////////////
-
-////////////////////////////////////////////////////////////////////////
-///                         PARAMETERS                               ///
-////////////////////////////////////////////////////////////////////////
-
-////////////////////////////////////////////////////////////////////////
-///                    STRUCTURE DEFINITIONS                         ///
-////////////////////////////////////////////////////////////////////////
-
-typedef enum { MIO_PHASE_UNKNOWN, MIO_PHASE_INV, MIO_PHASE_NONINV } Mio_PinPhase_t;
-
-typedef struct  Mio_LibraryStruct_t_      Mio_Library_t;
-typedef struct  Mio_GateStruct_t_         Mio_Gate_t;
-typedef struct  Mio_PinStruct_t_          Mio_Pin_t;
-
-////////////////////////////////////////////////////////////////////////
-///                       GLOBAL VARIABLES                           ///
-////////////////////////////////////////////////////////////////////////
-
-////////////////////////////////////////////////////////////////////////
-///                       MACRO DEFINITIONS                          ///
-////////////////////////////////////////////////////////////////////////
- 
-#define Mio_LibraryForEachGate( Lib, Gate )                   \
-    for ( Gate = Mio_LibraryReadGates(Lib);                   \
-          Gate;                                               \
-          Gate = Mio_GateReadNext(Gate) )
-#define Mio_LibraryForEachGateSafe( Lib, Gate, Gate2 )        \
-    for ( Gate = Mio_LibraryReadGates(Lib),                   \
-          Gate2 = (Gate? Mio_GateReadNext(Gate): NULL);       \
-          Gate;                                               \
-          Gate = Gate2,                                       \
-          Gate2 = (Gate? Mio_GateReadNext(Gate): NULL) )
-
-#define Mio_GateForEachPin( Gate, Pin )                       \
-    for ( Pin = Mio_GateReadPins(Gate);                       \
-          Pin;                                                \
-          Pin = Mio_PinReadNext(Pin) )
-#define Mio_GateForEachPinSafe( Gate, Pin, Pin2 )              \
-    for ( Pin = Mio_GateReadPins(Gate),                        \
-          Pin2 = (Pin? Mio_PinReadNext(Pin): NULL);           \
-          Pin;                                                \
-          Pin = Pin2,                                         \
-          Pin2 = (Pin? Mio_PinReadNext(Pin): NULL) )
-
-////////////////////////////////////////////////////////////////////////
-///                     FUNCTION DEFINITIONS                         ///
-////////////////////////////////////////////////////////////////////////
-
-/*=== mioApi.c =============================================================*/
-extern char *            Mio_LibraryReadName       ( Mio_Library_t * pLib );
-extern int               Mio_LibraryReadGateNum    ( Mio_Library_t * pLib );
-extern Mio_Gate_t *      Mio_LibraryReadGates      ( Mio_Library_t * pLib );
-extern DdManager *       Mio_LibraryReadDd         ( Mio_Library_t * pLib );
-extern Mio_Gate_t *      Mio_LibraryReadGateByName ( Mio_Library_t * pLib, char * pName );
-extern char *            Mio_LibraryReadSopByName  ( Mio_Library_t * pLib, char * pName );    
-extern Mio_Gate_t *      Mio_LibraryReadConst0     ( Mio_Library_t * pLib );
-extern Mio_Gate_t *      Mio_LibraryReadConst1     ( Mio_Library_t * pLib );
-extern Mio_Gate_t *      Mio_LibraryReadNand2      ( Mio_Library_t * pLib );
-extern Mio_Gate_t *      Mio_LibraryReadAnd2       ( Mio_Library_t * pLib );
-extern Mio_Gate_t *      Mio_LibraryReadBuf        ( Mio_Library_t * pLib );
-extern Mio_Gate_t *      Mio_LibraryReadInv        ( Mio_Library_t * pLib );
-extern float             Mio_LibraryReadDelayInvRise( Mio_Library_t * pLib );
-extern float             Mio_LibraryReadDelayInvFall( Mio_Library_t * pLib );
-extern float             Mio_LibraryReadDelayInvMax( Mio_Library_t * pLib );
-extern float             Mio_LibraryReadDelayNand2Rise( Mio_Library_t * pLib );
-extern float             Mio_LibraryReadDelayNand2Fall( Mio_Library_t * pLib );
-extern float             Mio_LibraryReadDelayNand2Max( Mio_Library_t * pLib );
-extern float             Mio_LibraryReadDelayAnd2Max( Mio_Library_t * pLib );
-extern float             Mio_LibraryReadAreaInv    ( Mio_Library_t * pLib );
-extern float             Mio_LibraryReadAreaBuf    ( Mio_Library_t * pLib );
-extern float             Mio_LibraryReadAreaNand2  ( Mio_Library_t * pLib );
-extern int               Mio_LibraryReadGateNameMax( Mio_Library_t * pLib );
-extern char *            Mio_GateReadName          ( Mio_Gate_t * pGate );      
-extern char *            Mio_GateReadOutName       ( Mio_Gate_t * pGate );      
-extern double            Mio_GateReadArea          ( Mio_Gate_t * pGate );      
-extern char *            Mio_GateReadForm          ( Mio_Gate_t * pGate );      
-extern Mio_Pin_t *       Mio_GateReadPins          ( Mio_Gate_t * pGate );      
-extern Mio_Library_t *   Mio_GateReadLib           ( Mio_Gate_t * pGate );      
-extern Mio_Gate_t *      Mio_GateReadNext          ( Mio_Gate_t * pGate );      
-extern int               Mio_GateReadInputs        ( Mio_Gate_t * pGate );      
-extern double            Mio_GateReadDelayMax      ( Mio_Gate_t * pGate );      
-extern char *            Mio_GateReadSop           ( Mio_Gate_t * pGate );      
-extern DdNode *          Mio_GateReadFunc          ( Mio_Gate_t * pGate );
-extern char *            Mio_PinReadName           ( Mio_Pin_t * pPin );  
-extern Mio_PinPhase_t    Mio_PinReadPhase          ( Mio_Pin_t * pPin );  
-extern double            Mio_PinReadInputLoad      ( Mio_Pin_t * pPin );  
-extern double            Mio_PinReadMaxLoad        ( Mio_Pin_t * pPin );  
-extern double            Mio_PinReadDelayBlockRise ( Mio_Pin_t * pPin );  
-extern double            Mio_PinReadDelayFanoutRise( Mio_Pin_t * pPin );  
-extern double            Mio_PinReadDelayBlockFall ( Mio_Pin_t * pPin );  
-extern double            Mio_PinReadDelayFanoutFall( Mio_Pin_t * pPin );  
-extern double            Mio_PinReadDelayBlockMax  ( Mio_Pin_t * pPin );  
-extern Mio_Pin_t *       Mio_PinReadNext           ( Mio_Pin_t * pPin );  
-/*=== mioRead.c =============================================================*/
-extern Mio_Library_t *   Mio_LibraryRead( void * pAbc, char * FileName, char * ExcludeFile, int fVerbose );
-extern int               Mio_LibraryReadExclude( void * pAbc, char * ExcludeFile, st_table * tExcludeGate );
-/*=== mioFunc.c =============================================================*/
-extern int               Mio_LibraryParseFormulas( Mio_Library_t * pLib );
-/*=== mioUtils.c =============================================================*/
-extern void              Mio_LibraryDelete( Mio_Library_t * pLib );
-extern void              Mio_GateDelete( Mio_Gate_t * pGate );
-extern void              Mio_PinDelete( Mio_Pin_t * pPin );
-extern Mio_Pin_t *       Mio_PinDup( Mio_Pin_t * pPin );
-extern void              Mio_WriteLibrary( FILE * pFile, Mio_Library_t * pLib, int fPrintSops );
-extern Mio_Gate_t **     Mio_CollectRoots( Mio_Library_t * pLib, int nInputs, float tDelay, bool fSkipInv, int * pnGates );
-extern void              Mio_DeriveTruthTable( Mio_Gate_t * pGate, unsigned uTruthsIn[][2], int nSigns, int nInputs, unsigned uTruthRes[] );
-extern void              Mio_DeriveGateDelays( Mio_Gate_t * pGate, 
-                            float ** ptPinDelays, int nPins, int nInputs, float tDelayZero, 
-                            float * ptDelaysRes, float * ptPinDelayMax );
-extern Mio_Gate_t *      Mio_GateCreatePseudo( int nInputs );
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-////////////////////////////////////////////////////////////////////////
-///                       END OF FILE                                ///
-////////////////////////////////////////////////////////////////////////
-
diff --git a/abc70930/src/map/mio/mioApi.c b/abc70930/src/map/mio/mioApi.c
deleted file mode 100644
index 73473f8b..00000000
--- a/abc70930/src/map/mio/mioApi.c
+++ /dev/null
@@ -1,172 +0,0 @@
-/**CFile****************************************************************
-
-  FileName    [mioApi.c]
-
-  PackageName [MVSIS 1.3: Multi-valued logic synthesis system.]
-
-  Synopsis    [File reading/writing for technology mapping.]
-
-  Author      [MVSIS Group]
-  
-  Affiliation [UC Berkeley]
-
-  Date        [Ver. 1.0. Started - September 8, 2003.]
-
-  Revision    [$Id: mioApi.c,v 1.4 2004/06/28 14:20:25 alanmi Exp $]
-
-***********************************************************************/
-
-#include "mioInt.h"
-
-////////////////////////////////////////////////////////////////////////
-///                        DECLARATIONS                              ///
-////////////////////////////////////////////////////////////////////////
-
-////////////////////////////////////////////////////////////////////////
-///                     FUNCTION DEFINITIONS                         ///
-////////////////////////////////////////////////////////////////////////
-
-/**Function*************************************************************
-
-  Synopsis    []
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-char *            Mio_LibraryReadName          ( Mio_Library_t * pLib )  { return pLib->pName;    }
-int               Mio_LibraryReadGateNum       ( Mio_Library_t * pLib )  { return pLib->nGates;   }
-Mio_Gate_t *      Mio_LibraryReadGates         ( Mio_Library_t * pLib )  { return pLib->pGates;   }
-DdManager *       Mio_LibraryReadDd            ( Mio_Library_t * pLib )  { return pLib->dd;       }
-Mio_Gate_t *      Mio_LibraryReadBuf           ( Mio_Library_t * pLib )  { return pLib->pGateBuf; }
-Mio_Gate_t *      Mio_LibraryReadInv           ( Mio_Library_t * pLib )  { return pLib->pGateInv; }
-Mio_Gate_t *      Mio_LibraryReadConst0        ( Mio_Library_t * pLib )  { return pLib->pGate0;     }
-Mio_Gate_t *      Mio_LibraryReadConst1        ( Mio_Library_t * pLib )  { return pLib->pGate1;     }
-Mio_Gate_t *      Mio_LibraryReadNand2         ( Mio_Library_t * pLib )  { return pLib->pGateNand2; }
-Mio_Gate_t *      Mio_LibraryReadAnd2          ( Mio_Library_t * pLib )  { return pLib->pGateAnd2;  }
-float             Mio_LibraryReadDelayInvRise  ( Mio_Library_t * pLib )  { return (float)(pLib->pGateInv?   pLib->pGateInv->pPins->dDelayBlockRise   : 0.0); }
-float             Mio_LibraryReadDelayInvFall  ( Mio_Library_t * pLib )  { return (float)(pLib->pGateInv?   pLib->pGateInv->pPins->dDelayBlockFall   : 0.0); }
-float             Mio_LibraryReadDelayInvMax   ( Mio_Library_t * pLib )  { return (float)(pLib->pGateInv?   pLib->pGateInv->pPins->dDelayBlockMax    : 0.0); }
-float             Mio_LibraryReadDelayNand2Rise( Mio_Library_t * pLib )  { return (float)(pLib->pGateNand2? pLib->pGateNand2->pPins->dDelayBlockRise : 0.0); }
-float             Mio_LibraryReadDelayNand2Fall( Mio_Library_t * pLib )  { return (float)(pLib->pGateNand2? pLib->pGateNand2->pPins->dDelayBlockFall : 0.0); }
-float             Mio_LibraryReadDelayNand2Max ( Mio_Library_t * pLib )  { return (float)(pLib->pGateNand2? pLib->pGateNand2->pPins->dDelayBlockMax  : 0.0); }
-float             Mio_LibraryReadDelayAnd2Max  ( Mio_Library_t * pLib )  { return (float)(pLib->pGateAnd2?  pLib->pGateAnd2->pPins->dDelayBlockMax   : 0.0); }
-float             Mio_LibraryReadAreaInv       ( Mio_Library_t * pLib )  { return (float)(pLib->pGateInv?   pLib->pGateInv->dArea   : 0.0); }
-float             Mio_LibraryReadAreaBuf       ( Mio_Library_t * pLib )  { return (float)(pLib->pGateBuf?   pLib->pGateBuf->dArea   : 0.0); }
-float             Mio_LibraryReadAreaNand2     ( Mio_Library_t * pLib )  { return (float)(pLib->pGateNand2? pLib->pGateNand2->dArea : 0.0); }
-
-/**Function*************************************************************
-
-  Synopsis    [Returns the longest gate name.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Mio_LibraryReadGateNameMax( Mio_Library_t * pLib )
-{
-    Mio_Gate_t * pGate;
-    int LenMax = 0, LenCur;
-    Mio_LibraryForEachGate( pLib, pGate )
-    {
-        LenCur = strlen( Mio_GateReadName(pGate) );
-        if ( LenMax < LenCur )
-            LenMax = LenCur;
-    }
-    return LenMax;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Read Mvc of the gate by name.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-Mio_Gate_t * Mio_LibraryReadGateByName( Mio_Library_t * pLib, char * pName )      
-{ 
-    Mio_Gate_t * pGate;
-    if ( st_lookup( pLib->tName2Gate, pName, (char **)&pGate ) )
-        return pGate;
-    return NULL;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Read Mvc of the gate by name.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-char * Mio_LibraryReadSopByName( Mio_Library_t * pLib, char * pName )      
-{ 
-    Mio_Gate_t * pGate;
-    if ( st_lookup( pLib->tName2Gate, pName, (char **)&pGate ) )
-        return pGate->pSop;
-    return NULL;
-}
-
-/**Function*************************************************************
-
-  Synopsis    []
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-char *            Mio_GateReadName    ( Mio_Gate_t * pGate )           { return pGate->pName;     }
-char *            Mio_GateReadOutName ( Mio_Gate_t * pGate )           { return pGate->pOutName;  }
-double            Mio_GateReadArea    ( Mio_Gate_t * pGate )           { return pGate->dArea;     }
-char *            Mio_GateReadForm    ( Mio_Gate_t * pGate )           { return pGate->pForm;     }
-Mio_Pin_t *       Mio_GateReadPins    ( Mio_Gate_t * pGate )           { return pGate->pPins;     }
-Mio_Library_t *   Mio_GateReadLib     ( Mio_Gate_t * pGate )           { return pGate->pLib;      }
-Mio_Gate_t *      Mio_GateReadNext    ( Mio_Gate_t * pGate )           { return pGate->pNext;     }
-int               Mio_GateReadInputs  ( Mio_Gate_t * pGate )           { return pGate->nInputs;   }
-double            Mio_GateReadDelayMax( Mio_Gate_t * pGate )           { return pGate->dDelayMax; }
-char *            Mio_GateReadSop     ( Mio_Gate_t * pGate )           { return pGate->pSop;      }
-DdNode *          Mio_GateReadFunc    ( Mio_Gate_t * pGate )           { return pGate->bFunc;     }
-
-/**Function*************************************************************
-
-  Synopsis    []
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-char *            Mio_PinReadName           ( Mio_Pin_t * pPin )      { return pPin->pName;           }
-Mio_PinPhase_t    Mio_PinReadPhase          ( Mio_Pin_t * pPin )      { return pPin->Phase;           }
-double            Mio_PinReadInputLoad      ( Mio_Pin_t * pPin )      { return pPin->dLoadInput;      }
-double            Mio_PinReadMaxLoad        ( Mio_Pin_t * pPin )      { return pPin->dLoadMax;        }
-double            Mio_PinReadDelayBlockRise ( Mio_Pin_t * pPin )      { return pPin->dDelayBlockRise; }
-double            Mio_PinReadDelayFanoutRise( Mio_Pin_t * pPin )      { return pPin->dDelayFanoutRise;}
-double            Mio_PinReadDelayBlockFall ( Mio_Pin_t * pPin )      { return pPin->dDelayBlockFall; }
-double            Mio_PinReadDelayFanoutFall( Mio_Pin_t * pPin )      { return pPin->dDelayFanoutFall;}
-double            Mio_PinReadDelayBlockMax  ( Mio_Pin_t * pPin )      { return pPin->dDelayBlockMax;          }
-Mio_Pin_t *       Mio_PinReadNext           ( Mio_Pin_t * pPin )      { return pPin->pNext;           }
-
-////////////////////////////////////////////////////////////////////////
-///                       END OF FILE                                ///
-////////////////////////////////////////////////////////////////////////
-
-
diff --git a/abc70930/src/map/mio/mioFunc.c b/abc70930/src/map/mio/mioFunc.c
deleted file mode 100644
index 21a078f9..00000000
--- a/abc70930/src/map/mio/mioFunc.c
+++ /dev/null
@@ -1,268 +0,0 @@
-/**CFile****************************************************************
-
-  FileName    [mioFunc.c]
-
-  PackageName [MVSIS 1.3: Multi-valued logic synthesis system.]
-
-  Synopsis    [File reading/writing for technology mapping.]
-
-  Author      [MVSIS Group]
-  
-  Affiliation [UC Berkeley]
-
-  Date        [Ver. 1.0. Started - September 8, 2003.]
-
-  Revision    [$Id: mioFunc.c,v 1.4 2004/06/28 14:20:25 alanmi Exp $]
-
-***********************************************************************/
-
-#include "mioInt.h"
-#include "parse.h"
-
-////////////////////////////////////////////////////////////////////////
-///                        DECLARATIONS                              ///
-////////////////////////////////////////////////////////////////////////
-
-// these symbols (and no other) can appear in the formulas
-#define MIO_SYMB_AND    '*'
-#define MIO_SYMB_OR     '+'
-#define MIO_SYMB_NOT    '!'
-#define MIO_SYMB_AFTNOT '\''
-#define MIO_SYMB_OPEN   '('
-#define MIO_SYMB_CLOSE  ')'
-
-static int Mio_GateParseFormula( Mio_Gate_t * pGate );
-static int Mio_GateCollectNames( char * pFormula, char * pPinNames[] );
-
-////////////////////////////////////////////////////////////////////////
-///                     FUNCTION DEFINITIONS                         ///
-////////////////////////////////////////////////////////////////////////
-
-/**Function*************************************************************
-
-  Synopsis    [Deriving the functionality of the gates.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Mio_LibraryParseFormulas( Mio_Library_t * pLib )
-{
-    Mio_Gate_t * pGate;
-
-    // count the gates
-    pLib->nGates = 0;
-    Mio_LibraryForEachGate( pLib, pGate )
-        pLib->nGates++;        
-
-    // start a temporary BDD manager
-    pLib->dd = Cudd_Init( 20, 0, CUDD_UNIQUE_SLOTS, CUDD_CACHE_SLOTS, 0 );
-    // introduce ZDD variables
-    Cudd_zddVarsFromBddVars( pLib->dd, 2 );
-
-    // for each gate, derive its function
-    Mio_LibraryForEachGate( pLib, pGate )
-        if ( Mio_GateParseFormula( pGate ) )
-            return 1;
-    return 0;
-}
-
-
-/**Function*************************************************************
-
-  Synopsis    [Deriving the functionality of the gates.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Mio_GateParseFormula( Mio_Gate_t * pGate )
-{
-    DdManager * dd = pGate->pLib->dd;
-    char * pPinNames[100];
-    char * pPinNamesCopy[100];
-    Mio_Pin_t * pPin, ** ppPin;
-    int nPins, iPin, i;
-
-    // set the maximum delay of the gate; count pins
-    pGate->dDelayMax = 0.0;
-    nPins = 0;
-    Mio_GateForEachPin( pGate, pPin )
-    {
-        // set the maximum delay of the gate
-        if ( pGate->dDelayMax < pPin->dDelayBlockMax )
-            pGate->dDelayMax = pPin->dDelayBlockMax;
-        // count the pin
-        nPins++;
-    }
-
-    // check for the gate with const function
-    if ( nPins == 0 )
-    {
-        if ( strcmp( pGate->pForm, MIO_STRING_CONST0 ) == 0 )
-        {
-            pGate->bFunc = b0;
-            pGate->pSop = Abc_SopRegister( pGate->pLib->pMmFlex, " 0\n" );
-            pGate->pLib->pGate0 = pGate;
-        }
-        else if ( strcmp( pGate->pForm, MIO_STRING_CONST1 ) == 0 )
-        {
-            pGate->bFunc = b1;
-            pGate->pSop = Abc_SopRegister( pGate->pLib->pMmFlex, " 1\n" );
-            pGate->pLib->pGate1 = pGate;
-        }
-        else
-        {
-            printf( "Cannot parse formula \"%s\" of gate \"%s\".\n", pGate->pForm, pGate->pName );
-            return 1;
-        }
-        Cudd_Ref( pGate->bFunc );
-        return 0;
-    }
-
-    // collect the names as they appear in the formula
-    nPins = Mio_GateCollectNames( pGate->pForm, pPinNames );
-    if ( nPins == 0 )
-    {
-        printf( "Cannot read formula \"%s\" of gate \"%s\".\n", pGate->pForm, pGate->pName );
-        return 1;
-    }
-
-    // set the number of inputs
-    pGate->nInputs = nPins;
-
-    // consider the case when all the pins have identical pin info
-    if ( strcmp( pGate->pPins->pName, "*" ) == 0 )
-    {
-        // get the topmost (generic) pin
-        pPin = pGate->pPins;
-        FREE( pPin->pName );
-
-        // create individual pins from the generic pin
-        ppPin = &pPin->pNext;
-        for ( i = 1; i < nPins; i++ )
-        {
-            // get the new pin
-            *ppPin = Mio_PinDup( pPin );
-            // set its name
-            (*ppPin)->pName = pPinNames[i];
-            // prepare the next place in the list
-            ppPin = &((*ppPin)->pNext);
-        }
-        *ppPin = NULL;
-
-        // set the name of the topmost pin
-        pPin->pName = pPinNames[0];
-    }
-    else
-    {
-        // reorder the variable names to appear the save way as the pins
-        iPin = 0;
-        Mio_GateForEachPin( pGate, pPin )
-        {
-            // find the pin with the name pPin->pName
-            for ( i = 0; i < nPins; i++ )
-            {
-                if ( pPinNames[i] && strcmp( pPinNames[i], pPin->pName ) == 0 )
-                {
-                    // free pPinNames[i] because it is already available as pPin->pName
-                    // setting pPinNames[i] to NULL is useful to make sure that
-                    // this name is not assigned to two pins in the list
-                    FREE( pPinNames[i] );
-                    pPinNamesCopy[iPin++] = pPin->pName;
-                    break;
-                }
-                if ( i == nPins )
-                {
-                    printf( "Cannot find pin name \"%s\" in the formula \"%s\" of gate \"%s\".\n", 
-                        pPin->pName, pGate->pForm, pGate->pName );
-                    return 1;
-                }
-            }
-        }
-
-        // check for the remaining names
-        for ( i = 0; i < nPins; i++ )
-            if ( pPinNames[i] )
-            {
-                printf( "Name \"%s\" appears in the formula \"%s\" of gate \"%s\" but there is no such pin.\n", 
-                    pPinNames[i], pGate->pForm, pGate->pName );
-                return 1;
-            }
-
-        // copy the names back
-        memcpy( pPinNames, pPinNamesCopy, nPins * sizeof(char *) );
-    }
-
-    // expand the manager if necessary
-    if ( dd->size < nPins )
-    {
-        Cudd_Quit( dd );
-        dd = Cudd_Init( nPins + 10, 0, CUDD_UNIQUE_SLOTS, CUDD_CACHE_SLOTS, 0 );
-        Cudd_zddVarsFromBddVars( dd, 2 );
-    }
-
-    // derive the formula as the BDD
-    pGate->bFunc = Parse_FormulaParser( stdout, pGate->pForm, nPins, 0, pPinNames, dd, dd->vars );
-    Cudd_Ref( pGate->bFunc );
-
-    // derive the cover (SOP)
-    pGate->pSop = Abc_ConvertBddToSop( pGate->pLib->pMmFlex, dd, pGate->bFunc, pGate->bFunc, nPins, 0, pGate->pLib->vCube, -1 );
-    return 0;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Collect the pin names in the formula.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Mio_GateCollectNames( char * pFormula, char * pPinNames[] )
-{
-    char Buffer[1000];
-    char * pTemp;
-    int nPins, i;
-
-    // save the formula as it was
-    strcpy( Buffer, pFormula );
-
-    // remove the non-name symbols
-    for ( pTemp = Buffer; *pTemp; pTemp++ )
-        if ( *pTemp == MIO_SYMB_AND  || *pTemp == MIO_SYMB_OR || *pTemp == MIO_SYMB_NOT
-          || *pTemp == MIO_SYMB_OPEN || *pTemp == MIO_SYMB_CLOSE || *pTemp == MIO_SYMB_AFTNOT )
-            *pTemp = ' ';
-
-    // save the names
-    nPins = 0;
-    pTemp = strtok( Buffer, " " );
-    while ( pTemp )
-    {
-        for ( i = 0; i < nPins; i++ )
-            if ( strcmp( pTemp, pPinNames[i] ) == 0 )
-                break;
-        if ( i == nPins )
-        { // cannot find this name; save it
-            pPinNames[nPins++] = Extra_UtilStrsav(pTemp);
-        }
-        // get the next name
-        pTemp = strtok( NULL, " " );
-    }
-    return nPins;
-}
-
-////////////////////////////////////////////////////////////////////////
-///                       END OF FILE                                ///
-////////////////////////////////////////////////////////////////////////
-
-
diff --git a/abc70930/src/map/mio/mioGENERIC.c b/abc70930/src/map/mio/mioGENERIC.c
deleted file mode 100644
index 972c4ffc..00000000
--- a/abc70930/src/map/mio/mioGENERIC.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/**CFile****************************************************************
-
-  FileName    [mio___.c]
-
-  PackageName [MVSIS 1.3: Multi-valued logic synthesis system.]
-
-  Synopsis    [File reading/writing for technology mapping.]
-
-  Author      [MVSIS Group]
-  
-  Affiliation [UC Berkeley]
-
-  Date        [Ver. 1.0. Started - September 8, 2003.]
-
-  Revision    [$Id: mio___.h,v 1.0 2003/09/08 00:00:00 alanmi Exp $]
-
-***********************************************************************/
-
-#include "mioInt.h"
-
-////////////////////////////////////////////////////////////////////////
-///                        DECLARATIONS                              ///
-////////////////////////////////////////////////////////////////////////
-
-////////////////////////////////////////////////////////////////////////
-///                     FUNCTION DEFINITIONS                         ///
-////////////////////////////////////////////////////////////////////////
-
-/**Function*************************************************************
-
-  Synopsis    []
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-
-
-////////////////////////////////////////////////////////////////////////
-///                       END OF FILE                                ///
-////////////////////////////////////////////////////////////////////////
-
-
diff --git a/abc70930/src/map/mio/mioInt.h b/abc70930/src/map/mio/mioInt.h
deleted file mode 100644
index 3f90b625..00000000
--- a/abc70930/src/map/mio/mioInt.h
+++ /dev/null
@@ -1,125 +0,0 @@
-/**CFile****************************************************************
-
-  FileName    [mioInt.h]
-
-  PackageName [MVSIS 2.0: Multi-valued logic synthesis system.]
-
-  Synopsis    [File reading/writing for technology mapping.]
-
-  Author      [MVSIS Group]
-  
-  Affiliation [UC Berkeley]
-
-  Date        [Ver. 1.0. Started - September 8, 2003.]
-
-  Revision    [$Id: mioInt.h,v 1.4 2004/06/28 14:20:25 alanmi Exp $]
-
-***********************************************************************/
-
-#ifndef __MIO_INT_H__
-#define __MIO_INT_H__
-
-////////////////////////////////////////////////////////////////////////
-///                          INCLUDES                                ///
-////////////////////////////////////////////////////////////////////////
-
-#include "abc.h"
-#include "mvc.h"
-#include "main.h"
-#include "mio.h"
-#include "extra.h"
-
-////////////////////////////////////////////////////////////////////////
-///                         PARAMETERS                               ///
-////////////////////////////////////////////////////////////////////////
-
-#define    MIO_STRING_GATE       "GATE"
-#define    MIO_STRING_PIN        "PIN"
-#define    MIO_STRING_NONINV     "NONINV"
-#define    MIO_STRING_INV        "INV"
-#define    MIO_STRING_UNKNOWN    "UNKNOWN"
-
-#define    MIO_STRING_CONST0     "CONST0"
-#define    MIO_STRING_CONST1     "CONST1"
- 
-// the bit masks
-#define    MIO_MASK(n)         ((~((unsigned)0)) >> (32-(n)))
-#define    MIO_FULL             (~((unsigned)0))
-
-////////////////////////////////////////////////////////////////////////
-///                    STRUCTURE DEFINITIONS                         ///
-////////////////////////////////////////////////////////////////////////
-
-struct  Mio_LibraryStruct_t_
-{
-    char *             pName;       // the name of the library
-    int                nGates;      // the number of the gates
-    Mio_Gate_t *       pGates;      // the linked list of all gates in no particular order
-    Mio_Gate_t *       pGate0;      // the constant zero gate
-    Mio_Gate_t *       pGate1;      // the constant one gate
-    Mio_Gate_t *       pGateBuf;    // the buffer
-    Mio_Gate_t *       pGateInv;    // the inverter
-    Mio_Gate_t *       pGateNand2;  // the NAND2 gate
-    Mio_Gate_t *       pGateAnd2;   // the AND2 gate
-    st_table *         tName2Gate;  // the mapping of gate names into their pointer
-    DdManager *        dd;          // the nanager storing functions of gates
-    Extra_MmFlex_t *   pMmFlex;     // the memory manaqer for SOPs
-    Vec_Str_t *        vCube;       // temporary cube
-}; 
-
-struct  Mio_GateStruct_t_
-{
-    // information derived from the genlib file
-    char *             pName;       // the name of the gate
-    double             dArea;       // the area of the gate
-    char *             pForm;       // the formula describing functionality of the gate
-    Mio_Pin_t *        pPins;       // the linked list of all pins (one pin if info is the same)
-    char *             pOutName;    // the name of the output pin 
-    // the library to which this gate belongs
-    Mio_Library_t *    pLib; 
-    // the next gate in the list
-    Mio_Gate_t *       pNext;    
-
-    // the derived information
-    int                nInputs;     // the number of inputs
-    double             dDelayMax;   // the maximum delay
-    DdNode *           bFunc;       // the functionality
-    char *             pSop;
-};
-
-struct  Mio_PinStruct_t_
-{
-    char *             pName;
-    Mio_PinPhase_t     Phase;
-    double             dLoadInput;
-    double             dLoadMax;
-    double             dDelayBlockRise;
-    double             dDelayFanoutRise;
-    double             dDelayBlockFall;
-    double             dDelayFanoutFall;
-    double             dDelayBlockMax;
-    Mio_Pin_t *        pNext;     
-};
-
-
-////////////////////////////////////////////////////////////////////////
-///                       GLOBAL VARIABLES                           ///
-////////////////////////////////////////////////////////////////////////
-
-////////////////////////////////////////////////////////////////////////
-///                       MACRO DEFINITIONS                          ///
-////////////////////////////////////////////////////////////////////////
-
-////////////////////////////////////////////////////////////////////////
-///                     FUNCTION DEFINITIONS                         ///
-////////////////////////////////////////////////////////////////////////
-
-/*=== mio.c =============================================================*/
-/*=== mioRead.c =============================================================*/
-/*=== mioUtils.c =============================================================*/
-
-#endif
-
-////////////////////////////////////////////////////////////////////////
-///                       END OF FILE                                ///
-////////////////////////////////////////////////////////////////////////
diff --git a/abc70930/src/map/mio/mioRead.c b/abc70930/src/map/mio/mioRead.c
deleted file mode 100644
index 13c2cdcd..00000000
--- a/abc70930/src/map/mio/mioRead.c
+++ /dev/null
@@ -1,582 +0,0 @@
-/**CFile****************************************************************
-
-  FileName    [mioRead.c]
-
-  PackageName [MVSIS 1.3: Multi-valued logic synthesis system.]
-
-  Synopsis    [File reading/writing for technology mapping.]
-
-  Author      [MVSIS Group]
-  
-  Affiliation [UC Berkeley]
-
-  Date        [Ver. 1.0. Started - September 8, 2003.]
-
-  Revision    [$Id: mioRead.c,v 1.9 2004/10/19 06:40:16 satrajit Exp $]
-
-***********************************************************************/
-
-#include "mioInt.h"
-
-////////////////////////////////////////////////////////////////////////
-///                        DECLARATIONS                              ///
-////////////////////////////////////////////////////////////////////////
-
-////////////////////////////////////////////////////////////////////////
-///                     FUNCTION DEFINITIONS                         ///
-////////////////////////////////////////////////////////////////////////
-
-static Mio_Library_t * Mio_LibraryReadOne( Abc_Frame_t * pAbc, char * FileName, bool fExtendedFormat, st_table * tExcludeGate, int fVerbose );
-static int          Mio_LibraryReadInternal( Mio_Library_t * pLib, char * pBuffer, bool fExtendedFormat, st_table * tExcludeGate, int fVerbose );
-static Mio_Gate_t * Mio_LibraryReadGate( char ** ppToken, bool fExtendedFormat );
-static Mio_Pin_t *  Mio_LibraryReadPin( char ** ppToken, bool fExtendedFormat );
-static char *       chomp( char *s );
-static void         Mio_LibraryDetectSpecialGates( Mio_Library_t * pLib );
-static void         Io_ReadFileRemoveComments( char * pBuffer, int * pnDots, int * pnLines );
-
-#ifdef WIN32
-extern int          isspace( int c );  // to silence the warning in VS
-#endif
-
-/**Function*************************************************************
-
-  Synopsis    [Read the genlib type of library.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-Mio_Library_t * Mio_LibraryRead( void * pAbc, char * FileName, char * ExcludeFile, int fVerbose )
-{
-    Mio_Library_t * pLib;
-    int num;
-
-    st_table * tExcludeGate = 0;
-
-    if ( ExcludeFile )
-    {
-        tExcludeGate = st_init_table(strcmp, st_strhash);
-        if ( (num = Mio_LibraryReadExclude( pAbc, ExcludeFile, tExcludeGate )) == -1 )
-        {
-            st_free_table( tExcludeGate );
-            tExcludeGate = 0;
-            return 0;
-        }
-       
-        fprintf ( Abc_FrameReadOut( pAbc ), "Read %d gates from exclude file\n", num );
-    }
-
-    pLib = Mio_LibraryReadOne( pAbc, FileName, 0, tExcludeGate, fVerbose );       // try normal format first ..
-    if ( pLib == NULL )
-    {
-        pLib = Mio_LibraryReadOne( pAbc, FileName, 1, tExcludeGate, fVerbose );   // .. otherwise try extended format 
-        if ( pLib != NULL )
-            printf ( "Warning: Read extended GENLIB format but ignoring extensions\n" );
-    }
-
-    return pLib;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Read the genlib type of library.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-Mio_Library_t * Mio_LibraryReadOne( Abc_Frame_t * pAbc, char * FileName, bool fExtendedFormat, st_table * tExcludeGate, int fVerbose )
-{
-    Mio_Library_t * pLib;
-    char * pBuffer = 0;
-
-    // allocate the genlib structure
-    pLib = ALLOC( Mio_Library_t, 1 );
-    memset( pLib, 0, sizeof(Mio_Library_t) );
-    pLib->pName = Extra_UtilStrsav( FileName );
-    pLib->tName2Gate = st_init_table(strcmp, st_strhash);
-    pLib->pMmFlex = Extra_MmFlexStart();
-    pLib->vCube = Vec_StrAlloc( 100 );
-
-    // read the file and clean comments
-    // pBuffer = Io_ReadFileFileContents( FileName, NULL );
-    // we don't use above function but actually do the same thing explicitly
-    // to handle open_path expansion correctly
-
-    {
-        FILE * pFile;
-        int nFileSize;
-
-        // open the BLIF file for binary reading
-        pFile = Io_FileOpen( FileName, "open_path", "rb", 1 );
-//        pFile = fopen( FileName, "rb" );
-        // if we got this far, file should be okay otherwise would
-        // have been detected by caller
-        assert ( pFile != NULL );
-        // get the file size, in bytes
-        fseek( pFile, 0, SEEK_END );  
-        nFileSize = ftell( pFile );  
-        // move the file current reading position to the beginning
-        rewind( pFile ); 
-        // load the contents of the file into memory
-        pBuffer   = ALLOC( char, nFileSize + 10 );
-        fread( pBuffer, nFileSize, 1, pFile );
-        // terminate the string with '\0'
-        pBuffer[ nFileSize ] = '\0';
-        strcat( pBuffer, "\n.end\n" );
-        // close file
-        fclose( pFile );
-    }
-
-    Io_ReadFileRemoveComments( pBuffer, NULL, NULL );
-
-    // parse the contents of the file
-    if ( Mio_LibraryReadInternal( pLib, pBuffer, fExtendedFormat, tExcludeGate, fVerbose ) )
-    {
-        Mio_LibraryDelete( pLib );
-        free( pBuffer );
-        return NULL;
-    }
-    free( pBuffer );
-
-    // derive the functinality of gates
-    if ( Mio_LibraryParseFormulas( pLib ) )
-    {
-        printf( "Mio_LibraryRead: Had problems parsing formulas.\n" );
-        Mio_LibraryDelete( pLib );
-        return NULL;
-    }
-
-    // detect INV and NAND2
-    Mio_LibraryDetectSpecialGates( pLib );
-//Mio_WriteLibrary( stdout, pLib );
-    return pLib;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Read the genlib type of library.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Mio_LibraryReadInternal( Mio_Library_t * pLib, char * pBuffer, bool fExtendedFormat, st_table * tExcludeGate, int fVerbose )
-{
-    Mio_Gate_t * pGate, ** ppGate;
-    char * pToken;
-    int nGates = 0;
-    int nDel = 0;
-
-    // start the linked list of gates
-    pLib->pGates = NULL;
-    ppGate = &pLib->pGates;
-
-    // read gates one by one
-    pToken = strtok( pBuffer, " \t\r\n" );
-    while ( pToken && strcmp( pToken, MIO_STRING_GATE ) == 0 )
-    {
-        // derive the next gate
-        pGate = Mio_LibraryReadGate( &pToken, fExtendedFormat );
-        if ( pGate == NULL )
-            return 1;
-        
-        // set the library
-        pGate->pLib = pLib;
-
-        // printf ("Processing: '%s'\n", pGate->pName);
-
-        if ( tExcludeGate && st_is_member( tExcludeGate, pGate->pName ) )
-        {
-            //printf ("Excluding: '%s'\n", pGate->pName);
-            Mio_GateDelete( pGate );
-            nDel++;
-        } 
-        else
-        {
-            // add this gate to the list
-            *ppGate = pGate;
-            ppGate  = &pGate->pNext;
-            nGates++;
-
-            // remember this gate by name
-            if ( !st_is_member( pLib->tName2Gate, pGate->pName ) )
-                st_insert( pLib->tName2Gate, pGate->pName, (char *)pGate );
-            else
-                printf( "The gate with name \"%s\" appears more than once.\n", pGate->pName );
-        }
-    }
-    if ( fVerbose )
-    printf( "The number of gates read = %d.\n", nGates );
-
-    // check what is the last word read
-    if ( pToken && strcmp( pToken, ".end" ) != 0 )
-        return 1;
-
-    if ( nDel != 0 ) 
-        printf( "Actually excluded %d cells\n", nDel );
-
-    return 0;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Read the genlib type of gate.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-Mio_Gate_t * Mio_LibraryReadGate( char ** ppToken, bool fExtendedFormat )
-{
-    Mio_Gate_t * pGate;
-    Mio_Pin_t * pPin, ** ppPin;
-    char * pToken = *ppToken;
-
-    // allocate the gate structure
-    pGate = ALLOC( Mio_Gate_t, 1 );
-    memset( pGate, 0, sizeof(Mio_Gate_t) );
-
-    // read the name
-    pToken = strtok( NULL, " \t\r\n" );
-    pGate->pName = Extra_UtilStrsav( pToken );
-
-    // read the area
-    pToken = strtok( NULL, " \t\r\n" );
-    pGate->dArea = atof( pToken );
-
-    // read the formula
-
-    // first the output name
-    pToken = strtok( NULL, "=" );
-    pGate->pOutName = chomp( pToken );
-
-    // then rest of the expression 
-    pToken = strtok( NULL, ";" );
-    pGate->pForm = Extra_UtilStrsav( pToken );
-
-    // read the pin info
-    // start the linked list of pins
-    pGate->pPins = NULL;
-    ppPin = &pGate->pPins;
-
-    // read gates one by one
-    pToken = strtok( NULL, " \t\r\n" );
-    while ( pToken && strcmp( pToken, MIO_STRING_PIN ) == 0 )
-    {
-        // derive the next gate
-        pPin = Mio_LibraryReadPin( &pToken, fExtendedFormat );
-        if ( pPin == NULL )
-        {
-            Mio_GateDelete( pGate );
-            *ppToken = pToken;
-            return NULL;
-        }
-        // add this pin to the list
-        *ppPin = pPin;
-        ppPin  = &pPin->pNext;
-        // get the next token
-        pToken = strtok( NULL, " \t\r\n" );
-    }
-
-    *ppToken = pToken;
-    return pGate;
-}
-
-
-
-/**Function*************************************************************
-
-  Synopsis    [Read the genlib type of pin.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-Mio_Pin_t * Mio_LibraryReadPin( char ** ppToken, bool fExtendedFormat )
-{
-    Mio_Pin_t * pPin;
-    char * pToken = *ppToken;
-
-    // allocate the gate structure
-    pPin = ALLOC( Mio_Pin_t, 1 );
-    memset( pPin, 0, sizeof(Mio_Pin_t) );
-
-    // read the name
-    pToken = strtok( NULL, " \t\r\n" );
-    pPin->pName = Extra_UtilStrsav( pToken );
-
-    // read the pin phase
-    pToken = strtok( NULL, " \t\r\n" );
-    if ( strcmp( pToken, MIO_STRING_UNKNOWN ) == 0 )
-        pPin->Phase = MIO_PHASE_UNKNOWN;
-    else if ( strcmp( pToken, MIO_STRING_INV ) == 0 )
-        pPin->Phase = MIO_PHASE_INV;
-    else if ( strcmp( pToken, MIO_STRING_NONINV ) == 0 )
-        pPin->Phase = MIO_PHASE_NONINV;
-    else 
-    {
-        printf( "Cannot read pin phase specification\n" );
-        Mio_PinDelete( pPin );
-        *ppToken = pToken;
-        return NULL;
-    }
-
-    pToken = strtok( NULL, " \t\r\n" );
-    pPin->dLoadInput = atof( pToken );
-
-    pToken = strtok( NULL, " \t\r\n" );
-    pPin->dLoadMax = atof( pToken );
-
-    pToken = strtok( NULL, " \t\r\n" );
-    pPin->dDelayBlockRise = atof( pToken );
-
-    pToken = strtok( NULL, " \t\r\n" );
-    pPin->dDelayFanoutRise = atof( pToken );
-
-    pToken = strtok( NULL, " \t\r\n" );
-    pPin->dDelayBlockFall = atof( pToken );
-
-    pToken = strtok( NULL, " \t\r\n" );
-    pPin->dDelayFanoutFall = atof( pToken );
-
-    if ( fExtendedFormat )
-    {
-        /* In extended format, the field after dDelayFanoutRise
-         * is to be ignored
-         **/
-
-        pPin->dDelayBlockFall  = pPin->dDelayFanoutFall;
-
-        pToken = strtok( NULL, " \t" );
-        pPin->dDelayFanoutFall = atof( pToken );
-
-        /* last field is ignored */
-        pToken = strtok( NULL, " \t\r\n" );
-    }
-
-    if ( pPin->dDelayBlockRise > pPin->dDelayBlockFall )
-        pPin->dDelayBlockMax = pPin->dDelayBlockRise;
-    else
-        pPin->dDelayBlockMax = pPin->dDelayBlockFall;
-
-    *ppToken = pToken;
-    return pPin;
-}
-
-
-/**Function*************************************************************
-
-  Synopsis    [Duplicates string and returns it with leading and 
-               trailing spaces removed.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-char *chomp( char *s )
-{
-    char *b = ALLOC(char, strlen(s)+1), *c = b;
-    while (*s && isspace(*s))
-        ++s;
-    while (*s && !isspace(*s))
-        *c++ = *s++;
-    *c = 0;
-    return b;
-}   
-        
-/**Function*************************************************************
-
-  Synopsis    [Duplicates string and returns it with leading and 
-               trailing spaces removed.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Mio_LibraryDetectSpecialGates( Mio_Library_t * pLib )
-{
-    Mio_Gate_t * pGate;
-    DdNode * bFuncBuf, * bFuncInv, * bFuncNand2, * bFuncAnd2;
-
-    bFuncBuf   = pLib->dd->vars[0];                                              Cudd_Ref( bFuncBuf );
-    bFuncInv   = Cudd_Not( pLib->dd->vars[0] );                                  Cudd_Ref( bFuncInv );
-    bFuncNand2 = Cudd_bddNand( pLib->dd, pLib->dd->vars[0], pLib->dd->vars[1] ); Cudd_Ref( bFuncNand2 );
-    bFuncAnd2  = Cudd_bddAnd( pLib->dd, pLib->dd->vars[0], pLib->dd->vars[1] );  Cudd_Ref( bFuncAnd2 );
-
-    // get buffer
-    Mio_LibraryForEachGate( pLib, pGate )
-        if ( pLib->pGateBuf == NULL && pGate->bFunc == bFuncBuf )
-        {
-            pLib->pGateBuf = pGate;
-            break;
-        }
-    if ( pLib->pGateBuf == NULL )
-    {
-        printf( "Warnings: GENLIB library reader cannot detect the buffer gate.\n" );
-        printf( "Some parts of the supergate-based technology mapper may not work correctly.\n" );
-    }
- 
-    // get inverter
-    Mio_LibraryForEachGate( pLib, pGate )
-        if ( pLib->pGateInv == NULL && pGate->bFunc == bFuncInv )
-        {
-            pLib->pGateInv = pGate;
-            break;
-        }
-    if ( pLib->pGateInv == NULL )
-    {
-        printf( "Warnings: GENLIB library reader cannot detect the invertor gate.\n" );
-        printf( "Some parts of the supergate-based technology mapper may not work correctly.\n" );
-    }
-
-    // get the NAND2 and AND2 gates
-    Mio_LibraryForEachGate( pLib, pGate )
-        if ( pLib->pGateNand2 == NULL && pGate->bFunc == bFuncNand2 )
-        {
-            pLib->pGateNand2 = pGate;
-            break;
-        }
-    Mio_LibraryForEachGate( pLib, pGate )
-        if ( pLib->pGateAnd2 == NULL && pGate->bFunc == bFuncAnd2 )
-        {
-            pLib->pGateAnd2 = pGate;
-            break;
-        }
-    if ( pLib->pGateAnd2 == NULL && pLib->pGateNand2 == NULL )
-    {
-        printf( "Warnings: GENLIB library reader cannot detect the AND2 or NAND2 gate.\n" );
-        printf( "Some parts of the supergate-based technology mapper may not work correctly.\n" );
-    }
-
-    Cudd_RecursiveDeref( pLib->dd, bFuncInv );
-    Cudd_RecursiveDeref( pLib->dd, bFuncNand2 );
-    Cudd_RecursiveDeref( pLib->dd, bFuncAnd2 );
-}
-
-/**Function*************************************************************
-
-  Synopsis    [populate hash table of gates to be exlcuded from genlib]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Mio_LibraryReadExclude( void * pAbc, char * ExcludeFile, st_table * tExcludeGate )
-{
-    int nDel = 0;
-    FILE *pEx;
-    char buffer[128];
-
-    assert ( tExcludeGate );
-
-    if ( ExcludeFile )
-    {
-        pEx = fopen( ExcludeFile, "r" );
-
-        if ( pEx == NULL )
-        {
-            fprintf ( Abc_FrameReadErr( pAbc ), "Error: Could not open exclude file %s. Stop.\n", ExcludeFile );
-            return -1;
-        }
-
-        while (1 == fscanf( pEx, "%127s", buffer ))
-        {
-            //printf ("Read: '%s'\n", buffer );
-            st_insert( tExcludeGate, Extra_UtilStrsav( buffer ), (char *)0 );
-            nDel++;
-        }
-
-        fclose( pEx );
-    }
-
-    return nDel;
-}
-    
-/**Function*************************************************************
-
-  Synopsis    [Eliminates comments from the input file.]
-
-  Description [As a byproduct, this procedure also counts the number
-  lines and dot-statements in the input file. This also joins non-comment 
-  lines that are joined with a backspace '\']
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Io_ReadFileRemoveComments( char * pBuffer, int * pnDots, int * pnLines )
-{
-    char * pCur;
-    int nDots, nLines;
-    // scan through the buffer and eliminate comments
-    // (in the BLIF file, comments are lines starting with "#")
-    nDots = nLines = 0;
-    for ( pCur = pBuffer; *pCur; pCur++ )
-    {
-        // if this is the beginning of comment
-        // clean it with spaces until the new line statement
-        if ( *pCur == '#' )
-            while ( *pCur != '\n' )
-                *pCur++ = ' ';
-    
-        // count the number of new lines and dots
-        if ( *pCur == '\n' ) {
-        if (*(pCur-1)=='\r') {
-        // DOS(R) file support
-        if (*(pCur-2)!='\\') nLines++;
-        else {
-            // rewind to backslash and overwrite with a space
-            *(pCur-2) = ' ';
-            *(pCur-1) = ' ';
-            *pCur = ' ';
-        }
-        } else {
-        // UNIX(TM) file support
-        if (*(pCur-1)!='\\') nLines++;
-        else {
-            // rewind to backslash and overwrite with a space
-            *(pCur-1) = ' ';
-            *pCur = ' ';
-        }
-        }
-    }
-        else if ( *pCur == '.' )
-            nDots++;
-    }
-    if ( pnDots )
-        *pnDots = nDots; 
-    if ( pnLines )
-        *pnLines = nLines; 
-}
-
-////////////////////////////////////////////////////////////////////////
-///                       END OF FILE                                ///
-////////////////////////////////////////////////////////////////////////
-
-
diff --git a/abc70930/src/map/mio/mioUtils.c b/abc70930/src/map/mio/mioUtils.c
deleted file mode 100644
index bd3d01f7..00000000
--- a/abc70930/src/map/mio/mioUtils.c
+++ /dev/null
@@ -1,531 +0,0 @@
-/**CFile****************************************************************
-
-  FileName    [mioUtils.c]
-
-  PackageName [MVSIS 1.3: Multi-valued logic synthesis system.]
-
-  Synopsis    [File reading/writing for technology mapping.]
-
-  Author      [MVSIS Group]
-  
-  Affiliation [UC Berkeley]
-
-  Date        [Ver. 1.0. Started - September 8, 2003.]
-
-  Revision    [$Id: mioUtils.c,v 1.6 2004/09/03 18:02:20 satrajit Exp $]
-
-***********************************************************************/
-
-#include "mioInt.h"
-
-////////////////////////////////////////////////////////////////////////
-///                        DECLARATIONS                              ///
-////////////////////////////////////////////////////////////////////////
-
-static void Mio_WriteGate( FILE * pFile, Mio_Gate_t * pGate, int fPrintSops );
-static void Mio_WritePin( FILE * pFile, Mio_Pin_t * pPin );
-static int  Mio_DelayCompare( Mio_Gate_t ** ppG1, Mio_Gate_t ** ppG2 );
-static void Mio_DeriveTruthTable_rec( DdNode * bFunc, unsigned uTruthsIn[][2], unsigned uTruthRes[] );
-
-////////////////////////////////////////////////////////////////////////
-///                     FUNCTION DEFINITIONS                         ///
-////////////////////////////////////////////////////////////////////////
-
-/**Function*************************************************************
-
-  Synopsis    []
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Mio_LibraryDelete( Mio_Library_t * pLib )
-{
-    Mio_Gate_t * pGate, * pGate2;
-    if ( pLib == NULL )
-        return;
-    // free the bindings of nodes to gates from this library for all networks
-    Abc_FrameUnmapAllNetworks( Abc_FrameGetGlobalFrame() );
-    // free the library
-    FREE( pLib->pName );
-    Mio_LibraryForEachGateSafe( pLib, pGate, pGate2 )
-        Mio_GateDelete( pGate );
-    Extra_MmFlexStop( pLib->pMmFlex );
-    Vec_StrFree( pLib->vCube );
-    if ( pLib->tName2Gate )
-        st_free_table( pLib->tName2Gate );
-    if ( pLib->dd )
-        Cudd_Quit( pLib->dd );
-    free( pLib );
-}
-
-/**Function*************************************************************
-
-  Synopsis    []
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Mio_GateDelete( Mio_Gate_t * pGate )
-{
-    Mio_Pin_t * pPin, * pPin2;
-    FREE( pGate->pOutName );
-    FREE( pGate->pName );
-    FREE( pGate->pForm );
-    if ( pGate->bFunc )
-        Cudd_RecursiveDeref( pGate->pLib->dd, pGate->bFunc );
-    Mio_GateForEachPinSafe( pGate, pPin, pPin2 )
-        Mio_PinDelete( pPin );    
-    free( pGate );
-}
-
-/**Function*************************************************************
-
-  Synopsis    []
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Mio_PinDelete( Mio_Pin_t * pPin )
-{
-    FREE( pPin->pName );
-    free( pPin );
-}
-
-/**Function*************************************************************
-
-  Synopsis    []
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-Mio_Pin_t * Mio_PinDup( Mio_Pin_t * pPin )
-{
-    Mio_Pin_t * pPinNew;
-
-    pPinNew = ALLOC( Mio_Pin_t, 1 );
-    *pPinNew = *pPin;
-    pPinNew->pName = (pPinNew->pName ? Extra_UtilStrsav(pPinNew->pName) : NULL);
-    pPinNew->pNext = NULL;
-
-    return pPinNew;
-}
-
-
-
-
-/**Function*************************************************************
-
-  Synopsis    []
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Mio_WriteLibrary( FILE * pFile, Mio_Library_t * pLib, int fPrintSops )
-{
-    Mio_Gate_t * pGate;
-
-    fprintf( pFile, "# The genlib library \"%s\".\n", pLib->pName );
-    Mio_LibraryForEachGate( pLib, pGate )
-        Mio_WriteGate( pFile, pGate, fPrintSops );
-}
-
-/**Function*************************************************************
-
-  Synopsis    []
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Mio_WriteGate( FILE * pFile, Mio_Gate_t * pGate, int fPrintSops )
-{
-    Mio_Pin_t * pPin;
-
-    fprintf( pFile, "GATE " );
-    fprintf( pFile, "%12s ",      pGate->pName );
-    fprintf( pFile, "%10.2f   ",  pGate->dArea );
-    fprintf( pFile, "%s=%s;\n",   pGate->pOutName,    pGate->pForm );
-    // print the pins
-    if ( fPrintSops )
-        fprintf( pFile, "%s",       pGate->pSop? pGate->pSop : "unspecified\n" );
-//    Extra_bddPrint( pGate->pLib->dd, pGate->bFunc );
-//    fprintf( pFile, "\n" );
-    Mio_GateForEachPin( pGate, pPin )
-        Mio_WritePin( pFile, pPin );
-}
-
-/**Function*************************************************************
-
-  Synopsis    []
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Mio_WritePin( FILE * pFile, Mio_Pin_t * pPin )
-{
-    char * pPhaseNames[10] = { "UNKNOWN", "INV", "NONINV" };
-    fprintf( pFile, "    PIN " );
-    fprintf( pFile, "%9s ",     pPin->pName );
-    fprintf( pFile, "%10s ",    pPhaseNames[pPin->Phase] );
-    fprintf( pFile, "%6d ",     (int)pPin->dLoadInput );
-    fprintf( pFile, "%6d ",     (int)pPin->dLoadMax );
-    fprintf( pFile, "%6.2f ",   pPin->dDelayBlockRise );
-    fprintf( pFile, "%6.2f ",   pPin->dDelayFanoutRise );
-    fprintf( pFile, "%6.2f ",   pPin->dDelayBlockFall );
-    fprintf( pFile, "%6.2f",    pPin->dDelayFanoutFall );
-    fprintf( pFile, "\n" );
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Collects the set of root gates.]
-
-  Description [Only collects the gates with unique functionality, 
-  which have fewer inputs and shorter delay than the given limits.]
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-Mio_Gate_t ** Mio_CollectRoots( Mio_Library_t * pLib, int nInputs, float tDelay, bool fSkipInv, int * pnGates )
-{
-    Mio_Gate_t * pGate;
-    Mio_Gate_t ** ppGates;
-    /* st_table * tFuncs; */
-    /* st_generator * gen; */
-    DdNode * bFunc;
-    DdManager * dd;
-    int nGates, iGate;
-
-    dd     = Mio_LibraryReadDd( pLib );
-    nGates = Mio_LibraryReadGateNum( pLib );
-
-    /*
-
-    // for each functionality select one gate; skip constants and buffers
-    tFuncs = st_init_table( st_ptrcmp, st_ptrhash );
-    Mio_LibraryForEachGate( pLib, pGate )
-    {
-        bFunc = Mio_GateReadFunc(pGate);
-        if ( pGate->nInputs > nInputs )
-            continue;
-        if ( pGate->dDelayMax > (double)tDelay )
-            continue;
-        if ( bFunc == b0 || bFunc == b1 )
-            continue;
-        if ( bFunc == dd->vars[0] )
-            continue;
-        if ( bFunc == Cudd_Not(dd->vars[0]) && fSkipInv )
-            continue;
-        if ( st_is_member( tFuncs, (char *)bFunc ) )
-            continue;
-        st_insert( tFuncs, (char *)bFunc, (char *)pGate );
-    }
-
-    // collect the gates into the array
-    ppGates = ALLOC( Mio_Gate_t *, nGates );
-    iGate = 0;
-    st_foreach_item( tFuncs, gen, (char **)&bFunc, (char **)&pGate )
-        ppGates[ iGate++ ] = pGate;
-    assert( iGate <= nGates );
-    st_free_table( tFuncs );
-
-    */
-
-    ppGates = ALLOC( Mio_Gate_t *, nGates );
-    iGate = 0;
-    Mio_LibraryForEachGate( pLib, pGate )
-    {
-        bFunc = Mio_GateReadFunc(pGate);
-        if ( pGate->nInputs > nInputs )
-            continue;
-        if ( pGate->dDelayMax > (double)tDelay )
-            continue;
-        if ( bFunc == b0 || bFunc == b1 )
-            continue;
-        if ( bFunc == dd->vars[0] )
-            continue;
-        if ( bFunc == Cudd_Not(dd->vars[0]) && fSkipInv )
-            continue;
-
-        assert( iGate < nGates );
-        ppGates[ iGate++ ] = pGate;
-    }
-
-    if ( iGate > 0 )
-    {
-        // sort the gates by delay
-        qsort( (void *)ppGates, iGate, sizeof(Mio_Gate_t *), 
-                (int (*)(const void *, const void *)) Mio_DelayCompare );
-        assert( Mio_DelayCompare( ppGates, ppGates + iGate - 1 ) <= 0 );
-    }
-
-    if ( pnGates )
-        *pnGates = iGate;
-    return ppGates;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Compares the max delay of two gates.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Mio_DelayCompare( Mio_Gate_t ** ppG1, Mio_Gate_t ** ppG2 )
-{
-    if ( (*ppG1)->dDelayMax < (*ppG2)->dDelayMax )
-        return -1;
-    if ( (*ppG1)->dDelayMax > (*ppG2)->dDelayMax )
-        return 1;
-    return 0;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Derives the truth table of the gate.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Mio_DeriveTruthTable( Mio_Gate_t * pGate, unsigned uTruthsIn[][2], int nSigns, int nInputs, unsigned uTruthRes[] )
-{
-    Mio_DeriveTruthTable_rec( pGate->bFunc, uTruthsIn, uTruthRes );
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Recursively derives the truth table of the gate.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Mio_DeriveTruthTable_rec( DdNode * bFunc, unsigned uTruthsIn[][2], unsigned uTruthRes[] )
-{
-    unsigned uTruthsCof0[2];
-    unsigned uTruthsCof1[2];
-
-    // complement the resulting truth table, if the function is complemented
-    if ( Cudd_IsComplement(bFunc) )
-    {
-        Mio_DeriveTruthTable_rec( Cudd_Not(bFunc), uTruthsIn, uTruthRes );
-        uTruthRes[0] = ~uTruthRes[0];
-        uTruthRes[1] = ~uTruthRes[1];
-        return;
-    }
-
-    // if the function is constant 1, return the constant 1 truth table
-    if ( bFunc->index == CUDD_CONST_INDEX )
-    {
-        uTruthRes[0] = MIO_FULL;
-        uTruthRes[1] = MIO_FULL;
-        return;
-    }
-
-    // solve the problem for both cofactors
-    Mio_DeriveTruthTable_rec( cuddE(bFunc), uTruthsIn, uTruthsCof0 );
-    Mio_DeriveTruthTable_rec( cuddT(bFunc), uTruthsIn, uTruthsCof1 );
-
-    // derive the resulting truth table using the input truth tables
-    uTruthRes[0] = (uTruthsCof0[0] & ~uTruthsIn[bFunc->index][0]) |
-                   (uTruthsCof1[0] &  uTruthsIn[bFunc->index][0]);
-    uTruthRes[1] = (uTruthsCof0[1] & ~uTruthsIn[bFunc->index][1]) |
-                   (uTruthsCof1[1] &  uTruthsIn[bFunc->index][1]);
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Derives the truth table of the root of the gate.]
-
-  Description [Given the truth tables of the leaves of the gate,
-  this procedure derives the truth table of the root.]
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Mio_DeriveTruthTable2( Mio_Gate_t * pGate, unsigned uTruthsIn[][2], int nTruths, int nInputs, unsigned uTruthRes[] )
-{
-    unsigned uSignCube[2];
-    int i, nFanins;
-    char * pCube;
-
-    // make sure that the number of input truth tables in equal to the number of gate inputs
-    assert( pGate->nInputs == nTruths );
-    assert( nInputs < 7 );
-
-    nFanins = Abc_SopGetVarNum( pGate->pSop );
-    assert( nFanins == nInputs );
-
-    // clean the resulting truth table
-    uTruthRes[0] = 0;
-    uTruthRes[1] = 0;
-    if ( nInputs < 6 )
-    {
-//        for ( c = 0; *(pCube = pGate->pSop + c * (nFanins + 3)); c++ )
-        Abc_SopForEachCube( pGate->pSop, nFanins, pCube )
-        {
-            // add the clause
-            uSignCube[0] = MIO_FULL;
-            for ( i = 0; i < nFanins; i++ )
-            {
-                if ( pCube[i] == '0' )
-                    uSignCube[0] &= ~uTruthsIn[i][0];
-                else if ( pCube[i] == '1' )
-                    uSignCube[0] &=  uTruthsIn[i][0];
-            }
-        }
-        if ( nInputs < 5 )
-            uTruthRes[0] &= MIO_MASK(1<<nInputs);
-    }
-    else
-    {
-        // consider the case when two unsigneds should be used
-//        for ( c = 0; *(pCube = pGate->pSop + c * (nFanins + 3)); c++ )
-        Abc_SopForEachCube( pGate->pSop, nFanins, pCube )
-        {
-            uSignCube[0] = MIO_FULL;
-            uSignCube[1] = MIO_FULL;
-            for ( i = 0; i < nFanins; i++ )
-            {
-                if ( pCube[i] == '0' )
-                {
-                    uSignCube[0] &= ~uTruthsIn[i][0];
-                    uSignCube[1] &= ~uTruthsIn[i][1];
-                }
-                else if ( pCube[i] == '1' )
-                {
-                    uSignCube[0] &=  uTruthsIn[i][0];
-                    uSignCube[1] &=  uTruthsIn[i][1];
-                }
-            }
-            uTruthRes[0] |= uSignCube[0];
-            uTruthRes[1] |= uSignCube[1];
-        }
-    }
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Derives the area and delay of the root of the gate.]
-
-  Description [Array of the resulting delays should be initialized 
-  to the (negative) SUPER_NO_VAR value.]
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Mio_DeriveGateDelays( Mio_Gate_t * pGate, 
-    float ** ptPinDelays, int nPins, int nInputs, float tDelayZero, 
-    float * ptDelaysRes, float * ptPinDelayMax )
-{
-    Mio_Pin_t * pPin;
-    float Delay, DelayMax;
-    int i, k;
-    assert( pGate->nInputs == nPins );
-    // set all the delays to the unused delay
-    for ( i = 0; i < nInputs; i++ )
-        ptDelaysRes[i] = tDelayZero;
-    // compute the delays for each input and the max delay at the same time
-    DelayMax = 0;
-    for ( i = 0; i < nInputs; i++ )
-    {
-        for ( k = 0, pPin = pGate->pPins; pPin; pPin = pPin->pNext, k++ )
-        {
-            if ( ptPinDelays[k][i] < 0 )
-                continue;
-            Delay = ptPinDelays[k][i] + (float)pPin->dDelayBlockMax;
-            if ( ptDelaysRes[i] < Delay )
-                ptDelaysRes[i] = Delay;
-        }
-        if ( k != nPins )
-        {
-            printf ("DEBUG: problem gate is %s\n", Mio_GateReadName( pGate ));
-        }
-        assert( k == nPins );
-        if ( DelayMax < ptDelaysRes[i] )
-            DelayMax = ptDelaysRes[i];
-    }
-    *ptPinDelayMax = DelayMax;
-}
-
-
-/**Function*************************************************************
-
-  Synopsis    [Creates a pseudo-gate.]
-
-  Description [The pseudo-gate is a N-input gate with all info set to 0.]
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-Mio_Gate_t * Mio_GateCreatePseudo( int nInputs )
-{
-    Mio_Gate_t * pGate;
-    Mio_Pin_t * pPin;
-    int i;
-    // allocate the gate structure
-    pGate = ALLOC( Mio_Gate_t, 1 );
-    memset( pGate, 0, sizeof(Mio_Gate_t) );
-    pGate->nInputs = nInputs;
-    // create pins
-    for ( i = 0; i < nInputs; i++ )
-    {
-        pPin = ALLOC( Mio_Pin_t, 1 );
-        memset( pPin, 0, sizeof(Mio_Pin_t) );
-        pPin->pNext = pGate->pPins;
-        pGate->pPins = pPin;
-    }
-    return pGate;
-}
-
-////////////////////////////////////////////////////////////////////////
-///                       END OF FILE                                ///
-////////////////////////////////////////////////////////////////////////
-
-
diff --git a/abc70930/src/map/mio/module.make b/abc70930/src/map/mio/module.make
deleted file mode 100644
index 26a4561c..00000000
--- a/abc70930/src/map/mio/module.make
+++ /dev/null
@@ -1,5 +0,0 @@
-SRC +=  src/map/mio/mio.c \
-    src/map/mio/mioApi.c \
-    src/map/mio/mioFunc.c \
-    src/map/mio/mioRead.c \
-    src/map/mio/mioUtils.c
diff --git a/abc70930/src/map/super/module.make b/abc70930/src/map/super/module.make
deleted file mode 100644
index 19ce8228..00000000
--- a/abc70930/src/map/super/module.make
+++ /dev/null
@@ -1,4 +0,0 @@
-SRC +=  src/map/super/super.c \
-    src/map/super/superAnd.c \
-    src/map/super/superGate.c \
-    src/map/super/superWrite.c
diff --git a/abc70930/src/map/super/super.c b/abc70930/src/map/super/super.c
deleted file mode 100644
index 97420c5c..00000000
--- a/abc70930/src/map/super/super.c
+++ /dev/null
@@ -1,319 +0,0 @@
-/**CFile****************************************************************
-
-  FileName    [super.c]
-
-  PackageName [MVSIS 1.3: Multi-valued logic synthesis system.]
-
-  Synopsis    [Pre-computation of supergates.]
-
-  Author      [MVSIS Group]
-  
-  Affiliation [UC Berkeley]
-
-  Date        [Ver. 1.0. Started - August 18, 2003.]
-
-  Revision    [$Id: super.c,v 1.6 2004/10/30 20:51:11 satrajit Exp $]
-
-***********************************************************************/
-
-#include "superInt.h"
-#include "mainInt.h"
-#include "mio.h"
-
-////////////////////////////////////////////////////////////////////////
-///                        DECLARATIONS                              ///
-////////////////////////////////////////////////////////////////////////
-
-static int Super_CommandSupergates   ( Abc_Frame_t * pAbc, int argc, char **argv );
-static int Super_CommandSupergatesAnd( Abc_Frame_t * pAbc, int argc, char **argv );
-
-////////////////////////////////////////////////////////////////////////
-///                     FUNCTION DEFINITIONS                         ///
-////////////////////////////////////////////////////////////////////////
-
-/**Function*************************************************************
-
-  Synopsis    []
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Super_Init( Abc_Frame_t * pAbc )
-{
-    Cmd_CommandAdd( pAbc, "SC mapping",  "super",   Super_CommandSupergates,    0 ); 
-    Cmd_CommandAdd( pAbc, "SC mapping",  "super2",  Super_CommandSupergatesAnd, 0 ); 
-}
-
-/**Function*************************************************************
-
-  Synopsis    []
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Super_End()
-{
-}
-
-
-
-/**Function*************************************************************
-
-  Synopsis    []
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Super_CommandSupergatesAnd( Abc_Frame_t * pAbc, int argc, char **argv )
-{
-    FILE * pOut, * pErr;
-    int nVarsMax, nLevels;
-    int fVerbose;
-    int c;
-
-    pOut = Abc_FrameReadOut(pAbc);
-    pErr = Abc_FrameReadErr(pAbc);
-
-    // set the defaults
-    nVarsMax = 4;
-    nLevels  = 3;
-    fVerbose = 0;
-    Extra_UtilGetoptReset();
-    while ( (c = Extra_UtilGetopt(argc, argv, "ilvh")) != EOF ) 
-    {
-        switch (c) 
-        {
-            case 'i':
-                nVarsMax = atoi(argv[globalUtilOptind]);
-                globalUtilOptind++;
-                if ( nVarsMax < 0 ) 
-                    goto usage;
-                break;
-            case 'l':
-                nLevels = atoi(argv[globalUtilOptind]);
-                globalUtilOptind++;
-                if ( nLevels < 0 ) 
-                    goto usage;
-                break;
-            case 'v':
-                fVerbose ^= 1;
-                break;
-            case 'h':
-                goto usage;
-                break;
-            default:
-                goto usage;
-        }
-    }
-
-    Super2_Precompute( nVarsMax, nLevels, fVerbose );
-
-    return 0;
-
-usage:
-    fprintf( pErr, "usage: super2 [-i num] [-l num] [-vh]\n");
-    fprintf( pErr, "\t         precomputes the supergates composed of AND2s and INVs\n" );  
-    fprintf( pErr, "\t-i num : the max number of inputs to the supergate [default = %d]\n", nVarsMax );
-    fprintf( pErr, "\t-l num : the max number of logic levels of gates [default = %d]\n", nLevels );
-    fprintf( pErr, "\t-v     : enable verbose output\n");
-    fprintf( pErr, "\t-h     : print the help message\n");
-    return 1;       /* error exit */
-}
-
-
-/**Function*************************************************************
-
-  Synopsis    []
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Super_CommandSupergates( Abc_Frame_t * pAbc, int argc, char **argv )
-{
-    FILE * pFile;
-    FILE * pOut, * pErr;
-    Mio_Library_t * pLib;
-    char * FileName, * ExcludeFile;
-    float DelayLimit;
-    float AreaLimit;
-    bool fSkipInvs;
-    bool fWriteOldFormat; 
-    int nVarsMax, nLevels, TimeLimit;
-    int fVerbose;
-    int c;
-
-    pOut = Abc_FrameReadOut(pAbc);
-    pErr = Abc_FrameReadErr(pAbc);
-
-    // set the defaults
-    nVarsMax   = 5;
-    nLevels    = 3;
-    DelayLimit = 3.5;
-    AreaLimit  = 9;
-    TimeLimit  = 10;
-    fSkipInvs  = 1;
-    fVerbose   = 0;
-    fWriteOldFormat = 0;
-    ExcludeFile = 0;
-
-    Extra_UtilGetoptReset();
-    while ( (c = Extra_UtilGetopt(argc, argv, "eiltdasovh")) != EOF ) 
-    {
-        switch (c) 
-        {
-            case 'e':
-                ExcludeFile = argv[globalUtilOptind];
-                if ( ExcludeFile == 0 )
-                    goto usage;
-                globalUtilOptind++;
-                break;
-            case 'i':
-                nVarsMax = atoi(argv[globalUtilOptind]);
-                globalUtilOptind++;
-                if ( nVarsMax < 0 ) 
-                    goto usage;
-                break;
-            case 'l':
-                nLevels = atoi(argv[globalUtilOptind]);
-                globalUtilOptind++;
-                if ( nLevels < 0 ) 
-                    goto usage;
-                break;
-            case 't':
-                TimeLimit = atoi(argv[globalUtilOptind]);
-                globalUtilOptind++;
-                if ( TimeLimit < 0 ) 
-                    goto usage;
-                break;
-            case 'd':
-                DelayLimit = (float)atof(argv[globalUtilOptind]);
-                globalUtilOptind++;
-                if ( DelayLimit <= 0.0 ) 
-                    goto usage;
-                break;
-            case 'a':
-                AreaLimit = (float)atof(argv[globalUtilOptind]);
-                globalUtilOptind++;
-                if ( AreaLimit <= 0.0 ) 
-                    goto usage;
-                break;
-            case 's':
-                fSkipInvs ^= 1;
-                break;
-            case 'o':
-                fWriteOldFormat ^= 1;
-                break;
-            case 'v':
-                fVerbose ^= 1;
-                break;
-            case 'h':
-                goto usage;
-                break;
-            default:
-                goto usage;
-        }
-    }
-
-
-    if ( argc != globalUtilOptind + 1 )
-    {
-        fprintf( pErr, "The GENLIB library file should be given on the command line.\n" );
-        goto usage;
-    }
-
-    if ( nVarsMax < 2 || nVarsMax > 6 )
-    {
-        fprintf( pErr, "The max number of variables (%d) should be more than 1 and less than 7.\n", nVarsMax );
-        goto usage;
-    }
-
-    // get the input file name
-    FileName = argv[globalUtilOptind];
-    if ( (pFile = Io_FileOpen( FileName, "open_path", "r", 0 )) == NULL )
-//    if ( (pFile = fopen( FileName, "r" )) == NULL )
-    {
-        fprintf( pErr, "Cannot open input file \"%s\". ", FileName );
-        if (( FileName = Extra_FileGetSimilarName( FileName, ".genlib", ".lib", ".gen", ".g", NULL ) ))
-            fprintf( pErr, "Did you mean \"%s\"?", FileName );
-        fprintf( pErr, "\n" );
-        return 1;
-    }
-    fclose( pFile );
-
-    // set the new network
-    pLib = Mio_LibraryRead( pAbc, FileName, ExcludeFile, fVerbose );
-    if ( pLib == NULL )
-    {
-        fprintf( pErr, "Reading library has failed.\n" );
-        goto usage;
-    }
-
-    // compute the gates
-    Super_Precompute( pLib, nVarsMax, nLevels, DelayLimit, AreaLimit, TimeLimit, fSkipInvs, fWriteOldFormat, fVerbose );
-
-    // delete the library
-    Mio_LibraryDelete( pLib );
-    return 0;
-
-usage:
-    fprintf( pErr, "usage: super [-i num] [-l num] [-d float] [-a float] [-t num] [-sovh] <genlib_file>\n");
-    fprintf( pErr, "\t         precomputes the supergates for the given GENLIB library\n" );  
-    fprintf( pErr, "\t-i num   : the max number of supergate inputs [default = %d]\n", nVarsMax );
-    fprintf( pErr, "\t-l num   : the max number of levels of gates [default = %d]\n", nLevels );
-    fprintf( pErr, "\t-d float : the max delay of the supergates [default = %.2f]\n", DelayLimit );
-    fprintf( pErr, "\t-a float : the max area of the supergates [default = %.2f]\n", AreaLimit );
-    fprintf( pErr, "\t-t num   : the approximate runtime limit in seconds [default = %d]\n", TimeLimit );
-    fprintf( pErr, "\t-s       : toggle the use of inverters at the inputs [default = %s]\n", (fSkipInvs? "no": "yes") );
-    fprintf( pErr, "\t-o       : toggle dumping the supergate library in old format [default = %s]\n", (fWriteOldFormat? "yes": "no") );
-    fprintf( pErr, "\t-e file  : file contains list of genlib gates to exclude\n" );
-    fprintf( pErr, "\t-v       : enable verbose output [default = %s]\n", (fVerbose? "yes" : "no") );
-    fprintf( pErr, "\t-h       : print the help message\n");
-    fprintf( pErr, "\n");
-    fprintf( pErr, "\tHere is a piece of advice on precomputing supergate libraries:\n");
-    fprintf( pErr, "\t\n");
-    fprintf( pErr, "\tStart with the number of inputs equal to 5 (-i 5), the number of \n");
-    fprintf( pErr, "\tlevels equal to 3 (-l 3), the delay equal to 2-3 delays of inverter, \n");
-    fprintf( pErr, "\tthe area equal to 3-4 areas of two input NAND, and runtime limit equal \n");
-    fprintf( pErr, "\tto 10 seconds (-t 10). Run precomputation and learn from the result.\n");
-    fprintf( pErr, "\tDetermine what parameter is most constraining and try to increase \n");
-    fprintf( pErr, "\tthe value of that parameter. The goal is to have a well-balanced\n");
-    fprintf( pErr, "\tset of constraints and the resulting supergate library containing\n");
-    fprintf( pErr, "\tapproximately 100K-200K supergates. Typically, it is better to increase\n");
-    fprintf( pErr, "\tdelay limit rather than area limit, because having large-area supergates\n");
-    fprintf( pErr, "\tmay result in a considerable increase in area.\n");
-    fprintf( pErr, "\t\n");
-    fprintf( pErr, "\tNote that a good supergate library for experiments typically can be \n");
-    fprintf( pErr, "\tprecomputed in 30 sec. Increasing the runtime limit makes sense when\n");
-    fprintf( pErr, "\tother parameters are well-balanced and it is needed to enumerate more\n");
-    fprintf( pErr, "\tchoices to have a good result. In the end, to compute the final library\n");
-    fprintf( pErr, "\tthe runtime can be set to 300 sec to ensure the ultimate quality.\n");
-    fprintf( pErr, "\tIn some cases, the runtime has to be reduced if the supergate library\n");
-    fprintf( pErr, "\tcontains too many supergates (> 500K).\n");
-    fprintf( pErr, "\t\n");
-    fprintf( pErr, "\tWhen precomputing libraries of 6 inputs (-i 6), start with even more \n");
-    fprintf( pErr, "\trestricted parameters and gradually increase them until the goal is met.\n");
-    fprintf( pErr, "\t\n");
-    return 1;       /* error exit */
-}
-
-////////////////////////////////////////////////////////////////////////
-///                       END OF FILE                                ///
-////////////////////////////////////////////////////////////////////////
-
-
diff --git a/abc70930/src/map/super/super.h b/abc70930/src/map/super/super.h
deleted file mode 100644
index a7169924..00000000
--- a/abc70930/src/map/super/super.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/**CFile****************************************************************
-
-  FileName    [super.h]
-
-  PackageName [MVSIS 2.0: Multi-valued logic synthesis system.]
-
-  Synopsis    [Pre-computation of supergates (delay-limited gate combinations).]
-
-  Author      [MVSIS Group]
-  
-  Affiliation [UC Berkeley]
-
-  Date        [Ver. 1.0. Started - September 8, 2003.]
-
-  Revision    [$Id: super.h,v 1.3 2004/06/28 14:20:25 alanmi Exp $]
-
-***********************************************************************/
-
-#ifndef __SUPER_H__
-#define __SUPER_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-////////////////////////////////////////////////////////////////////////
-///                          INCLUDES                                ///
-////////////////////////////////////////////////////////////////////////
-
-////////////////////////////////////////////////////////////////////////
-///                         PARAMETERS                               ///
-////////////////////////////////////////////////////////////////////////
-
-////////////////////////////////////////////////////////////////////////
-///                    STRUCTURE DEFINITIONS                         ///
-////////////////////////////////////////////////////////////////////////
-
-////////////////////////////////////////////////////////////////////////
-///                       GLOBAL VARIABLES                           ///
-////////////////////////////////////////////////////////////////////////
-
-////////////////////////////////////////////////////////////////////////
-///                       MACRO DEFINITIONS                          ///
-////////////////////////////////////////////////////////////////////////
- 
-////////////////////////////////////////////////////////////////////////
-///                     FUNCTION DEFINITIONS                         ///
-////////////////////////////////////////////////////////////////////////
-
-/*=== superCore.c =============================================================*/
-    
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-////////////////////////////////////////////////////////////////////////
-///                       END OF FILE                                ///
-////////////////////////////////////////////////////////////////////////
diff --git a/abc70930/src/map/super/superAnd.c b/abc70930/src/map/super/superAnd.c
deleted file mode 100644
index 52473fba..00000000
--- a/abc70930/src/map/super/superAnd.c
+++ /dev/null
@@ -1,696 +0,0 @@
-/**CFile****************************************************************
-
-  FileName    [superAnd.c]
-
-  PackageName [MVSIS 1.3: Multi-valued logic synthesis system.]
-
-  Synopsis    [Pre-computation of supergates.]
-
-  Author      [MVSIS Group]
-  
-  Affiliation [UC Berkeley]
-
-  Date        [Ver. 1.0. Started - September 8, 2003.]
-
-  Revision    [$Id: superAnd.c,v 1.3 2004/06/28 14:20:25 alanmi Exp $]
-
-***********************************************************************/
-
-#include "superInt.h"
-
-////////////////////////////////////////////////////////////////////////
-///                        DECLARATIONS                              ///
-////////////////////////////////////////////////////////////////////////
-
-// the bit masks
-#define SUPER_MASK(n)     ((~((unsigned)0)) >> (32-n))
-#define SUPER_FULL         (~((unsigned)0))
-
-// data structure for AND2 subgraph precomputation
-typedef struct Super2_ManStruct_t_     Super2_Man_t;   // manager
-typedef struct Super2_LibStruct_t_     Super2_Lib_t;   // library
-typedef struct Super2_GateStruct_t_    Super2_Gate_t;  // supergate
-
-struct Super2_ManStruct_t_
-{
-    Extra_MmFixed_t *   pMem;         // memory manager for all supergates
-    stmm_table *        tTable;       // mapping of truth tables into gates
-    int                 nTried;       // the total number of tried
-};
-
-struct Super2_LibStruct_t_
-{
-    int                 i;            // used to iterate through the table
-    int                 k;            // used to iterate through the table
-    int                 nInputs;      // the number of inputs
-    int                 nMints;       // the number of minterms
-    int                 nLevels;      // the number of logic levels
-    int                 nGates;       // the number of gates in the library
-    int                 nGatesAlloc;  // the number of allocated places
-    Super2_Gate_t **    pGates;       // the gates themselves
-    unsigned            uMaskBit;     // the mask used to determine the compl bit
-};
-
-struct Super2_GateStruct_t_
-{
-    unsigned            uTruth;       // the truth table of this supergate
-    Super2_Gate_t *     pOne;         // the left wing
-    Super2_Gate_t *     pTwo;         // the right wing
-    Super2_Gate_t *     pNext;        // the next gate in the table
-};
-
-
-// manipulation of complemented attributes
-#define Super2_IsComplement(p)    (((int)((unsigned long) (p) & 01)))
-#define Super2_Regular(p)         ((Super2_Gate_t *)((unsigned long)(p) & ~01)) 
-#define Super2_Not(p)             ((Super2_Gate_t *)((unsigned long)(p) ^ 01)) 
-#define Super2_NotCond(p,c)       ((Super2_Gate_t *)((unsigned long)(p) ^ (c)))
-
-// iterating through the gates in the library
-#define Super2_LibForEachGate( Lib, Gate )                        \
-    for ( Lib->i = 0;                                             \
-          Lib->i < Lib->nGates && (Gate = Lib->pGates[Lib->i]);   \
-          Lib->i++ )
-#define Super2_LibForEachGate2( Lib, Gate2 )                      \
-    for ( Lib->k = 0;                                             \
-          Lib->k < Lib->i && (Gate2 = Lib->pGates[Lib->k]);       \
-          Lib->k++ )
-
-// static functions
-static Super2_Man_t * Super2_ManStart();
-static void           Super2_ManStop( Super2_Man_t * pMan );
-static Super2_Lib_t * Super2_LibStart();
-static Super2_Lib_t * Super2_LibDup( Super2_Lib_t * pLib );
-static void           Super2_LibStop( Super2_Lib_t * pLib );
-static void           Super2_LibAddGate( Super2_Lib_t * pLib, Super2_Gate_t * pGate );
-static Super2_Lib_t * Super2_LibFirst( Super2_Man_t * pMan, int nInputs );
-static Super2_Lib_t * Super2_LibCompute( Super2_Man_t * pMan, Super2_Lib_t * pLib );
-
-static void           Super2_LibWrite( Super2_Lib_t * pLib );
-static void           Super2_LibWriteGate( FILE * pFile, Super2_Lib_t * pLib, Super2_Gate_t * pGate );
-static char *         Super2_LibWriteGate_rec( Super2_Gate_t * pGate, int fInv, int Level );
-static int            Super2_LibWriteCompare( char * pStr1, char * pStr2 );
-static int            Super2_LibCompareGates( Super2_Gate_t ** ppG1, Super2_Gate_t ** ppG2 );
-
-////////////////////////////////////////////////////////////////////////
-///                     FUNCTION DEFINITIONS                         ///
-////////////////////////////////////////////////////////////////////////
-
-/**Function*************************************************************
-
-  Synopsis    [Precomputes the library of AND2 gates.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Super2_Precompute( int nInputs, int nLevels, int fVerbose )
-{
-    Super2_Man_t * pMan;
-    Super2_Lib_t * pLibCur, * pLibNext;
-    int Level;
-    int clk;
-
-    assert( nInputs < 6 );
-
-    // start the manager
-    pMan = Super2_ManStart();
-
-    // get the starting supergates
-    pLibCur = Super2_LibFirst( pMan, nInputs );
-
-    // perform the computation of supergates
-printf( "Computing supergates for %d inputs and %d levels:\n", nInputs, nLevels );
-    for ( Level = 1; Level <= nLevels; Level++ )
-    {
-clk = clock();
-        pLibNext = Super2_LibCompute( pMan, pLibCur );
-        pLibNext->nLevels = Level;
-        Super2_LibStop( pLibCur );
-        pLibCur = pLibNext;
-printf( "Level %d:  Tried = %7d.  Computed = %7d.  ", Level, pMan->nTried, pLibCur->nGates );
-PRT( "Runtime", clock() - clk );
-fflush( stdout );
-    }
-
-printf( "Writing the output file...\n" );
-fflush( stdout );
-    // write them into a file
-    Super2_LibWrite( pLibCur );
-    Super2_LibStop( pLibCur );
-
-    // stop the manager
-    Super2_ManStop( pMan );
-}
-
-
-
-
-/**Function*************************************************************
-
-  Synopsis    [Starts the manager.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-Super2_Man_t * Super2_ManStart()
-{
-    Super2_Man_t * pMan;
-    pMan = ALLOC( Super2_Man_t, 1 );
-    memset( pMan, 0, sizeof(Super2_Man_t) );
-    pMan->pMem   = Extra_MmFixedStart( sizeof(Super2_Gate_t) );
-    pMan->tTable = stmm_init_table( st_ptrcmp, st_ptrhash );
-    return pMan;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Stops the manager.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Super2_ManStop( Super2_Man_t * pMan )
-{
-    Extra_MmFixedStop( pMan->pMem );
-    stmm_free_table( pMan->tTable );
-    free( pMan );
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Starts the library.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-Super2_Lib_t * Super2_LibStart()
-{
-    Super2_Lib_t * pLib;
-    pLib = ALLOC( Super2_Lib_t, 1 );
-    memset( pLib, 0, sizeof(Super2_Lib_t) );
-    return pLib;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Duplicates the library.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-Super2_Lib_t * Super2_LibDup( Super2_Lib_t * pLib )
-{
-    Super2_Lib_t * pLibNew;
-    pLibNew = Super2_LibStart();
-    pLibNew->nInputs     = pLib->nInputs;
-    pLibNew->nMints      = pLib->nMints;
-    pLibNew->nLevels     = pLib->nLevels;
-    pLibNew->nGates      = pLib->nGates;
-    pLibNew->uMaskBit    = pLib->uMaskBit;
-    pLibNew->nGatesAlloc = 1000 + pLib->nGatesAlloc;
-    pLibNew->pGates      = ALLOC( Super2_Gate_t *, pLibNew->nGatesAlloc );
-    memcpy( pLibNew->pGates, pLib->pGates, pLibNew->nGates * sizeof(Super2_Gate_t *) );
-    return pLibNew;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Add gate to the library.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Super2_LibAddGate( Super2_Lib_t * pLib, Super2_Gate_t * pGate )
-{
-    if ( pLib->nGates == pLib->nGatesAlloc )
-    {
-        pLib->pGates  = REALLOC( Super2_Gate_t *, pLib->pGates,  3 * pLib->nGatesAlloc );
-        pLib->nGatesAlloc *= 3;
-    }
-    pLib->pGates[ pLib->nGates++ ] = pGate;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Stops the library.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Super2_LibStop( Super2_Lib_t * pLib )
-{
-    free( pLib->pGates );
-    free( pLib );
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Derives the starting supergates.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-Super2_Lib_t * Super2_LibFirst( Super2_Man_t * pMan, int nInputs )
-{
-    Super2_Lib_t * pLib;
-    int v, m;    
-
-    // start the library
-    pLib = Super2_LibStart();
-
-    // create the starting supergates
-    pLib->nInputs     = nInputs;
-    pLib->nMints      = (1 << nInputs);
-    pLib->nLevels     = 0;
-    pLib->nGates      = nInputs + 1;
-    pLib->nGatesAlloc = nInputs + 1;
-    pLib->uMaskBit    = (1 << (pLib->nMints-1));
-    pLib->pGates      = ALLOC( Super2_Gate_t *, nInputs + 1 );
-    // add the constant 0
-    pLib->pGates[0] = (Super2_Gate_t *)Extra_MmFixedEntryFetch( pMan->pMem );
-    memset( pLib->pGates[0], 0, sizeof(Super2_Gate_t) );
-    // add the elementary gates
-    for ( v = 0; v < nInputs; v++ )
-    {
-        pLib->pGates[v+1] = (Super2_Gate_t *)Extra_MmFixedEntryFetch( pMan->pMem );
-        memset( pLib->pGates[v+1], 0, sizeof(Super2_Gate_t) );
-        pLib->pGates[v+1]->pTwo = (Super2_Gate_t *)v;
-    }
-
-    // set up their truth tables
-    for ( m = 0; m < pLib->nMints; m++ )
-        for ( v = 0; v < nInputs; v++ )
-            if ( m & (1 << v) )
-                pLib->pGates[v+1]->uTruth |= (1 << m);
-    return pLib;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Precomputes one level of supergates.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-Super2_Lib_t * Super2_LibCompute( Super2_Man_t * pMan, Super2_Lib_t * pLib )
-{
-    Super2_Lib_t * pLibNew;
-    Super2_Gate_t * pGate1, * pGate2, * pGateNew;
-    Super2_Gate_t ** ppGate;
-    unsigned Mask = SUPER_MASK(pLib->nMints);
-    unsigned uTruth, uTruthR, uTruth1, uTruth2, uTruth1c, uTruth2c;
-
-    // start the new library
-    pLibNew = Super2_LibDup( pLib );
-
-    // reset the hash table
-    stmm_free_table( pMan->tTable );
-    pMan->tTable = stmm_init_table( st_ptrcmp, st_ptrhash );
-    // set the starting things into the hash table
-    Super2_LibForEachGate( pLibNew, pGate1 )
-    {
-        uTruthR = ((pGate1->uTruth & pLibNew->uMaskBit)? Mask & ~pGate1->uTruth : pGate1->uTruth);
-
-        if ( stmm_lookup( pMan->tTable, (char *)uTruthR, (char **)&pGate2 ) )
-        {
-            printf( "New gate:\n" );
-            Super2_LibWriteGate( stdout, pLibNew, pGate1 );
-            printf( "Gate in the table:\n" );
-            Super2_LibWriteGate( stdout, pLibNew, pGate2 );
-            assert( 0 );
-        }
-        stmm_insert( pMan->tTable, (char *)uTruthR, (char *)pGate1 );
-    }
-
-
-    // set the number of gates tried
-    pMan->nTried = pLibNew->nGates;
-
-    // go through the gate pairs
-    Super2_LibForEachGate( pLib, pGate1 )
-    {
-        if ( pLib->i && pLib->i % 300 == 0 )
-        {
-            printf( "Tried %5d first gates...\n", pLib->i );
-            fflush( stdout );
-        }
-
-        Super2_LibForEachGate2( pLib, pGate2 )
-        {
-            uTruth1  = pGate1->uTruth;
-            uTruth2  = pGate2->uTruth;
-            uTruth1c = Mask & ~uTruth1;
-            uTruth2c = Mask & ~uTruth2;
-
-            // none complemented
-            uTruth  = uTruth1  & uTruth2;
-            uTruthR = ((uTruth & pLibNew->uMaskBit)? Mask & ~uTruth : uTruth);
-
-            if ( !stmm_find_or_add( pMan->tTable, (char *)uTruthR, (char ***)&ppGate ) )
-            {
-                pGateNew = (Super2_Gate_t *)Extra_MmFixedEntryFetch( pMan->pMem );
-                pGateNew->pOne  = pGate1;
-                pGateNew->pTwo  = pGate2;
-                pGateNew->uTruth = uTruth;
-                *ppGate = pGateNew;
-                Super2_LibAddGate( pLibNew, pGateNew );
-            }                
-
-            // one complemented
-            uTruth  = uTruth1c & uTruth2;
-            uTruthR = ((uTruth & pLibNew->uMaskBit)? Mask & ~uTruth : uTruth);
-
-            if ( !stmm_find_or_add( pMan->tTable, (char *)uTruthR, (char ***)&ppGate ) )
-            {
-                pGateNew = (Super2_Gate_t *)Extra_MmFixedEntryFetch( pMan->pMem );
-                pGateNew->pOne  = Super2_Not(pGate1);
-                pGateNew->pTwo  = pGate2;
-                pGateNew->uTruth = uTruth;
-                *ppGate = pGateNew;
-                Super2_LibAddGate( pLibNew, pGateNew );
-            }                
-
-            // another complemented
-            uTruth  = uTruth1  & uTruth2c;
-            uTruthR = ((uTruth & pLibNew->uMaskBit)? Mask & ~uTruth : uTruth);
-
-            if ( !stmm_find_or_add( pMan->tTable, (char *)uTruthR, (char ***)&ppGate ) )
-            {
-                pGateNew = (Super2_Gate_t *)Extra_MmFixedEntryFetch( pMan->pMem );
-                pGateNew->pOne  = pGate1;
-                pGateNew->pTwo  = Super2_Not(pGate2);
-                pGateNew->uTruth = uTruth;
-                *ppGate = pGateNew;
-                Super2_LibAddGate( pLibNew, pGateNew );
-            }                
-
-            // both complemented
-            uTruth  = uTruth1c & uTruth2c;
-            uTruthR = ((uTruth & pLibNew->uMaskBit)? Mask & ~uTruth : uTruth);
-
-            if ( !stmm_find_or_add( pMan->tTable, (char *)uTruthR, (char ***)&ppGate ) )
-            {
-                pGateNew = (Super2_Gate_t *)Extra_MmFixedEntryFetch( pMan->pMem );
-                pGateNew->pOne  = Super2_Not(pGate1);
-                pGateNew->pTwo  = Super2_Not(pGate2);
-                pGateNew->uTruth = uTruth;
-                *ppGate = pGateNew;
-                Super2_LibAddGate( pLibNew, pGateNew );
-            }                
-
-            pMan->nTried += 4;
-        }
-    }
-    return pLibNew;
-}
-
-
-static unsigned s_uMaskBit;
-static unsigned s_uMaskAll;
-
-/**Function*************************************************************
-
-  Synopsis    [Writes the library into the file.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Super2_LibWrite( Super2_Lib_t * pLib )
-{
-    Super2_Gate_t * pGate;
-    FILE * pFile;
-    char FileName[100];
-    int clk;
-
-    if ( pLib->nLevels > 5 )
-    {
-        printf( "Cannot write file for %d levels.\n", pLib->nLevels );
-        return;
-    }
-
-clk = clock();
-    // sort the supergates by truth table
-    s_uMaskBit = pLib->uMaskBit;
-    s_uMaskAll = SUPER_MASK(pLib->nMints);
-    qsort( (void *)pLib->pGates, pLib->nGates, sizeof(Super2_Gate_t *), 
-            (int (*)(const void *, const void *)) Super2_LibCompareGates );
-    assert( Super2_LibCompareGates( pLib->pGates, pLib->pGates + pLib->nGates - 1 ) < 0 );
-PRT( "Sorting", clock() - clk );
-
-
-    // start the file
-    sprintf( FileName, "superI%dL%d", pLib->nInputs, pLib->nLevels );
-    pFile = fopen( FileName, "w" );
-    fprintf( pFile, "# AND2/INV supergates derived on %s.\n", Extra_TimeStamp() );
-    fprintf( pFile, "# Command line: \"super2 -i %d -l %d\".\n", pLib->nInputs, pLib->nLevels );
-    fprintf( pFile, "# The number of inputs     = %6d.\n", pLib->nInputs );
-    fprintf( pFile, "# The number of levels     = %6d.\n", pLib->nLevels );
-    fprintf( pFile, "# The number of supergates = %6d.\n", pLib->nGates  );
-    fprintf( pFile, "# The total functions      = %6d.\n", (1<<(pLib->nMints-1)) );
-    fprintf( pFile, "\n" );
-    fprintf( pFile, "%6d\n", pLib->nGates );
-
-    // print the gates
-    Super2_LibForEachGate( pLib, pGate )
-        Super2_LibWriteGate( pFile, pLib, pGate );
-    fclose( pFile );
-
-    printf( "The supergates are written into file \"%s\" ", FileName );
-    printf( "(%0.2f Mb).\n", ((double)Extra_FileSize(FileName))/(1<<20) );
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Writes the gate into the file.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Super2_LibCompareGates( Super2_Gate_t ** ppG1, Super2_Gate_t ** ppG2 )
-{
-    Super2_Gate_t * pG1  = *ppG1;
-    Super2_Gate_t * pG2  = *ppG2;
-    unsigned uTruth1, uTruth2;
-
-    uTruth1 = (pG1->uTruth & s_uMaskBit)? s_uMaskAll & ~pG1->uTruth : pG1->uTruth;
-    uTruth2 = (pG2->uTruth & s_uMaskBit)? s_uMaskAll & ~pG2->uTruth : pG2->uTruth;
-
-    if ( uTruth1 < uTruth2 )
-        return -1;
-    return 1;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Writes the gate into the file.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Super2_LibWriteGate( FILE * pFile, Super2_Lib_t * pLib, Super2_Gate_t * pGate )
-{
-//    unsigned uTruthR;
-    unsigned uTruth;
-    int fInv;
-
-    // check whether the gate need complementation
-    fInv = (int)(pGate->uTruth & pLib->uMaskBit);
-    uTruth = (fInv? ~pGate->uTruth : pGate->uTruth);
-/*
-    // reverse the truth table
-    uTruthR = 0;
-    for ( m = 0; m < pLib->nMints; m++ )
-        if ( uTruth & (1 << m) )
-            uTruthR |= (1 << (pLib->nMints-1-m));
-*/
-    // write the truth table
-    Extra_PrintBinary( pFile, &uTruth, pLib->nMints );
-    fprintf( pFile, "   " );
-    // write the symbolic expression
-    fprintf( pFile, "%s", Super2_LibWriteGate_rec( pGate, fInv, pLib->nLevels ) );
-    fprintf( pFile, "\n" );
-}
-
-
-/**Function*************************************************************
-
-  Synopsis    [Recursively writes the gate into the file.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-char * Super2_LibWriteGate_rec( Super2_Gate_t * pGate, int fInv, int Level )
-{
-    static char Buff01[  3], Buff02[  3];    // Max0              =  1
-    static char Buff11[  6], Buff12[  6];    // Max1 = 2*Max0 + 2 =  4
-    static char Buff21[ 12], Buff22[ 12];    // Max2 = 2*Max1 + 2 = 10
-    static char Buff31[ 25], Buff32[ 25];    // Max3 = 2*Max2 + 2 = 22
-    static char Buff41[ 50], Buff42[ 50];    // Max4 = 2*Max3 + 2 = 46
-    static char Buff51[100], Buff52[100];    // Max5 = 2*Max4 + 2 = 94
-    static char * pBuffs1[6] = { Buff01, Buff11, Buff21, Buff31, Buff41, Buff51 };
-    static char * pBuffs2[6] = { Buff02, Buff12, Buff22, Buff32, Buff42, Buff52 };
-    char * pBranch;
-    char * pBuffer1 = pBuffs1[Level];
-    char * pBuffer2 = pBuffs2[Level];
-    Super2_Gate_t * pGateNext1, * pGateNext2;
-    int fInvNext1, fInvNext2;
-    int RetValue;
-
-    // consider the last level
-    assert( Level >= 0 );
-    if ( pGate->pOne == NULL )
-    {
-        if ( pGate->uTruth == 0 )
-        {
-            pBuffer1[0] = (fInv? '1': '0');
-            pBuffer1[1] = '$';
-            pBuffer1[2] = 0;
-        }
-        else
-        {
-            pBuffer1[0] = (fInv? 'A' + ((int)pGate->pTwo): 'a' + ((int)pGate->pTwo));
-            pBuffer1[1] = 0;
-        }
-        return pBuffer1;
-    }
-    assert( Level > 0 );
-
-
-    // get the left branch
-    pGateNext1 = Super2_Regular(pGate->pOne);
-    fInvNext1  = Super2_IsComplement(pGate->pOne);
-    pBranch    = Super2_LibWriteGate_rec(pGateNext1, fInvNext1, Level - 1);
-    // copy into Buffer1
-    strcpy( pBuffer1, pBranch );
-
-    // get the right branch
-    pGateNext2 = Super2_Regular(pGate->pTwo);
-    fInvNext2  = Super2_IsComplement(pGate->pTwo);
-    pBranch    = Super2_LibWriteGate_rec(pGateNext2, fInvNext2, Level - 1);
-
-    // consider the case when comparison is not necessary
-    if ( fInvNext1 ^ fInvNext2 )
-    {
-        if ( fInvNext1 > fInvNext2 )
-            sprintf( pBuffer2, "%c%s%s%c", (fInv? '<': '('), pBuffer1, pBranch, (fInv? '>': ')') );
-        else
-            sprintf( pBuffer2, "%c%s%s%c", (fInv? '<': '('), pBranch, pBuffer1, (fInv? '>': ')') );
-    }
-    else
-    {
-        // compare the two branches
-        RetValue = Super2_LibWriteCompare( pBuffer1, pBranch );
-        if ( RetValue == 1 )
-            sprintf( pBuffer2, "%c%s%s%c", (fInv? '<': '('), pBuffer1, pBranch, (fInv? '>': ')') );
-        else // if ( RetValue == -1 )
-        {
-            sprintf( pBuffer2, "%c%s%s%c", (fInv? '<': '('), pBranch, pBuffer1, (fInv? '>': ')') );
-            if ( RetValue == 0 )
-                printf( "Strange!\n" );
-        }
-    }
-    return pBuffer2;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Compares the two branches of the tree.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Super2_LibWriteCompare( char * pStr1, char * pStr2 )
-{
-    while ( 1 )
-    {
-        // skip extra symbols
-        while ( *pStr1 && *pStr1 < 'A' )
-            pStr1++;
-        while ( *pStr2 && *pStr2 < 'A' )
-            pStr2++;
-
-        // check if any one is finished
-        if ( *pStr1 == 0 || *pStr2 == 0 )
-        {
-            if ( *pStr2 )
-                return 1;
-            return -1;
-        }
-
-        // compare
-        if ( *pStr1 == *pStr2 )
-        {
-            pStr1++;
-            pStr2++;
-        }
-        else
-        {
-            if ( *pStr1 < *pStr2 )
-                return 1;
-            return -1;
-        }
-    }
-    return 0;
-}
-
-////////////////////////////////////////////////////////////////////////
-///                       END OF FILE                                ///
-////////////////////////////////////////////////////////////////////////
-
-
diff --git a/abc70930/src/map/super/superGENERIC.c b/abc70930/src/map/super/superGENERIC.c
deleted file mode 100644
index 1f2b7651..00000000
--- a/abc70930/src/map/super/superGENERIC.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/**CFile****************************************************************
-
-  FileName    [super__.c]
-
-  PackageName [MVSIS 1.3: Multi-valued logic synthesis system.]
-
-  Synopsis    [Pre-computation of supergates.]
-
-  Author      [MVSIS Group]
-  
-  Affiliation [UC Berkeley]
-
-  Date        [Ver. 1.0. Started - September 8, 2003.]
-
-  Revision    [$Id: super__.h,v 1.0 2003/09/08 00:00:00 alanmi Exp $]
-
-***********************************************************************/
-
-#include "superInt.h"
-
-////////////////////////////////////////////////////////////////////////
-///                        DECLARATIONS                              ///
-////////////////////////////////////////////////////////////////////////
-
-////////////////////////////////////////////////////////////////////////
-///                     FUNCTION DEFINITIONS                         ///
-////////////////////////////////////////////////////////////////////////
-
-/**Function*************************************************************
-
-  Synopsis    []
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-
-
-////////////////////////////////////////////////////////////////////////
-///                       END OF FILE                                ///
-////////////////////////////////////////////////////////////////////////
-
-
diff --git a/abc70930/src/map/super/superGate.c b/abc70930/src/map/super/superGate.c
deleted file mode 100644
index 91a1e513..00000000
--- a/abc70930/src/map/super/superGate.c
+++ /dev/null
@@ -1,1324 +0,0 @@
-/**CFile****************************************************************
-
-  FileName    [superGate.c]
-
-  PackageName [MVSIS 1.3: Multi-valued logic synthesis system.]
-
-  Synopsis    [Pre-computation of supergates.]
-
-  Author      [MVSIS Group]
-  
-  Affiliation [UC Berkeley]
-
-  Date        [Ver. 1.0. Started - September 8, 2003.]
-
-  Revision    [$Id: superGate.c,v 1.7 2004/08/03 00:11:40 satrajit Exp $]
-
-***********************************************************************/
-
-#include "superInt.h"
-
-////////////////////////////////////////////////////////////////////////
-///                        DECLARATIONS                              ///
-////////////////////////////////////////////////////////////////////////
-
-// the bit masks
-#define SUPER_MASK(n)     ((~((unsigned)0)) >> (32-(n)))
-#define SUPER_FULL         (~((unsigned)0))
-#define SUPER_NO_VAR         (-9999.0)
-#define SUPER_EPSILON        (0.001)
-
-// data structure for supergate precomputation
-typedef struct Super_ManStruct_t_     Super_Man_t;   // manager
-typedef struct Super_GateStruct_t_    Super_Gate_t;  // supergate
-
-struct Super_ManStruct_t_
-{
-    // parameters
-    char *              pName;        // the original genlib file name
-    int                 nVarsMax;     // the number of inputs
-    int                 nMints;       // the number of minterms
-    int                 nLevels;      // the number of logic levels
-    float               tDelayMax;    // the max delay of the supergates in the library
-    float               tAreaMax;     // the max area of the supergates in the library
-    int                 fSkipInv;     // the flag says about skipping inverters
-    int                 fWriteOldFormat; // in addition, writes the file in the old format
-    int                 fVerbose;
-
-    // supergates
-    Super_Gate_t *      pInputs[10];  // the input supergates
-    int                 nGates;       // the number of gates in the library
-    Super_Gate_t **     pGates;       // the gates themselves
-    stmm_table *        tTable;       // mapping of truth tables into gates
-
-    // memory managers
-    Extra_MmFixed_t *   pMem;         // memory manager for the supergates
-    Extra_MmFlex_t *    pMemFlex;     // memory manager for the fanin arrays
-
-    // statistics
-    int                 nTried;       // the total number of tried
-    int                 nAdded;       // the number of entries added
-    int                 nRemoved;     // the number of entries removed
-    int                 nUnique;      // the number of unique gates
-    int                 nLookups;     // the number of hash table lookups
-    int                 nAliases;     // the number of hash table lookups thrown away due to aliasing
-
-    // runtime
-    int                 Time;         // the runtime of the generation procedure
-    int                 TimeLimit;    // the runtime limit (in seconds)
-    int                 TimeSec;      // the time passed (in seconds)
-    int                 TimeStop;     // the time to stop computation (in miliseconds)
-    int                 TimePrint;    // the time to print message
-};
-
-struct Super_GateStruct_t_
-{
-    Mio_Gate_t *        pRoot;        // the root gate for this supergate
-    unsigned            fVar :     1; // the flag signaling the elementary variable
-    unsigned            fSuper :   1; // the flag signaling the elementary variable
-    unsigned            nFanins :  6; // the number of fanin gates
-    unsigned            Number :  24; // the number assigned in the process
-    unsigned            uTruth[2];    // the truth table of this supergate
-    Super_Gate_t *      pFanins[6];   // the fanins of the gate
-    float               Area;         // the area of this gate
-    float               ptDelays[6];  // the pin-to-pin delays for all inputs
-    float               tDelayMax;    // the maximum delay
-    Super_Gate_t *      pNext;        // the next gate in the table
-};
-
-
-// iterating through the gates in the library
-#define Super_ManForEachGate( GateArray, Limit, Index, Gate )    \
-    for ( Index = 0;                                             \
-          Index < Limit && (Gate = GateArray[Index]);            \
-          Index++ )
-
-// static functions
-static Super_Man_t *  Super_ManStart();
-static void           Super_ManStop( Super_Man_t * pMan );
-
-static void           Super_AddGateToTable( Super_Man_t * pMan, Super_Gate_t * pGate );
-static void           Super_First( Super_Man_t * pMan, int nVarsMax );
-static Super_Man_t *  Super_Compute( Super_Man_t * pMan, Mio_Gate_t ** ppGates, int nGates, bool fSkipInv );
-static Super_Gate_t * Super_CreateGateNew( Super_Man_t * pMan, Mio_Gate_t * pRoot, Super_Gate_t ** pSupers, int nSupers, unsigned uTruth[], float Area, float tPinDelaysRes[], float tDelayMax, int nPins );
-static bool           Super_CompareGates( Super_Man_t * pMan, unsigned uTruth[], float Area, float tPinDelaysRes[], int nPins );
-static int            Super_DelayCompare( Super_Gate_t ** ppG1, Super_Gate_t ** ppG2 );
-static int            Super_AreaCompare( Super_Gate_t ** ppG1, Super_Gate_t ** ppG2 );
-static void           Super_TranferGatesToArray( Super_Man_t * pMan );
-static int            Super_CheckTimeout( ProgressBar * pPro, Super_Man_t * pMan );
- 
-static void           Super_Write( Super_Man_t * pMan );
-static int            Super_WriteCompare( Super_Gate_t ** ppG1, Super_Gate_t ** ppG2 );
-static void           Super_WriteFileHeader( Super_Man_t * pMan, FILE * pFile );
-
-static void           Super_WriteLibrary( Super_Man_t * pMan );
-static void           Super_WriteLibraryGate( FILE * pFile, Super_Man_t * pMan, Super_Gate_t * pGate, int Num );
-static char *         Super_WriteLibraryGateName( Super_Gate_t * pGate );
-static void           Super_WriteLibraryGateName_rec( Super_Gate_t * pGate, char * pBuffer );
-
-static void           Super_WriteLibraryTree( Super_Man_t * pMan );
-static void           Super_WriteLibraryTree_rec( FILE * pFile, Super_Man_t * pMan, Super_Gate_t * pSuper, int * pCounter );
-
-////////////////////////////////////////////////////////////////////////
-///                     FUNCTION DEFINITIONS                         ///
-////////////////////////////////////////////////////////////////////////
-
-/**Function*************************************************************
-
-  Synopsis    [Precomputes the library of supergates.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Super_Precompute( Mio_Library_t * pLibGen, int nVarsMax, int nLevels, float tDelayMax, float tAreaMax, int TimeLimit, bool fSkipInv, bool fWriteOldFormat, int fVerbose )
-{
-    Super_Man_t * pMan;
-    Mio_Gate_t ** ppGates;
-    int nGates, Level, clk, clockStart;
-
-    assert( nVarsMax < 7 );
-
-    // get the root gates
-    ppGates = Mio_CollectRoots( pLibGen, nVarsMax, tDelayMax, 0, &nGates );
-
-    // start the manager
-    pMan = Super_ManStart();
-    pMan->pName     = Mio_LibraryReadName(pLibGen);
-    pMan->fSkipInv  = fSkipInv;
-    pMan->tDelayMax = tDelayMax;
-    pMan->tAreaMax  = tAreaMax;
-    pMan->TimeLimit = TimeLimit; // in seconds
-    pMan->TimeStop  = TimeLimit * CLOCKS_PER_SEC + clock(); // in CPU ticks
-    pMan->fWriteOldFormat = fWriteOldFormat;
-    pMan->fVerbose = fVerbose;
-
-    if ( nGates == 0 )
-    {
-        fprintf( stderr, "Error: No genlib gates satisfy the limits criteria. Stop.\n");
-        fprintf( stderr, "Limits: max delay =  %.2f, max area =  %.2f, time limit = %d sec.\n", 
-            pMan->tDelayMax, pMan->tAreaMax, pMan->TimeLimit );
-
-        // stop the manager
-        Super_ManStop( pMan );
-        free( ppGates );
-
-        return;
-    }
-
-    // get the starting supergates
-    Super_First( pMan, nVarsMax );
-
-    // perform the computation of supergates
-    clockStart = clock();
-if ( fVerbose )
-{
-    printf( "Computing supergates with %d inputs and %d levels.\n", 
-        pMan->nVarsMax, nLevels );
-    printf( "Limits: max delay =  %.2f, max area =  %.2f, time limit = %d sec.\n", 
-        pMan->tDelayMax, pMan->tAreaMax, pMan->TimeLimit );
-}
-
-    for ( Level = 1; Level <= nLevels; Level++ )
-    {
-        if ( clock() > pMan->TimeStop )
-            break;
-clk = clock();
-        Super_Compute( pMan, ppGates, nGates, fSkipInv );
-        pMan->nLevels = Level;
-if ( fVerbose )
-{
-        printf( "Lev %d: Try =%12d. Add =%6d. Rem =%5d. Save =%6d. Lookups =%12d. Aliases =%12d. ",
-           Level, pMan->nTried, pMan->nAdded, pMan->nRemoved, pMan->nAdded - pMan->nRemoved, pMan->nLookups, pMan->nAliases );
-PRT( "Time", clock() - clk );
-fflush( stdout );
-}
-    }
-    pMan->Time = clock() - clockStart;
-
-if ( fVerbose )
-{
-printf( "Writing the output file...\n" );
-fflush( stdout );
-}
-    // write them into a file
-    Super_Write( pMan );
-
-    // stop the manager
-    Super_ManStop( pMan );
-    free( ppGates );
-}
-
-
-/**Function*************************************************************
-
-  Synopsis    [Derives the starting supergates.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Super_First( Super_Man_t * pMan, int nVarsMax )
-{
-    Super_Gate_t * pSuper;
-    int nMintLimit, nVarLimit;
-    int v, m;
-    // set the parameters
-    pMan->nVarsMax  = nVarsMax;
-    pMan->nMints    = (1 << nVarsMax);
-    pMan->nLevels   = 0;
-    // allocate room for the gates
-    pMan->nGates    = nVarsMax;  
-    pMan->pGates    = ALLOC( Super_Gate_t *, nVarsMax + 2 ); 
-    // create the gates corresponding to the elementary variables
-    for ( v = 0; v < nVarsMax; v++ )
-    {
-        // get a new gate
-        pSuper = (Super_Gate_t *)Extra_MmFixedEntryFetch( pMan->pMem );
-        memset( pSuper, 0, sizeof(Super_Gate_t) );
-        // assign the elementary variable, the truth table, and the delays
-        pSuper->fVar = 1;
-        pSuper->Number = v;
-        for ( m = 0; m < nVarsMax; m++ )
-            pSuper->ptDelays[m] = SUPER_NO_VAR;
-        pSuper->ptDelays[v] = 0.0;
-        // set the gate
-        pMan->pGates[v] = pSuper;
-        Super_AddGateToTable( pMan, pSuper );
-        pMan->pInputs[v] = pSuper;
-    }
-    // set up their truth tables
-    nVarLimit  = (nVarsMax >= 5)? 5 : nVarsMax;
-    nMintLimit = (1 << nVarLimit);
-    for ( m = 0; m < nMintLimit; m++ )
-        for ( v = 0; v < nVarLimit; v++ )
-            if ( m & (1 << v) )
-                pMan->pGates[v]->uTruth[0] |= (1 << m);
-    // make adjustments for the case of 6 variables
-    if ( nVarsMax == 6 )
-    {
-        for ( v = 0; v < 5; v++ )
-            pMan->pGates[v]->uTruth[1] = pMan->pGates[v]->uTruth[0];
-        pMan->pGates[5]->uTruth[0] = 0;
-        pMan->pGates[5]->uTruth[1] = ~((unsigned)0);
-    }
-    else
-    {
-        for ( v = 0; v < nVarsMax; v++ )
-            pMan->pGates[v]->uTruth[1] = 0;
-    }
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Precomputes one level of supergates.]
-
-  Description [This procedure computes the set of supergates that can be
-  derived from the given set of root gates (from GENLIB library) by composing
-  the root gates with the currently available supergates. This procedure is
-  smart in the sense that it tries to avoid useless emuration by imposing
-  tight bounds by area and delay. Only the supergates and are guaranteed to 
-  have smaller area and delay are enumereated. See comments below for details.]
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-Super_Man_t * Super_Compute( Super_Man_t * pMan, Mio_Gate_t ** ppGates, int nGates, bool fSkipInv )
-{
-    Super_Gate_t * pSupers[6], * pGate0, * pGate1, * pGate2, * pGate3, * pGate4, * pGate5, * pGateNew;
-    float tPinDelaysRes[6], * ptPinDelays[6], tPinDelayMax, tDelayMio;
-    float Area, Area0, Area1, Area2, Area3, Area4, AreaMio;
-    unsigned uTruth[2], uTruths[6][2];
-    int i0, i1, i2, i3, i4, i5; 
-    Super_Gate_t ** ppGatesLimit;
-    int nFanins, nGatesLimit, k, s, t;
-    ProgressBar * pProgress;
-    int fTimeOut;
-    int fPrune = 1;                     // Shall we prune?
-    int iPruneLimit = 3;                // Each of the gates plugged into the root gate will have 
-                                        // less than these many fanins
-    int iPruneLimitRoot = 4;            // The root gate may have only less than these many fanins
-
-    // put the gates from the unique table into the array
-    // the gates from the array will be used to compose other gates
-    // the gates in tbe table are used to check uniqueness of collected gates
-    Super_TranferGatesToArray( pMan );
-
-    // sort the gates in the increasing order of maximum delay
-    if ( pMan->nGates > 10000 )
-    {
-        printf( "Sorting array of %d supergates...\r", pMan->nGates );
-        fflush( stdout );
-    }
-    qsort( (void *)pMan->pGates, pMan->nGates, sizeof(Super_Gate_t *), 
-            (int (*)(const void *, const void *)) Super_DelayCompare );
-    assert( Super_DelayCompare( pMan->pGates, pMan->pGates + pMan->nGates - 1 ) <= 0 );
-    if ( pMan->nGates > 10000 )
-    {
-        printf( "                                       \r" );
-    }
-
-    pProgress = Extra_ProgressBarStart( stdout, pMan->TimeLimit );
-    pMan->TimePrint = clock() + CLOCKS_PER_SEC;
-    ppGatesLimit = ALLOC( Super_Gate_t *, pMan->nGates );
-    // go through the root gates
-    // the root gates are sorted in the increasing gelay
-    fTimeOut = 0;
-    for ( k = 0; k < nGates; k++ )
-    {
-        if ( fTimeOut ) break;
-
-        if ( fPrune )
-        {
-            if ( pMan->nLevels >= 1 )  // First level gates have been computed
-            {
-                if ( Mio_GateReadInputs(ppGates[k]) >= iPruneLimitRoot )
-                    continue;
-            }
-        }
-
-        // select the subset of gates to be considered with this root gate
-        // all the gates past this point will lead to delay larger than the limit
-        tDelayMio = (float)Mio_GateReadDelayMax(ppGates[k]);
-        for ( s = 0, t = 0; s < pMan->nGates; s++ )
-        {
-            if ( fPrune && ( pMan->nLevels >= 1 ) && ( ((int)pMan->pGates[s]->nFanins) >= iPruneLimit ))
-                continue;
-            
-            ppGatesLimit[t] = pMan->pGates[s];
-            if ( ppGatesLimit[t++]->tDelayMax + tDelayMio > pMan->tDelayMax )
-                break;
-        }
-        nGatesLimit = t;
-
-        if ( pMan->fVerbose )
-        {
-            printf ("Trying %d choices for %d inputs\n", t, Mio_GateReadInputs(ppGates[k]) );
-        }
-
-        // resort part of this range by area
-        // now we can prune the search by going up in the list until we reach the limit on area
-        // all the gates beyond this point can be skipped because their area can be only larger
-        if ( nGatesLimit > 10000 )
-            printf( "Sorting array of %d supergates...\r", nGatesLimit );
-        qsort( (void *)ppGatesLimit, nGatesLimit, sizeof(Super_Gate_t *), 
-                (int (*)(const void *, const void *)) Super_AreaCompare );
-        assert( Super_AreaCompare( ppGatesLimit, ppGatesLimit + nGatesLimit - 1 ) <= 0 );
-        if ( nGatesLimit > 10000 )
-            printf( "                                       \r" );
-
-        // consider the combinations of gates with the root gate on top
-        AreaMio = (float)Mio_GateReadArea(ppGates[k]);
-        nFanins = Mio_GateReadInputs(ppGates[k]);
-        switch ( nFanins )
-        {
-        case 0: // should not happen
-            assert( 0 ); 
-            break;
-        case 1: // interter root
-            Super_ManForEachGate( ppGatesLimit, nGatesLimit, i0, pGate0 )
-            {
-              if ( fTimeOut ) break;
-              fTimeOut = Super_CheckTimeout( pProgress, pMan );
-              // skip the inverter as the root gate before the elementary variable
-              // as a result, the supergates will not have inverters on the input side
-              // but inverters still may occur at the output of or inside complex supergates
-              if ( fSkipInv && pGate0->tDelayMax == 0 )
-                  continue;
-              // compute area
-              Area = AreaMio + pGate0->Area;
-              if ( Area > pMan->tAreaMax )
-                  break;
-
-              pSupers[0] = pGate0;  uTruths[0][0] = pGate0->uTruth[0];  uTruths[0][1] = pGate0->uTruth[1];  ptPinDelays[0] = pGate0->ptDelays; 
-              Mio_DeriveGateDelays( ppGates[k], ptPinDelays, nFanins, pMan->nVarsMax, SUPER_NO_VAR, tPinDelaysRes, &tPinDelayMax );
-              Mio_DeriveTruthTable( ppGates[k], uTruths, nFanins, pMan->nVarsMax, uTruth );
-              if ( !Super_CompareGates( pMan, uTruth, Area, tPinDelaysRes, pMan->nVarsMax ) )
-                  continue;
-              // create a new gate
-              pGateNew = Super_CreateGateNew( pMan, ppGates[k], pSupers, nFanins, uTruth, Area, tPinDelaysRes, tPinDelayMax, pMan->nVarsMax );
-              Super_AddGateToTable( pMan, pGateNew );
-           }
-            break;
-        case 2: // two-input root gate
-            Super_ManForEachGate( ppGatesLimit, nGatesLimit, i0, pGate0 )
-            {
-              Area0 = AreaMio + pGate0->Area;
-              if ( Area0 > pMan->tAreaMax )
-                  break;
-              pSupers[0] = pGate0;  uTruths[0][0] = pGate0->uTruth[0];  uTruths[0][1] = pGate0->uTruth[1];  ptPinDelays[0] = pGate0->ptDelays; 
-              Super_ManForEachGate( ppGatesLimit, nGatesLimit, i1, pGate1 )
-              if ( i1 != i0 )
-              {
-                if ( fTimeOut ) goto done;
-                fTimeOut = Super_CheckTimeout( pProgress, pMan );
-                // compute area
-                Area = Area0 + pGate1->Area;
-                if ( Area > pMan->tAreaMax )
-                    break;
-
-                pSupers[1] = pGate1;  uTruths[1][0] = pGate1->uTruth[0];  uTruths[1][1] = pGate1->uTruth[1];  ptPinDelays[1] = pGate1->ptDelays;
-                Mio_DeriveGateDelays( ppGates[k], ptPinDelays, nFanins, pMan->nVarsMax, SUPER_NO_VAR, tPinDelaysRes, &tPinDelayMax );
-                Mio_DeriveTruthTable( ppGates[k], uTruths, nFanins, pMan->nVarsMax, uTruth );
-                if ( !Super_CompareGates( pMan, uTruth, Area, tPinDelaysRes, pMan->nVarsMax ) )
-                    continue;
-                // create a new gate
-                pGateNew = Super_CreateGateNew( pMan, ppGates[k], pSupers, nFanins, uTruth, Area, tPinDelaysRes, tPinDelayMax, pMan->nVarsMax );
-                Super_AddGateToTable( pMan, pGateNew );
-              }
-            }
-            break;
-        case 3: // three-input root gate
-            Super_ManForEachGate( ppGatesLimit, nGatesLimit, i0, pGate0 )
-            {
-              Area0 = AreaMio + pGate0->Area;
-              if ( Area0 > pMan->tAreaMax )
-                  break;
-              pSupers[0] = pGate0;  uTruths[0][0] = pGate0->uTruth[0];  uTruths[0][1] = pGate0->uTruth[1];  ptPinDelays[0] = pGate0->ptDelays; 
-
-              Super_ManForEachGate( ppGatesLimit, nGatesLimit, i1, pGate1 )
-              if ( i1 != i0 )
-              {
-                Area1 = Area0 + pGate1->Area;
-                if ( Area1 > pMan->tAreaMax )
-                    break;
-                pSupers[1] = pGate1;  uTruths[1][0] = pGate1->uTruth[0];  uTruths[1][1] = pGate1->uTruth[1];  ptPinDelays[1] = pGate1->ptDelays;
-
-                Super_ManForEachGate( ppGatesLimit, nGatesLimit, i2, pGate2 )
-                if ( i2 != i0 && i2 != i1 )
-                {
-                  if ( fTimeOut ) goto done;
-                  fTimeOut = Super_CheckTimeout( pProgress, pMan );
-                  // compute area
-                  Area = Area1 + pGate2->Area;
-                  if ( Area > pMan->tAreaMax )
-                      break;
-                  pSupers[2] = pGate2;  uTruths[2][0] = pGate2->uTruth[0];  uTruths[2][1] = pGate2->uTruth[1];   ptPinDelays[2] = pGate2->ptDelays;
-
-                  Mio_DeriveGateDelays( ppGates[k], ptPinDelays, nFanins, pMan->nVarsMax, SUPER_NO_VAR, tPinDelaysRes, &tPinDelayMax );
-                  Mio_DeriveTruthTable( ppGates[k], uTruths, nFanins, pMan->nVarsMax, uTruth );
-                  if ( !Super_CompareGates( pMan, uTruth, Area, tPinDelaysRes, pMan->nVarsMax ) )
-                      continue;
-                  // create a new gate
-                  pGateNew = Super_CreateGateNew( pMan, ppGates[k], pSupers, nFanins, uTruth, Area, tPinDelaysRes, tPinDelayMax, pMan->nVarsMax );
-                  Super_AddGateToTable( pMan, pGateNew );
-                }
-              }
-            }
-            break;
-        case 4: // four-input root gate
-            Super_ManForEachGate( ppGatesLimit, nGatesLimit, i0, pGate0 )
-            {
-              Area0 = AreaMio + pGate0->Area;
-              if ( Area0 > pMan->tAreaMax )
-                  break;
-              pSupers[0] = pGate0;  uTruths[0][0] = pGate0->uTruth[0];  uTruths[0][1] = pGate0->uTruth[1];  ptPinDelays[0] = pGate0->ptDelays; 
-
-              Super_ManForEachGate( ppGatesLimit, nGatesLimit, i1, pGate1 )
-              if ( i1 != i0 )
-              {
-                Area1 = Area0 + pGate1->Area;
-                if ( Area1 > pMan->tAreaMax )
-                    break;
-                pSupers[1] = pGate1;  uTruths[1][0] = pGate1->uTruth[0];  uTruths[1][1] = pGate1->uTruth[1];  ptPinDelays[1] = pGate1->ptDelays;
-
-                Super_ManForEachGate( ppGatesLimit, nGatesLimit, i2, pGate2 )
-                if ( i2 != i0 && i2 != i1 )
-                {
-                  Area2 = Area1 + pGate2->Area;
-                  if ( Area2 > pMan->tAreaMax )
-                      break;
-                  pSupers[2] = pGate2;  uTruths[2][0] = pGate2->uTruth[0];  uTruths[2][1] = pGate2->uTruth[1];   ptPinDelays[2] = pGate2->ptDelays;
-
-                  Super_ManForEachGate( ppGatesLimit, nGatesLimit, i3, pGate3 )
-                  if ( i3 != i0 && i3 != i1 && i3 != i2 )
-                  {
-                    if ( fTimeOut ) goto done;
-                    fTimeOut = Super_CheckTimeout( pProgress, pMan );
-                    // compute area
-                    Area = Area2 + pGate3->Area;
-                    if ( Area > pMan->tAreaMax )
-                        break;
-                    pSupers[3] = pGate3;   uTruths[3][0] = pGate3->uTruth[0];  uTruths[3][1] = pGate3->uTruth[1];   ptPinDelays[3] = pGate3->ptDelays;
-
-                    Mio_DeriveGateDelays( ppGates[k], ptPinDelays, nFanins, pMan->nVarsMax, SUPER_NO_VAR, tPinDelaysRes, &tPinDelayMax );
-                    Mio_DeriveTruthTable( ppGates[k], uTruths, nFanins, pMan->nVarsMax, uTruth );
-                    if ( !Super_CompareGates( pMan, uTruth, Area, tPinDelaysRes, pMan->nVarsMax ) )
-                        continue;
-                    // create a new gate
-                    pGateNew = Super_CreateGateNew( pMan, ppGates[k], pSupers, nFanins, uTruth, Area, tPinDelaysRes, tPinDelayMax, pMan->nVarsMax );
-                    Super_AddGateToTable( pMan, pGateNew );
-                  }
-                }
-              }
-            }
-            break;
-        case 5: // five-input root gate
-            Super_ManForEachGate( ppGatesLimit, nGatesLimit, i0, pGate0 )
-            {
-              Area0 = AreaMio + pGate0->Area;
-              if ( Area0 > pMan->tAreaMax )
-                  break;
-              pSupers[0] = pGate0;  uTruths[0][0] = pGate0->uTruth[0];  uTruths[0][1] = pGate0->uTruth[1];  ptPinDelays[0] = pGate0->ptDelays; 
-
-              Super_ManForEachGate( ppGatesLimit, nGatesLimit, i1, pGate1 )
-              if ( i1 != i0 )
-              {
-                Area1 = Area0 + pGate1->Area;
-                if ( Area1 > pMan->tAreaMax )
-                    break;
-                pSupers[1] = pGate1;  uTruths[1][0] = pGate1->uTruth[0];  uTruths[1][1] = pGate1->uTruth[1];  ptPinDelays[1] = pGate1->ptDelays;
-
-                Super_ManForEachGate( ppGatesLimit, nGatesLimit, i2, pGate2 )
-                if ( i2 != i0 && i2 != i1 )
-                {
-                  Area2 = Area1 + pGate2->Area;
-                  if ( Area2 > pMan->tAreaMax )
-                      break;
-                  pSupers[2] = pGate2;  uTruths[2][0] = pGate2->uTruth[0];  uTruths[2][1] = pGate2->uTruth[1];   ptPinDelays[2] = pGate2->ptDelays;
-
-                  Super_ManForEachGate( ppGatesLimit, nGatesLimit, i3, pGate3 )
-                  if ( i3 != i0 && i3 != i1 && i3 != i2 )
-                  {
-                    Area3 = Area2 + pGate3->Area;
-                    if ( Area3 > pMan->tAreaMax )
-                        break;
-                    pSupers[3] = pGate3;   uTruths[3][0] = pGate3->uTruth[0];  uTruths[3][1] = pGate3->uTruth[1];   ptPinDelays[3] = pGate3->ptDelays;
-
-                    Super_ManForEachGate( ppGatesLimit, nGatesLimit, i4, pGate4 )
-                    if ( i4 != i0 && i4 != i1 && i4 != i2 && i4 != i3 )
-                    {
-                      if ( fTimeOut ) goto done;
-                      fTimeOut = Super_CheckTimeout( pProgress, pMan );
-                      // compute area
-                      Area = Area3 + pGate4->Area;
-                      if ( Area > pMan->tAreaMax )
-                          break;
-                      pSupers[4] = pGate4;   uTruths[4][0] = pGate4->uTruth[0];  uTruths[4][1] = pGate4->uTruth[1];  ptPinDelays[4] = pGate4->ptDelays;
-
-                      Mio_DeriveGateDelays( ppGates[k], ptPinDelays, nFanins, pMan->nVarsMax, SUPER_NO_VAR, tPinDelaysRes, &tPinDelayMax );
-                      Mio_DeriveTruthTable( ppGates[k], uTruths, nFanins, pMan->nVarsMax, uTruth );
-                      if ( !Super_CompareGates( pMan, uTruth, Area, tPinDelaysRes, pMan->nVarsMax ) )
-                          continue;
-                      // create a new gate
-                      pGateNew = Super_CreateGateNew( pMan, ppGates[k], pSupers, nFanins, uTruth, Area, tPinDelaysRes, tPinDelayMax, pMan->nVarsMax );
-                      Super_AddGateToTable( pMan, pGateNew );
-                    }
-                  }
-                }
-              }
-            }
-            break;
-        case 6: // six-input root gate
-            Super_ManForEachGate( ppGatesLimit, nGatesLimit, i0, pGate0 )
-            {
-              Area0 = AreaMio + pGate0->Area;
-              if ( Area0 > pMan->tAreaMax )
-                  break;
-              pSupers[0] = pGate0;  uTruths[0][0] = pGate0->uTruth[0];  uTruths[0][1] = pGate0->uTruth[1];  ptPinDelays[0] = pGate0->ptDelays; 
-
-              Super_ManForEachGate( ppGatesLimit, nGatesLimit, i1, pGate1 )
-              if ( i1 != i0 )
-              {
-                Area1 = Area0 + pGate1->Area;
-                if ( Area1 > pMan->tAreaMax )
-                    break;
-                pSupers[1] = pGate1;  uTruths[1][0] = pGate1->uTruth[0];  uTruths[1][1] = pGate1->uTruth[1];  ptPinDelays[1] = pGate1->ptDelays;
-
-                Super_ManForEachGate( ppGatesLimit, nGatesLimit, i2, pGate2 )
-                if ( i2 != i0 && i2 != i1 )
-                {
-                  Area2 = Area1 + pGate2->Area;
-                  if ( Area2 > pMan->tAreaMax )
-                      break;
-                  pSupers[2] = pGate2;  uTruths[2][0] = pGate2->uTruth[0];  uTruths[2][1] = pGate2->uTruth[1];   ptPinDelays[2] = pGate2->ptDelays;
-
-                  Super_ManForEachGate( ppGatesLimit, nGatesLimit, i3, pGate3 )
-                  if ( i3 != i0 && i3 != i1 && i3 != i2 )
-                  {
-                    Area3 = Area2 + pGate3->Area;
-                    if ( Area3 > pMan->tAreaMax )
-                        break;
-                    pSupers[3] = pGate3;   uTruths[3][0] = pGate3->uTruth[0];  uTruths[3][1] = pGate3->uTruth[1];   ptPinDelays[3] = pGate3->ptDelays;
-
-                    Super_ManForEachGate( ppGatesLimit, nGatesLimit, i4, pGate4 )
-                    if ( i4 != i0 && i4 != i1 && i4 != i2 && i4 != i3 )
-                    {
-                      if ( fTimeOut ) break;
-                      fTimeOut = Super_CheckTimeout( pProgress, pMan );
-                      // compute area
-                      Area4 = Area3 + pGate4->Area;
-                      if ( Area > pMan->tAreaMax )
-                          break;
-                      pSupers[4] = pGate4;   uTruths[4][0] = pGate4->uTruth[0];  uTruths[4][1] = pGate4->uTruth[1];  ptPinDelays[4] = pGate4->ptDelays;
-
-                      Super_ManForEachGate( ppGatesLimit, nGatesLimit, i5, pGate5 )
-                      if ( i5 != i0 && i5 != i1 && i5 != i2 && i5 != i3 && i5 != i4 )
-                      {
-                        if ( fTimeOut ) goto done;
-                        fTimeOut = Super_CheckTimeout( pProgress, pMan );
-                        // compute area
-                        Area = Area4 + pGate5->Area;
-                        if ( Area > pMan->tAreaMax )
-                            break;
-                        pSupers[5] = pGate5;   uTruths[5][0] = pGate5->uTruth[0];  uTruths[5][1] = pGate5->uTruth[1];  ptPinDelays[5] = pGate5->ptDelays;
-
-                        Mio_DeriveGateDelays( ppGates[k], ptPinDelays, nFanins, pMan->nVarsMax, SUPER_NO_VAR, tPinDelaysRes, &tPinDelayMax );
-                        Mio_DeriveTruthTable( ppGates[k], uTruths, nFanins, pMan->nVarsMax, uTruth );
-                        if ( !Super_CompareGates( pMan, uTruth, Area, tPinDelaysRes, pMan->nVarsMax ) )
-                            continue;
-                        // create a new gate
-                        pGateNew = Super_CreateGateNew( pMan, ppGates[k], pSupers, nFanins, uTruth, Area, tPinDelaysRes, tPinDelayMax, pMan->nVarsMax );
-                        Super_AddGateToTable( pMan, pGateNew );
-                      }
-                    }
-                  }
-                }
-              }
-            }
-            break;
-        default :
-            assert( 0 );
-            break;
-        }
-    }
-done: 
-    Extra_ProgressBarStop( pProgress );
-    free( ppGatesLimit );
-    return pMan;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Transfers gates from table into the array.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Super_CheckTimeout( ProgressBar * pPro, Super_Man_t * pMan )
-{
-    int TimeNow = clock();
-    if ( TimeNow > pMan->TimePrint )
-    {
-        Extra_ProgressBarUpdate( pPro, ++pMan->TimeSec, NULL );
-        pMan->TimePrint = clock() + CLOCKS_PER_SEC;
-    }
-    if ( TimeNow > pMan->TimeStop )
-    {
-        printf ("Timeout!\n");
-        return 1;
-    }
-    pMan->nTried++;
-    return 0;
-}
-
-
-/**Function*************************************************************
-
-  Synopsis    [Transfers gates from table into the array.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Super_TranferGatesToArray( Super_Man_t * pMan )
-{
-    stmm_generator * gen;
-    Super_Gate_t * pGate, * pList;
-    unsigned Key;
-
-    // put the gates fron the table into the array
-    free( pMan->pGates );
-    pMan->pGates = ALLOC( Super_Gate_t *, pMan->nAdded );
-    pMan->nGates = 0;
-    stmm_foreach_item( pMan->tTable, gen, (char **)&Key, (char **)&pList )
-    {
-        for ( pGate = pList; pGate; pGate = pGate->pNext )
-            pMan->pGates[ pMan->nGates++ ] = pGate;
-    }
-//    assert( pMan->nGates == pMan->nAdded - pMan->nRemoved );
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Adds one supergate into the unique table.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Super_AddGateToTable( Super_Man_t * pMan, Super_Gate_t * pGate )
-{
-    Super_Gate_t ** ppList;
-    unsigned Key;
-//    Key = pGate->uTruth[0] + 2003 * pGate->uTruth[1];
-    Key = pGate->uTruth[0] ^ pGate->uTruth[1];
-    if ( !stmm_find_or_add( pMan->tTable, (char *)Key, (char ***)&ppList ) )
-        *ppList = NULL;
-    pGate->pNext = *ppList;
-    *ppList = pGate;
-    pMan->nAdded++;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Check the manager's unique table for comparable gates.]
-
-  Description [Returns 0 if the gate is dominated by others. Returns 1 
-  if the gate is new or is better than the available ones. In this case, 
-  cleans the table by removing the gates that are worse than the given one.]
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-bool Super_CompareGates( Super_Man_t * pMan, unsigned uTruth[], float Area, float tPinDelaysRes[], int nPins )
-{
-    Super_Gate_t ** ppList, * pPrev, * pGate, * pGate2;
-    int i, fNewIsBetter, fGateIsBetter;
-    unsigned Key;
-
-    // skip constant functions
-    if ( pMan->nVarsMax < 6 )
-    {
-        if ( uTruth[0] == 0 || ~uTruth[0] == 0 )
-            return 0;
-    }
-    else
-    {
-        if ( ( uTruth[0] == 0 && uTruth[1] == 0 ) || ( ~uTruth[0] == 0 && ~uTruth[1] == 0 ) )
-            return 0;
-    }
-
-    // get hold of the place where the entry is stored
-//    Key = uTruth[0] + 2003 * uTruth[1];
-    Key = uTruth[0] ^ uTruth[1];
-    if ( !stmm_find( pMan->tTable, (char *)Key, (char ***)&ppList ) )
-        return 1; 
-    // the entry with this truth table is found
-    pPrev = NULL;
-    for ( pGate = *ppList, pGate2 = pGate? pGate->pNext: NULL; pGate; 
-        pGate = pGate2, pGate2 = pGate? pGate->pNext: NULL )
-    {
-        pMan->nLookups++;
-        if ( pGate->uTruth[0] != uTruth[0] || pGate->uTruth[1] != uTruth[1] )
-        {
-            pMan->nAliases++;
-            continue;
-        }
-        fGateIsBetter = 0;
-        fNewIsBetter  = 0;
-        if ( pGate->Area + SUPER_EPSILON < Area )
-            fGateIsBetter = 1;
-        else if ( pGate->Area > Area + SUPER_EPSILON )
-            fNewIsBetter = 1;
-        for ( i = 0; i < nPins; i++ )
-        {
-            if ( pGate->ptDelays[i] == SUPER_NO_VAR || tPinDelaysRes[i] == SUPER_NO_VAR )
-                continue;
-            if ( pGate->ptDelays[i] + SUPER_EPSILON < tPinDelaysRes[i] )
-                fGateIsBetter = 1;
-            else if ( pGate->ptDelays[i] > tPinDelaysRes[i] + SUPER_EPSILON )
-                fNewIsBetter = 1;
-            if ( fGateIsBetter && fNewIsBetter )
-                break;
-        }
-        // consider 4 cases
-        if ( fGateIsBetter && fNewIsBetter ) // Pareto points; save both
-            pPrev = pGate;
-        else if ( fNewIsBetter ) // gate is worse; remove the gate
-        {
-            if ( pPrev == NULL )
-                *ppList = pGate->pNext;
-            else
-                pPrev->pNext = pGate->pNext;
-            Extra_MmFixedEntryRecycle( pMan->pMem, (char *)pGate );
-            pMan->nRemoved++;
-        }
-        else if ( fGateIsBetter ) // new is worse, already dominated no need to see others
-            return 0;
-        else // if ( !fGateIsBetter && !fNewIsBetter ) // they are identical, no need to see others
-            return 0;
-    }
-    return 1;
-}
-
-
-/**Function*************************************************************
-
-  Synopsis    [Create a new supergate.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-Super_Gate_t * Super_CreateGateNew( Super_Man_t * pMan, Mio_Gate_t * pRoot, Super_Gate_t ** pSupers, int nSupers, 
-    unsigned uTruth[], float Area, float tPinDelaysRes[], float tDelayMax, int nPins )
-{
-    Super_Gate_t * pSuper;
-    pSuper = (Super_Gate_t *)Extra_MmFixedEntryFetch( pMan->pMem );
-    memset( pSuper, 0, sizeof(Super_Gate_t) );
-    pSuper->pRoot     = pRoot;
-    pSuper->uTruth[0] = uTruth[0];
-    pSuper->uTruth[1] = uTruth[1];
-    memcpy( pSuper->ptDelays, tPinDelaysRes, sizeof(float) * nPins );
-    pSuper->Area      = Area;
-    pSuper->nFanins   = nSupers;
-    memcpy( pSuper->pFanins, pSupers, sizeof(Super_Gate_t *) * nSupers );
-    pSuper->pNext     = NULL;
-    pSuper->tDelayMax = tDelayMax;
-    return pSuper;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Starts the manager.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-Super_Man_t * Super_ManStart()
-{
-    Super_Man_t * pMan;
-    pMan = ALLOC( Super_Man_t, 1 );
-    memset( pMan, 0, sizeof(Super_Man_t) );
-    pMan->pMem     = Extra_MmFixedStart( sizeof(Super_Gate_t) );
-    pMan->tTable   = stmm_init_table( st_ptrcmp, st_ptrhash );
-    return pMan;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Stops the manager.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Super_ManStop( Super_Man_t * pMan )
-{
-    Extra_MmFixedStop( pMan->pMem );
-    if ( pMan->tTable ) stmm_free_table( pMan->tTable );
-    FREE( pMan->pGates );
-    free( pMan );
-}
-
-
-
-
-
-/**Function*************************************************************
-
-  Synopsis    [Writes the supergate library into the file.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Super_Write( Super_Man_t * pMan )
-{
-    Super_Gate_t * pGateRoot, * pGate;
-    stmm_generator * gen;
-    int fZeroFound, clk, v;
-    unsigned Key;
-
-    if ( pMan->nGates < 1 )
-    {
-        printf( "The generated library is empty. No output file written.\n" );
-        return;
-    }
-
-    // Filters the supergates by removing those that have fewer inputs than 
-    // the given limit, provided that the inputs are not consequtive. 
-    // For example, NAND2(a,c) is removed, but NAND2(a,b) is left, 
-    // because a and b are consequtive.
-    FREE( pMan->pGates );
-    pMan->pGates = ALLOC( Super_Gate_t *, pMan->nAdded );
-    pMan->nGates = 0;
-    stmm_foreach_item( pMan->tTable, gen, (char **)&Key, (char **)&pGateRoot )
-    {
-        for ( pGate = pGateRoot; pGate; pGate = pGate->pNext )
-        {
-            // skip the elementary variables
-            if ( pGate->pRoot == NULL )
-                continue;
-            // skip the non-consequtive gates
-            fZeroFound = 0;
-            for ( v = 0; v < pMan->nVarsMax; v++ )
-                if ( pGate->ptDelays[v] < SUPER_NO_VAR + SUPER_EPSILON )
-                    fZeroFound = 1;
-                else if ( fZeroFound )
-                    break;
-            if ( v < pMan->nVarsMax )
-                continue;
-            // save the unique gate
-            pMan->pGates[ pMan->nGates++ ] = pGate;
-        }
-    }
-
-clk = clock();
-    // sort the supergates by truth table
-    qsort( (void *)pMan->pGates, pMan->nGates, sizeof(Super_Gate_t *), 
-            (int (*)(const void *, const void *)) Super_WriteCompare );
-    assert( Super_WriteCompare( pMan->pGates, pMan->pGates + pMan->nGates - 1 ) <= 0 );
-if ( pMan->fVerbose )
-{
-PRT( "Sorting", clock() - clk );
-}
-
-
-    // write library in the old format
-clk = clock();
-    if ( pMan->fWriteOldFormat )
-        Super_WriteLibrary( pMan );
-if ( pMan->fVerbose )
-{
-PRT( "Writing old format", clock() - clk );
-}
-
-    // write the tree-like structure of supergates
-clk = clock();
-    Super_WriteLibraryTree( pMan );
-if ( pMan->fVerbose )
-{
-PRT( "Writing new format", clock() - clk );
-}
-}
-
-
-/**Function*************************************************************
-
-  Synopsis    [Writes the file header.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Super_WriteFileHeader( Super_Man_t * pMan, FILE * pFile )
-{
-    fprintf( pFile, "#\n" );
-    fprintf( pFile, "# Supergate library derived for \"%s\" on %s.\n", pMan->pName, Extra_TimeStamp() );
-    fprintf( pFile, "#\n" );
-    fprintf( pFile, "# Command line: \"super  -i %d  -l %d  -d %.2f  -a %.2f  -t %d  %s  %s\".\n", 
-        pMan->nVarsMax, pMan->nLevels, pMan->tDelayMax, pMan->tAreaMax, pMan->TimeLimit, (pMan->fSkipInv? "" : "-s"), pMan->pName );
-    fprintf( pFile, "#\n" );
-    fprintf( pFile, "# The number of inputs      = %10d.\n", pMan->nVarsMax );
-    fprintf( pFile, "# The number of levels      = %10d.\n", pMan->nLevels );
-    fprintf( pFile, "# The maximum delay         = %10.2f.\n", pMan->tDelayMax  );
-    fprintf( pFile, "# The maximum area          = %10.2f.\n", pMan->tAreaMax );
-    fprintf( pFile, "# The maximum runtime (sec) = %10d.\n", pMan->TimeLimit );
-    fprintf( pFile, "#\n" );
-    fprintf( pFile, "# The number of attempts    = %10d.\n", pMan->nTried  );
-    fprintf( pFile, "# The number of supergates  = %10d.\n", pMan->nGates  );
-    fprintf( pFile, "# The number of functions   = %10d.\n", pMan->nUnique );
-    fprintf( pFile, "# The total functions       = %.0f (2^%d).\n", pow(2,pMan->nMints), pMan->nMints );
-    fprintf( pFile, "#\n" );
-    fprintf( pFile, "# Generation time (sec)     = %10.2f.\n", (float)(pMan->Time)/(float)(CLOCKS_PER_SEC) );
-    fprintf( pFile, "#\n" );
-    fprintf( pFile, "%s\n", pMan->pName );
-    fprintf( pFile, "%d\n", pMan->nVarsMax );
-    fprintf( pFile, "%d\n", pMan->nGates );
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Compares the truth tables of two gates.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Super_WriteCompare( Super_Gate_t ** ppG1, Super_Gate_t ** ppG2 )
-{
-    unsigned * pTruth1 = (*ppG1)->uTruth;
-    unsigned * pTruth2 = (*ppG2)->uTruth;
-    if ( pTruth1[1] < pTruth2[1] )
-        return -1;
-    if ( pTruth1[1] > pTruth2[1] )
-        return 1;
-    if ( pTruth1[0] < pTruth2[0] )
-        return -1;
-    if ( pTruth1[0] > pTruth2[0] )
-        return 1;
-    return 0;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Compares the max delay of two gates.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Super_DelayCompare( Super_Gate_t ** ppG1, Super_Gate_t ** ppG2 )
-{
-    if ( (*ppG1)->tDelayMax < (*ppG2)->tDelayMax )
-        return -1;
-    if ( (*ppG1)->tDelayMax > (*ppG2)->tDelayMax )
-        return 1;
-    return 0;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Compares the area of two gates.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Super_AreaCompare( Super_Gate_t ** ppG1, Super_Gate_t ** ppG2 )
-{
-    if ( (*ppG1)->Area < (*ppG2)->Area )
-        return -1;
-    if ( (*ppG1)->Area > (*ppG2)->Area )
-        return 1;
-    return 0;
-}
-
-
-
-
-
-
-/**Function*************************************************************
-
-  Synopsis    [Writes the gates into the file.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Super_WriteLibrary( Super_Man_t * pMan )
-{
-    Super_Gate_t * pGate, * pGateNext;
-    FILE * pFile;
-    char FileName[100];
-    char * pNameGeneric;
-    int i, Counter;
-
-    // get the file name
-    pNameGeneric = Extra_FileNameGeneric( pMan->pName );
-    sprintf( FileName, "%s.super_old", pNameGeneric );
-    free( pNameGeneric );
-
-    // count the number of unique functions
-    pMan->nUnique = 1;
-    Super_ManForEachGate( pMan->pGates, pMan->nGates, i, pGate )
-    {
-        if ( i == pMan->nGates - 1 )
-            break;
-        // print the newline if this gate is different from the following one
-        pGateNext = pMan->pGates[i+1];
-        if ( pGateNext->uTruth[0] != pGate->uTruth[0] || pGateNext->uTruth[1] != pGate->uTruth[1] )
-            pMan->nUnique++;
-    }
-
-    // start the file
-    pFile = fopen( FileName, "w" );
-    Super_WriteFileHeader( pMan, pFile );
-
-    // print the gates
-    Counter = 0;
-    Super_ManForEachGate( pMan->pGates, pMan->nGates, i, pGate )
-    {
-        Super_WriteLibraryGate( pFile, pMan, pGate, ++Counter );
-        if ( i == pMan->nGates - 1 )
-            break;
-        // print the newline if this gate is different from the following one
-        pGateNext = pMan->pGates[i+1];
-        if ( pGateNext->uTruth[0] != pGate->uTruth[0] || pGateNext->uTruth[1] != pGate->uTruth[1] )
-            fprintf( pFile, "\n" );
-    }
-    assert( Counter == pMan->nGates );
-    fclose( pFile );
-
-if ( pMan->fVerbose )
-{
-    printf( "The supergates are written using old format \"%s\" ", FileName );
-    printf( "(%0.3f Mb).\n", ((double)Extra_FileSize(FileName))/(1<<20) );
-}
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Writes the supergate into the file.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Super_WriteLibraryGate( FILE * pFile, Super_Man_t * pMan, Super_Gate_t * pGate, int Num )
-{
-    int i;
-    fprintf( pFile, "%04d  ", Num );                         // the number
-    Extra_PrintBinary( pFile, pGate->uTruth, pMan->nMints ); // the truth table
-    fprintf( pFile, "   %5.2f", pGate->tDelayMax );          // the max delay
-    fprintf( pFile, "  " );                                  
-    for ( i = 0; i < pMan->nVarsMax; i++ )                   // the pin-to-pin delays
-        fprintf( pFile, " %5.2f", pGate->ptDelays[i]==SUPER_NO_VAR? 0.0 : pGate->ptDelays[i] );  
-    fprintf( pFile, "   %5.2f", pGate->Area );               // the area
-    fprintf( pFile, "   " );
-    fprintf( pFile, "%s", Super_WriteLibraryGateName(pGate) );      // the symbolic expression
-    fprintf( pFile, "\n" );
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Recursively generates symbolic name of the supergate.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-char * Super_WriteLibraryGateName( Super_Gate_t * pGate )
-{
-    static char Buffer[2000];
-    Buffer[0] = 0;
-    Super_WriteLibraryGateName_rec( pGate, Buffer );
-    return Buffer;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Recursively generates symbolic name of the supergate.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Super_WriteLibraryGateName_rec( Super_Gate_t * pGate, char * pBuffer )
-{
-    char Buffer[10];
-    int i;
-
-    if ( pGate->pRoot == NULL )
-    {
-        sprintf( Buffer, "%c", 'a' + pGate->Number );
-        strcat( pBuffer, Buffer );
-        return;
-    }
-    strcat( pBuffer, Mio_GateReadName(pGate->pRoot) );
-    strcat( pBuffer, "(" );
-    for ( i = 0; i < (int)pGate->nFanins; i++ )
-    {
-        if ( i )
-            strcat( pBuffer, "," );
-        Super_WriteLibraryGateName_rec( pGate->pFanins[i], pBuffer );
-    }
-    strcat( pBuffer, ")" );
-}
-
-
-
-
-
-/**Function*************************************************************
-
-  Synopsis    [Recursively writes the gates.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Super_WriteLibraryTree( Super_Man_t * pMan )
-{
-    Super_Gate_t * pSuper;
-    FILE * pFile;
-    char FileName[100];
-    char * pNameGeneric;
-    int i, Counter;
-    int posStart;
-
-    // get the file name
-    pNameGeneric = Extra_FileNameGeneric( pMan->pName );
-    sprintf( FileName, "%s.super", pNameGeneric );
-    free( pNameGeneric );
- 
-    // write the elementary variables
-    pFile = fopen( FileName, "w" );
-    Super_WriteFileHeader( pMan, pFile );
-    // write the place holder for the number of lines
-    posStart = ftell( pFile );
-    fprintf( pFile, "         \n" );
-    // mark the real supergates
-    Super_ManForEachGate( pMan->pGates, pMan->nGates, i, pSuper )
-        pSuper->fSuper = 1;
-    // write the supergates
-    Counter = pMan->nVarsMax;
-    Super_ManForEachGate( pMan->pGates, pMan->nGates, i, pSuper )
-        Super_WriteLibraryTree_rec( pFile, pMan, pSuper, &Counter );
-    fclose( pFile );
-    // write the number of lines
-    pFile = fopen( FileName, "rb+" );
-    fseek( pFile, posStart, SEEK_SET );
-    fprintf( pFile, "%d", Counter );
-    fclose( pFile );
-
-if ( pMan->fVerbose )
-{
-    printf( "The supergates are written using new format \"%s\" ", FileName );
-    printf( "(%0.3f Mb).\n", ((double)Extra_FileSize(FileName))/(1<<20) );
-}
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Recursively writes the gate.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Super_WriteLibraryTree_rec( FILE * pFile, Super_Man_t * pMan, Super_Gate_t * pSuper, int * pCounter )
-{
-    int nFanins, i;
-    // skip an elementary variable and a gate that was already written
-    if ( pSuper->fVar || pSuper->Number > 0 )
-        return;
-    // write the fanins
-    nFanins = Mio_GateReadInputs(pSuper->pRoot);
-    for ( i = 0; i < nFanins; i++ )
-        Super_WriteLibraryTree_rec( pFile, pMan, pSuper->pFanins[i], pCounter );
-    // finally write the gate
-    pSuper->Number = (*pCounter)++;
-    fprintf( pFile, "%s", pSuper->fSuper? "* " : "" );
-    fprintf( pFile, "%s", Mio_GateReadName(pSuper->pRoot) );
-    for ( i = 0; i < nFanins; i++ )
-        fprintf( pFile, " %d", pSuper->pFanins[i]->Number );
-    // write the formula 
-    // this step is optional, the resulting library will work in any case
-    // however, it may be helpful to for debugging to compare the same library 
-    // written in the old format and written in the new format with formulas
-//    fprintf( pFile, "    # %s", Super_WriteLibraryGateName( pSuper ) );
-    fprintf( pFile, "\n" );
-}
-
-
-////////////////////////////////////////////////////////////////////////
-///                       END OF FILE                                ///
-////////////////////////////////////////////////////////////////////////
-
diff --git a/abc70930/src/map/super/superInt.h b/abc70930/src/map/super/superInt.h
deleted file mode 100644
index ec6d0a38..00000000
--- a/abc70930/src/map/super/superInt.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/**CFile****************************************************************
-
-  FileName    [superInt.h]
-
-  PackageName [MVSIS 2.0: Multi-valued logic synthesis system.]
-
-  Synopsis    [Pre-computation of supergates.]
-
-  Author      [MVSIS Group]
-  
-  Affiliation [UC Berkeley]
-
-  Date        [Ver. 1.0. Started - September 8, 2003.]
-
-  Revision    [$Id: superInt.h,v 1.4 2004/07/06 04:55:59 alanmi Exp $]
-
-***********************************************************************/
-
-#ifndef __super_INT_H__
-#define __super_INT_H__
-
-////////////////////////////////////////////////////////////////////////
-///                          INCLUDES                                ///
-////////////////////////////////////////////////////////////////////////
-
-#include "abc.h"
-#include "mainInt.h"
-#include "mvc.h"
-#include "mio.h"
-#include "stmm.h"
-#include "super.h"
-
-////////////////////////////////////////////////////////////////////////
-///                         PARAMETERS                               ///
-////////////////////////////////////////////////////////////////////////
-
-////////////////////////////////////////////////////////////////////////
-///                    STRUCTURE DEFINITIONS                         ///
-////////////////////////////////////////////////////////////////////////
-
-////////////////////////////////////////////////////////////////////////
-///                       GLOBAL VARIABLES                           ///
-////////////////////////////////////////////////////////////////////////
-
-////////////////////////////////////////////////////////////////////////
-///                       MACRO DEFINITIONS                          ///
-////////////////////////////////////////////////////////////////////////
-
-////////////////////////////////////////////////////////////////////////
-///                     FUNCTION DEFINITIONS                         ///
-////////////////////////////////////////////////////////////////////////
-
-/*=== superAnd.c =============================================================*/
-extern void       Super2_Precompute( int nInputs, int nLevels, int fVerbose );
-/*=== superGate.c =============================================================*/
-extern void       Super_Precompute( Mio_Library_t * pLibGen, int nInputs, int nLevels, float tDelayMax, float tAreaMax, int TimeLimit, bool fSkipInv, bool fWriteOldFormat, int fVerbose );
-
-#endif
-
-////////////////////////////////////////////////////////////////////////
-///                       END OF FILE                                ///
-////////////////////////////////////////////////////////////////////////
diff --git a/abc70930/src/map/super/superWrite.c b/abc70930/src/map/super/superWrite.c
deleted file mode 100644
index 395ef145..00000000
--- a/abc70930/src/map/super/superWrite.c
+++ /dev/null
@@ -1,76 +0,0 @@
-/**CFile****************************************************************
-
-  FileName    [superWrite.c]
-
-  PackageName [MVSIS 1.3: Multi-valued logic synthesis system.]
-
-  Synopsis    [Pre-computation of supergates.]
-
-  Author      [MVSIS Group]
-  
-  Affiliation [UC Berkeley]
-
-  Date        [Ver. 1.0. Started - September 8, 2003.]
-
-  Revision    [$Id: superWrite.c,v 1.1 2004/04/03 01:36:45 alanmi Exp $]
-
-***********************************************************************/
-
-#include "superInt.h"
-
-/*
-    One record in the supergate library file consists of:
-
-    <gate_number> <truth_table> <delay_max> <pin-to-pin-delays> <area> <gate_formula>
-
-    <gate_number>       is a zero-based integer
-    <truth_table>       is a string of 2^n bits representing the value of the function for each minterm
-    <delay_max>         is the maximum delay of the gate
-    <pin-to-pin-delays> is the array of n double values
-    <area>              is a floating point value
-    <gate_formula>      is the string representing the gate in the following format:
-        GATENAME1( GATENAME2( a, c ), GATENAME3( a, d ), ... )
-        The gate names (GATENAME1, etc) are the names as they appear in the .genlib library.
-        The primary inputs of the gates are denoted by lowercase chars 'a', 'b', etc.
-        The parantheses are mandatory for each gate, except for the wire. 
-        The wire name can be omitted, so that "a" can be used instead of "**wire**( a )".
-        The spaces are optional in any position of this string.
-
-
-    The supergates are generated exhaustively from all gate combinations that
-    have the max delay lower than the delay given by the user, or until the specified time
-    limit is reached.
-
-    The supergates are stored in supergate classes by their functionality. 
-    Among the gates with the equivalent functionaly only those are dropped, which are
-    dominated by at least one other gate in the class in terms of both delay and area.
-    For the definition of gate dominance see pliGenCheckDominance().
-*/
-
-
-////////////////////////////////////////////////////////////////////////
-///                        DECLARATIONS                              ///
-////////////////////////////////////////////////////////////////////////
-
-////////////////////////////////////////////////////////////////////////
-///                     FUNCTION DEFINITIONS                         ///
-////////////////////////////////////////////////////////////////////////
-
-/**Function*************************************************************
-
-  Synopsis    []
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-
-
-////////////////////////////////////////////////////////////////////////
-///                       END OF FILE                                ///
-////////////////////////////////////////////////////////////////////////
-
-