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author | Alan Mishchenko <alanmi@berkeley.edu> | 2011-08-01 11:25:46 +0700 |
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committer | Alan Mishchenko <alanmi@berkeley.edu> | 2011-08-01 11:25:46 +0700 |
commit | ab3c537072854a95c7da6e1dcc7f155c808fb837 (patch) | |
tree | 0d5f7ac717d0689fcbb2a55e706e426352a8a61b | |
parent | 88251e97e3e7e668ebd81bcc65eb77e3cd61ac2a (diff) | |
download | abc-ab3c537072854a95c7da6e1dcc7f155c808fb837.tar.gz abc-ab3c537072854a95c7da6e1dcc7f155c808fb837.tar.bz2 abc-ab3c537072854a95c7da6e1dcc7f155c808fb837.zip |
Undoing previous change in 'resim' (do not initialize flops using their values in the CEX because the number of flops in the CEX can be different).
-rw-r--r-- | src/aig/cec/cecSeq.c | 14 |
1 files changed, 12 insertions, 2 deletions
diff --git a/src/aig/cec/cecSeq.c b/src/aig/cec/cecSeq.c index 7e7549c0..dd561971 100644 --- a/src/aig/cec/cecSeq.c +++ b/src/aig/cec/cecSeq.c @@ -49,20 +49,30 @@ void Cec_ManSeqDeriveInfoFromCex( Vec_Ptr_t * vInfo, Gia_Man_t * pAig, Abc_Cex_t assert( pCex->nBits == pCex->nRegs + pCex->nPis * (pCex->iFrame + 1) ); assert( pCex->nBits - pCex->nRegs + Gia_ManRegNum(pAig) <= Vec_PtrSize(vInfo) ); nWords = Vec_PtrReadWordsSimInfo( vInfo ); +/* + // user register values + assert( pCex->nRegs == Gia_ManRegNum(pAig) ); for ( k = 0; k < pCex->nRegs; k++ ) { pInfo = (unsigned *)Vec_PtrEntry( vInfo, k ); for ( w = 0; w < nWords; w++ ) pInfo[w] = Gia_InfoHasBit( pCex->pData, k )? ~0 : 0; } -/* +*/ + // print warning about register values + for ( k = 0; k < pCex->nRegs; k++ ) + if ( Gia_InfoHasBit( pCex->pData, k ) ) + break; + if ( k < pCex->nRegs ) + Abc_Print( 0, "The CEX has flop values different from 0, but they are currently not used by \"resim\".\n" ); + + // assign zero register values for ( k = 0; k < Gia_ManRegNum(pAig); k++ ) { pInfo = (unsigned *)Vec_PtrEntry( vInfo, k ); for ( w = 0; w < nWords; w++ ) pInfo[w] = 0; } -*/ for ( i = pCex->nRegs; i < pCex->nBits; i++ ) { pInfo = (unsigned *)Vec_PtrEntry( vInfo, k++ ); |