library ieee;
use ieee.std_logic_1164.all;

entity vram is
    generic (
        addr_width  : natural := 17;
        video_width : natural := 2
        );
    port (
        wr_clk  : in  std_logic;
        wr_en   : in  std_logic;
        wr_addr : in  std_logic_vector(addr_width-1 downto 0);
        wr_data : in  std_logic_vector(video_width-1 downto 0);
        rd_clk  : in  std_logic;
        rd_addr : in  std_logic_vector(addr_width-1 downto 0);
        rd_data : out std_logic_vector(video_width-1 downto 0)
        );
end vram;

architecture beh of vram is
    signal wr_en_v : std_logic_vector(0 downto 0);
begin

    wr_en_v(0) <= wr_en;

    vram_impl0 : entity work.vram_spartan6_impl
        port map (
            clka  => wr_clk,
            wea   => wr_en_v,
            addra => wr_addr,
            dina  => wr_data,
            clkb  => rd_clk,
            doutb => rd_data,
            addrb => rd_addr
            );
end beh;