library ieee;
use ieee.std_logic_1164.all;

entity vram is
    generic (
        addr_width  : natural := 17;
        video_width : natural := 2
        );
    port (
        wr_clk  : in  std_logic;
        wr_en   : in  std_logic;
        wr_addr : in  std_logic_vector(addr_width-1 downto 0);
        wr_data : in  std_logic_vector(video_width-1 downto 0);
        rd_clk  : in  std_logic;
        rd_addr : in  std_logic_vector(addr_width-1 downto 0);
        rd_data : out std_logic_vector(video_width-1 downto 0)
        );
end vram;

architecture beh of vram is
begin



    vram_impl0 : entity work.vram_cyclone4_impl
        port map (
            wrclock   => wr_clk,
            wren      => wr_en,
            wraddress => wr_addr,
            data      => wr_data,
            rdclock   => rd_clk,
            q         => rd_data,
            rdaddress => rd_addr
            );
end beh;