library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.all;

entity vnc_hw is
    generic (
        video_width : integer := 2
        );
    port (
        vnc_clk   : in std_logic;
        vnc_valid : in std_logic;
        vnc_data  : in std_logic_vector(video_width -1 downto 0);
        vnc_index : in std_logic;

        sys_rst_n : in std_logic;

        run : in std_logic;

        clk_50m : in std_logic;

        axi_aclk    : in std_logic;
        axi_aresetn : in std_logic;

        axi_awaddr  : out std_logic_vector (31 downto 0);
        axi_awvalid : out std_logic;
        axi_awready : in  std_logic;
        axi_wdata   : out std_logic_vector (63 downto 0);
        axi_wstrb   : out std_logic_vector (7 downto 0);
        axi_wvalid  : out std_logic;
        axi_wready  : in  std_logic;
        axi_bvalid  : in  std_logic;
        axi_bready  : out std_logic
        );
end vnc_hw;
architecture Behavioural of vnc_hw is

    signal fifo_rst_cnt : natural;
    signal fifo_rst     : std_logic;
    signal fifo_wr_en   : std_logic;
    signal fifo_wdata   : std_logic_vector(64 downto 0);
    signal fifo_rd_en   : std_logic;
    signal fifo_rdata   : std_logic_vector(64 downto 0);
    signal fifo_empty   : std_logic;

begin

    vnc_serializer_i : entity work.vnc_serializer
        generic map (
            video_width => video_width
            )
        port map (
            clk       => vnc_clk,
            vnc_valid => vnc_valid,
            vnc_data  => vnc_data,
            vnc_index => vnc_index,

            fifo_data => fifo_wdata,
            fifo_wren => fifo_wr_en);


    process (clk_50m)
    begin
        if rising_edge(clk_50m) then
            if sys_rst_n = '0' then
                fifo_rst_cnt <= 20;
                fifo_rst     <= '1';
            elsif fifo_rst_cnt /= 0 then
                fifo_rst_cnt <= fifo_rst_cnt -1;
            else
                fifo_rst <= '0';
            end if;
        end if;
    end process;

    fifo_i : entity work.fifo_generator_0
        port map (
            rst    => fifo_rst,
            wr_clk => vnc_clk,
            din    => fifo_wdata,
            wr_en  => fifo_wr_en,
            rd_clk => axi_aclk,
            rd_en  => fifo_rd_en,
            dout   => fifo_rdata,
            empty  => fifo_empty
            );



    fifo_to_axi_i : entity work.fifo_to_axi
        port map(
            aclk        => axi_aclk,
            aresetn     => axi_aresetn,
            axi_awaddr  => axi_awaddr,
            axi_awvalid => axi_awvalid,
            axi_awready => axi_awready,
            axi_wdata   => axi_wdata,
            axi_wstrb   => axi_wstrb,
            axi_wvalid  => axi_wvalid,
            axi_wready  => axi_wready,
            axi_bvalid  => axi_bvalid,
            axi_bready  => axi_bready,

            run => run,

            fifo_empty => fifo_empty,
            fifo_rdata => fifo_rdata,
            fifo_rd_en => fifo_rd_en
            );

end Behavioural;